JP2002157290A - Method for clearly showing clock name by hardware description language - Google Patents

Abstract

(57) [Summary] (Modified) [PROBLEMS] When describing a synchronous circuit in a hardware description language, the relationship must be such that setup and hold errors do not occur without returning to the circuit for creating the input signal of the flip-flop. Can be confirmed, and the design time can be reduced. First, it is determined whether all flip-flop cells have been selected (step S1). If all flip-flop cells have not been selected, a clock name is added to the output signals of the cells (step S2) and the process returns to step S1. Next, it is determined whether all the combinational circuit cells have been selected (step S3), and the process proceeds to add a clock name to the output signal of the cell (step S4).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for specifying a clock name in a hardware description language for designing a digital circuit using a hardware description language such as VHDL.

[0002]

2. Description of the Related Art In recent years, hardware description languages (Hardware Description Language)
A programming language called Description Language) used for circuit design of a semiconductor device or the like has appeared. Semiconductor devices are manufactured through multiple design processes such as operation design and logic design.If the design data created once is described in different expressions in various design processes, the data in the previous process Data conversion was required one by one to utilize. Thus, by using a hardware description language, the design data once created can be uniformly used without converting the data in each process. As a typical hardware description language, VHDL (VHSIC Hardware Description Langu
age).

[0003]

In a synchronous circuit, that is, a circuit composed of a flip-flop or the like in which a signal changes in synchronization with a clock pulse, when a signal is transferred with a different clock pulse, a different clock is used. If the phase relationship between the pulses is undefined and fluctuates, and there is a possibility that the change point of the input signal of the flip-flop substantially coincides with the timing of the drive clock pulse, a setup or hold error occurs.

Conventionally, when a synchronous circuit is designed using a description language such as VHDL, clock information is not included in a signal name. Therefore, it was not clear just by looking at the description language which clock the signal was based on. Therefore, at the time of design, return to the circuit for creating the input signal of the flip-flop, investigate the drive clock pulse, and make sure that the phase relationship with the received drive clock pulse of the flip-flop does not cause a setup and hold error It was necessary to check and was spending a lot of time at the time of design.

According to the present invention, in order to solve such a problem, when a synchronous circuit is described in a hardware description language, a setup and hold error does not occur without returning to a circuit for generating an input signal of a flip-flop. It is an object of the present invention to provide a clock name specifying method using a hardware description language that can confirm that the clock name is shorter and can reduce the design time.

[0006]

According to the present invention, when a synchronous circuit is described in a hardware description language, a clock name based on which the signal was created is added to a created signal name. This is a clock name specification method using a characteristic hardware description language.

In the present invention, by automatically or manually adding the clock name based on which the signal is generated, the clock returns to the circuit for generating the input signal of the flip-flop and the drive clock pulse is wasted. lose.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a clock specifying method according to the present invention. In step S1, it is determined whether all flip-flop cells have been selected. If all flip-flop cells have not been selected, the process proceeds to step S2, where a clock name is added to the output signal of the cell, and the process returns to step S1. That is, a flip-flop is selected from the circuit description, and the addition of the driving clock name to the output signal of the selected cell is executed until all the flip-flops are selected and added.

Next, in step S3, it is determined whether all the combinational circuit cells have been selected.
To add a clock name to the output signal of the cell. That is, a combination circuit that has not been selected is selected, a clock name is added to the output of the output signal of the selected cell, and the processing is executed until all the combination circuits are selected and added.

According to the above operation, in the description portion of the flip-flop, the drive clock pulse of the input signal and the drive clock pulse of the flip-flop can be easily determined, and a setup hold error occurs based on phase information between clocks. It is possible to determine whether or not to do so.

FIG. 2 is a block diagram showing a synchronous circuit using flip-flops. FIG. 1A shows an example of a flip-flop extracted from the entire circuit, and FIG. 1B shows an example of a combinational circuit. FIG. 3 is an example of VHDL describing this synchronous circuit.

From the entire circuit, the flip-flop 11,
Extract 12 and 13. Outputs of the extracted flip-flops 11, 12, and 13 are as shown in FIG.
The drive clock pulse names A, B, and C are added to the output signal names. That is, as shown in FIG. 3A, when described in VHDL, A, B, and C, which are the drive clock pulse names, are added to the output signal name.

On the other hand, the combinational circuit of FIG.
R circuit 14, and flip-flops 11, 12, 13
Are connected. In this combination circuit 14,
SIGNAL1_A to SIG in which all of the clock names A, B, and C to which the input signal is added are added to the output.
NAL3_C is input and the output signal SIGNAL4_A
Create a BC. As shown in FIG. 3 (b), when described in VHDL, the combinational circuit 14 adds all the clock names A, B, and C to which the input signal is added to its output, thereby outputting the output signal. SIGNAL4
Create _ABC. From the description of FIG. 3, for example, B_B
In the LOCK, it can be determined that a signal is transferred between the A clock and the B clock.

Further, the rising timing of the A clock pulse and the rising timing of the B clock pulse may not be uniquely determined and may fluctuate, so that the change point of the input signal of the flip-flop of the B block may substantially coincide with the timing of the B clock pulse. At some point, it can be determined that a setup or hold error has occurred. Therefore, by adding a clock name to a signal name, a setup and hold error can be easily detected from phase information between clocks and a circuit description.

[0015]

According to the present invention, in a description of a synchronous circuit in a description language, a clock name based on which the signal was created is automatically or manually added to a created signal name. By looking at the circuit description and the phase information between clocks, the setup and hold errors at the time of signal transfer between certain clocks are
It is possible to make an immediate judgment, thereby speeding up the design and reducing the probability of occurrence of design defects.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a clock specifying method according to the present invention.

FIG. 2 is a block diagram showing a synchronous circuit using a flip-flop.

FIG. 3 is an example of VHDL describing the synchronous circuit.

[Explanation of symbols]

 11 Flip-flop A 12 Flip-flop B 13 Flip-flop C 14 OR circuit

Claims (1)

[Claims] When a synchronous circuit is described in a hardware description language, a clock name based on the generation of the signal is added to a generated signal name. Explicit method.