JP2002162950A - Display driver IC - Google Patents

Abstract

(57) [Problem] To provide a display driver IC with a built-in RAM capable of suppressing an increase in power consumption even when the total number of memories in a column direction increases. SOLUTION: A main read line MR shared by a plurality of memory cells M11 to Mn1 arranged along a column direction and transmitting display data read from one memory cell sequentially selected in the column direction is provided. Have. The plurality of memory cells are divided by a predetermined number in the column direction and a plurality of blocks B
1 to B35 are formed. The plurality of blocks B1 to B
35, one of the sub read lines SR1 to SR35
A book is provided, and display data read from one memory cell in each block is transmitted via a sub read line. A plurality of main switches MSW1 to MSW35 for selectively connecting one of the plurality of sub read lines SR1 to SR35 to the main read line MR are provided. Each of the memory cells in each block is provided with one of sub-switches SSW1 to SSW8, and one of them is selectively connected to a corresponding one of the sub-read lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a display driver IC for driving a display unit such as a liquid crystal display panel, and more particularly to a display driver IC having a built-in RAM having a readout port for display.

[0002]

2. Description of the Related Art In a RAM built-in driver of this type, a data read line for driving a display unit, for example, a liquid crystal display panel is a bit line pair for reading and writing data with an MPU. And is provided separately.

FIG. 7 shows a display read line O commonly connected to a plurality of memory cells M11 to Mn1 arranged in the column direction.
4 shows an LCD.

Although not shown in FIG. 7, the memory cell M1
A switch (for example, a P-type MOS transistor) that is alternatively connected to the display read line OLCD is provided in 1 to Mn1.

[0005] One end of the display read line OLCD is connected to an N-type MOS transistor Tr for precharging the display read line OLCD to, for example, a LOW potential before reading data.

In recent years, with the miniaturization of the semiconductor process, it has become possible to manufacture a RAM having a large memory capacity. At this time, the number n of the memory cells arranged in the column direction in FIG. 7 also increases.

As a result, the total length of the display read line OLCD is increased, and the parasitic resistance and the parasitic capacitance are increased. Also,
The number of memory cells (specifically, the above-described P-type MOS transistors) connected to the display read line OLCD increases,
This is the load capacity.

As described above, when the load on the readout line for display increases, the transistor for precharge Tr also needs to have a high current driving capability, so that the power consumption during precharge increases and the precharge time also increases.

On the other hand, when the display data is read, a large precharge transistor also becomes a load.
The current drive capability of the output driver connected to the display read line OLCD must also be increased.

For this reason, as the memory capacity increases, RA
The power consumed by the M increases, and in particular, a large capacity of a memory built in a display driving IC used in a portable device that needs to be charged such as a mobile phone has been a problem.

Therefore, an object of the present invention is to provide a display driver I which can suppress an increase in power consumption when a memory has a large capacity.
C.

[0012]

A display driver IC according to the present invention comprises a plurality of memory cells arranged in a column direction and a plurality of display cells for sequentially selecting the plurality of memory cells in a column direction. A word line, a main read line shared by the plurality of memory cells, and transmitting display data read from one memory cell sequentially selected by the plurality of display word lines; and the plurality of memory cells. Are provided for each of a plurality of blocks divided by a predetermined number in the column direction, and a plurality of sub-reads each transmitting display data read from one memory cell in each of the plurality of blocks. A plurality of main switches selectively connecting the plurality of sub-read lines and the main read line; and a plurality of main switches provided in each of the plurality of memory cells. Are respectively selected by each of the plurality of display word lines, and having a plurality of sub-switches respectively connecting each of said plurality of memory cells in a corresponding one of the sub-read line.

In the display driver IC according to the present invention, the load connected to one main read line is one of the plurality of main switches, one sub read line connected to the main switch, and one of the main read lines. There are a plurality of sub-switches connected to the sub-read lines, and they are not dependent on the total number of memory cells in the column direction. Therefore, even if the memory capacity increases and the total number of memory cells in the column direction increases, the load on the main read line is significantly reduced as compared with the conventional case.

Also in the present invention, it is necessary to precharge the read path before the data read operation. Therefore, the precharge means may be connected to each of the plurality of sub read lines, or the precharge means may be connected to the main read line. Further, a precharge unit may be connected to each of the plurality of sub readout lines and the main readout line.

The plurality of display word lines are arranged for each of the plurality of blocks, and a plurality of main word lines for selecting one block, and one memory cell for selecting one block in the plurality of blocks in a column direction. And a plurality of sub-word lines.

In this case, one of a plurality of main word lines can be activated by an upper bit signal of an address signal for selecting a plurality of memory cells. Thereby, one of the plurality of main switches is turned on.

Further, one of the plurality of sub-word lines can be activated by the lower bit signal of the address signal. As a result, one of the plurality of sub-switches is turned on.

The pre-charging means may be configured to connect the main read line with the main read line within a period in which one of the plurality of main switches is turned on and before each period in which each of the plurality of sub switches is turned on one by one. , It is preferable to precharge both the corresponding sub-word lines. Thereby, the entire data read path can be precharged.

When the total number of the plurality of memory cells is 280 or more, the effect of the present invention can be further exhibited. If the total number of memories is equal to the above number, it is difficult to put the portable device into practical use in terms of power consumption if the conventional configuration is used.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a display driver I.
The RAM area included in C is schematically shown. In addition,
The display driver IC to which the present invention is applied includes, in addition to the RAM shown in FIG. 1, an interface with an external MPU, and an MPU that controls the RAM in accordance with a command from the MPU.
It can include a system control circuit, an LCD system control circuit for controlling a RAM for display such as a liquid crystal display, a driver unit for converting data read from the RAM to a voltage suitable for driving a display element such as a liquid crystal element, and the like. .

(Schematic Configuration of RAM) In FIG. 1, the number of display driver ICs is m in the row direction and n in the column direction.
A RAM having a total of m × n memory cells M11 to Mmn is built in. In this embodiment, n =
280, and has 280 memory cells in one column.

This column of 280 memory cells M11 to M
n1 is divided into 35 blocks B1 to B35 such that one block includes, for example, eight memory cells.

FIG. 1 mainly shows a configuration in which data is read out to a display unit, for example, a liquid crystal display unit.
The main read lines MR are arranged one by one along the column direction.

Each of the blocks B1 to B35 is provided with one sub read line SR1 to SR35. These sub read lines SR1 to SR35 are connected to one main read line MR via corresponding main switches MSW1 to MSW35.

These main switches MSW1 to MSW3
5 is a corresponding display main word line MW1 to MW35.
Is selectively driven on / off.

In each of the blocks B1 to B35, display sub word lines SW1 to SW8 for controlling connection of any one of eight memory cells are arranged on each of the sub read lines SR1 to SR35. I have.

Precharge transistors Tr1 to Tr35 are connected between each of the sub read lines SR1 to SR35 and a precharge power source, for example, the ground. This precharge transistor Tr
1 to Tr35 are the corresponding precharge signal lines PC1 to PC35.
It is turned on / off by the potential of PC35.

(Explanation of Memory Cell) Next, the memory cell will be described. Each of the memory cells M11 to Mmn has the same configuration, and one of them, the memory cell M11, is shown in FIG.

In FIG. 2, a memory cell M11 has a flip-flop 10 formed by connecting two inverters 12 and 14 in a loop. This flip flop 10 is connected to first and second word lines WL11 and WL12.
The first to fourth transistors 20, 22, 24, formed of, for example, N-type MOS transistors driven by
26, it is connected to a bit line pair BM, / BM and a bit line pair BS, / BS.

Here, the first and second word lines WL11, WL11,
WL12 is a memory cell of the first row shown in FIG.
M12,... Are shared by M1m. These first and second word lines are provided corresponding to each of the memory cells M11 to Mn1 of each row, and these are connected to the first word lines WL11 and W11.
L21,... WLn1 and second word lines WL12, WL
22,... WLn2.

Then, the first word lines WL11, WL2
By selecting one out of 1,... WLn1, a memory cell in a certain row can be selected. By selecting one of the second word lines WL12, WL22,... WLn2 asynchronously with the selection operation, memory cells in other rows can be selected.

In FIG. 2, the first word line WL
11 is selected, the first and second transistors 20,
22 is turned on, and the flip-flop 10 becomes the bit line pair B
S, / BS. Therefore, the bit line pair BS, /
Data from the MPU can be written to the memory cell M11 via the BS.

In the three-port RAM shown in FIG. 1, another memory cell belonging to the same column as the memory cell M11 can be selected while the memory cell M11 is selected.

For example, the second word line WL2 in the second row
By selecting 2, the flip-flop 10 in the memory cell M21 is connected to the bit line pair BM, / BM. Thus, data can be read from the memory cell M21 via the bit line pair BM, / BM and output to the MPU.

Here, the bit line pair BM, / BM can be used exclusively for data reading, and the bit line pair BS, / BS can be used exclusively for data writing, or vice versa. However, not limited to this example, the bit line pair B
Both M and / BM and the pair of bit lines BS and / BS may be used for both data writing and data reading.

(Configuration for Reading Display Data) In this triple port RAM, in order to sequentially select the memory cells in each column along the column direction and read the display data to the display unit,
The above-described display main word lines MW1 to MW35 are provided, and display sub-word lines SW1 to SW8 are further provided in the blocks B1 to B35, respectively.

Here, before data is read from the main read line MR, one of the main read line MR and the selected sub read lines SR1 to SR8 is precharged to a predetermined potential. For this reason, in the present embodiment, the precharge transistors Tr1 to Tr1 shown in FIG.
It is precharged to a LOW potential by Tr35.
In FIG. 1, one precharge transistor is connected to each sub read line, but one precharge transistor may be provided for the main read line MR instead.

In order to supply HIGH data to the sub and main read lines precharged LOW in accordance with the potential held in the flip-flop 10, a transistor 28 formed of, for example, a P-type MOS transistor is used. , 29 are provided. This transistor 2
8, 29 are connected in series between the supply line of the power supply potential VDD and the sub readout line SR1 in FIG. 2, for example.

The gate of the transistor 28 is connected to the inverter 1
2 and the display sub-word line SW 1 is connected to the gate of the transistor 29.

Therefore, for example, the display sub-word line SW1
Becomes low and the memory cell M11 is selected for display, the transistor 29 is turned on. At this time, if the output of the inverter 12 is LOW, the transistor 28 is also turned on, so that the sub read line SR1 that has been precharged to LOW is charged to the VDD potential and HIGH is read. Conversely, the inverter 12
Is high, the transistor 28 is turned off, so that LOW is read without changing the potential of the sub read line SR1 that has been precharged LOW.

The transistor 29 is connected to the main switches MSW1 to MSW35 shown in FIG.
Called W1. Each of the blocks B1 to B35 has a sub-switch SSW1 to SSW8 corresponding to the number of memory cells.
Will be arranged.

(Display Data Read Operation) In a read operation for display, one line data of the display section is sequentially read from the RAM by sequentially selecting a plurality of memory cells in the same row along the column direction. It is. This operation is illustrated in FIG.
This will be described with reference to FIG.

First, the block B1 is selected by setting the potential of the display main word line MW1 to HIGH. The potential of the display main word line MW1 is changed from the first line to the first line.
It rises from LOW to HIGH based on the common upper bits of each address signal that specifies the memory cell on the eighth line. As a result, all the main switches MSW1 in the block B1 are turned on, and each main read line MR
Are connected to the sub read line SR1 in the block B1.

During the period in which the block B1 is selected, as shown in FIG.
Reading of display data from the memory cells located in each of the eighth rows is performed for each line.

Here, data is read from the memory cells located on each line by a plurality of display sub-word lines S by the lower bit signal of the above-mentioned address signal.
W1 to SW8 are activated one by one (in this embodiment, LOW
Active). As a result, one of the plurality of sub-switches SSW1 to SSW8 (the transistor 29 shown in FIG. 2) is sequentially turned on. Thereby, as described above, data in the memory cell is read via the corresponding sub read line SR and main read line MR.

Prior to reading out the display data, it is necessary to precharge the readout line.

Therefore, the precharge signal line PC1 for driving all the precharge transistors Tr1 in the block B1 is in the period in which the main switch MSW1 is turned on (selection period of the block B1) and in the sub switch SSW1. ＳSSW8 is activated (HIGH active) before each period in which it is turned on one by one (see FIG. 3).

In each precharge period, both the main read line MR and the corresponding sub read line SR1 are precharged.

Hereinafter, the operation during the selection of the block B1 will be described.
What is necessary is just to carry out repeatedly, every time the blocks B2 to B35 are selected.

(Regarding the Effect of Reducing Power Consumption) In the present embodiment, one of the main switches MSW1 to MSW35 is connected to the display main read line MR.
Sub readout line S corresponding to the selected main switch
R1 to SR35 and eight sub-switches sSSW1-SS connected to the one display sub-readout line.
W8 and a precharge transistor Tr1. These connection targets are the same even if the total number n of the memory cells in the column direction increases, and the wiring length is extended.

On the other hand, the display read line OLC shown in FIG.
D includes a total of n P-type Ms in a total of n memory cells.
OS transistor and precharge transistor Tr
And the number of loads increases depending on the total number n.

Therefore, the main readout line MR for display of the present embodiment has a longer overall length (longer by the connection of the sub readout lines), but has a higher load than the display readout line OLCD of FIG. It is clear that the capacity is greatly reduced.

Therefore, it is clear that the precharge transistor of the present embodiment requires a smaller current driving capability and a smaller size than the conventional precharge transistor shown in FIG.

This also reduces the load capacitance of the main display read line MR of the present embodiment, shortens the precharge time, and reduces power consumption during precharge. Further, the display main read line MR
In this case, the output driver connected to the power supply also has a low current driving capability, so that the power consumption is also reduced here.

(Explanation of Modification) FIG. 4 shows a modification in which a precharge transistor TrMR is added to one end of all the main read lines MR in FIG.

The plurality of precharge transistors T
A precharge signal line PC is commonly connected to the gate of the rMR. The same signal as the signal supplied to the precharge line PC1 is supplied to the precharge signal line PC when, for example, the block B1 is selected.
That is, when the block Bn (n is one of the selected block numbers 1 to 35) is selected, the same signal as the signal supplied to the precharge line PCn is supplied to the precharge signal line PC. Is done.

FIG. 5 is an operation waveform diagram when data is read from the memory having the structure of FIG. In FIG.
Only the case where blocks B1 and B2 are continuously selected is shown.

As shown in FIG. 5, in the precharge period before data is read from each line, all the precharge transistors Tr1 to Tr35 and TrMR are turned on, and all the main read lines MR and all the sub read lines MR are turned on. The read lines SR1 to SR35 are precharged.

At the time of data reading, the precharge of only the sub read lines of the selected block and all the main read lines MR used for data read are released, but the other sub read lines are precharged. Will remain. Therefore, while the block B1 is selected, HIGH is input to PC2 to PC3, and the sub read lines SR1 to SR35 remain precharged. However, once the charge reaches the precharge potential, there is no movement of electric charge, so that power consumption does not increase.

Instead of the precharge method shown in FIG. 5, the present invention may be implemented as shown in FIG. In FIG. 6, all the main / sub read lines MR and SR1 to SR35 are precharged only in the first precharge period in which the block is selected. At the time of the subsequent data read, the precharge operation of the sub read lines of the blocks other than the selected block is not performed. This is because the pre-charge is not required for the sub-read lines of the unselected blocks since there is no potential change after the pre-charge.

After the data read, only the sub read lines in the selected block and all the main read lines used for reading are precharged.

Also in this case, a precharge operation substantially similar to that of FIG. 5 can be performed.

It should be noted that the present invention is not limited to the above-described embodiment, but can be implemented in various modes within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a RAM area incorporated in a display driver IC according to an embodiment of the present invention, mainly illustrating a configuration of a data read system for display driving.

FIG. 2 is a circuit diagram of the memory cell shown in FIG. 1;

FIG. 3 is a timing chart illustrating a read operation of the RAM illustrated in FIG. 1;

FIG. 4 is a diagram showing a modification of FIG. 1;

FIG. 5 is a driving waveform diagram used for a precharge and data read operation in the memory shown in FIG. 4;

FIG. 6 is a waveform chart showing a modification of the waveform shown in FIG.

FIG. 7 is a schematic explanatory view showing a conventional connection between a memory cell in a column direction and a display read line.

[Explanation of symbols]

10 Flip flop 12, 14 Inverter 20, 22, 24, 26, 28, 29 Transistor M11, M12,... Mnm Memory cell BM, / BM Bit line pair BS, / BS Bit line pair WL11, WL21,. WLn2 WL22,... WLn2 Second word line MR Main read line SR1 to SR35 Sub read line B1 to B35 Block MSW1 to MSW35 Main switch SSW1 to SSW35 Subswitch Tr1 to Tr35, TrMR Precharge transistor OLCD Display Readout line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 631 G09G 3/20 631H 680 680G F-term (Reference) 2H093 NA41 NC09 NC11 ND39 5C006 BB16 BC03 BC06 BC12 BC20 BF06 BF09 BF27 BF34 EB05 FA47 5C080 AA10 BB05 DD25 DD26 FF11 JJ03 JJ04

Claims (8)

[Claims] A plurality of memory cells arranged along a column direction, a plurality of display word lines for sequentially selecting the plurality of memory cells along a column direction, shared by the plurality of memory cells, A main read line through which display data read from one memory cell sequentially selected by the plurality of display word lines is transmitted; and a plurality of memory cells divided into a predetermined number in the column direction. A plurality of sub-read lines provided one by one for each of the blocks, and each of which transmits display data read from one memory cell in each of the plurality of blocks; the plurality of sub-read lines and the main read A plurality of main switches for selectively connecting lines; and a plurality of main switches provided in each of the plurality of memory cells, each of the plurality of display word lines being provided by each of the plurality of display word lines. Is-option, the display driver IC and having a plurality of sub-switches respectively connecting each of said plurality of memory cells in a corresponding one of the sub-read line. 2. The display driver IC according to claim 1, wherein a precharge means for precharging a read path before a read operation is connected to each of the plurality of sub read lines. 3. The display driver IC according to claim 1, further comprising a precharge unit connected to the main read line and precharging a read path before a read operation. 4. The plurality of display word lines according to claim 1, wherein the plurality of display word lines are arranged for each of the plurality of blocks to select one block; And a plurality of sub-word lines for selecting one memory cell in the column direction within the display driver IC. 5. The one of the plurality of main word lines according to claim 4, wherein an upper bit signal of an address signal for selecting the plurality of memory cells is used.
A display driver IC wherein a book is activated and one of the plurality of main switches is turned on. 6. The device according to claim 5, wherein one of the plurality of sub-word lines is activated by a lower bit signal of the address signal, and one of the plurality of sub-switches is turned on. Display driver IC. 7. The precharge means according to claim 2, wherein the precharge means is turned on one by one of the plurality of sub switches during a period in which one of the plurality of main switches is turned on. A display driver IC that precharges both the main read line and a corresponding sub-word line before each period. 8. The display driver IC according to claim 1, wherein the total number of the plurality of memory cells is 280 or more.