JP2002124950A - Memory control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FIFO memory control circuit which can protect the writing and reading control of an FIFO memory from being transferred or put into incorrect operation sequence by incorrect data inputted by the influence of a transient state of a device start-up, noises, etc. SOLUTION: A WENB generating unit 3 generates a WENB signal and practices the write control of an FIFO memory unit 1. If an SOC-IN signal is detected once, even if the next SOC-IN signal is detected before 53 counts, '0' is not loaded on a counter. The WENB generating unit 3 also controls an SOC mask unit 6 so as not to write an incorrect SOC signal in the FIFO memory unit 1. This control is practiced during a period from the detection of the SOC-IN signal till the count reaches 53 by masking the inputted SOC-IN signal so as to have a level 'L' by the SOC mask unit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO memory control circuit, and more particularly to an ATM (Asynchronous) circuit.
Transfer Mode (Asynchronous Transfer Mode) When transferring cells between different blocks, UTOPIA (Un
versal Test and Operational
n PHY Interface for ATM)
FIFO (First-Interface) such as I / F (interface)
The present invention relates to write control to a FIFO memory in a circuit that uses an In First-Out memory.

[0002]

2. Description of the Related Art In many cases, an ATM cell is transferred between different blocks via a FIFO memory.
This is because ATM is an asynchronous transfer.
This is because speed conversion can be easily performed by using the FO memory. UTO recommended by ATM Forum
The PIA I / F also uses a FIFO memory and is widely used for ATM cell transfer.

FIG. 7 shows a configuration around the FIFO memory. This configuration example has five processing blocks, ie, FIFO
Memory unit 1, UTOPIA I / F unit 2, and WENB
(Write Enable) generation unit 7 and RENB
(Read Enable) generation unit 4 and timing adjustment unit 5.

[0004] The FIFO memory unit 1 has a UTOPIA I /
F stores ATM cells in accordance with the control state of F
The PIA I / F unit 2 converts the data read from the FIFO memory unit 1 into a UTOPIA I / F.

[0005] The WENB generation unit 7 controls the writing of data to be written to the FIFO memory unit 1, and the RENB generation unit 4 controls the reading of data read from the FIFO memory unit 1. The timing adjustment unit 5 adjusts the phase of data to be written in the FIFO memory unit 1.

[0006] The WENB generation unit 7 generates an S-R F /
F (S-R flip-flop) and 53 counter, and the S-R F / F is connected to the SOC (Star).
tOf Cell: Indicates the beginning of the ATM cell) "L" Set (low level set) by the -IN signal input, and "H" after 53 counts from the SOC-IN signal input
Set (high level set).

[0007] The S-RF / F output is used as a WENB signal, and WSOC (write SOC) and WDATA (write data) are written to the FIFO memory unit 1 in the "L" section. However, assuming that ATM cells are transferred without interruption,
"H" Set after 53 counts and ATM input next
When the SOC-IN inputs of the cells occur simultaneously, WE
“L” Set of the NB signal output is prioritized.

The timing adjusting unit 5 receives the input S
The phases of the OC-IN signal and the DATA-IN signal are adjusted according to the output timing of the WENB signal, and
It has a function of outputting as an OC signal and a WDATA signal, and has several stages of DF / F (D-type flip-flop).
It is composed of

Incidentally, in the conventional configuration example shown in FIG.
The TM cell is 8-byte parallel data, and is input as a DATA-IN signal one byte at a time per 1 CLK (clock). The SOC-IN signal is a signal which becomes "H" for 1 CLK width in the first byte of the ATM cell. It is assumed that

[0010]

The above-mentioned conventional FIF
In the write control to the O memory, the SOC-I other than the head of the ATM cell is added due to the influence of the transient state at the start of the device and noise.
When the N signal is input, it is expected that a circuit or a device transitions or enters an incorrect operation sequence.

The cause of this problem is WEN
The first method that the B generation unit 7 has in the method of generating the WENB signal.
Of the ATM cell or by mistake
When the C-IN signal is input, the illegal WSOC signal is also written to the FIFO memory unit 1.
There are factors.

The first factor is a problem in the circuit configuration that loads (loads) "0" to the 53 counter in the WENB generation unit 7 every time the SOC-IN signal is input.
This causes data to be written in units of 53 bytes or more when the C signal is input.

FIG. 8 is a timing chart in the case where data of 53 bytes or more is written. In the conventional write control, an illegal SOC12 signal or an SOC13 signal input during the writing of the ATM cell g is
Each time an input is made, "0" is loaded into the 53 counter. Therefore, the end of 53 count is determined by the SOC13 signal from “5
3 ”counted position (53th count position), AT
A portion exceeding the data of the M cell g is also written into the FIFO memory unit 1.

The extra written illegal data is stored in the FIFO
This is a hindrance when data is simply read in units of 53 bytes on the read side of the O memory unit 1 and causes a problem that data cannot be read in units of written ATM cells. Since this state does not recover spontaneously, it is expected that a reset of the FIFO memory unit 1 or a complicated recovery circuit will be required.

The second factor is that, when an SOC-IN signal is erroneously input at a position other than the head of an ATM cell, the incorrect WSOC signal is also written to the FIFO memory unit 1. The SOC signal indicating the beginning of the ATM cell is
VPI (Virtual Path Identifier)
er) and VCI (Virtual Channel Id)
This is an important signal that is often used to detect the value of the “entifier” (indicating the routing information of the ATM cell). Reading and transferring an incorrect SOC signal as it is causes a malfunction of the next block circuit and causes a malfunction. ATM
It is also conceivable that cell transfer may be adversely affected.

Accordingly, an object of the present invention is to solve the above-mentioned problem, and to control the writing and reading of the FIFO memory to an erroneous operation sequence due to a transient state at the start of the apparatus or incorrect data input due to the influence of noise or the like. Another object of the present invention is to provide a FIFO memory control circuit which can prevent the memory from getting stuck.

[0017]

According to the FIFO memory control circuit of the present invention, when a cell in the asynchronous transfer mode is transferred between different blocks, an SOC (S) indicating the head of the cell is transferred.
A memory control circuit that writes data to a memory in response to detection of a signal of "start of cell", and has a function of always writing data to the memory in units of one cell counted from the detection of the SOC signal. .

Another FIFO memory control circuit according to the present invention has, in addition to the above functions, a mask function for invalidating the SOC signal input erroneously during the write operation to the memory.

That is, the FIFO memory control circuit of the present invention uses an ATM (Asynchronous Trans).
fer Mode: Asynchronous transfer mode) Even when a SOC (Start Of Cell: indicating the beginning of an ATM cell) -IN signal is input in addition to the head of the cell, the FIF
Control is performed such that data is always written to an O (First-In First-Out) memory in units of 53 bytes (in units of one cell).

More specifically, the FIFO memory control circuit of the present invention comprises: a FIFO memory; a control means for always writing data in units of 53 bytes to the FIFO memory;
Means for masking an SOC-IN signal located at a position other than the head of data in byte units as an incorrect SOC signal.

With the above-described configuration, the FIFO memory control circuit of the present invention controls data writing to the FIFO memory in 53-byte units at all times. In the FI
On the read side of the FO memory, it is only necessary to always take out data in units of 53 bytes, and complicated read control is not required.

Also, the head of the read data must be SO
Since the illegal SOC signal other than the data head is masked so that the C signal is located, UTOPIA (Universal) is used.
sal Test and Operation PH
Y Interface for ATM) I / F
Unauthorized data that causes a malfunction to the next block connected via (Interface) is not transmitted.

Therefore, according to the present invention, the write and read control of the FIFO memory used in the UTOPIA I / F or the like transits to an erroneous operation sequence due to a transient state at the start of the apparatus or incorrect data input due to the influence of noise or the like. It is possible to prevent getting stuck.

This also controls not to send illegal data to the next block connected via the UTOPIA I / F, and prevents malfunction of the next block. The illegal data defined here is a FIFO
In the data of 53 bytes read from the memory,
The data at the beginning of which no SOC signal is located are shown.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a FIFO memory control circuit according to one embodiment of the present invention. In FIG. 1, a FIFO memory control circuit according to one embodiment of the present invention includes six processing blocks, namely, a FIFO memory unit 1, a UTOPIA I / F unit 2, and a WENB.
(Write Enable) generation unit 3 and RENB
(Read Enable) generation unit 4, timing adjustment unit 5, and SOC mask unit 6. That is, in the embodiment of the present invention, the SOC mask unit 6 is added,
The configuration is the same as the conventional technology shown in FIG. 7 except that a function for controlling the SOC mask unit 6 is added to the WENB generation unit 3.

The FIFO memory unit 1 has a UTOPIA I /
F stores ATM cells in accordance with the control state of F
The PIA I / F unit 2 converts the data read from the FIFO memory unit 1 into a UTOPIA I / F.

The WENB generation unit 3 controls the writing of data to be written to the FIFO memory unit 1, and the RENB generation unit 4 controls the reading of data read from the FIFO memory unit 1. The timing adjustment unit 5 adjusts the phase of data to be written in the FIFO memory unit 1. The SOC mask unit 6 masks the SOC-IN signal as needed.

The WENB generation unit 3 generates a WENB signal and controls writing to the FIFO memory unit 1 in the same manner as in the prior art. The WENB generation unit 3 performs S-RF
/ F (SR flip-flop) and the 53 counter are the same as those in the prior art. The SOC-IN signal input sets the WENB signal to "L" Set (low level set), and the 53 count counts the WENB signal. To “H” Set
(High level set). However, once the SOC-IN signal is detected, the circuit configuration does not load "0" into the counter even if the next SOC-IN signal is detected 53 counts before.

Further, the WENB generation unit 3 also controls the SOC mask unit 6 so as not to write an incorrect SOC signal to the FIFO memory unit 1. This control is based on SOC-
This is performed during the period of counting “53” from the detection of the IN signal, and is performed by masking the input SOC-IN signal to “L” by the SOC mask unit 6.

FIG. 2 is a timing chart showing the operation of the FIFO memory control circuit according to one embodiment of the present invention.
Hereinafter, the signals shown in FIG. 2 are the SOC-IN signal and the DATA
The case where the signal is input to the −IN signal will be described.

When the ATM cell a in which the SOC1 signal is located at the top is input as the SOC-IN signal and the DATA-IN signal, the WENB generator 3 sets the WENB signal to "L" upon detection of the SOC1 signal, and counts 53 counts. Start. Since the SOC1 signal and the ATM cell a are written into the FIFO memory unit 1 during the "L" section of the WENB signal, the phase adjustment with the WENB signal is performed by the timing adjustment unit 6 and output to the FIFO memory unit 1.

When an ATM cell b starting with the SOC2 signal is input successively to the ATM cell a, an "H" Set of the WENB signal at the end of 53 counts and an "L" Set by the detection of the SOC2 signal. Happen simultaneously. WENB
Since “L” Set has priority inside the generation unit 3, WE
The NB signal continuously controls the writing of the SOC2 signal and the ATM cell b while keeping the "L" output.

However, the SOC3 signal and the SOC4 signal input during the writing of the ATM cell b are the SOC signals input during the 53 counts counted from the SOC2 signal. Is not used for the load signal for setting “0” to “0”.

The SOC3 signal and the SOC4 signal are W
The mask is masked in the SOC mask unit 6 in accordance with the control signal from the ENB generation unit 3, so that the FIFO memory unit 1
Not written to. Since the end of the ATM cell b is at the position where the 53 counter in the WENB generation unit 3 has finished counting "53", the WE is output at the timing when the 53 count ends.
The NB signal is set to "H", and the writing of the ATM cell b is completed.

The control of the ATM cell c is performed in the same manner as the above-described ATM cell a and ATM cell b.
A series of write control for starting writing after detection of five signals is continued.

FIG. 3 shows a normal A in one embodiment of the present invention.
9 is a timing chart illustrating an operation when an incorrect SOC6 signal and an incorrect SOC7 signal are input before a TM cell d is input.

In the FIFO memory control circuit according to one embodiment of the present invention, the generation of the WENB signal cannot be started with the normal SOC8 signal, and
The WENB signal is generated by the C6 signal.

Further, for convenience, the WENB generation unit 3
Since the C7 signal and the SOC8 signal are processed as illegal SOC signals and mask control is also performed, the ATM cell d is FIFO-based.
Writing to the memory unit 1 cannot be performed normally. However, the only ATM cell that cannot be normally written is the ATM cell d immediately after the illegal data, and the normal write control can be normally performed on the next normal SOC9 signal and the ATM cell e to be input. ing.

Since the write control of the illegal data is also performed in units of 53 bytes (one cell unit) in which the SOC signal is located at the head, the read control for the FIFO memory unit 1 can always be performed in units of 53 bytes. Has become.

FIG. 4 is a diagram showing a circuit configuration of the WENB generation unit 3, the timing adjustment unit 5, and the SOC mask unit 6 in FIG. In FIG. 4, the WENB generation unit 3 includes an AND circuit 3
1, 42, 43 and inverters 32, 35, 38 to 41
And an S-RF / F (SR flip-flop) 33,
An OR circuit 34 and counter circuits 36 and 37 are provided.

The timing adjusting section 5 is composed of DF / Fs (D-type flip-flops) 51 and 52, and the SOC masking section 6 includes an inverter 61, AND circuits 62 and 64,
And an S-RF / F (SR flip-flop) 63.

In the above circuit configuration, CLK is an arbitrary clock, RST is an "L" reset signal, and two counter circuits are used as the 53 counter. Further, the S-RF / F3 shown in FIG.
The operations of 3 and 63 are as shown in the truth table shown in FIG.

The signal 101 outputs "H" at the time of counting 53 (when counting from "0", the value becomes "52"), and is used for the "H" Set of the WENB signal. At the time of 52 counts (when counting from “0”, the value becomes “51”), “H” is output and used for “H” Set of the signal 103 for masking an incorrect SOC signal.

FIG. 6 is a timing chart showing the operation when the circuit configuration shown in FIG. 4 is used. When an incorrect SOC signal is input, the signal 10 shown in FIG.
3 shows a state in which the signal is masked by the “L” section and is not output as a WSOC signal.

As described above, the ATM cell writing to the FIFO memory unit 1 is controlled by the WENB generation unit 3 and the SOC mask unit 6 so that the ATM cell writing is always performed in units of 53 bytes (one cell unit). ATM
When reading a cell, incorrect data is stored in the FIFO memory unit 1
, It is only necessary to always take out 53 bytes at a time, and complicated read control is not required.

In addition, the write and read control of the FIFO memory unit 1 is prevented from transitioning into an erroneous operation sequence or being stuck due to incorrect data input due to a transient state at the start of the apparatus or the influence of noise or the like. be able to. In this case, only a small number of control circuits are required, and the circuit scale does not increase.

[0047]

As described above, according to the present invention, when a cell in the asynchronous transfer mode is transferred between different blocks, writing to the memory is performed in response to the detection of the SOC signal indicating the head of the cell. In the memory control circuit, the data writing to the memory is always performed in units of one cell (53 byte unit) counted from the detection of the SOC signal, so that the writing and reading control of the FIFO memory can be performed in a transient state at the start of the apparatus or noise. There is an effect that it is possible to prevent transition or intrusion into an erroneous operation sequence due to illegal data input due to the influence.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a FIFO memory control circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the FIFO memory control circuit according to one embodiment of the present invention.

FIG. 3 is a timing chart showing an operation when an incorrect SOC signal is input before a normal ATM cell is input in one embodiment of the present invention.

FIG. 4 is a diagram showing a WENB generation unit, a timing adjustment unit, and S in FIG. 1;
FIG. 3 is a diagram illustrating a circuit configuration with an OC mask unit.

FIG. 5 is a diagram showing a truth table representing an operation of the S-RF / F in FIG. 4;

6 is a timing chart showing an operation when the circuit configuration shown in FIG. 4 is used.

FIG. 7 is a block diagram illustrating a configuration example of a conventional FIFO memory control circuit.

FIG. 8 is a timing chart showing an operation of a conventional FIFO memory control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 FIFO memory part 2 UTOPIA I / F part 3 WENB generation part 4 RENB generation part 5 Timing adjustment part 6 SOC mask part 31,42,43,62,64 AND circuit 32,35,38-41,61 Inverter 33,63 S-RF / F 34 OR circuit 36, 37 Counter circuit 51, 52 DF / F

Claims (3)

[Claims] When transferring a cell in an asynchronous transfer mode between different blocks, an SOC (St) indicating the head of the cell is transferred.
art control circuit for writing data to a memory in response to detection of an "art of cell" signal, the memory control circuit having a function of always writing data to the memory in units of one cell counted from the detection of the SOC signal. Characteristic memory control circuit. 2. When transferring the cell, UTOPIA is used.
[Universal Test and Opera
Tion PHY Interface for AT
M (Asynchronous Transfer M)
mode) interface FIFO (First-In)
2. The memory control circuit according to claim 1, wherein a first-out (First-Out) memory is used. 3. A memory control circuit comprising a mask function for invalidating the SOC signal input erroneously during a write operation to the memory.