JP2002246339A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To easily thin a semiconductor substrate into a mirror-finished state. SOLUTION: When a thin film which is difficult to process by the plasma CVM method, for example, an Au film is formed on a main surface or a back surface of a semiconductor substrate 2, the semiconductor substrate 2 is mechanically polished by a grinding wheel 1 to form the semiconductor substrate. After the Si is exposed, processing by the plasma CVM method using the etching gas 4 and the inert gas 5 in a radical state is performed. When processing the semiconductor substrate 2 from the main surface side, the processing by the plasma CVM method and the mechanical polishing by the grinding wheel 1 are combined to uniformly process the interlayer insulating film and the wiring having different etching rates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor device in which a semiconductor substrate is thinned by a polishing method.

[0002]

2. Description of the Related Art In recent years, multilayer wiring and miniaturization of LSIs have been advanced, and it has become difficult to analyze the causes of failure when various failures occur. Therefore, in a semiconductor chip on which the LSI is formed, a method of analyzing a semiconductor element and a lower layer wiring from a back surface thereof has attracted attention.

[0003] For example, Japanese Patent Application Laid-Open No. H11-287840 discloses a failure analysis device capable of analyzing a semiconductor chip from the back surface. This device has a configuration in which a semiconductor chip is mounted on a substrate for backside analysis in a flip-chip manner, a probe is applied to electrodes provided around the substrate to drive an integrated circuit, and abnormalities are detected from the backside of the semiconductor chip. ing. In addition, the backside analysis substrate is provided with a plurality of dimensionally standardized electrodes in the peripheral area so that it can be connected to probe cards and packages, so that the same probe card can be used to probe semiconductor chips with different dimensions. It is configured.

Japanese Patent Application Laid-Open No. H11-111759 discloses a faulty integrated circuit assembly capable of performing both a back surface analysis and a front surface analysis on an LSI chip assembled in a package. This assembly uses a TAB tape having both sides of a power supply, a ground, and a wiring pattern necessary for applying a signal necessary for analysis of an LSI, and a pad for making an electrical connection with a socket. It is assembled and attached to a socket having a pogo pin for applying the TCP to the pad.
The LSI chip is mounted face-up on the socket when performing the front surface analysis, and mounted face-down on the socket when performing the back surface analysis.

In order to analyze a semiconductor chip from the back side, it is necessary to reduce the thickness of a semiconductor substrate on which wirings are formed in multiple layers to a thickness that enables failure analysis. Further, at the time of analysis, the analysis is performed by observation using a microscope, so that the semiconductor substrate needs to be thinned in a mirror-like state in order to prevent irregular reflection of light that hinders observation.

For example, LSI Testing Symposium 1
998 Proceedings (1998.11.5), "Study of Backside Fault Isolation by Thinning Silicon Chip", pre-processing of backside analysis, thinning of silicon substrate by polishing, EMMI (Emission Microscopy) analysis from backside, and E
There have been reports on B testing.

According to this report, a silicon substrate was thinned by polishing in order to improve the detection sensitivity of backside emission analysis, and the transmission characteristics and emission detection characteristics at each substrate thickness were examined. As a result, the silicon substrate was thinned to 15 μm. It has been found that, by the conversion, a transmittance of 50% or more for a wavelength of 500 nm to 1.2 μm can be obtained.

The above-mentioned thinning of the semiconductor substrate can be performed by, for example, a dimple polishing apparatus. This dimple polishing apparatus rotates a small disk around which a polishing cloth is wound, arranges a polishing surface of a sample (semiconductor chip) in a direction perpendicular to the rotation surface, and moves the sample in a direction parallel to the polishing surface. The semiconductor substrate is removed and processed in a semi-spherical shape by supplying paste-like abrasive grains between the small disk and the sample while rotating. Further, it is possible to make the semiconductor substrate a mirror-finished state by changing the polishing abrasive grains to finer ones according to the progress of the processing of the semiconductor substrate.

For another method for thinning a semiconductor substrate, see, for example, (a) November 20, 1997,
Published by Nikkan Kogyo Shimbun, “Semiconductor Manufacturing Equipment Glossary No. 4
Edition ", p240, (b) Journal of the Japan Society for Precision Engineering, Vol. 66,
No. 4, 2000, pages 517 to 522.

The above document (a) includes RIE (Reactive
There is a description of the processing technology by the Ion Etching) method. The RIE method utilizes reactive gas plasma, and etches (processes) a semiconductor substrate by a synergistic effect of a neutral active species and reactive gas ions. Also, in the above document (b), plasma CVM (Chemical
There is a description of processing technology by the Vaporization Machining method. In the plasma CVM method, an etching gas and an inert gas are supplied at a pressure higher than the atmospheric pressure, a plasma is generated by applying a VHF (Very High Frequency) high frequency to a rotating electrode, and neutral radicals of the generated etching gas are generated. And the atoms constituting the semiconductor substrate are chemically reacted with each other to etch (process) the reacted portion of the semiconductor substrate at a non-contact and high speed at an atomic level.

[0011]

However, the present inventors have found that the above-mentioned technology has the following problems.

That is, when a semiconductor substrate is polished (thinned) by a dimple polishing apparatus, the polishing abrasive grains are sequentially changed to finer ones according to the progress of the processing. There is a problem that the processing time and the finished state are different. That is, the skill for operating the dimple polishing apparatus is required. Further, since the processing area is determined by the diameter of the small disk used for polishing, there is a problem that the analyzable area obtained in a mirror state on the back surface of the semiconductor substrate is limited.
Therefore, when the analysis of semiconductor elements, wiring, and the like is performed in a state of a semiconductor wafer before being divided into individual semiconductor chips, it is difficult to polish the entire rear surface of the semiconductor substrate in a mirror state.

In the RIE method, a semiconductor substrate is thinned by irradiating an ionized etching gas to a portion to be processed. However, there is a problem that the ionized etching gas causes ion damage to a semiconductor element or the like in a portion to be processed, which makes analysis of the semiconductor element or the like difficult.

On the other hand, since the plasma CVM method is a processing method using an electrically neutral radical, the possibility of damaging a semiconductor element or the like is lower than that of the processing by the RIE method. However, since the plasma CVM method is a non-contact processing method, for example, when an Au film (gold) for improving solderability to a ceramic plate is provided on the back surface of a semiconductor substrate, the Au film is chemically treated. Since it is a very stable (low reactivity) material, there is a problem that processing becomes difficult.

When the surface (main surface) of the semiconductor substrate on which the multilayer wiring is formed is processed by the plasma CVM method,
In particular, when processing up to the intermediate layer where the wiring is formed, it is necessary to simultaneously process the interlayer insulating film and the wiring.
As a wiring material used for a semiconductor device, an aluminum wiring (Al wiring) containing Al (aluminum) as a main component and adding Cu (copper) and Si (silicon) is most common. In addition to the Al wiring, Cu wiring and W (tungsten) wiring are known. Then, for the purpose of preventing migration or the like, W or TiN (titanium nitride)
Is applied to the wiring as a barrier film. Further, since SiO ₂ (silicon oxide) or SiN (silicon nitride) is used as the interlayer insulating film, it is difficult to uniformly process the wiring, barrier film and interlayer insulating film made of these materials in a mirror-like state because of the difference in etching rate. There is a problem of difficulty. Further, even if an etching residue of a wiring or an interlayer insulating film is generated on the surface to be processed, the etching residue cannot be completely removed due to the non-contact processing, and it becomes difficult to obtain a mirror surface state that can be analyzed for failure. There is also a problem.

Further, in the plasma CVM apparatus described in the above document (b), a gap is controlled by irradiating a laser beam to a gap between a rotating electrode and a workpiece and making the transmission intensity constant. I have. However, this method
It is necessary to irradiate laser light at an angle close to parallel to the surface to be processed, and it is difficult to apply to a packaged semiconductor chip due to its structure.

Further, in the plasma CVM apparatus described in the above document (b), although the elevating table and the work table are illustrated, there is no description about setting and detection of the processing depth.

In general, a semiconductor wafer is warped due to a stress generated by a heat treatment at the time of forming a wiring or an insulating film. Similarly, in a packaged semiconductor chip, the lower surface of the package and the surface to be processed of the chip are not parallel. On the other hand, since the plasma CVM device described in the above document (b) is provided with a vacuum chuck, the warpage is somewhat improved by this. However, there is no description about the function of matching the parallelism between the processing surface of the rotating electrode and the processing surface.

An object of the present invention is to provide a technique capable of easily thinning a semiconductor substrate in a mirror state.

Another object of the present invention is to provide a technique capable of processing a wide area of a semiconductor substrate in a short time in a mirror-like state.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention relates to a semiconductor substrate having a semiconductor element or a wiring and an insulating film on its main surface.
A first member having a first member made of a conductive material and a second member made of abrasive grains fixed to an outer peripheral portion of the first member.
Performing a process using a tool to partially or completely thin the semiconductor substrate, wherein the step of thinning the semiconductor substrate includes supplying a process gas containing radicals to a surface to be polished of the semiconductor substrate. Etching a predetermined region of the surface to be polished, mechanically polishing the predetermined region of the surface to be polished while the second member is in contact with the surface to be polished, and the radical Under a situation where the semiconductor substrate is etched by supplying a process gas containing the same to the surface to be polished, a predetermined region of the surface to be polished is mechanically moved while the second member is in contact with the surface to be polished. It has two or more steps selected from the steps of polishing.

According to the present invention, there is provided a semiconductor device having a semiconductor element or a wiring and an insulating film on its main surface, a first member made of a conductive material and a polishing member fixed to an outer peripheral portion of the first member. Performing a process using a first tool having a second member made of abrasive grains to partially or completely thin the semiconductor substrate, wherein the step of thinning the semiconductor substrate includes a process including radicals A step of etching a predetermined region of the surface to be polished by supplying gas to the surface to be polished of the semiconductor substrate; and a step of etching the predetermined region of the surface to be polished while the second member is in contact with the surface to be polished. Mechanically polishing the semiconductor substrate, and contacting the second member with the surface to be polished under a condition in which the semiconductor substrate is etched by supplying a process gas containing the radical to the surface to be polished. And two or more steps selected from the steps of mechanically polishing a predetermined area of the surface to be polished in a state of being removed, and removing a residue generated by the etching or the mechanical polishing by the first tool. Is what you do.

The present invention also relates to a first semiconductor substrate having a semiconductor element or a wiring and an insulating film on its main surface.
A first member having a first member made of a conductive material and a second member made of abrasive grains fixed to an outer peripheral portion of the first member.
Performing a process using a tool to partially or completely thin the first semiconductor substrate; performing an inspection on the thinned first semiconductor substrate; 2) a step of thinning the first semiconductor substrate, wherein the step of thinning the first semiconductor substrate is performed by supplying a process gas containing radicals to the surface of the first semiconductor substrate. Etching a predetermined region, mechanically polishing a predetermined region of the surface to be polished while the second member is in contact with the surface to be polished, and polishing the process gas containing the radical to the surface to be polished In a step of mechanically polishing a predetermined region of the surface to be polished in a state where the second member is in contact with the surface to be polished under a situation where the first semiconductor substrate is etched by supplying the surface to the surface to be polished. Choice Have two or more steps which are those removed by the etching or the residual material caused by the mechanical polishing first tool.

The present invention also includes (a) a first member made of a conductive material and a second member made of abrasive grains fixed to an outer peripheral portion of the first member. A first tool to be mechanically polished; and (b) a first stage having a horizontal moving means and a second stage having a vertical moving means, and electrically connected to a ground potential. A stage, (c) a holding mechanism for holding the semiconductor substrate on the stage, (d) an observation mechanism having means for moving the semiconductor substrate in a vertical direction, and optically observing the semiconductor substrate; A process gas supply mechanism for supplying a process gas containing radicals between the tool and the surface to be polished at a pressure higher than the atmospheric pressure.

Further, the present invention includes (a) a first member made of a conductive material and a second member made of abrasive grains fixed to an outer peripheral portion of the first member, wherein a polished surface of the semiconductor substrate is formed. A first tool to be mechanically polished; and (b) a first stage having a horizontal moving means and a second stage having a vertical moving means, and electrically connected to a ground potential. A stage, (c) a holding mechanism for holding the semiconductor substrate on the stage, (d) an observation mechanism having means for moving the semiconductor substrate up and down and optically observing the semiconductor substrate, and (e) the first mechanism. A process gas supply mechanism for supplying a process gas containing radicals between the tool and the surface to be polished at a pressure higher than the atmospheric pressure, wherein the observation mechanism optically detects the position of the surface to be polished of the semiconductor substrate The amount of processing of the semiconductor substrate It is intended to.

Further, the present invention includes (a) a first member made of a conductive substance and a second member made of abrasive grains fixed to an outer peripheral portion of the first member, wherein a polished surface of the semiconductor substrate is formed. A first tool to be mechanically polished; and (b) a first stage having a horizontal moving means and a second stage having a vertical moving means, and electrically connected to a ground potential. A stage, (c) a holding mechanism for holding the semiconductor substrate on the stage, (d) an observation mechanism having means for moving the semiconductor substrate up and down and optically observing the semiconductor substrate, and (e) the first mechanism. A process gas supply mechanism for supplying a process gas containing radicals between the tool and the surface to be polished at a pressure higher than the atmospheric pressure, wherein the second stage section has a plurality of drive mechanisms, Mechanism to adjust the tilt of the stage. And the observation mechanism is for detecting the amount of machining said semiconductor substrate by detecting the position of the polished surface of the semiconductor substrate optically.

The present invention also includes (a) a first member made of a conductive substance and a second member made of abrasive grains fixed to an outer peripheral portion of the first member, wherein the back surface of the semiconductor substrate is mechanically fixed. A first tool for polishing the semiconductor substrate, and (b) a conductor pattern used for evaluating electrical characteristics of the semiconductor substrate, and a bump electrode for electrically connecting the conductor pattern and the semiconductor substrate. An optically transparent glass substrate fixed to the surface; and (c) a first stage having a horizontal moving means and a second stage having a vertical moving means, and electrically connected to a ground potential. And (d) a holding mechanism for fixing the glass substrate and holding the semiconductor substrate on the stage, and (e) optically observing the semiconductor substrate having a vertical moving means. Observation mechanism and ( ) A process gas containing radicals is intended to include a process gas supply mechanism for supplying a pressure above atmospheric pressure between the rear surface of the first tool the semiconductor substrate.

The present invention also includes (a) a first member made of a conductive material and a second member made of abrasive grains fixed to an outer peripheral portion of the first member, wherein the back surface of the semiconductor substrate is mechanically fixed. A first tool to be polished, and (b) a needle contact pad used for evaluation of electrical characteristics of the semiconductor substrate, a conductor pattern, and a bump electrode for electrically connecting the conductor pattern to the semiconductor substrate, An optically transparent glass substrate fixed to the main surface of the semiconductor substrate; and (c) a first stage unit having a horizontal moving unit and a second stage unit having a vertical moving unit, and grounded. A stage electrically connected to an electric potential, (d) a holding mechanism for fixing the glass substrate and holding the semiconductor substrate on the stage, and (e) a means for vertically moving the semiconductor substrate, To observe And (f) a process gas supply mechanism for supplying a process gas containing radicals at a pressure equal to or higher than the atmospheric pressure between the first tool and the back surface of the semiconductor substrate. And electrically connects the needle pad and the bump electrode.

According to the present invention, since the etching process by the radical of the chemically activated process gas and the mechanical polishing by the first tool are combined, the surface to be polished of the semiconductor substrate is formed. If a chemically stable material that is difficult to process by etching is formed, the first
After mechanically polishing with a tool and exposing the semiconductor substrate containing Si as a main component, the semiconductor substrate is processed by etching and mechanical polishing with the first tool,
The semiconductor substrate can be processed continuously irrespective of its layer structure.

Further, according to the present invention, since the residue generated by the etching process by the radical of the chemically activated process gas can be removed by the first tool, the semiconductor substrate can be removed in a mirror-finished state. Processing becomes possible.

Further, according to the present invention, since the processed surface of the semiconductor substrate can be locally optically observed, the observation mechanism is defocused at a plurality of observation positions on the processed surface of the semiconductor substrate. By comparing the amounts, it is possible to detect the inclination of the semiconductor substrate or the undulation occurring in the semiconductor substrate.

Further, according to the present invention, since the inclination or undulation of the semiconductor substrate to be processed can be detected, the stage on which the semiconductor substrate is mounted is driven based on the detection result, and the processed surface of the semiconductor substrate is processed. Makes it possible to perform processing at a uniform depth in the processing region of the semiconductor substrate.

Further, according to the present invention, since the processing surface of the semiconductor substrate can be optically observed, the processing depth can be detected from the movement amount of the observation mechanism for observing the processing surface before and after the processing. It is possible to do.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
1 is a configuration diagram of a semiconductor manufacturing apparatus of FIG. This semiconductor manufacturing apparatus employs a semiconductor substrate 2 (first processing) using processing by a plasma CVM method and mechanical polishing by a grinding wheel 1 (first tool).
(Semiconductor substrate) is processed (thinned). For example, even when a chemically stable Au film, which is difficult to process by the plasma CVM method described in the above-described conventional technique, is provided on the back surface of the semiconductor substrate 2, the Au film is mechanically polished. After the removal, the exposed Si substrate is thinned by a combined process of etching and mechanical polishing, so that the semiconductor substrate 2 can be continuously processed regardless of its layer structure.

For example, as shown in FIG. 2, an n-channel type M is formed on a main surface (semiconductor element formation surface) of Si.
ISFET (Metal Insulator Semiconductor Field Ef
fect Transistor) Qn, p-channel type MISFETQ
semiconductor substrate 2 on which p and wirings M1 to M7 are formed
From the back side to a predetermined position, or FIG.
As shown in FIG. 2, by thinning a semiconductor substrate 2 similar to the semiconductor substrate 2 shown in FIG. 2 from the main surface side to a predetermined position, the n-channel MISFET Qn, the p-channel MISFET Qp, the wirings M1 to M7, etc. It is possible to perform analysis. The amount of processing of the semiconductor substrate 2 and whether the thinning of the semiconductor substrate 2 is performed from the main surface side or the rear surface side are determined by the n-channel MISFET Qn,
It can be determined by analysis contents of the p-channel type MISFET Qp or the wirings M1 to M7. Also, n
Channel type MISFET Qn, p channel type MISFE
The semiconductor substrate 2 may be processed during the process of forming the TQp or the wirings M1 to M7.

When processing the semiconductor substrate 2 from the main surface side,
In particular, when processing up to the intermediate layer on which the wiring is formed, it is necessary to simultaneously process the interlayer insulating film and the wiring. In the first embodiment, the interlayer insulating film and the wiring are simultaneously processed by using the processing by the plasma CVM method and the mechanical polishing by the grinding wheel 1 at the same time. However, since it is difficult to obtain an etching gas having the same etching rate for the interlayer insulating film and the wiring, in the first embodiment, the interlayer insulating film having a larger removal volume than the wiring is mainly processed by the plasma CVM method. And the wiring is processed mainly by mechanical polishing with the grinding wheel 1.

Here, when both the interlayer insulating film and the wiring are simultaneously processed only by mechanical polishing by the grinding wheel 1,
From the viewpoint of the processing speed and the mirror surface processing, it is necessary to sequentially change from the grinding wheel 1 having large abrasive grains to the grinding wheel 1 having small abrasive grains in accordance with the progress of the processing, which is a complicated operation.
As described above, in the first embodiment, the grinding wheel 1
Since the object to be processed mainly by mechanical polishing is a wiring and an etching residue having a smaller removal volume than the interlayer insulating film, the grinding wheel 1 having a small abrasive grain can be used from the beginning of the processing. That is, according to the semiconductor manufacturing apparatus of the first embodiment, it is possible to uniformly process the interlayer insulating films and the wirings having different etching rates in a mirror state without reducing the processing speed.

In the semiconductor manufacturing apparatus shown in FIG.
The grinding wheel 1 is made of a conductive base metal 1A (first member) and polishing abrasive grains (diamond, alumina, Si
A grinding wheel 1B (second member) made of C (silicon carbide), CBN (Cubic Boron Nitride, or a combination thereof), and a high frequency power supply 3 Is connected. The width of the grinding wheel 1 can be appropriately selected according to the processing area for the semiconductor substrate 2. That is, the semiconductor substrate 2 can be processed even in the state of the semiconductor wafer before being divided into individual semiconductor chips, and the semiconductor substrate 2 can be processed after being divided into individual semiconductor chips.
Since the grindstone 1B is porous and secures air permeability,
The process gas (etching gas 4 and inert gas 5) blown to the grinding wheel 1 can easily reach the base metal 1A. Further, since a high frequency voltage from the high frequency power supply 3 is applied to the base 1A, plasma of the process gas is easily generated. Further, since the grindstone 1B is porous and secures air permeability, the supply of the process gas in a radical state to the surface to be processed of the semiconductor substrate 2 and the removal of the etching residue generated in the portion to be processed are improved. can do.

FIGS. 4A to 4C show the grinding wheel 1 described above.
It is the side view and front view which expanded and showed.

Instead of making the grindstone 1B porous so as to secure air permeability, the surface (working surface) of the grindstone 1B is formed with grooves 6A or 4C as shown in FIGS. 4 (a) and 4 (b). A pit 6B as shown in FIG. Further, grooves 6A or pits 6B may be provided in the porous grinding wheel 1B. Thus, the process gas in the radical state can be more effectively supplied to the processing surface of the semiconductor substrate 2. Further, by scraping off the residue of the semiconductor substrate 2 generated by the etching with the groove 6A or the pit 6B, the residue can be more effectively removed from the processed surface.

The cylinder 7A shown in FIG.
Feed mechanism)_Two, CF_FourOr SF ₆Such as fluorine
Halogen compound or Cl_TwoOr XeCl_TwoSuch as
Etching gas mainly containing chlorine-based halogen compounds
4 and filled in a cylinder 7B (process gas supply machine).
He), N_TwoOr filled with an inert gas 5 such as Ar.
Have been packed. The cylinders 7A and 7B are each provided with a valve 8
A and 8B are connected to the pipes 9A and 9B. Piping
9A and 9B have nozzles 10A and 10B, respectively.
A process gas is provided from the nozzles 10A and 10B.
(Etching gas 4 and inert gas 5)
Is sprayed over the entire area in the width direction.

The above process gas is supplied to the grinding wheel 1 at a pressure higher than the atmospheric pressure. Base metal 1A from high frequency power supply 3
, A plasma is generated around the grinding wheel 1 by the supply of the process gas. Since the process gas is supplied at a pressure higher than the atmospheric pressure,
Plasma generated by application of a high-frequency voltage is more likely to be extinguished by colliding with molecules constituting the process gas, and the spatial spread is reduced. Therefore, it is possible to prevent ions in the plasma from being implanted into the semiconductor substrate 2. In other words, the n-channel MISFET Qn and the p-channel MIS due to the ions in the plasma being implanted into the semiconductor substrate 2
Variations in characteristics of the FET Qp and the wirings M1 to M7 can be prevented. Further, the process gas is supplied at a pressure higher than the atmospheric pressure, the collision frequency of the molecules constituting the process gas is high, and the etching probability of the highly reactive neutral radical of the etching gas 4 is high. The density of radicals is increased. As a result, it is possible to process the semiconductor substrate 2 at high speed while preventing changes in the characteristics of the n-channel MISFET Qn, the p-channel MISFET Qp, and the wirings M1 to M7. Further, the residue of the semiconductor substrate 2 etched by the process gas in a radical state is scraped off by the rotating porous grindstone 1B, and can be removed from the processed surface of the semiconductor substrate 2.

The hood 11 covering the grinding wheel 1 is provided to efficiently supply the process gas to the processing portion of the semiconductor substrate 2 without diffusing the process gas to the periphery. Further, the exhaust device 12 and the hood 11 are connected by an exhaust pipe 13, so that the gas generated by the etching reaction of the semiconductor substrate 2 and the excess process gas can be exhausted without diffusing to the periphery. Furthermore, even if the residue of the semiconductor substrate 2 that has been removed by etching remains on the processed surface of the semiconductor substrate 2, the residue can be discharged by the exhaust device 12 after being removed by the grinding wheel 1. Is the semiconductor substrate 2
Can be prevented from remaining on the processed surface. That is,
When the residue of the semiconductor substrate 2 remains on the processed surface of the semiconductor substrate 2, it is possible to prevent the mirror processing from being hindered.

The semiconductor substrate 2 to be processed is held by being attracted to the vacuum chuck 16 (holding mechanism). The vacuum chuck 16 is connected to a vacuum pump 15 by a pipe 14 and is grounded by an earth 17. Here, the semiconductor substrate 2 is thicker than the wiring layers formed on the main surface thereof in a multilayer structure. Therefore, when the semiconductor substrate 2 is processed from the back surface side of the semiconductor substrate 2, it is necessary to reinforce the mechanical strength. Alternatively, a glass plate or a metal plate may be attached to the main surface of the semiconductor substrate 2 on which the wiring layers are formed in multiple layers. When a metal plate is used, by selecting a ferromagnetic material such as Ni as the material of the metal plate, the semiconductor substrate 2 can be fixed using an electromagnetic chuck instead of the vacuum chuck. On the other hand, when a glass plate is attached, analysis can be performed while optically observing various patterns such as wiring through the glass plate.

Further, by providing a conductive pattern and solder bumps on the above-mentioned glass plate to form a glass substrate for analyzing the back surface, it is possible to analyze from the front surface and the back surface in the operating state. Hereinafter, the glass substrate for back surface analysis will be described.

As shown in FIG. 5A, the first embodiment
The glass substrate GS for back surface analysis of the above comprises an optically transparent glass substrate GS ₁ , a needle contact pad NP formed on the glass substrate GS ₁ , a solder bump B (bump electrode) corresponding to a pad of a semiconductor substrate to be analyzed, and It has a wiring L (conductor pattern) for connecting the solder bump B and the needle contact pad NP.

As shown in FIG. 5B, the solder bumps B on the rear surface analysis glass substrate GS having the structure shown in FIG.
And the pad P ₁ of the semiconductor substrate 2 are opposed to each other, and reflow is performed. As a result, the semiconductor substrate 2 is fixed to the back surface analysis glass substrate GS, and power can be supplied to the semiconductor substrate 2 and signals can be transmitted and received through the needle contact pads NP.
Thereafter, by performing the combined processing of the etching and the mechanical polishing of the first embodiment described above, a back surface analysis sample can be prepared.

As described above, by using the above-described glass substrate GS for back surface analysis, it is possible to obtain optical information from the main surface (element formation surface) of the semiconductor substrate 2 as necessary in various energized states. Becomes

[0052] In the above configuration backside analysis glass substrate GS, by imparting an antireflection film on both surfaces of the glass substrate GS _1, it is possible to perform clearer light microscopic observation. Further, for example, when the sample fixed to the back surface analysis glass substrate GS is a BGA (Ball Grid Array) and the above-described solder bump B is formed on the BGA, the solder bump B corresponding to the solder bump B on the glass substrate GS ₁ is used. By forming a solder pad at a position and electrically connecting the solder pad and the above-mentioned needle pad NP with a wiring L made of a light-transmitting conductive material such as tin oxide or indium oxide, Glass substrate GS for backside analysis
It is possible to secure a light microscopic observation area through. In addition,
In the configuration shown in FIG. 5, the case where the solder bumps B are formed is illustrated, but a conductive paste having, for example, Ag (silver) or Cu (copper) may be used instead of the solder bumps B.

The stage 18 on which the semiconductor substrate 2 held by the vacuum chuck 16 (see FIG. 1) is mounted is an XY stage 19 (first stage section) that can move in the horizontal direction.
And a tilt stage 20 (second stage section) including three drive mechanisms 20A to 20C. By expanding and contracting the three drive mechanisms 20A to 20C by an arbitrary amount,
The stage 18 can be inclined at an arbitrary angle. In addition, by expanding and contracting the three drive mechanisms 20A to 20C by the same amount, the stage 18 can be moved in the vertical direction without tilting.

The optical system 21 (observation mechanism) includes the semiconductor substrate 2
The objective lens 22, the illumination light source 23, and the camera 24 are for detecting and observing the processing amount of the (sample).
Having. The camera 24 and the camera controller 25 are used to image the processed surface of the semiconductor substrate 2, and the imaged processed surface of the semiconductor substrate 2 is displayed on a monitor 26. The driving mechanism 27 (moving means in the up-down direction) is used to move the optical system 21 in the up-down direction, and the encoder 28 can detect the moving amount of the optical system 21 in the up-down direction.

Next, a method of detecting and observing the processing amount of the semiconductor substrate 2 by the optical system 21 will be described with reference to FIGS.

When the optical system 21 shown in FIG. 1 is illustrated in more detail, the configuration shown in FIG. 6A can be exemplified.

In the configuration shown in FIG. 6A, the illumination unit 30 has an illumination light source 23 and a half mirror 31. The illumination light 32 emitted from the illumination light source 23 is
After the optical path is bent by the half mirror 31 and condensed by the objective lens 22, the light is irradiated onto the semiconductor substrate 2. The reflected light 33 from the semiconductor substrate 2 is
After being collected by the camera 2, the light passes through the half mirror 31 and passes through the camera 2
After image formation at 4, for example, as shown in FIG.
It can be displayed on the monitor 26.

For adjusting the tilt of the semiconductor substrate 2, the driving mechanism 20A of the tilt stage 20 is adjusted so that the focal positions of the objective lens 22 at a plurality of positions in the processing area become the same.
２０20C is stretched appropriately. When the semiconductor substrate 2 serving as a sample is the entire semiconductor wafer before being divided into individual semiconductor chips, as shown in FIG. 6C, for example, three observation positions 34A to 34C are connected to the driving mechanism 20A. ~
Set near 20C. When the region in which the observation positions 34A to 34C are set is apart from the driving mechanisms 20A to 20C, the driving mechanism 20A is used to adjust the focal position of the objective lens 22 for one of the three observation positions 34A to 34C. To 20C, the observation positions 34A to 34C are changed to drive mechanisms 20A to 20C.
, The focal position of the objective lens 22 can be adjusted by one expansion and contraction of the drive mechanisms 20A to 20C close to the observation positions 34A to 34C, respectively.

At this time, it is assumed that the same pattern, for example, the alignment mark 35 and the bonding pad used for forming the wiring as shown in FIG. 6B are formed at the observation positions 34A to 34C. . By expanding and contracting the drive mechanisms 20A to 20C with the same pattern in the observation positions 34A to 34C as an object to be observed, the objective lenses 2 at a plurality of positions in the processing region of the semiconductor substrate 2 are expanded.
The two focal positions can be the same.

When the semiconductor substrate 2 to be observed is in the state of a semiconductor wafer, the above-mentioned observation positions 34A to 34A
The semiconductor substrate 2 can be locally observed as if 34C was set. From this, the observation positions 34A to 34A
4C, the inclination of the semiconductor substrate 2 or the semiconductor substrate 2 is determined.
Can be detected. Utilizing this, before processing the semiconductor substrate 2, the surface heights of at least three positions in the processing area are measured. Based on this measurement result, the tilt stage 20 is driven to make the measured surface height the same. Thereby, when processing the semiconductor substrate 2, it is possible to obtain a uniform processing depth over the entire processing region.

Regarding the detection of the processing amount of the semiconductor substrate 2,
First, the drive mechanism 2 shown in FIG. 1 is used so that the alignment mark 35 or the bonding pad formed on the main surface of the semiconductor substrate 2 before the processing is started can be imaged by the camera 24.
The optical system 21 is moved up and down by 7 to focus the objective lens 22. When the objective lens 22 is focused, the operation of the drive mechanism 27 is stopped and the optical system 21 is fixed. Then, after processing the semiconductor substrate 2, the optical system 21 is moved up and down by the driving mechanism 27 so that the observation positions 34A to 34C of the main surface of the processed semiconductor substrate 2 can be imaged by the camera 24. The focus of the objective lens 22 is adjusted. At this time, the amount of movement of the optical system 21 before and after processing the semiconductor substrate 2 is detected by the encoder 28, and the amount of movement of the optical system 21 is the amount of processing of the semiconductor substrate 2.

When the optical system 21 shown in FIG. 6A is used, since the processing of the semiconductor substrate 2 is performed on the main surface side, the alignment formed on the main surface side of the semiconductor substrate 2 is performed. The mark 35 or the bonding pad serves as an index for focusing the objective lens 22.

FIG. 7A is another example of the configuration showing the optical system 21 shown in FIG. 1 in more detail.

The configuration shown in FIG. 7A includes a reference light unit 40 having a reference light source 36, a color filter 37, an aperture plate 38 and a half mirror 39 in addition to the illumination unit 30.

Reference light 41 emitted from reference light source 36
Is a specific wavelength selected by the color filter 37.
The reference light 41 whose specific wavelength is selected is shaped by the aperture plate 38 and then the optical path is bent by the half mirror 39. Thereafter, the reference light 41 is condensed by the objective lens 22 and is formed on the semiconductor substrate 2 as a projection image of the aperture plate 38 at a reciprocal (1 / M) of the magnification M of the objective lens 22. The optical path of the illumination light 32 from the illumination unit 30 shown in FIG. 6A is the same in the configuration of FIG. 7A. The reflected light from the sample of the reference light 41 imaged on the sample becomes reflected light 42 together with the reflected light of the illumination light 32 from the illumination unit 30 from the sample. After being reflected by the objective lens 22, the reflected light 42 passes through the half mirrors 31 and 39 and can be imaged by the camera 24. FIG. 7B
As shown in the figure, the image formed by the camera 24 is displayed on the screen of the monitor 26 as an observation image of the sample, and the reference light 41
The projection unit 43 of the reflected light from the sample is projected brighter in the projection unit of the reflected light of the illumination light 32 from the sample. The tilt adjustment of the semiconductor substrate 2 is the same as that described with reference to FIG.

In the case where the back surface of the semiconductor substrate 2 having no alignment marks 35 or pads shown in FIG. 6 is processed, if the back surface is in a mirror surface state (including before processing), the reference light 41 is applied to the semiconductor substrate 2. By irradiating the back surface of the device, the position of the back surface can be detected. That is, the objective lens 22 is focused by moving the optical system 21 up and down so that the outline of the projection unit 43 is clearly displayed on the monitor 26 in the same shape as the opening of the aperture plate 38. The position of the semiconductor substrate 2 of the sample is detected.
Then, after processing the back surface of the semiconductor substrate 2 in a mirror surface state,
The optical system 2 so that the outline of the projection unit 43 is again clearly displayed on the monitor 26 in the same shape as the opening of the aperture plate 38.
1 is moved up and down, and the position of the back surface of the semiconductor substrate 2 at that time is detected. Here, the difference between the positions of the back surface of the semiconductor substrate 2 before and after processing the semiconductor substrate 2 is the amount of processing of the semiconductor substrate 2. Here, for the same reason as that described with reference to FIG. 6C, as shown in FIG. 7C, the entire semiconductor wafer before the semiconductor substrate 2 serving as a sample is divided into individual semiconductor chips. , The observation positions 34A to 34A
4C can be set above the drive mechanisms 20A to 20C. By such means, the objective lens 22 can be focused on the back surface of the sample having no alignment mark 35 or pad shown in FIG.

The optical system 21 shown in FIG. 6 or FIG.
It is also possible to know the processing end point by using. That is,
After setting the cutting amount (working depth) per time and reciprocating the XY stage 19 several times, the semiconductor substrate 2 is arranged below the optical system 21 shown in FIG.
The processing end point is determined based on whether or not the target pattern appears on the screen. This method is effective when the thickness of the semiconductor substrate 2 itself is not clear in the back surface processing. Further, the grinding wheel 1 is viewed from the semiconductor substrate 2.
The illumination light from the grinding wheel 1 may be detected by providing an illumination on the side and providing a photodetector on the vacuum chuck 16 (see FIG. 1). Since the amount of transmitted illumination light increases as the semiconductor substrate 2 becomes thinner by processing, the processing of the semiconductor substrate 2 is stopped when the light detector detects illumination light of a predetermined light amount or transmittance. This makes it possible to detect the end point of the processing of the semiconductor substrate 2.

FIG. 8A shows another example of the configuration of the optical system 21 shown in FIG. 1 in further detail. In this configuration, the camera 24 in the configuration shown in FIGS. 6A and 7A is replaced with a light amount measuring device 44, and an aperture plate having an opening between the light amount measuring device 44 and the objective lens 22. 45 and a condenser lens 22A.

The lighting unit 30 is the same as the lighting unit 30 shown in FIG. The reflected light 33 from the processing surface of the illumination light 32 irradiated on the processing surface of the semiconductor substrate 2
After being focused by the objective lens 22, the light passes through the half mirror 31 and forms an image on the aperture plate 45. Then, only the reflected light 33 that has passed through the opening of the aperture plate 45 is condensed by the condenser lens 22A and enters the light quantity measuring device 44. At this time, the light quantity measuring device 44 outputs a current or a voltage according to the incident light quantity.

Assuming that the shift between the focal position of the objective lens 22 and the sample processing surface shown in FIG. 8B is a defocus amount d, the aperture plate 45 increases as the defocus amount d increases.
The amount of the reflected light 33 passing through the opening is decreased. Further, as shown in FIG. 8C, when the defocus amount d becomes 0, the reflected light 33 passing through the opening of the aperture plate 45 is used.
Is maximum, and the amount of light detected by the light amount measuring device 44 is maximum. That is, the driving mechanism 2 described with reference to FIG.
By operating 7, the focal position of the objective lens 22 can be adjusted to the processing surface of the sample. FIG. 8 (a)
In the above, the case where the light quantity measuring device 44 is used is shown, but by observing the light quantity measuring device 44 with the camera 24 shown in FIGS. 6A and 7A, an observation image of the processed surface of the sample can be obtained. Becomes possible.

In the configuration shown in FIG. 8, the tilt stage 20 (see FIG. 1) is driven by driving the tilt stage 20 (see FIG. 1) so that the amount of reflected light 33 at a plurality of locations on the processed surface of the sample becomes a predetermined value. The tilt can be adjusted.
Thereby, the height of the processing surface of the sample can be made the same, and when processing the sample, it is possible to obtain a uniform processing depth over the entire processing region.

By the way, the configuration of the grinding wheel 1 and its peripheral portion may be as shown in FIG. 9 and FIG. In the configurations shown in FIGS. 9 and 10, the inside of the base 1A constituting the grinding wheel 1 is hollow, and the base 1
A plurality of through holes 45 penetrating from the inside of A to the outside are formed.

In the configuration shown in FIG. 9, the plasma generation chamber 47 has therein an electrode 46 electrically connected to the high frequency power supply 3 and the ground 17. A process gas is supplied into such a plasma generation chamber 47 to generate a plasma. The electrode 46 can be formed of, for example, Au. Au having low reactivity as a material of the electrode 46
By using this, it is possible to prevent the electrodes 46 from being damaged by ions of the etching gas 4 generated at the same time as generating the plasma.

In the configuration shown in FIG. 9, the process gas in a radical state in the plasma generation chamber 47 is supplied to the inside of the base metal 1A, and is passed through the plurality of through holes TH and the porous grinding wheel 1B. 1 is released to the outside. Further, in the configuration shown in FIG. 10, an electrode 46 electrically connected to the high frequency power supply 3 and the ground 17 is provided inside the base metal 1A. Under these circumstances, cylinders 7A, 7B
Thus, the plasma is generated by supplying the etching gas 4 and the inert gas 5 into the base metal 1A. After that, the process gas in the radical state is discharged to the outside of the grinding wheel 1 along the same route as in the case of the configuration shown in FIG. That is, in the configuration shown in FIGS. 9 and 10, the process gas in the radical state
The semiconductor substrate 2 can be uniformly processed because the semiconductor substrate 2 is uniformly supplied from the inside.

Further, the illumination is provided on the grinding wheel 1 side as viewed from the semiconductor substrate 2 and the photodetector is provided on the vacuum chuck 16 (see FIG. 1), so that the illumination light from the grinding wheel 1 side is detected. Is also good. Since the amount of transmitted illumination light increases as the semiconductor substrate 2 becomes thinner by processing, the processing of the semiconductor substrate 2 is stopped when the light detector detects illumination light of a predetermined light amount or transmittance. This makes it possible to detect the end point of the processing of the semiconductor substrate 2.

As described above, according to the first embodiment, the mechanical polishing using the grinding wheel 1 and the plasma C using the etching gas 4 and the inert gas 5 in a radical state are performed.
The semiconductor substrate 2 is processed using etching by the VM method. Therefore, the semiconductor substrate 2 can be easily processed continuously regardless of the layer structure. Therefore, the n-channel MISFET Qn performed after the processing of the semiconductor substrate 2
P-channel type MISFET Qp and wirings M1 to M7
The time required for analysis (see FIG. 2) can be reduced. Further, since the time required for the analysis can be shortened, the analysis result is converted into the n-channel type MISFET Qn,
This can be promptly reflected in the redesign of the semiconductor substrate 2 (second semiconductor substrate) having the p-channel type MISFET Qp and the wirings M1 to M7 and the adjustment of the manufacturing process.
That is, since the number of analysis cycles can be increased,
The development period of a product using the semiconductor substrate 2 can be shortened.

(Embodiment 2) FIG. 11 is a configuration diagram of a semiconductor manufacturing apparatus according to Embodiment 2 of the present invention. The semiconductor manufacturing apparatus first supplies the etching gas 4 and the inert gas 5 described with reference to FIG. 1 in the first embodiment to the plasma generation chamber 47, and the radical state generated in the plasma generation chamber 47 is The process gas (etching gas 4 and inert gas 5) is blown to the grinding wheel 1. In addition, the hood 11 covering the grinding wheel 1 in the first embodiment is replaced with an airtight chamber having the grinding wheel 1, the semiconductor substrate 2, the vacuum chuck 16, the stage 18 and the objective lens 22 therein. It is a replacement. Other configurations are the same as those of the semiconductor manufacturing apparatus described in the first embodiment with reference to FIG. Therefore, the description of those similar configurations is omitted.

The plasma generation chamber 47 is provided in the first embodiment.
Has an electrode 46 made of Au in the interior thereof, similarly to the plasma generation chamber 47 described with reference to FIG.
The nozzle 10 for blowing the process gas in the radical state onto the grinding wheel 1 and the plasma generation chamber 47 are connected by one pipe 9.

The etching gas 4 and the inert gas 5 are supplied from the cylinders 7A and 7B to the plasma generation chamber 47 through the pipes 9A and 9B provided with the valves 8A and 8B. Subsequently, a high frequency voltage is applied to the electrode 46 from the high frequency power supply 3. Thereby, plasma of the etching gas 4 and the inert gas 5 can be generated in the plasma generation chamber 47. Also in the second embodiment, as in the first embodiment, the etching gas 4 and the inert gas 5 are supplied at a pressure equal to or higher than the atmospheric pressure. The probability of disappearance due to collision with molecules constituting the gas increases, and the spatial spread decreases. for that reason,
It is possible to prevent ions in the plasma from being implanted into the semiconductor substrate 2. That is, an n-channel MISFET Qn and a p-channel MISFET Qn caused by ions in the plasma being implanted into the semiconductor substrate 2
Variations in characteristics such as p and the wirings M1 to M7 can be prevented. Further, as in the case of the first embodiment, since the density of the obtained radicals is high, the n-channel MI
The semiconductor substrate 2 can be processed at a high speed while preventing changes in characteristics of the SFET Qn, the p-channel MISFET Qp, and the wirings M1 to M7.

In the second embodiment, instead of the hood 11 used in the first embodiment, a chamber for hermetically sealing the grinding wheel 1, the semiconductor substrate 2, the vacuum chuck 16, the stage 18, and the objective lens 22 therein. 50 is used. When the chamber 50 is used, the loading and unloading of the semiconductor substrate 2 are performed with the door 51 opened. By using the chamber 50, the plasma CVM
The airtightness at the time of processing the semiconductor substrate 2 by the method and the grinding wheel 1 can be ensured, so that the hood 11 described with reference to FIG.
Diffusion of the process gas to the periphery can be reliably prevented. Further, as in the case of the first embodiment, the gas generated by the etching reaction of the semiconductor substrate 2, the excess process gas, and the residue of the semiconductor substrate 2 removed by the etching are exhausted by the exhaust device 12 and the exhaust pipe 13. Can be discharged through.

In the configuration shown in FIG. 11, the piping 9A for the etching gas 4 and the piping 9B for the inert gas 5 are connected to the plasma generation chamber 47. However, as shown in FIG. Connected to the chamber 47,
A mixing chamber 52 is provided in the middle of
May be connected. With such a configuration, the etching gas 4 supplied to the mixing chamber 52 can be turned into a radical state by the energy when the plasma of the inert gas 5 turns into a radical state.

Further, in the case of the configuration shown in FIG. 12, since only the plasma of the inert gas 5 is generated in the plasma generation chamber 47, damage to the electrode 46 by ions can be suppressed. Therefore, a material other than Au can be selected as the material of the electrode 46, and the manufacturing cost of the semiconductor manufacturing apparatus according to the second embodiment can be reduced.

Instead of the plasma generation chamber 47, a high-frequency coil 54 wound around a tube 53 made of glass or alumina as shown in FIG. 13 may be used. One end of the high-frequency coil 54 is electrically connected to the high-frequency power supply 3, and the other end is electrically connected to the ground 17. Under this condition, when the etching gas 4 and the inert gas 5 are supplied from the pipes 9A and 9B to the pipe 53 and a high-frequency voltage is applied to the high-frequency coil 54 by the high-frequency power supply 3, the etching gas 4 and the inert gas A plasma of the active gas 5 can be generated. Similarly to the case where the plasma generation chamber 47 is used, even when the tube 53 and the high-frequency coil 54 are used, the etching gas 4 and the inert gas 5 are supplied at a pressure higher than the atmospheric pressure. The plasma of the active gas 5 can be turned into a radical state in the pipe 9 on the way of being supplied to the nozzle 10.

Further, as shown in FIG.
The process gas may be radicalized using V.

In the configuration shown in FIG. 14, an ultraviolet light source UV is disposed inside the radical generation chamber RP, and a reflection film (not shown) for reflecting ultraviolet light from the ultraviolet light source UV is provided on the inner surface of the radical generation chamber RP. Are formed. The ultraviolet light source UV can be, for example, a mercury lamp, an excimer lamp, a deuterium lamp, or the like. The shorter the emission wavelength, the more efficiently the process gas can be in a radical state. The etching gas 4 and the inert gas 5 are supplied from the cylinders 7A and 7B to the radical generation chamber RP through pipes 9A and 9B provided with valves 8A and 8B, respectively.

In the radical generation process in the configuration shown in FIG. 14, first, the ultraviolet light source UV is turned on. Subsequently, the valves 8A and 8B are opened to supply the process gas (the etching gas 4 and the inert gas 5) into the radical generation chamber RP. The process gas supplied into the radical generation chamber RP is excited by the ultraviolet light from the ultraviolet light source UV to be in a radical state. The process gas in the radical state is guided to the nozzle 10 by the pipe 9 and can be supplied to the grinding wheel 1.

In the configuration shown in FIG. 14, the case where both the etching gas 4 and the inert gas 5 are supplied into the radical generation chamber RP has been exemplified.
Is supplied into the radical generation chamber RP, and a mixing chamber similar to the mixing chamber 52 described with reference to FIG. 12 is provided. In this mixing chamber, the inert gas 5 and the etching gas 4 in the radical state are mixed. It is good also as composition which mixes. Further, instead of providing the radical generation chamber RP, a quartz tube may be wound around the ultraviolet light source UV and a process gas may be supplied into the quartz tube, so that the process gas can be radicalized.

(Third Embodiment) FIG. 15 is a configuration diagram of a semiconductor manufacturing apparatus according to a third embodiment. This semiconductor manufacturing apparatus is capable of processing even a semiconductor chip or a package product which is difficult to process because of the dimensions of the grinding wheel 1 in the semiconductor manufacturing apparatuses described in the first and second embodiments. It is. Further, even when the processing target is a semiconductor wafer, it can be used when the processing area is small.

In the semiconductor manufacturing apparatus according to the third embodiment, a sample 61 (semiconductor substrate) obtained by packaging a semiconductor chip with a mold resin or the like is processed using a tool 62.

The tool 62 (first tool) is fixed to one end of a shaft 64 of the motor 63 by a nut 65. The other end of the shaft 64 is connected to the plasma generation chamber 47 via a joint 66 and the pipe 9. Since the process gas (the etching gas 4 and the inert gas 5) is supplied at a pressure equal to or higher than the atmospheric pressure in the same manner as in the first and second embodiments, the process gas enters a radical state while passing through the pipe 9. can do. Here, the tool 62, the motor 63, and the shaft 64 are hollow.
A process gas in a radical state is sprayed onto the processed surface of the sample 61 via the motor 63 and the shaft 64, and the sample 61 can be processed (etched) by the plasma CVM method.

FIG. 16 is an enlarged sectional view of the tool 62.
As shown in FIG. 16, the tool 62 includes a cylindrical base 62A.
The grindstone 62B (second member) is fixed to the end of the (first member). The base metal 62A is a conductive base metal like the base metal 1A shown in FIG. 4 in the first embodiment.
Further, the grinding stone 62B is made of diamond, alumina, Si, and the like in the same manner as the grinding stone 1B shown in FIG.
It is made of abrasive grains of C, CBN or a combination of a plurality of them, and is porous and secures air permeability. The sample 61 can be mechanically polished by rotating the tool 62 having such a configuration horizontally on the processing surface of the sample 61 by the motor 63. That is, similarly to the first and second embodiments, even when an Au film or the like, which is difficult to process by the plasma CVM method, is formed on the processing surface of the sample 61, the sample 61 is used as the tool 62. By mechanically polishing the sample 61, the sample 61 can be processed. As described above, in the semiconductor manufacturing apparatus according to the third embodiment, the processing of the sample 61 can be continuously performed by the etching by the plasma CVM method and the mechanical polishing by the tool 62. Further, similarly to the first and second embodiments, the etching by the plasma CVM method and the tool 62 are performed.
By performing the mechanical polishing simultaneously, the interlayer insulating films and wirings having different etching rates can be uniformly processed in a mirror state.

The hood 11 shown in FIG. 15 is similar to the hood 11 described in the first embodiment with reference to FIG. It is provided to supply to the processing section. The gas generated by the etching reaction of the sample 61 and the excess process gas can be exhausted without being diffused to the surroundings through the exhaust pipe 13 connected to the hood 11. Further, even when the residue of the sample 61 that has been removed by etching with the process gas remains on the processed surface of the sample 61, the residue is removed by the tool 62.
After the gas is removed by the exhaust pipe 13, the residue can be prevented from remaining on the processed surface of the sample 61. That is, the residue of the sample 61
It is possible to prevent the mirror surface processing from being hindered by remaining on the processed surface.

Further, not only the tool 62 for mechanically polishing the sample 61 but also, for example, an end mill or the like capable of processing a mold resin for sealing the sample 61 with resin can be attached to the shaft 64. Tool 62
By properly replacing the tool with another tool such as an end mill, the semiconductor manufacturing apparatus according to the third embodiment allows the sample 61 to be used.
Can be processed consistently.

FIGS. 17 (a) and 17 (b) are a cross-sectional view of a main part and a plan view of the main part viewed from above showing a modification of the tool 62, respectively. As shown in FIG. 17A, the diameter of the end of the base metal 62A may be increased, and a lid having a ventilation hole 67 may be provided at the end. At this time, the grindstone 62B is permeable.

FIG. 18A is a sectional view of a main part showing a modification of the tool 62, and FIGS.
FIG. 19C is a plan view of a main part of the tool 62 shown in FIG. The grindstone 62B may be provided with a radial groove 68 as shown in FIG.

As described above, the tool 62 is moved to the position shown in FIG.
With the configuration as shown in FIG. 8, it becomes possible to more effectively feed the process gas in the radical state to the processed surface of the sample 61. That is, the processing of the semiconductor substrate 2 can be performed more effectively.

FIG. 19 shows that the tool 62 is used without using the motor 63.
1 shows an example of a configuration for rotating. FIG. 19A is a cross-sectional view of a main part showing the configuration, and FIG. 19B is a plan view taken along line AA in FIG. 19A.

In the configuration shown in FIG. 19, a hollow case 70 connected to the plasma generation chamber 47 is used instead of the motor 63. Inside the case 70, a rotating blade 71 is attached to a shaft 64, and the shaft 64 is rotatably held on the upper and lower surfaces of the case 70 by a seal bearing 72. Also, the shaft 6
4 is provided with a vent hole 73 for supplying a process gas to the tool 62.

The shaft 64 to which the rotating blade 71 is attached
Can be rotated by the pressure of the process gas supplied to the case 70. That is, the tool 62 can be rotated at the pressure at which the process gas is supplied, and the sample 61 can be processed, so that driving equipment such as the motor 63 shown in FIG. 15 can be omitted. Thus, a power source for driving the driving device can be omitted, so that the manufacturing cost of the semiconductor manufacturing apparatus of the third embodiment and the manufacturing cost of the semiconductor device manufactured by the semiconductor manufacturing apparatus can be reduced. Becomes

As shown in FIG. 20, in the configuration described with reference to FIG. 19, the illumination unit 30 described with reference to FIG.
By using the inner surface of the base metal 62A and the inner surface of the shaft 64 as light guides, it is possible to detect the gap G between the tool 62 and the sample 61 based on the amount of reflected light from the sample 61.

As shown in FIG. 20A, the illumination light source 23
The illumination light 32 emitted from the optical path is bent by the half mirror 31 and condensed by the condenser lens 75, and then passes through the light transmission window 76 provided on the seal bearing 72, and the shaft 64 and the tool 62 Sample 6 via the inside
Irradiated on 1 The reflected light 77 from the sample 61 passes through the shaft 64 and the tool 62, and is condensed by the condensing lens 75, then passes through the half mirror 31, and passes through the
8 detected.

According to an experiment conducted by the present inventors, FIG.
FIG. 20C shows a gap between the gap G between the tool 62 and the processed surface of the sample 61 shown in FIG.
It has been found that there is a relationship as shown in FIG. That is, as the gap G becomes smaller, the tool 62 and the sample 61
And the amount of reflected light 77 detected by the photodetector 78 increases, and the reflected light 7
The gap G becomes 0 at the time when the light quantity of No. 7 becomes maximum.
As a result, the tool 62 is gradually approached to the sample 61, and the descent of the tool 62 is stopped when the amount of light detected by the light detector 78 stops changing, so that processing can be performed without damaging the sample 61. It becomes possible.

The structure shown in FIG. 21 or FIG.
Is a modification of the configuration in which the tool 62 is rotated without using the motor 63 described with reference to FIG.
Alternatively, by providing the reflection type objective lens 80B coaxially with the tool 62, the processed surface of the sample 61 can be observed even during the processing of the sample 61.

In the configuration shown in FIGS. 21 and 22, fins 81 are provided on the inner surface of the tool 62, and the plasma generation chamber 4 is provided similarly to the configuration described with reference to FIG.
7 by the pressure of the process gas supplied from
Can be rotated. Thus, similarly to the configuration described with reference to FIG. 19, the motor 63 shown in FIG.
And other driving equipment can be omitted.

In the configuration shown in FIG.
The illumination light 32 emitted from the light source 3 has its optical path bent by the half mirror 31 and then passes through the light transmission window 82 to the case 83.
Get in. The illumination light 32 entering the case 83 passes through the inside of the lens tube 84 and is condensed by the objective lens 80 </ b> A, and is irradiated on the sample 61. Reflected light 77 from sample 61
Is collected by the relay lens 85 via the lens tube 84, the light transmission window 82 and the half mirror 31 after being collected by the objective lens 80A. The illumination light 32 condensed by the relay lens 85 is imaged by the camera 24, and the image can be displayed on the screen of the monitor 26 as an observation image of the sample 61.

In the configuration shown in FIG. 22, the objective lens 80B has the same function as the case 83 shown in FIG. 21, and has a lens 80C capable of reflecting light on its inner surface.
And a lens 80D provided inside the lens 80C and capable of reflecting light. The illumination light 32 entering the case 83 through the light transmission window 82 enters the inside of the lens 80C from the light transmission window 82 provided on the upper surface of the lens 80C, and is reflected by the lens 80D. The illumination light 32 reflected by the lens 80D reaches the inner surface of the lens 80C, is reflected by the lens 80C, and irradiates the sample 61. The reflected light 77 from the sample 61 is
After arriving at the inner surface of the lens 80C, the light is reflected by the lens 80C and condensed on the lens 80D. The reflected light 77 condensed on the lens 80D is reflected by the lens 80D and exits the lens 80C through the light transmission window 82. The reflected light 77 emitted to the outside of the lens 80C is transmitted through the half mirror 31 and then condensed by the relay lens 85 to be imaged by the camera 24. The image formed by the camera 24 can be displayed on the screen of the monitor 26 as an observation image of the sample 61.

As described above, in the configuration shown in FIGS. 21 and 22, the processed surface of the sample 61 can be observed even during the processing of the sample 61. That is, sample 6
During the processing 1, the processing is stopped when a predetermined pattern such as the n-channel MISFET Qn, the p-channel MISFET Qp, or the wirings M <b> 1 to M <b> 7 described with reference to FIG. It is possible to do. Thus, the third embodiment
The processing accuracy of the semiconductor manufacturing apparatus can be improved.

(Embodiment 4) In Embodiment 4, after forming a wiring groove in an insulating film, a conductive film for forming a wiring is deposited on the main surface of the semiconductor substrate, and a region other than the wiring groove is formed. The semiconductor manufacturing apparatus described in Embodiment 1, Embodiment 2, or Embodiment 3 is applied to a manufacturing process of a semiconductor device in which a wiring is formed in a wiring groove by removing a conductive film. Things.

Hereinafter, the steps of manufacturing the above-described semiconductor device will be described in the order of steps with reference to FIGS.

First, as shown in FIG.
The semiconductor substrate 2 made of single crystal silicon of about Ωcm
A heat treatment is performed at about 50 ° C. to form a thin silicon oxide film (pad oxide film) having a thickness of about 10 nm on the main surface, and then a silicon nitride film having a thickness of about 120 nm is formed on the silicon oxide film by CVD (Chemical After deposition by a vapor deposition method, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using a photoresist film as a mask. The silicon oxide film is formed for the purpose of relieving stress applied to the substrate when densifying (burning) the silicon oxide film embedded in the element isolation trench in a later step. Further, since the silicon nitride film has a property of being hardly oxidized, it is used as a mask for preventing oxidation of the substrate surface below (the active region).

Subsequently, the semiconductor substrate 2 in the element isolation region is subjected to dry etching with a depth of 3
After forming a groove of about 50 nm, the semiconductor substrate 2 is heat-treated at about 1000 ° C. to remove a damaged layer formed on the inner wall of the groove by etching, and a thin silicon oxide film 94 of about 10 nm thickness is formed on the inner wall of the groove. To form

Subsequently, a film thickness of 380 nm is formed on the semiconductor substrate 2.
The silicon oxide film 95 is deposited by a CVD method, and then, in order to improve the film quality of the silicon oxide film 95, the semiconductor substrate 2 is heat-treated and the silicon oxide film 95 is densified (baked). Then, FIG.
Using the semiconductor manufacturing apparatus described with reference to FIG. 11, the semiconductor manufacturing apparatus described with reference to FIG. 11 in Embodiment 2, or the semiconductor manufacturing apparatus described with reference to FIG. 15 in Embodiment 3. The film 95 is polished. In this manner, by leaving the silicon oxide film 95 inside the groove, the element isolation groove 96 whose surface is flattened can be formed.

Subsequently, after removing the silicon nitride film remaining on the active region of the semiconductor substrate 2 by wet etching using hot phosphoric acid, the n-channel MISF of the semiconductor substrate 2 is removed.
B (boron) is ion-implanted into the region where
A mold well 97 is formed.

Subsequently, after removing the silicon oxide film of the p-type well 97 using a HF (hydrofluoric acid) -based cleaning solution, FIG.
As shown in FIG. 4, the semiconductor substrate 2 is wet-oxidized to form a clean gate oxide film 99 having a thickness of about 3.5 nm on the surface of the p-type well 97.

Next, a film having a thickness of 90 to 100
A non-doped polycrystalline silicon film of about nm is deposited by a CVD method. Subsequently, for example, P (phosphorus) is ion-implanted into the non-doped polycrystalline silicon film on the p-type well 97 using an ion implantation mask to form an n-type polycrystalline silicon film. Further, a silicon oxide film is deposited on the surface of the n-type polycrystalline silicon film to form a laminated film, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate electrode 100.
Then, a cap insulating film 101A is formed. Incidentally, the upper portion of the gate electrode 100 WSi _x, MoSi _x, TiS
i _x, it may be stacked refractory metal silicide film such as TaSi _x or CoSi _x. Cap insulating film 101A
Can be formed by, for example, a CVD method.

Next, after removing the photoresist film used for processing the gate electrode 100, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 97 so that the p-type wells on both sides of the gate electrode 100 are removed. N ^- type semiconductor region 10 at 97
Form 2

Next, a silicon oxide film having a thickness of about 100 nm is deposited on the semiconductor substrate 2 by the CVD method, and the silicon oxide film is anisotropically etched by the reactive ion etching (RIE) method. n-channel MIS
A sidewall spacer 101B is formed on the side wall of the gate electrode 100 of the FET Qn. Subsequently, the p-type well 97
Is ion-implanted with an n-type impurity, for example, As (arsenic).
N ⁺ type semiconductor region 103 of channel type MISFET Qn
(Source, drain) are formed. Thereby, the LDD (Lightly Doped Draid) is applied to the n-channel type MISFET Qn.
n) Source and drain regions having a structure are formed, and an n-channel MISFET Qn is completed.

Next, after a silicon oxide film is deposited on the semiconductor substrate 2 by the CVD method, the semiconductor manufacturing apparatus described in the first embodiment with reference to FIG. The silicon oxide film is polished using the semiconductor manufacturing apparatus described with reference to FIG. 15 or the semiconductor manufacturing apparatus described in Embodiment 3 with reference to FIG. Thus, the insulating film 104 whose surface is flattened can be formed.

Next, as shown in FIG.
The insulating film 104 on the n ⁺ type semiconductor region 103 on the main surface of
The connection hole 105 is opened using a photolithography technique.

Next, a barrier conductor film 10 made of, for example, titanium nitride is formed on the semiconductor substrate 2 by sputtering.
6A, and a conductive film 106B such as tungsten is deposited by blanket CVD.

Next, the barrier conductor film 106A and the conductive film 106B on the insulating film 104 other than the connection hole 105 are formed by using the semiconductor manufacturing apparatus described in the first embodiment with reference to FIG. 15 using the semiconductor manufacturing apparatus described with reference to FIG. 11 or the semiconductor manufacturing apparatus described with reference to FIG.
6 is formed.

Next, as shown in FIG.
A silicon nitride film is deposited thereon by, for example, a plasma CVD method, and the etch stopper film 107 having a thickness of about 100 nm is formed.
To form The etch stopper film 107 is used to prevent the lower layer from being damaged due to excessive digging and to prevent the processing dimensional accuracy from deteriorating when a trench or a hole for forming a wiring is formed in the insulating film on the upper layer. Things.

Subsequently, for example, the etch stopper film 107
Silicon oxide (S) doped with fluorine by CVD on the surface of
iOF) film, and an insulating film 10 having a thickness of about 400 nm.
8 is deposited. When an SiOF film is used as the insulating film 108, since the SiOF film is a low dielectric constant film, the overall dielectric constant of the wiring of the semiconductor device can be reduced, and the wiring delay can be improved.

Next, the etching stopper film 107 and the insulating film 108 are processed using a photolithography technique and a dry etching technique to form a wiring groove 109.

Next, as shown in FIG. 27, a titanium nitride film to be a barrier conductor film 110 is deposited. Barrier conductor film 1
10 can be deposited by, for example, a CVD method or a sputtering method. The deposition of the barrier conductor film 110 is performed to improve the adhesion of the copper film formed in the next step and to prevent the diffusion of copper.
It can be. In the fourth embodiment, a titanium nitride film is exemplified as the barrier conductor film 110. However, a metal film such as a tantalum film or a tantalum nitride film may be used. Has better adhesion to a copper film than when a titanium nitride film is used.

It is also possible to sputter-etch the surface of the barrier conductor film 110 immediately before the next step of depositing a copper film. By such sputter etching, water, oxygen molecules, and the like adsorbed on the surface of the barrier conductor film 110 can be removed, and the adhesiveness of the copper film can be improved. In particular, after the barrier conductor film 110 is deposited, the effect is great when vacuum breaking is performed to expose the surface to the atmosphere and deposit the copper film.
This technique is not limited to the case where the barrier conductor film 110 is a titanium nitride film, but is effective even when the barrier conductor film 110 is a tantalum nitride film, although the effect is different.

Next, a copper film or a copper alloy film, which is a metal to be the conductive film 111, is deposited, fluidized by heat treatment, and the conductive film 111 well embedded in the wiring groove 109.
To form When the conductive film 111 is a copper alloy film, the alloy should contain about 80% by weight or more of copper. For forming the conductive film 111, a normal sputtering method can be used, but a physical vapor deposition method such as an evaporation method or a plating method may be used. When the plating method is used, it is necessary to deposit a seed film before depositing a copper film or a copper alloy film to be the conductive film 111, and this seed film is deposited by a sputtering method. Further, the conditions of the heat treatment require a temperature and a time at which the copper film or the copper alloy film constituting the conductive film 111 is fluidized,
For example, it can be about 400 ° C. to 450 ° C. for about 3 minutes to 5 minutes.

Next, as shown in FIG.
By removing the excess barrier conductor film 110 and conductive film 111 above and leaving the barrier conductor film 110 and conductive film 111 in the wiring groove 109 to form the embedded wiring 112, the fourth embodiment A semiconductor device is manufactured. The removal of the barrier conductor film 110 and the conductive film 111 may be performed by the semiconductor manufacturing apparatus described in Embodiment 1 with reference to FIG. 1, the semiconductor manufacturing apparatus described in Embodiment 2 with reference to FIG. 11, or The polishing can be performed by using the semiconductor manufacturing apparatus described in Embodiment 3 with reference to FIG.

The removal of the barrier conductor film 110 and the conductive film 111 is performed by CMP (Chemical Mechanical).
When the polishing is performed by the cal polishing method, it is necessary to change the abrasive grains to be used from large to small according to the progress of polishing. Since the grindstone 1B or the grindstone 62B in the above-described semiconductor manufacturing apparatus is made of small-sized abrasive grains, the step of replacing the abrasive grains can be omitted. Further, in the above-described semiconductor manufacturing apparatus, since the processing by the plasma CVM method and the processing using the grinding wheel 1 or the tool 62 are performed at the same time, the barrier conductor film 110 having a different etching rate and the conductivity can be obtained without lowering the processing speed. The film 111 can be processed uniformly.

In the case where the above-mentioned CMP method is used, the processing near the center of the wiring groove 109 progresses quickly due to the elasticity of the polishing pad and the chemical effect of the slurry, and dents (dishing) occur. May occur.
Here, for example, the width of grinding wheel 1 described with reference to FIG. 1 in the first embodiment can be set according to the size of semiconductor substrate 2 to be processed.
The load from the grinding wheel 1 can be prevented from being applied to the vicinity of the center of the wheel. That is, dishing can be prevented when the above-described semiconductor manufacturing apparatus is used.

(Fifth Embodiment) As shown in FIG. 29A, a glass substrate GS for back surface analysis according to a fifth embodiment is formed on an optically transparent glass substrate GS ₂ and a glass substrate GS _2. Needle pad NP, semiconductor substrate 2 to be analyzed
And a wiring L connecting the bump electrode B and the bump electrode B corresponding to the pads P ₁ of the needle support pad NP.

The optically transparent glass substrate GS ₂ does not necessarily have to have a high transmittance in the entire range from the ultraviolet region to the infrared region. For example, quartz, which is one of various glass substrates, has a high transmittance in an ultraviolet range of about 180 nm to an infrared range of about 3 μm. Further, the sapphire substrate has a high transmittance in the infrared range from about 150 nm to about 6 μm, and the zinc selenide substrate has a high transmittance in the visible range from 600 nm or more to about 15 μm in the infrared range. Has transmittance. Therefore, it may be appropriately selected from various glass substrates according to the content of the analysis. Further, by forming an antireflection film on the surface of the glass substrate GS ₂ as necessary, thereby enabling clearer analysis.

The needle contact pad NP and the wiring L formed on the glass substrate GS ₂ are made of Al, Au, Cu, Cr, Ni, W
And the like, or an alloy or a laminate thereof. The needle contact pad NP and the wiring L may be simultaneously formed simultaneously using the same material. And the normal LS
Similarly to I, higher reliability can be obtained by appropriately selecting and forming a protective film made of silicon oxide, silicon nitride, polyimide resin, or the like on the wiring L. The bump electrode B is made of solder when the electrode on the semiconductor substrate (chip) side to be analyzed is made of a pad, and Au or the like having excellent wettability to solder when it is made of a solder bump. Of a metal film formed on the surface.

FIG. 29 (b) shows a state in which a semiconductor substrate (chip) 2 to be analyzed is fixed to the glass substrate GS for back surface analysis so as to face each other. In the fifth embodiment,
For example, a chip bonding apparatus 12 as shown in FIG.
0 is used to perform bonding of the semiconductor substrate 2.

The chip bonding apparatus 120 includes a collet 121 movable vertically and a substrate holder 122 for supporting the semiconductor substrate 2. The collet 121 is provided with an exhaust port 123 for vacuum-sucking the semiconductor substrate 2 and a heater 124 for heating the semiconductor substrate 2, and the semiconductor substrate 2 can be heated to a desired temperature by a temperature controller (not shown). It has become. The substrate holder 122 also has an exhaust port 125 for vacuum suction and a heater 1.
26, and a vacuum-adsorbed glass substrate GS
₂ can be heated to a desired temperature. The substrate holder 122 is movable in the XY directions and rotatable in the θ direction.

The bonding procedure is as follows.
2 is vacuum-adsorbed face down on the collet 121
Both are glass substrate GS_TwoTo the substrate holder 122 by vacuum suction
Then, the substrate holder 122 is moved in the XY direction and the θ direction.
And the pad P of the semiconductor substrate 2 ₁And analysis glass substrate GS
With the bump electrode B of FIG.

Next, the collet 121 and the substrate holder 1
After heating the semiconductor substrate 2 and the analysis glass substrate GS to a predetermined temperature (the melting temperature of the solder bumps) in an inert gas atmosphere, the collet 121 is moved to a predetermined position (reference numeral G in the drawing). (The position indicated by), and the semiconductor substrate 2 is pressed against the glass substrate for analysis GS. Next, the energization of the heaters 124 and 126 is stopped, and the vacuum suction of the collet 121 is also stopped.
Increase 1 Thereby, the semiconductor substrate 2 is fixed to the analysis glass substrate GS. By providing a pipe through which various kinds of refrigerant such as water passes inside the collet 121 and the substrate holder 122, the time for fixing the semiconductor substrate 2 to the analysis glass substrate GS can be reduced.

Next, as shown in FIG. 31, mechanical polishing using various abrasives such as alumina and diamond and CMP
(Chemical mechanical polishing) and fixed on a stage 131 of a polishing apparatus 130 (or a CVM apparatus using a process gas such as a halogen compound by radicalizing),
The silicon substrate portion of the semiconductor substrate 2 is polished to a thickness of 15 μm or less.

This thinning treatment is not limited to the above-mentioned polishing method, but may be, for example, a dry etching method using ionized halogen compounds, a wet etching method using hydrofluoric acid or the like, or a sputtering method of ionizing and irradiating an inert gas. It can also be performed using such as. Furthermore, these methods may be used in combination, for example, plasma CVM
Various abrasive grains such as alumina or diamond may be fixed on the electrode surface of the apparatus, and the etching may be combined with the mechanical polishing by rotating the electrode.

The thinning process of the semiconductor substrate 2 is performed by using the chip bonding apparatus 120.
Is fixed to the glass substrate GS for analysis, the semiconductor substrate 2
Is substantially parallel to the analysis glass substrate GS. Therefore, the semiconductor substrate 2 can be moved to the analysis glass substrate GS without providing a tilt adjusting mechanism in the polishing apparatus 130 for thinning the semiconductor substrate 2.
Can be reduced in parallel with the thickness of the semiconductor substrate 2, so that when performing the back surface analysis, it is possible to reduce variations in image detection and the like caused by the difference in the remaining film thickness of the semiconductor substrate 2.

Through the above steps, the semiconductor substrate 2 is electrically connected to the analysis glass substrate GS, and the semiconductor substrate 2 is connected to the analysis glass substrate GS via the needle contact pads NP.
Power supply and transmission and reception of signals. In addition, since the semiconductor substrate 2 is thinned, the wavelength transmitted through the silicon substrate portion extends not only to the infrared region but also to the short wavelength region. Therefore, as in the case of EMMI analysis, the power supply and the signal supply to the semiconductor substrate 2 are performed. Analysis of the generated light emission is possible not only for infrared light but also for visible light. Conversely, analysis using laser light having a wavelength in the visible range is also possible.

Next, the analysis glass substrate GS to which the semiconductor substrate 2 is fixed is fixed on a stage 141 of an analyzer 140 as shown in FIG. 32, and a prober (or probe card) 142 is applied to the needle application pad NP. To supply power and send and receive signals.

A part of the stage 141 includes the semiconductor substrate 2
The size of the opening 143 is provided, and the analysis means 144 and 145 are provided on the upper and lower sides of the stage 141, respectively, so that the semiconductor substrate 2 can be analyzed from both sides. For example, an OBIC is applied by irradiating a laser beam in the visible light range from the back side of the semiconductor substrate 2 to the element or the element isolation portion.
Performs (Optical Beam Induced Current) analysis, by irradiating a laser beam in the infrared region to the wiring through a glass substrate GS ₂ from the surface side of the semiconductor substrate 2, OBIRC
H (Optical Beam Induced Resistance Change) analysis can be performed.

For example, while performing EMMI analysis from both sides, it is also possible to perform failure analysis of elements and contact holes from the back side and failure analysis of via holes and wiring from the front side. Further, for example, in the OBIRCH analysis, if the optical system is arranged on both surfaces of the semiconductor substrate 2 and the same coordinate system is irradiated with laser light from both surfaces or can be individually scanned and irradiated, the semiconductor substrate 2 having a multilayer structure can be obtained. Not only is possible, but it is also possible to obtain analysis results that could not be obtained by conventional one-sided irradiation alone. As described above, by performing the analysis by appropriately combining various analysis methods, the analysis time can be reduced, and a new analysis method that has been difficult with the conventional method can be realized.

It is also assumed that the analysis device 140 is a semiconductor substrate 2
In the case where the configuration is not such that analysis from both sides is possible, for example, as in the prior art (Japanese Unexamined Patent Application Publication No. 11-111759), the glass substrate G for analysis is selected according to the analysis direction.
What is necessary is just to rotate S suitably. For this purpose, a needle contact pad NP is also provided on the back side of the glass substrate for analysis GS, and the one connected to the pad NP on the front side through a through hole is used. Then, as shown in FIG. 33, the semiconductor substrate 2 was mounted on a stage 148 having a jig 147 provided with an opening 146 having a size larger than that of the semiconductor substrate 2, and provided on the back side of the analysis glass substrate GS. Needle pad NP
The probe card 115 is used to perform various analyzes. In this case, the analysis is performed from the front side of the semiconductor substrate 2. However, when the analysis is performed from the back side, the glass substrate GS for analysis is turned over and placed on the stage 148 in the direction shown in FIG. The analysis may be performed by mounting it.

(Embodiment 6) As shown in FIG. 34A, the basic structure of an analysis glass substrate GS used in Embodiment 6 is the same as that of Embodiment 5 described above.
(B), the thickness is a glass substrate GS ₃ different partially. That is, the glass substrate GS _3, the needle against thicker central portion than the peripheral portion where the pad NP and wires L is formed, and the central portion height is lower by a distance (h) than the height of the bump electrode B It is configured as follows.

In order to analyze the semiconductor substrate 2 using the analysis glass substrate GS, for example, as shown in FIG. 35, the chip bonding apparatus 120 of the fifth embodiment is used.
After fixing the semiconductor substrate 2 to the glass substrate GS for analysis using
, And the analysis glass substrate GS is vacuum-sucked to the substrate holder 122 in which the heater 126 is built.

Subsequently, the pad P ₁ of the semiconductor substrate 2 is opposed to the bump electrode B of the glass substrate GS for analysis, and the heater 1 of the collet 121 and the substrate holder 122
24 and 126, the semiconductor substrate 2 and the analysis glass substrate GS are heated to a predetermined temperature (in the case of the bump electrode B being a solder bump, the melting temperature of solder) in an inert gas atmosphere. Lowers the collet 121 to a position where the collet 121 contacts the analysis glass substrate GS.

Next, the energization of the heaters 124 and 126 is stopped, the vacuum suction of the collet 121 is also stopped, and the collet 121 is raised. Thereby, the semiconductor substrate 2
It is secured to the central portion of the glass substrate GS ₃ (a thick portion of the plate thickness). Then, as shown in FIG. 36, the silicon substrate portion of the semiconductor substrate 2 is thinned using the polishing apparatus 130 used in the fifth embodiment.

In the sixth embodiment, since the front side of the semiconductor substrate 2 is in contact with the glass substrate GS ₃ ,
The thin semiconductor substrate 2 is deformed by the pressing force of the whetstone 0,
There is no problem that the thickness of the semiconductor substrate 2 varies during the thinning process.

(Embodiment 7) The present embodiment 7 relates to a so-called area array type BGA (Ball Gr) in which solder bumps or base films thereof are formed over the entire surface of the semiconductor substrate 2.
id Array) It is useful for analyzing chips.

The glass substrate for analysis GS used in the seventh embodiment includes an optically transparent glass substrate GS ₄ , a needle pad NP formed on the glass substrate GS ₄ , and a solder for the semiconductor substrate 2 to be analyzed. Bump electrode B corresponding to bump
And a wiring L for connecting the bump electrode B and the needle contact pad NP, and the wiring L is formed of an optically transparent film.

[0153] optically transparent lines L are for example thin film made of a translucent material such as tin oxide and indium oxide was deposited on a glass substrate GS _4, formed by patterning the same. As described above, by forming the wiring L from an optically transparent film, the wiring L can be formed under the semiconductor substrate 2.
, The wiring L does not hinder the analysis. In addition, the base film of the bump electrode B and the needle contact pad NP may be made of a light-transmitting material. However, if the needle contact pad NP is made optically transparent, it becomes difficult to apply the probe to the needle.

As in the fifth embodiment, a protective film made of silicon oxide, silicon nitride, polyimide resin, or the like may be appropriately selected and formed on wiring L. Further, by forming the wiring L in a multilayer structure, it is possible to analyze a multi-pin BGA chip having a very large number of connection points. In this case, since increases the number of needle support pad NP, disposed in two rows or three rows on the periphery of the glass substrate GS _4.

Using the chip bonding apparatus 120 of the fifth embodiment, the semiconductor substrate 2 is attached to the glass substrate GS for analysis.
Then, the semiconductor substrate 2 is vacuum-sucked to the collet 121 face down, and the analysis glass substrate GS is vacuum-sucked to the substrate holder 122 in which the heater 126 is built.

The method of fixing the semiconductor substrate 2 to the analysis glass substrate GS and the method of thinning the silicon substrate portion of the semiconductor substrate 2 may be the same as those described in the fifth and sixth embodiments.

(Eighth Embodiment) The glass substrate for analysis GS of the eighth embodiment is useful when the semiconductor substrate 2 is a wafer. FIG. 38 is a plan view showing an analysis glass substrate GS of the eighth embodiment, and FIG. 39 is a cross-sectional view showing a state in which a semiconductor substrate (wafer) 2 is fixed to the analysis glass substrate GS.

The analysis glass substrate GS has an optically transparent glass substrate GS ₅ , and a plurality of chip areas in the semiconductor substrate (wafer) 2 to be analyzed are provided on the surface side of the glass substrate GS _5. Are formed, and an analysis pad 114 connected to the bump electrode B through the through hole 113 is formed on the back surface side.

The method of fixing the semiconductor substrate (wafer) 2 to the analysis glass substrate GS and the method of thinning the silicon substrate portion of the semiconductor substrate 2 may be the same as the methods described in the fifth and sixth embodiments. Then, the analysis glass substrate GS is mounted on the analysis device 140 shown in FIG. 32 to perform a predetermined analysis.

Ninth Embodiment As shown in FIG. 40, an analysis glass substrate GS of the ninth embodiment is different from the opening substrate S in which the opening 149 is formed at a position corresponding to the analysis target area of the semiconductor substrate 2. , a wire L that connects the open board S on the formed needle support pad NP, the bump electrode B and the bump electrode B corresponding to the pads P ₁ of the semiconductor substrate 2 and the needle support pad NP to be analyzed I have. Needle pad N
The P, the bump electrode B and the wiring L may be the same as those in the fifth embodiment, but the aperture substrate S does not need to be an optically transparent glass substrate, and may be made of a material other than glass.

In the ninth embodiment, the semiconductor substrate 2 is bonded using a chip bonding apparatus 150 as shown in FIG. 41, for example.

A convex vacuum suction unit 153 is formed on the upper surface of the substrate holder 152 of the chip bonding apparatus 150. When the analysis glass substrate GS is fixed to the upper surface of the substrate holder 152, the vacuum suction unit 153 is turned off. It is configured to project upward from the opening 149 of the opening substrate S. At this time, the height of the upper surface of the vacuum suction part 153 is set to be lower than the height of the bump electrode B by the distance (h).

Then, the collet 151 is face down.
The semiconductor substrate 2 vacuum-adsorbed is pressed against the analysis glass substrate GS while being heated to a predetermined temperature by the heater 154.
The amount by which the semiconductor substrate 2 is pressed against the analysis glass substrate GS depends on whether the semiconductor substrate 2 is in the vacuum suction portion 15 of the substrate holder 152.
Until it touches 3.

Next, after stopping the energization of the heaters 154 and 156 and stopping the vacuum suction of the collet 151,
Collet 1 starts vacuum suction of substrate holder 152
21 is raised. Thus, the semiconductor substrate 2 is fixed to the analysis glass substrate GS in a state where the semiconductor substrate 2 is vacuum-sucked to the substrate holder 152.

Next, the polishing apparatus 130 shown in FIG.
The silicon substrate portion of the semiconductor substrate 2 to a thickness of 1
Polish until it becomes 5 μm or less. When the chip bonding apparatus 150 and the polishing apparatus 130 are arranged in one apparatus, as shown in FIG.
The semiconductor substrate 2 is polished by moving the wafer 2 to the polishing apparatus 130 side. Then, the analysis glass substrate GS is placed in FIG.
2 is mounted on the analysis device 140 to perform a predetermined analysis.

The analysis glass substrate GS of Embodiment 9 is
Since the glass substrate does not exist at a position corresponding to the analysis target region of the semiconductor substrate 2, analysis using a charged beam such as an electron beam or a focused ion beam is also possible in addition to the above-described light source.

(Embodiment 10) FIG. 43A is a plan view showing an analysis glass substrate GS according to Embodiment 10 of the present invention.
FIG. 3B is a cross-sectional view showing a state where the semiconductor substrate (wafer) 2 is fixed to the glass substrate GS for analysis.

Analysis glass substrate GS of Embodiment 10
It is the surface of the glass substrate GS ₆ needle support pad NP, to form a bump electrode B and the wiring L, the bump electrodes B
A self-determination circuit 157 of the semiconductor substrate 2 is formed between the semiconductor device 2 and the wiring L.

The self-determination circuit 157 is composed of, for example, a test pattern generation section, a data measurement section, a data storage section, a data analysis / determination section and the like.

To analyze the semiconductor substrate 2, first, the semiconductor substrate 2 is fixed to the analysis glass substrate GS by using the method described in each of the above embodiments, and then the semiconductor substrate 2 is subjected to a thinning process. After that, the analyzer 14 shown in FIG.
Analyze using 0. At this time, for example, a predetermined test pattern is supplied to the semiconductor substrate 2 from the test pattern generation unit of the self-determination circuit 157 by power supply from the prober, so that light emission is monitored from both surfaces of the semiconductor substrate 2 to check the operation state. Becomes possible.

By using the analysis glass substrate GS with a self-judgment circuit of the tenth embodiment, failure analysis can be performed without using an expensive LSI tester if the operation is simple. In addition, the analysis time can be reduced. Further, the analysis can be performed not only in the standby state but also in various states. By combining with the various analysis methods such as OBIRCH described above, the analysis range can be expanded.

In the tenth embodiment, the glass substrate G
Needle support pad NP to the surface side of the S _6, the bump electrode B, is not limited to the configuration of forming the wiring L and self determination circuit 157, for example, a self determination circuit 157 is formed on the back side of the glass substrate GS ₆ Alternatively, it may be connected to the bump electrode B, the wiring L, and the semiconductor substrate 2 through a through hole. Also, the semiconductor substrate 2 as adhered to a glass substrate GS _6, the self determination circuit 157 may be secured to the glass substrate GS ₆ using, for example, the bump electrode. In this way, various self-determination circuits 157 can be connected to the glass substrate G according to the analysis contents.
Since it is possible to mount the S _6, the glass substrate GS is obtained for versatile analysis.

The invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0174]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) According to the present invention, processing by the plasma CVM method and mechanical polishing by a grinding wheel are combined to form a plasma CV.
Materials that are difficult to process by the M method are mechanically polished with a grinding wheel, and after the Si constituting the semiconductor substrate is exposed, the semiconductor substrate is thinned by performing processing by the plasma CVM method. Processing can be performed continuously irrespective of the layer structure. (2) According to the present invention, the residue generated by the processing by the plasma CVM method can be removed by a grinding wheel, so that the semiconductor substrate can be processed in a mirror-finished state. (3) According to the present invention, since the processed surface of the semiconductor substrate can be locally optically observed, the defocus amounts of the objective lens at a plurality of observation positions on the processed surface of the semiconductor substrate are compared. This makes it possible to detect the inclination of the semiconductor substrate or the undulation occurring in the semiconductor substrate. (4) According to the present invention, since the inclination or undulation of the semiconductor substrate to be processed can be detected, the stage on which the semiconductor substrate is mounted is driven based on the detection result to level the processed surface of the semiconductor substrate. Thus, a process with a uniform depth can be performed in a process region of the semiconductor substrate. (5) According to the present invention, since the processed surface of the semiconductor substrate can be optically observed, the processed depth can be detected from the amount of movement of the optical system for observing the processed surface before and after processing. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIGS. 4A to 4C are sets of side and front views of the grinding wheel shown in FIG. 1, respectively.

FIG. 5A is a plan view of a main part of a glass substrate for back surface analysis used for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. It is principal part sectional drawing at the time of fixing.

FIG. 6 is a configuration diagram showing an example of the optical system shown in FIG. 1 in detail.

FIG. 7 is a configuration diagram showing an example of the optical system shown in FIG. 1 in detail.

FIG. 8 is a configuration diagram showing an example of the optical system shown in FIG. 1 in detail.

FIG. 9 is a cross-sectional view of a main part showing a modification of the grinding wheel shown in FIGS. 1 and 4;

FIG. 10 is a sectional view of a main part showing a modified example of the grinding wheel shown in FIGS. 1 and 4;

FIG. 11 is a configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

FIG. 12 is a configuration diagram showing a modification of the configuration near the plasma generation chamber shown in FIG. 11;

FIG. 13 is a configuration diagram when the plasma generation chamber shown in FIG. 11 is replaced with a high-frequency coil.

14 is a configuration diagram when the plasma generation chamber and the electrodes shown in FIG. 11 are replaced with a radical generation chamber and an ultraviolet light source, respectively.

FIG. 15 is a configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.

FIG. 16 is an enlarged cross-sectional view of a main part of the tool shown in FIG. 15;

17A and 17B are a cross-sectional view and a plan view of a main part, respectively, showing a modified example of the tool shown in FIG.

18A is a sectional view of a main part showing a modification of the tool shown in FIG. 15, and FIGS. 18B and 18C are plan views of a main part showing a modification of the tool shown in FIG. FIG.

19A and 19B are a cross-sectional view and a plan view of a main part, respectively, showing a modification of the configuration near the tool shown in FIG.

20 (a), (b) and (c) are cross-sectional views of a main part showing a modification of the configuration of the tool shown in FIG. 19, and a cross-section of the main part explaining a gap between the tool and the sample. FIG. 4 is an explanatory diagram showing a relationship between a gap and a reflected light amount.

FIG. 21 is a cross-sectional view of a main part showing a modification of the configuration of the tool shown in FIG. 19;

FIG. 22 is a cross-sectional view of a principal part showing a modification of the configuration of the tool shown in FIG. 19;

FIG. 23 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor device according to one embodiment of the present invention;

24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23;

25 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 24;

26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 25;

27 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 26;

FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27;

FIG. 29A is a plan view of a main part of a semiconductor manufacturing apparatus according to another embodiment of the present invention, and FIG. 29B is a cross-sectional view of the main part.

FIG. 30 is a fragmentary cross-sectional view showing the semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view showing a semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view showing the semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view showing the semiconductor manufacturing method according to another embodiment of the present invention;

34A is a plan view of a main part of a semiconductor manufacturing apparatus according to another embodiment of the present invention, and FIG. 34B is a cross-sectional view of the main part.

FIG. 35 is a fragmentary cross-sectional view showing a semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view showing the semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 37 is a plan view of relevant parts of a semiconductor manufacturing apparatus according to another embodiment of the present invention;

FIG. 38 is a main part plan view of a semiconductor manufacturing apparatus according to another embodiment of the present invention;

FIG. 39 is a cross-sectional view of main parts of a semiconductor manufacturing apparatus according to another embodiment of the present invention.

FIG. 40 is a plan view of relevant parts of a semiconductor manufacturing apparatus according to another embodiment of the present invention.

FIG. 41 is a fragmentary cross-sectional view showing a semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view showing the semiconductor manufacturing method according to another embodiment of the present invention;

FIG. 43 (a) is a plan view of a main part of a semiconductor manufacturing apparatus according to another embodiment of the present invention, and FIG. 43 (b) is a cross-sectional view of the main part.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 grinding wheel (first tool) 1A base metal (first member) 1B grinding wheel (second member) 2 semiconductor substrate 3 high-frequency power supply 4 etching gas 5 inert gas 6A groove 6B pit 7A cylinder 7B cylinder 8A valve 8B valve 9 piping 9A Piping 9B Piping 10 Nozzle 10A Nozzle 10B Nozzle 11 Hood 12 Exhaust Device 13 Exhaust Pipe 14 Piping 15 Vacuum Pump 16 Vacuum Chuck (Holding Mechanism) 17 Earth 18 Stage 19 XY Stage (First Stage) 20 Tilt Stage (Second Stage) Unit) 20A to 20C Driving mechanism 21 Optical system (observation mechanism) 22 Objective lens 22A Condensing lens 23 Illumination light source 24 Camera 25 Camera controller 26 Monitor 27 Driving mechanism (vertical moving means) 28 Encoder 30 Illumination unit 31 Half mirror 32 Bright light 33 Reflected light 34A to 34C Observation position 35 Alignment mark 36 Reference light source 37 Color filter 38 Opening plate 39 Half mirror 40 Reference light unit 41 Reference light 42 Reflected light 43 Projection unit 44 Light quantity measuring device 45 Opening plate 46 Electrode 47 Plasma generation Chamber 50 Chamber 51 Door 52 Mixing chamber 53 Tube 54 High frequency coil 61 Sample 62 Tool (first tool) 62A Base metal (first member) 62B Grindstone (second member) 63 Motor 64 Shaft 65 Nut 66 Joint 67 Vent hole 68 Groove 70 Case 71 Rotary Wing 72 Seal Bearing 73 Vent Hole 75 Condensing Lens 76 Light Transmission Window 77 Reflected Light 78 Photo Detector 80A Objective Lens 80B Objective Lens 80C Lens 80D Lens 81 Fin 82 Light Transmission Window 83 Case 84 Lens Tube 85 Relay Wren 94 silicon oxide film 95 a silicon oxide film 96 isolation trench 97 p-type well 99 a gate oxide film 100 gate electrode 101A cap insulating film 101B sidewall spacers 102 n ^- -type semiconductor region 103 n ⁺ -type semiconductor region 104 insulating film 105 connection hole 106 Plug 106A Barrier conductive film 106B Conductive film 107 Etch stopper film 108 Insulating film 109 Wiring groove 110 Barrier conductive film 111 Conductive film 112 Embedded wiring 113 Through hole 114 Analysis pad 115 Probe card 120 Chip bonding device 121 Collet 122 Substrate holder 123 Exhaust port 124 Heater 125 Exhaust port 126 Heater 130 Polisher 131 Stage 140 Analyzer 141 Stage 142 Prober (probe card) 143 Open Mouth 144, 145 Analysis means 146 Opening 147 Jig 148 Stage 149 Opening 150 Chip bonding apparatus 151 Collet 152 Substrate holder 153 Vacuum suction section 154, 156 Heater 157 Self-determination circuit B Solder bump (bump electrode) d Defocus amount G Gap GS backside analysis glass substrate GS ₁ ~GS ₆ glass substrate S open board L wiring (conductive pattern) NP needle support pad M1~M7 wiring P ₁ pad Qn n-channel type MISFET Qp p-channel type MISFET RP radical producing chamber TH through hole UV UV light source

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/3065 H01L 21/88 K 21/3205 21/302 B (72) Inventor Shingo Yorizaki Josui, Kodaira-shi, Tokyo 5-20-1, Honmachi, Hitachi, Ltd., Semiconductor Group, Inc. (72) Inventor Takeshi Suzuki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo, Ltd., Hitachi, Ltd., Semiconductor Group (72) Inventor, Satoshi Kogushi Hitachi, Ltd. Semiconductor Group Co., Ltd. (72) Inventor Toshinobu Mizumura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. (Reference) 5F004 DB08 EA27 EA40 5F033 HH11 HH12 HH21 HH32 JJ19 JJ33 KK01 MM01 MM12 MM13 NN06 NN07 PP06 PP15 QQ09 QQ11 QQ12 QQ25 QQ37 QQ47 RR04 RR06 RR11 SS11 SS15

Claims (8)

[Claims] 1. A semiconductor substrate having a semiconductor element or a wiring and an insulating film on its main surface, comprising a first member made of a conductive material and abrasive grains fixed to an outer peripheral portion of the first member. Performing a process using a first tool having a second member to partially or entirely thin the semiconductor substrate, wherein the step of thinning the semiconductor substrate comprises: (a) a process gas containing radicals; Supplying a second member to the surface to be polished of the semiconductor substrate to etch a predetermined region of the surface to be polished, and (b) a predetermined region of the surface to be polished while the second member is in contact with the surface to be polished. Mechanically polishing the region of (c); and (c) contacting the second member with the surface to be polished under the condition that the semiconductor substrate is etched by supplying a process gas containing the radical to the surface to be polished. Let A method of mechanically polishing a predetermined area of the surface to be polished in a state, the method including two or more selected steps. 2. A semiconductor device having a semiconductor element or a wiring and an insulating film on its main surface, comprising a first member made of a conductive material and abrasive grains fixed to an outer peripheral portion of the first member. Performing a process using a first tool having a second member to partially or entirely thin the semiconductor substrate, wherein the step of thinning the semiconductor substrate comprises: (a) a process gas containing radicals; Supplying a second member to the surface to be polished of the semiconductor substrate to etch a predetermined region of the surface to be polished, and (b) a predetermined region of the surface to be polished while the second member is in contact with the surface to be polished. Mechanically polishing the region of (c); and (c) contacting the second member with the surface to be polished under the condition that the semiconductor substrate is etched by supplying a process gas containing the radical to the surface to be polished. Let A step of mechanically polishing a predetermined area of the surface to be polished in the state; and a step of removing residues generated in the steps (a) to (c) by the first tool. A method for manufacturing a semiconductor device, comprising: removing a semiconductor device; 3. A first member made of a conductive material and abrasive grains fixed to an outer peripheral portion of the first member with respect to a first semiconductor substrate having a semiconductor element or a wiring and an insulating film on its main surface. Processing using a first tool having a second member made of the first semiconductor substrate to partially or completely thin the first semiconductor substrate, and performing an inspection on the thinned first semiconductor substrate. And a step of using the result of the inspection as a processing condition for the second semiconductor substrate. The step of thinning the first semiconductor substrate includes: (a) applying a process gas containing radicals to the first semiconductor substrate; A step of etching a predetermined region of the surface to be polished by supplying the surface to the surface to be polished; (b) mechanically moving the predetermined region of the surface to be polished while the second member is in contact with the surface to be polished; Polishing step, (c) the radio In a situation where the first semiconductor substrate is etched by supplying a process gas containing Cu to the surface to be polished, a predetermined region of the surface to be polished in a state where the second member is in contact with the surface to be polished Mechanically polishing the above, comprising two or more selected steps;
(C) A method for manufacturing a semiconductor device, comprising: removing a residue generated in the step with the first tool. 4. A semiconductor substrate having a semiconductor element or a wiring and an insulating film on a main surface thereof, comprising a first member made of a conductive material and abrasive grains fixed to an outer peripheral portion of the first member. A step of thinning the semiconductor substrate partially or entirely by performing processing using a first tool having a second member, wherein the step of thinning the semiconductor substrate includes the steps of: Adjusting a tilt of the semiconductor substrate with respect to a processing surface; (b) etching a predetermined region of the polished surface by supplying a process gas containing radicals to the polished surface of the semiconductor substrate;
(C) mechanically polishing a predetermined region of the polished surface while the second member is in contact with the polished surface;
(D) in a state where the semiconductor substrate is etched by supplying the process gas containing the radical to the surface to be polished, the second member is brought into contact with the surface to be polished and the predetermined surface of the surface to be polished is fixed. And a step of mechanically polishing the region. 5. A semiconductor device having a semiconductor element or a wiring and an insulating film on its main surface, comprising a first member made of a conductive substance and abrasive grains fixed to an outer peripheral portion of the first member. Performing a process using a first tool having a second member to partially or entirely thin the semiconductor substrate, wherein the step of thinning the semiconductor substrate comprises: (a) a process gas containing radicals; Supplying a second member to the surface to be polished of the semiconductor substrate to etch a predetermined region of the surface to be polished, and (b) a predetermined region of the surface to be polished while the second member is in contact with the surface to be polished. Mechanically polishing the region of (c); and (c) contacting the second member with the surface to be polished under the condition that the semiconductor substrate is etched by supplying a process gas containing the radical to the surface to be polished. Let Mechanically polishing a predetermined region of the surface to be polished in a state, comprising the steps of: mechanically polishing a predetermined region of the surface to be polished, and optically moving the position of the surface to be polished before and after the step of thinning the semiconductor substrate. A method of manufacturing a semiconductor device, comprising detecting a processing amount of the semiconductor substrate by detecting the amount of processing. 6. An analysis board is provided in which a needle contact pad, an electrode corresponding to a pad of a semiconductor substrate to be analyzed, and a wiring connecting the needle contact pad and the electrode are formed. (B) mounting the semiconductor substrate to be analyzed on the analysis substrate in a face-down manner, and electrically connecting pads of the semiconductor substrate and electrodes of the analysis substrate; (c) A) thinning the semiconductor substrate to a predetermined thickness by grinding a back surface of the semiconductor substrate mounted on the analysis substrate;
(D) a step of performing power supply and signal transmission / reception to the semiconductor substrate through the needle contact pad and irradiating light of a predetermined wavelength to the back surface or the front surface of the semiconductor substrate to analyze an integrated circuit formed on the semiconductor substrate; A method for manufacturing a semiconductor device, wherein the analysis substrate includes an opening at a position corresponding to an analysis target region of the semiconductor substrate. 7. An analysis board is provided in which a needle contact pad, an electrode corresponding to a pad of a semiconductor substrate to be analyzed, and a wiring connecting the needle contact pad and the electrode are formed. (B) mounting the semiconductor substrate to be analyzed on the analysis substrate in a face-down manner, and electrically connecting pads of the semiconductor substrate and electrodes of the analysis substrate; (c) A) thinning the semiconductor substrate to a predetermined thickness by grinding a back surface of the semiconductor substrate mounted on the analysis substrate;
(D) a step of performing power supply and signal transmission / reception to the semiconductor substrate through the needle contact pad and irradiating light of a predetermined wavelength to the back surface or the front surface of the semiconductor substrate to analyze an integrated circuit formed on the semiconductor substrate; Including, the analysis substrate is made of an optically transparent glass substrate, the electrode,
A method of manufacturing a semiconductor device, wherein the wiring is formed at a position corresponding to a region to be analyzed on the semiconductor substrate, and the wiring is formed of an optically transparent film. 8. An analysis substrate having a needle contact pad, an electrode corresponding to a pad of a semiconductor substrate to be analyzed, and a wiring connecting between the needle contact pad and the electrode is prepared. (B) mounting the semiconductor substrate to be analyzed on the analysis substrate in a face-down manner, and electrically connecting pads of the semiconductor substrate and electrodes of the analysis substrate; (c) A) thinning the semiconductor substrate to a predetermined thickness by grinding a back surface of the semiconductor substrate mounted on the analysis substrate;
(D) a step of performing power supply and signal transmission / reception to the semiconductor substrate through the needle contact pad and irradiating light of a predetermined wavelength to the back surface or the front surface of the semiconductor substrate to analyze an integrated circuit formed on the semiconductor substrate; A method for manufacturing a semiconductor device, wherein a circuit for determining whether the integrated circuit operates properly is provided on a part of the analysis substrate.