JP2002247002A - Asynchronous signal transmission device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To transmit an asynchronous signal while maintaining small size and low power consumption of a device even when the speed of a tributary signal is increased. SOLUTION: In an asynchronous signal transmission device for mapping / demapping and transmitting an asynchronous tributary signal with respect to a transmission rate of a transmission frame, when mapping, an asynchronous signal mapping unit first performs parallel conversion by a serial / parallel conversion circuit. Further, while performing a mapping process on the memory 104 as a tributary signal of a lower speed, the phase comparison circuit 106 detects a phase difference between writing and reading with respect to the memory 104, and based on the detection result, determines the phase of the tributary signal. Upon knowing the advance or delay, the stuff control circuit 107 instructs stuff insertion and deletion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous high-speed tributary signal received in a transmission frame, and an asynchronous high-speed tributary signal is extracted from the transmission frame and output, thereby transmitting the asynchronous tributary signal. More particularly, the present invention relates to an asynchronous signal transmission device having an asynchronous signal mapping circuit and an asynchronous signal demapping circuit.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a configuration of a conventional asynchronous mapping circuit which accommodates an input asynchronous high-speed tributary signal in a transmission frame and outputs it as a transmission line output signal speed-converted into a transmission line clock. FIG. 10 is a block diagram showing a configuration of a conventional asynchronous signal demapping circuit for extracting and outputting an asynchronous high-speed tributary signal from the transmission frame.

In the conventional asynchronous signal mapping circuit shown in FIG. 9, a tributary clock signal extracted from a tributary input signal is used to input a tributary clock according to an address from a write counter 103 for generating a write address of a memory 104. The signals are sequentially stored in the memory 104, and are sequentially read according to an address from a read counter 105 that generates a read address of the memory based on a transmission line clock input. When the frequency of the tributary clock and the frequency of the transmission path clock are asynchronous, the phases of the write address and the read address gradually approach, a memory slip occurs, and data read from the memory 104 is lost or duplicated. To prevent this, the phase comparison circuit 106 includes the write counter 103 and the read counter 10.
When the phase difference exceeds a predetermined threshold value, a stuff request signal is output to the stuff control 107. The stuff control circuit 107 controls the address value of the read counter 105 at the stuff control timing from the frame counter 111 based on the stuff request signal, and inserts a dummy signal into the output of the memory 104.

On the other hand, in the conventional asynchronous signal demapping circuit shown in FIG. 10, an address from a write counter 207 for generating a write address of a memory 208 based on a transmission line clock input extracted from a transmission line input signal. , The transmission line input signal is sequentially stored in the memory 208 and sequentially read out according to the address from the read counter 209 which generates the read address of the memory 208 based on the tributary clock. The dummy signal inserted in the asynchronous signal mapping circuit shown in FIG. 9 is detected by the destuff control circuit 204. Without deleting. The phase difference between the write counter 207 and the read counter 209 which fluctuates due to the dummy signal deletion is detected by the phase comparison circuit 210, smoothed by the low-pass filter 211, and
By controlling the oscillation frequency of No. 2, the tributary clock is reproduced.

[0005]

However, in the asynchronous signal mapping circuit or the asynchronous signal demapping circuit constituting the conventional asynchronous signal transmission apparatus described above,
When the clock speed of the tributary clock or the transmission line clock increases, it is necessary to configure the elements constituting the circuit with ECL components or GaAs material elements in order to cope with the increase in the clock speed. Since the power consumption of the transmission device is increased and the integration is difficult, there is a problem that the size and power consumption of the device are hindered.

[0006] The present invention has been made in view of the above,
Even if the speed of the tributary signal increases,
It is an object of the present invention to provide an asynchronous signal transmission device capable of transmitting an asynchronous signal while maintaining a small size and low power consumption of the device.

[0007]

In order to achieve the above object, an asynchronous signal transmission apparatus according to the present invention provides an asynchronous signal transmission for mapping / demapping and transmitting a tributary signal which is asynchronous with respect to the transmission speed of a transmission frame. In the device, while performing a receiving conversion of the input asynchronous tributary input signal, outputting a tributary signal, extracting a clock from the tributary input signal, and outputting as a tributary clock, tributary receiving means, and the tributary receiving means First clock dividing means for dividing the output first tributary clock and outputting the divided clock as a divided tributary clock; and dividing the tributary signal output by the tributary receiving means into the divided tributary clock. Serial-to-parallel conversion based on the tally clock A first serial-to-parallel converter for outputting a tributary signal, a second clock divider for dividing a transmission line input clock asynchronous with the tributary clock, and outputting the divided clock as a divided transmission line input clock; The parallel tributary signal is mapped to a predetermined transmission frame based on the divided tributary clock,
An asynchronous signal mapping unit that outputs a parallel tributary signal after mapping based on the divided transmission line input clock, and a parallel tributary signal output from the asynchronous signal mapping unit based on the divided transmission line input clock. A second parallel / serial converter for performing parallel / serial conversion and outputting the serial tributary signal as a serial tributary signal; and a transmission path transmitting means for transmitting / outputting the serial tributary signal output from the second parallel / serial converter as a transmission path signal to a transmission path When,
And a transmission-side device having a transmission line signal that is input through the transmission line to perform reception conversion, and outputs the reception-converted serial tributary signal, and converts the transmission line input clock from the transmission line signal. Transmission path receiving means for extracting and outputting, third clock frequency dividing means for dividing the frequency of the transmission path input clock and outputting the divided frequency divided transmission path input clock, and third clock frequency division Second serial-to-parallel conversion means for serial-to-parallel conversion of the serial tributary signal output from the transmission path receiving means based on the frequency-divided transmission path input clock output from the means, and outputting as a parallel tributary signal; The parallel tributary signal output from the second serial / parallel converter is demapped based on the frequency-divided transmission line clock output from the third clock frequency divider. An asynchronous signal demapping means for outputting a parallel tributary signal after the tapping, extracting and outputting a tributary clock from the demapped parallel tributary signal, and multiplying the tributary clock output from the asynchronous signal demapping means. A clock multiplying means for outputting the multiplied clock as a multiplied tributary clock; and a parallel to serial conversion of a parallel tributary signal output from the asynchronous signal demapping means based on the multiplied tributary clock. A second parallel-to-serial converter for outputting as a signal; and a tributary transmitting unit for transmitting and outputting a serial tributary signal output from the second parallel-to-serial converter based on the multiplied tributary clock. Having a receiving device And it features.

According to the present invention, in the transmitting device,
The tributary receiving means performs reception conversion of the input asynchronous tributary input signal, outputs a tributary signal, extracts a clock from the tributary input signal, outputs the clock as a tributary clock, and outputs the tributary clock. Divides the first tributary clock output by the tributary receiving means, and outputs the divided clock as a divided tributary clock;
The first serial-to-parallel converter converts the tributary signal output from the tributary receiver into a serial-to-parallel converter based on the frequency-divided tributary clock, and outputs the parallel tributary signal. The asynchronous transmission line input clock is frequency-divided from the tributary clock and output as a divided transmission line input clock, and the asynchronous signal mapping unit converts the parallel tributary signal into a predetermined signal based on the divided tributary clock. Mapping to a transmission frame, outputting as a parallel tributary signal after mapping based on the divided transmission path input clock,
Parallel-to-serial conversion means converts the parallel tributary signal output from the asynchronous signal mapping means to parallel-serial conversion based on the frequency-divided transmission path input clock, and outputs the serial tributary signal as a serial tributary signal. The serial tributary signal output from the second parallel-to-serial converter is transmitted and output to the transmission line as a transmission line signal. On the other hand, in the receiving device, the transmission path receiving means performs reception conversion of the transmission path signal input via the transmission path, outputs this reception-converted serial tributary signal, and Extracting and outputting a transmission line input clock, a third clock frequency dividing means divides the transmission line input clock, and outputs the divided frequency divided transmission line input clock;
A second serial-to-parallel conversion unit that performs serial-to-parallel conversion on the serial tributary signal output from the transmission line receiving unit based on the frequency-divided transmission line input clock output from the third clock frequency division unit; A parallel tributary signal is output as a parallel tributary signal, and the asynchronous signal demapping means outputs the parallel tributary signal output from the second serial / parallel conversion means based on the frequency-divided transmission line clock output from the third clock frequency dividing means. The signal is demapped, a parallel tributary signal after the demapped is output, and a tributary clock is extracted and output from the demapped parallel tributary signal, and the clock multiplying means outputs from the asynchronous signal demapping means. The multiplied tributary clock is multiplied, and the multiplied clock is output as a multiplied tributary clock. And a second parallel / serial conversion means for performing parallel / serial conversion of the parallel tributary signal output from the asynchronous signal demapping means on the basis of the multiplied tributary clock, and outputting the serial tributary signal as a serial tributary signal; However, based on the multiplied tributary clock, a serial tributary signal output from the second parallel / serial conversion means is transmitted and output.

An asynchronous signal transmission device according to the next invention is an asynchronous signal transmission device for mapping and transmitting an asynchronous tributary signal with respect to a transmission rate of a transmission frame. To output a tributary signal, extract a clock from the tributary input signal, output the tributary clock, and divide the first tributary clock output by the tributary receiving means. First clock frequency dividing means for outputting the frequency-divided clock as a frequency-divided tributary clock, and serial-to-parallel conversion of the tributary signal output by the tributary receiving means based on the frequency-divided tributary clock, as a parallel tributary signal. The first serial-parallel converter to output A second clock divider for dividing a transmission line input clock asynchronous with the tributary clock and outputting the divided clock as a divided transmission line input clock; and the parallel tributary clock based on the divided tributary clock. Map the signal into a given transmission frame,
An asynchronous signal mapping unit that outputs a parallel tributary signal after mapping based on the divided transmission line input clock, and a parallel tributary signal output from the asynchronous signal mapping unit based on the divided transmission line input clock. A second parallel / serial converter for performing parallel / serial conversion and outputting the serial tributary signal as a serial tributary signal; and a transmission path transmitting means for transmitting / outputting the serial tributary signal output from the second parallel / serial converter as a transmission path signal to a transmission path And characterized in that:

According to the present invention, the tributary receiving means performs reception conversion of the input asynchronous tributary input signal, outputs a tributary signal, extracts a clock from the tributary input signal, and outputs the clock as a tributary clock. And the first clock frequency dividing means
The first tributary clock output by the tributary receiving means is divided, and the divided clock is output as a divided tributary clock. The first serial / parallel conversion means outputs the tributary clock output by the tributary receiving means. The signal is serial-to-parallel converted based on the divided tributary clock, and is output as a parallel tributary signal. Output as a divided transmission line input clock, and the asynchronous signal mapping means maps the parallel tributary signal to a predetermined transmission frame based on the divided tributary clock, based on the divided transmission line input clock. A parallel tributary signal after the mapping is output, and the second parallel / serial conversion means outputs the asynchronous signal. The parallel tributary signal output from the tapping means is parallel-to-serial converted based on the frequency-divided transmission path input clock and output as a serial tributary signal, and the transmission path transmission means is output from the second parallel-serial conversion means. The serial tributary signal is transmitted and output to the transmission line as a transmission line signal.

According to another aspect of the present invention, there is provided an asynchronous signal transmission apparatus for demapping and transmitting a tributary signal which is asynchronous with respect to a transmission rate of a transmission frame. Transmission path receiving means for performing signal reception conversion, outputting the reception converted serial tributary signal, and extracting and outputting the transmission path input clock from the transmission path signal;
Third clock frequency dividing means for dividing the transmission line input clock and outputting the divided frequency divided transmission line input clock, and a frequency division transmission line input clock output from the third clock frequency dividing means A second serial-to-parallel converter for serial-to-parallel conversion of the serial tributary signal output from the transmission path receiver and outputting the parallel tributary signal, and an output from the third clock divider. The parallel tributary signal output from the second serial / parallel conversion means is demapped based on the frequency-divided transmission path clock, and the demapped parallel tributary signal is output, and the demapped parallel tributary signal is output. Signal demapping means for extracting and outputting a tributary clock from the A clock multiplying means for multiplying the buttery clock and outputting the multiplied clock as a multiplied tributary clock; and Second parallel / serial conversion means for converting and outputting as a serial tributary signal; and tributary transmission means for transmitting / outputting a serial tributary signal output from the second parallel / serial conversion means based on the multiplied tributary clock. And characterized in that:

According to the present invention, the transmission path receiving means performs reception conversion of the transmission path signal input via the transmission path, outputs the reception-converted serial tributary signal, and outputs the transmission path signal. And a third clock dividing means divides the transmission line input clock, outputs the divided frequency divided transmission line input clock, and outputs a second serial clock. The parallel converting means converts the serial tributary signal output from the transmission path receiving means from serial to parallel based on the frequency-divided transmission path input clock output from the third clock frequency dividing means, and converts the serial tributary signal into a parallel tributary signal. The asynchronous signal demapping means outputs the parallel signal output from the second serial-parallel conversion means based on the frequency-divided transmission line clock output from the third clock frequency dividing means. De-mapping the Byutari signal,
A parallel tributary signal after the demapping is output, and a tributary clock is extracted and output from the demapped parallel tributary signal. The multiplied clock is output as a multiplied tributary clock, and the second parallel / serial conversion means parallelizes the parallel tributary signal output from the asynchronous signal demapping means based on the multiplied tributary clock. The serialized tributary signal is output as a serial tributary signal, and the tributary transmission means transmits and outputs the serial tributary signal output from the second parallel-serial conversion means based on the multiplied tributary clock.

[0013] In the asynchronous signal transmission apparatus according to the next invention, in the above invention, the asynchronous signal mapping means further performs serial-to-parallel conversion on the input parallel tributary signal, and outputs the result as a low-speed parallel tributary signal. A first dividing circuit for further dividing the frequency-divided tributary clock and outputting the divided clock as a low-speed tributary clock; and generating a write address using the low-speed tributary clock. A write counter, a second frequency divider for further dividing the frequency-divided transmission line input clock, and outputting the frequency-divided clock as a low-speed transmission line input clock; and a read address using the low-speed transmission line input clock. And a read counter that generates an output from the serial / parallel conversion circuit based on the write address. A low-speed parallel tributary signal stored therein, and a memory for outputting the stored low-speed parallel tributary signal based on the read address; and a phase difference between the write address and the read address. A phase comparison circuit that outputs a stuff request signal indicating stuff insertion / deletion according to the phase difference when the predetermined value is exceeded, and a low-speed frequency-divided transmission line input clock output from the second frequency divider are also used. And a frame counter that counts the number of bits of the transmission frame and outputs a control timing of insertion / deletion of the stuff, and inserts a dummy signal based on the stuff request signal and control timing from the frame counter. A stuff control circuit for outputting a control instruction to the read counter; and A register array for shifting the read low-speed parallel tributary signal by a predetermined bit and outputting the same, and a low-speed parallel tributary signal output from the register array based on a dummy signal insertion control instruction output from the stuff control circuit. And a parallel-to-serial conversion circuit that performs parallel-to-serial conversion on the low-speed parallel tributary signal output from the selector based on the low-speed frequency-divided transmission line input clock, and outputs the result as a high-speed parallel tributary signal. It is characterized by having.

According to the present invention, in the asynchronous signal mapping means, the serial-to-parallel conversion circuit further performs serial-to-parallel conversion on the input parallel tributary signal, and outputs the parallel tributary signal as a low-speed parallel tributary signal. Further divides the divided tributary clock, outputs the divided clock as a low-speed tributary clock, and a write counter generates a write address using the low-speed tributary clock, A frequency divider further divides the frequency-divided transmission line input clock, outputs the frequency-divided clock as a low-speed transmission line input clock, and a read counter generates a read address using the low-speed transmission line input clock. A memory configured to store the low-speed parallel tributary signal output from the serial-to-parallel conversion circuit based on the write address; And outputs the stored low-speed parallel tributary signal based on the read address. A phase comparison circuit detects a phase difference between the write address and the read address, and the phase difference is a predetermined value. When the signal exceeds the threshold value, a stuff request signal indicating insertion / deletion of stuff is output according to the phase difference, and the frame counter outputs the stuff request signal based on the low-speed frequency-divided transmission line input clock output from the second frequency divider. Counting the number of bits of the transmission frame, outputting the control timing of insertion / deletion of the stuff, and the stuff control circuit inserts a dummy signal based on the stuff request signal and the control timing from the frame counter. A control instruction is output to the read counter, and the register array reads the low speed read from the memory based on the low speed divided transmission line clock. The column tributary signal by a predetermined bit shifted output, selector,
Based on a dummy signal insertion control instruction output from the stuff control circuit, a low-speed parallel tributary signal output from the register array is selectively output, and a parallel-serial conversion circuit converts the low-speed frequency-divided transmission line input clock. Originally, the low-speed parallel tributary signal output from the selector is parallel-to-serial converted and output as a high-speed parallel tributary signal.

In the asynchronous signal transmission apparatus according to the next invention, in the above-mentioned invention, the asynchronous signal mapping means includes a second memory provided between the selector and the parallel-to-serial conversion circuit; A second write counter for generating a write address of the memory, and a variable frequency divider that divides the frequency of the frequency-divided transmission path input clock, and divides the variable frequency-divided low-speed variable frequency-divided transmission path input clock into the frame counter and the read. Counting the number of bits of the transmission frame based on a counter and a variable frequency dividing circuit for outputting to the second write counter, and a low frequency frequency dividing transmission line input clock output from the second frequency dividing circuit; A second frame counter for counting the overhead area, the tributary area and the FEC area of the transmission frame; and a count value of the second frame counter. A second read counter for generating a read address for reading the low-speed parallel tributary signals stored in the second memory, a phase difference between said second write counter and the second read counter is detected,
A second phase comparison circuit for controlling a frequency division ratio of the variable frequency division circuit according to a phase advance / lag.

According to the present invention, in the asynchronous signal mapping means, a second memory is provided between the selector and the parallel / serial conversion circuit, and a second write counter is provided in the second memory. Generate a write address,
A variable frequency dividing circuit variably divides the frequency-divided transmission line input clock and outputs the variable frequency-divided low-speed variable frequency-divided transmission line input clock to the frame counter, the read counter, and the second write counter. And a second frame counter counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock output from the second frequency dividing circuit, and calculates an overhead area of the transmission frame;
Counting a tributary area and an FEC area, a second read counter generating a read address for reading a low-speed parallel tributary signal stored in the second memory based on a count value of the second frame counter; A second phase comparison circuit detects a phase difference between the second write counter and the second read counter, and controls a frequency dividing ratio of the variable frequency dividing circuit according to a leading / lagging phase. I have to.

In the asynchronous signal transmission apparatus according to the next invention, in the above invention, the asynchronous signal demapping means further divides the frequency of the frequency-divided transmission path input clock,
A third frequency dividing circuit for outputting a low-speed divided transmission line input clock; a third frame counter for counting the number of bits of a transmission frame based on the low-speed divided transmission line input clock; A second serial-to-parallel conversion circuit that outputs a low-speed parallel tributary signal obtained by further serial-to-parallel conversion of the parallel tributary signal output from the serial-to-parallel conversion means;
A destuff control circuit for detecting presence / absence of stuff stored in a transmission frame from a low-speed parallel tributary signal output from the second serial-parallel conversion circuit, and performing destuff control; Based on
A second register array that shifts the low-speed parallel tributary signal output from the second serial-parallel conversion circuit by a predetermined bit and outputs the second register array under the control of the destuff control circuit; A second selector for selecting and deleting a stuff from the output low-speed parallel tributary signal; and generating a write address based on the low-speed frequency-divided transmission line input clock and a control instruction from the destuff control circuit. A second write counter, a second read counter that generates a read address, and the second write counter based on a write address generated by the second write counter.
And a third memory for storing the low-speed parallel tributary signal output from the selector of (a) and outputting the stored low-speed parallel tributary signal based on the read address generated by the second read counter. A third phase comparison circuit for detecting a phase difference between the write address generated by the write counter and the read address generated by the second read counter; and a value of the phase difference detected by the third phase comparison circuit. A low-pass filter for smoothing, a voltage-controlled oscillator for outputting a frequency-divided tributary clock having a frequency corresponding to the value smoothed by the low-pass filter, and a frequency-divided tributary clock output by the voltage-controlled oscillator; A fourth frequency divider circuit for outputting the frequency-divided clock to the second read counter as a low-speed frequency-divided tributary clock; A second parallel-serial conversion circuit for converting the low-speed parallel tributary signal read from the third memory into a parallel-serial signal based on the low-speed divided tributary clock output from the path, and outputting a high-speed parallel tributary signal And characterized in that:

According to the present invention, in the asynchronous signal demapping means, the third frequency dividing circuit further divides the frequency of the divided transmission line input clock and outputs the low frequency divided transmission line input clock. The frame counter 3 counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock, and the second serial-to-parallel conversion circuit outputs the parallel A low-speed parallel tributary signal obtained by further serial-to-parallel conversion of the tributary signal is output. Detect, perform destuff control, and the second register array
Based on the low-speed divided transmission path input clock, the low-speed parallel tributary signal output from the second serial-to-parallel conversion circuit is shifted by a predetermined bit and output, and a second selector is provided for the destuff control circuit. Under control, the second
The stuff is selected and deleted from the low-speed parallel tributary signal output from the register array, and the second write counter calculates the stuff based on the low-speed frequency-divided transmission line input clock and a control instruction from the destuff control circuit. A write address is generated, a second read counter generates a read address, and a third memory outputs from the second selector based on the write address generated by the second write counter. The low-speed parallel tributary signal thus stored is stored in the second
And outputting a stored low-speed parallel tributary signal based on the read address generated by the read counter. The third phase comparison circuit outputs the write address generated by the second write counter and the second read Detecting a phase difference from the read address generated by the counter; a low-pass filter smoothing the value of the phase difference detected by the third phase comparison circuit;
A voltage controlled oscillator outputs a frequency-divided tributary clock having a frequency corresponding to the value smoothed by the low-pass filter, and a fourth frequency divider divides the frequency-divided tributary clock output by the voltage controlled oscillator. The divided clock is output to the second read counter as a low-speed divided tributary clock. Originally, the low-speed parallel tributary signal read from the third memory is parallel-to-serial converted and a high-speed parallel tributary signal is output.

In the asynchronous signal transmission apparatus according to the next invention, in the above invention, the asynchronous signal demapping means variably divides the frequency of the frequency-divided transmission line input clock, and variably divides the low-speed variable frequency division transmission. A second variable frequency dividing circuit for outputting a clock input clock, and a reference counter for counting the number of clocks of the second variable frequency dividing circuit, wherein the third phase comparing circuit includes a second write counter. A fourth phase comparison circuit for detecting a phase difference between the second read counter and the reference counter, and a fifth phase comparison circuit for detecting a phase difference between the second read counter and the reference counter. The phase comparison circuit controls the frequency division ratio of the second variable frequency division circuit based on the detected phase difference, and the fifth phase comparison circuit compares the detected phase difference value with the low-pass filter. And outputting the data.

According to the present invention, in the asynchronous signal demapping means, the second variable frequency dividing circuit variably divides the frequency of the frequency dividing transmission line input clock and variably frequency-divides the low-speed variable frequency dividing transmission line. An input clock is output, a reference counter counts the number of clocks of the second variable frequency dividing circuit, and in the third phase comparing circuit, a fourth phase comparing circuit comprises A phase difference from the reference counter is detected, and a frequency division ratio of the second variable frequency dividing circuit is controlled based on the detected phase difference.
The phase comparison circuit detects the phase difference between the second read counter and the reference counter, and outputs the value of the detected phase difference to the low-pass filter.

In the asynchronous signal transmission device according to the next invention, in the above-mentioned invention, the asynchronous signal demapping means includes a second serial-parallel conversion circuit provided between the second serial-parallel conversion circuit and the second register array. 4, and counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock output from the third frequency dividing circuit, and calculates the overhead area, tributary area, and FEC area of the transmission frame. And a third write for generating a write address for the fourth memory based on the low-speed frequency-divided transmission line input clock and the count value of the fourth frame counter. A counter and variably dividing the frequency-divided transmission path input clock;
A third variable frequency dividing circuit for generating a variable frequency-divided low-speed variable frequency division transmission line input clock; and A third read counter for generating a read address of the low-speed parallel tributary signal stored in the fourth memory, and a phase difference between the third write counter and the third read counter are detected. And a sixth phase comparison circuit for controlling a frequency division ratio of the third variable frequency dividing circuit, wherein the third frame counter comprises: The number of bits of the transmission frame is counted based on the transmission path input clock, and the second
Is characterized in that a write address is generated based on a low-speed variable frequency division transmission line input clock output from the third variable frequency frequency dividing circuit.

According to the present invention, in the asynchronous signal demapping means, a fourth memory is provided between the second serial / parallel conversion circuit and the second register array, and a fourth frame counter is provided. Is based on the low-speed frequency-divided transmission line input clock output from the third frequency divider,
The number of bits of the transmission frame is counted, and the overhead area, tributary area, and F of the transmission frame are counted.
Counting the EC area, a third write counter generates a write address for the fourth memory based on the low-speed divided transmission path input clock and the count value of the fourth frame counter, A third variable frequency dividing circuit variably frequency-dividing the frequency-divided transmission line input clock to generate a variable-frequency-divided low-speed variable frequency-divided transmission line input clock; A read address of a low-speed parallel tributary signal stored in the fourth memory is generated based on a low-speed variable frequency-divided transmission line input clock output from the variable frequency divider, and a sixth phase comparison circuit generates the read address. 3 and a phase difference between the third read counter and the third read counter, and a frequency division ratio of the third variable frequency dividing circuit is controlled based on the phase difference. Third
The second write counter counts the number of bits of the transmission frame based on the low-speed variable frequency dividing transmission line input clock output by the variable frequency dividing circuit. The write address is generated based on the frequency-divided transmission line input clock.

In the asynchronous signal transmission apparatus according to the next invention, in the above invention, the asynchronous signal demapping means includes a reference counter for counting the number of clocks of the third variable frequency dividing circuit, and A phase comparison circuit for detecting a phase difference between the third write counter and the reference counter; and an eighth phase detection circuit for detecting a phase difference between the third read counter and the reference counter. A phase comparison circuit, wherein the seventh phase comparison circuit controls a frequency division ratio of the third variable frequency division circuit based on the detected phase difference,
Is characterized by outputting the detected value of the phase difference to the low-pass filter.

According to this invention, in the asynchronous signal demapping means, the reference counter counts the number of clocks of the third variable frequency dividing circuit, and
Of the third variable counter circuit based on the detected phase difference. A seventh phase comparison circuit in the phase comparison circuit detects a phase difference between the third write counter and the reference counter. An eighth phase comparator detects a phase difference between the third read counter and the reference counter, and outputs a value of the detected phase difference to the low-pass filter.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an asynchronous signal transmission device according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of the asynchronous signal transmission device according to the first embodiment of the present invention. In FIG. 1, a transmitting device 100 includes a tributary receiving unit 1, a clock frequency dividing unit 2, a serial / parallel converting unit 3,
It has an asynchronous signal mapping unit 4, a clock frequency dividing unit 5, and a transmission path transmitting unit 7. The tributary receiving unit 1 performs reception conversion of the tributary input signal, outputs the converted tributary signal to the serial / parallel conversion unit 3, and outputs a clock extracted from the tributary input signal to the clock frequency dividing unit 2. The clock divider 2 divides the frequency of the clock extracted from the tributary input signal, and outputs the divided tributary clock to the serial / parallel converter 3 and the asynchronous signal mapping unit 4. The serial-parallel conversion unit 3
Based on the frequency-divided tributary clock, the tributary signal after reception conversion is serial-parallel-converted and output to the asynchronous signal mapping unit 4 as a parallel tributary signal. The asynchronous signal mapping unit 4 maps this parallel tributary signal to a transmission frame and outputs it to the parallel-to-serial conversion unit 6 as a parallel transmission line signal. The clock frequency divider 5 divides the frequency of the transmission path input clock, and divides the frequency-divided transmission path clock into the asynchronous signal mapping section 4 and the transmission path transmitter 7.
Output to The parallel-to-serial converter 6 converts the parallel transmission line signal from serial to parallel based on the frequency-divided transmission line clock, and outputs the signal to the transmission line transmitter 7 as a transmission line signal. The transmission path transmission unit 7 performs transmission conversion of the transmission path signal and sends the transmission signal as a transmission path output signal to the transmission path.

On the other hand, the receiving apparatus 200 includes a transmission path receiving section 8, a clock frequency dividing section 9, a serial / parallel converting section 10, an asynchronous signal demapping section 11, a clock multiplying section 12, a parallel / serial converting section 13, and a tributary transmitting section 14. Having. The transmission path receiving unit 8 performs reception conversion of the transmission path input signal input via the transmission path, outputs the transmission path reception signal after the reception conversion to the serial / parallel conversion unit 10, and converts the transmission path reception signal from the transmission path input signal. The extracted clock is output to the clock divider 9. The clock divider 9 divides the frequency of the clock extracted from the transmission line input signal, and outputs the divided frequency-divided transmission line clock to the serial / parallel converter 10 and the asynchronous signal demapper 11. The serial-to-parallel converter 10 performs serial-to-parallel conversion on the reception-converted transmission path signal based on the frequency-divided transmission path clock, and outputs the signal to the asynchronous signal demapping section 11 as a parallel transmission path signal. Asynchronous signal demapping unit 11
Demaps the parallel tributary signal from the transmission frame of the parallel transmission path signal and outputs it to the parallel-serial conversion unit 13, and also reproduces the frequency-divided tributary clock synchronized with the parallel tributary signal and outputs it to the clock multiplication unit 12. I do. The clock multiplying unit 12 multiplies the divided tributary clock to generate a tributary clock, and outputs the tributary clock to the tributary transmitting unit 14. Parallel / serial converter 13
Converts the parallel tributary signal from serial to parallel based on the tributary clock, and outputs the tributary signal to the tributary transmission unit 14 as a tributary signal. The tributary transmission unit 14 performs transmission conversion of the tributary signal, and outputs the tributary signal after the transmission conversion as a tributary output signal.

Here, the configuration of the transmission frame will be described with reference to FIG. FIG. 2A shows an example of a transmission frame used by the asynchronous transmission device shown in FIG. As shown in FIG. 2A, the transmission frame has an overhead (OH) area and a tributary signal area. The OH byte stores a frame synchronization signal and information for monitoring transmission quality, and the JC byte stores NJ
Information indicating whether the signal is a tributary signal or a dummy signal is stored in the E byte and the PJE byte.
Normally, a dummy signal is stored in the NJO byte, a tributary signal is stored only in the frame in which the negative stuff is performed, and a tributary signal is generally stored in the PJO byte, and the positive stuff is performed. A dummy signal is stored only in a frame. As described above, by performing the positive / negative stuff in accordance with the sign of the frequency deviation between the tributary clock and the transmission line clock, an asynchronous tributary signal can be mapped to the transmission frame. In addition, FIG.
3 shows a mapping state of a tributary signal.

FIG. 3 is a block diagram showing a detailed configuration of the asynchronous signal mapping unit 4 shown in FIG. In FIG. 3, a serial / parallel conversion circuit 101 converts a parallel tributary input signal into a parallel signal with a lower speed and outputs the parallel signal to the memory 104. The frequency dividing circuit 102 divides the frequency of the frequency-divided tributary clock into a lower-speed clock, and
03 is output. The write counter 103 includes the frequency divider 1
A write address of the memory 104 is generated based on the low-speed frequency-divided tributary clock output from the second circuit. The memory 104 stores a low-speed parallel tributary signal input from the serial-to-parallel conversion circuit 101 based on a write address output from the write counter 103. The read counter 105 generates a read address of the memory 104 based on the low-speed frequency-divided transmission line clock output from the frequency dividing circuit 110, and reads low-speed parallel data from the memory 104.
The phase comparison circuit 106 compares the phases of the write counter 103 and the read counter 105, and outputs a positive / negative stuff request signal to the stuff control circuit 107 when the phase difference exceeds a predetermined threshold. Staff control circuit 107
Is the positive / negative stuff request signal and the frame counter 11
A dummy signal insertion control signal is output to the read counter 105 and the selector 109 based on the stuff control timing output from 1. Register array 108 shifts the read data from memory 104 by a predetermined bit and outputs the data to selector 109. The selector 109 selects the bit-shifted data according to a dummy signal insertion control signal from the stuff control, and outputs the data to the parallel-to-serial conversion circuit 112. The frequency dividing circuit 110 divides the frequency of the frequency-divided transmission line clock input into a lower-speed clock, and outputs the frequency-divided low-speed frequency-divided transmission line clock to the read counter 105, the register array 108, and the frame counter 111. The frame counter 111 counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line clock from the frequency dividing circuit 110, and outputs the stuff control timing to the stuff control circuit 107. The parallel-to-serial conversion circuit 112 performs parallel-to-serial conversion on the output of the selector 109 and outputs it as a parallel transmission line output signal.

Here, the mapping process by the asynchronous signal mapping unit 4 shown in FIG. 3 will be described with reference to FIG. As shown in FIG. 2B, the low-speed parallel tributary signal output from the serial-parallel conversion circuit 101 is 128 parallel, and an OH area is added to the signal read from the memory 104. NJO
A dummy signal is stored in the byte, and a tributary signal is stored in the PJO byte. When the frequency ft of the low-speed frequency-divided tributary clock is lower than the low-speed frequency-divided transmission line clock f0, the phase of the read address with respect to the write address gradually advances, and the phase comparison circuit 106 determines that the phase difference is a predetermined threshold. Value is exceeded,
A positive stuff request signal is output to the stuff control circuit 107. In this case, the stuff control circuit 107 stops the count of the read counter 105 at the timing from the frame counter 110 so that the signal read from the memory 104 becomes a dummy signal for all bytes of the PJO byte sequence. The selector 109 selects the data shifted by a predetermined bit in the register array 108 so that a portion other than the PJO byte in the column of the PJO byte becomes a tributary signal.

On the other hand, when the frequency ft of the low-speed frequency-divided tributary clock is higher than the low-speed frequency-divided transmission line clock f 0, the phase of the read address with respect to the write address is gradually delayed. It is detected that the threshold value is exceeded, and a negative stuff request signal is output to the stuff control circuit 107. In this case, the stuff control circuit 1 outputs the output of the memory 104 such that all the columns in the OH area shown in FIG. 2B become tributary signals.
07, the count of the read counter 105 is advanced at the timing from the frame counter 111, and the selector 109
Then, data shifted by a predetermined bit in the register array 108 is selected so that only NJO becomes a tributary signal. The transmission frame mapped in this way is subjected to parallel / serial conversion by the parallel / serial conversion circuit 112, and is output as a parallel transmission line output signal.

FIG. 4 is a block diagram showing a detailed configuration of the asynchronous signal demapping unit 11 shown in FIG. In FIG. 4, a serial / parallel conversion circuit 201 converts a parallel transmission line input signal into a parallel signal of a lower speed and registers the parallel signal.
03 is output. The frequency dividing circuit 202 outputs a low-speed divided transmission line clock obtained by dividing the frequency-divided transmission line clock to a lower-speed divided clock to the write counter 207 and the frame counter 205. The register array 203 shifts the read data of the serial / parallel conversion circuit 201 by a predetermined bit and outputs the data to the selector 206. Destuff control circuit 20
4 detects the presence / absence of positive / negative stuff from the JC byte shown in FIG.
06 and the write counter 207. The frame counter 205 counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line clock output from the frequency dividing circuit 202, and outputs the destuff control timing to the destuff control circuit 204. The selector 206 selects the bit-shifted data according to the dummy signal deletion control signal from the stuff control, and outputs the selected data to the memory 208. The write counter 207 stores the memory 208 based on the low-speed frequency-divided transmission line clock output from the frequency divider 202.
Is generated. The memory 208 stores a signal from the selector 206 based on the write address output from the write counter 207. Read counter 2
09 generates a read address of the memory 208 based on the low-speed divided tributary clock output from the frequency dividing circuit 213 and reads a low-speed parallel tributary signal from the memory 208. The phase comparison circuit 210 includes a write counter 2
07 and the read counter 209, and outputs the phase difference to the low-pass filter 211. The low-pass filter 211 smoothes the phase difference output from the phase comparison circuit 210 and outputs a control voltage to the voltage control oscillator 212. The voltage controlled oscillator 212 includes a low-pass filter 211
And outputs a frequency-divided tributary clock having a frequency corresponding to the control voltage to the frequency-dividing circuit 213. The dividing circuit 213
A low-frequency divided tributary clock obtained by dividing the frequency-divided tributary clock from the voltage controlled oscillator 212 into a lower-speed clock is output to the read counter 209. The parallel-to-serial conversion circuit 214 converts the output of the memory 208 from parallel to serial, and outputs a parallel tributary output signal.

The output signal of the serial / parallel conversion circuit 201 includes:
As shown in FIG. 2B, normally, a dummy signal is stored in the NJO byte, and a tributary signal is stored in the PJO byte. The destuff control circuit 204 determines the presence / absence of positive / negative stuff from a predetermined code stored in the JC byte. The write counter 207 and the selector 206 are controlled. When detecting the negative stuff, the destuff control circuit 204 stores the OH area and the NJO byte in the memory 2.
The write counter 207 and the selector 206 are controlled so as not to write the value 08. When the control of the positive / negative stuff is performed, the phase difference between the write counter 207 and the read counter 209 fluctuates. , The parallel tributary clock with reduced number is reproduced. Based on the reproduced frequency-divided tributary clock, the frequency divider 213 generates a low-speed frequency-divided tributary clock. The read counter 209 generates a read address in accordance with the low-speed frequency-divided tributary clock. Outputs only a tributary signal, and outputs a parallel tributary output signal that has been subjected to parallel / serial conversion by the parallel / serial conversion circuit 214.

In the first embodiment, the parallel tributary signal and the parallel transmission path signal are parallel-expanded at a lower speed.
Register arrays 108 and 203 and selectors 109 and 20
6, a dummy signal of a write signal or a read signal of the memories 104 and 208 is inserted / deleted, so that high integration can be achieved with low power consumption and CMOS.
The asynchronous signal mapping unit 4 and the asynchronous signal demapping unit 11 can be configured using elements and the like, and a small-sized and low power consumption asynchronous signal transmission device can be realized.

Embodiment 2 Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram illustrating a configuration of an asynchronous signal demapping unit of the asynchronous signal transmission device according to the second embodiment of the present invention. The same components as those of the asynchronous signal demapping unit shown in FIG. 4 are denoted by the same reference numerals. In FIG. 5, the asynchronous signal demapping unit includes a variable frequency dividing circuit 217 and a phase comparing circuit 21.
9 and a reference counter 221, and the phase comparison circuit 210 compares the phase of the read counter 209 with the phase of the reference counter 221.

In FIG. 5, the variable frequency dividing circuit 217 further divides the frequency based on the frequency-divided transmission line clock, and outputs the variable frequency-divided low-speed variable frequency-divided clock to the reference counter 221. The phase comparator 219 compares the phase of the reference counter 221 with the phase of the write counter 207 and controls the frequency division ratio of the variable frequency divider 217. The reference counter 221 includes the variable frequency divider 21
The number of low-speed variable frequency-divided clocks output from 7 is counted by a predetermined number of bits, and the counted counter value is output to the phase comparison circuit 219 and the phase comparison circuit 210.

Here, when the positive / negative stuff is controlled, the write counter 207 and the reference counter 22 are controlled.
The phase difference from 1 changes, and the phase comparator 219 detects the phase difference and controls the frequency division ratio of the variable frequency divider 217. For example, when the variable frequency dividing circuit 217 normally divides the frequency by n (n is an integer) and the positive stuff is executed, the phase of the write counter 207 changes to the low-speed frequency dividing transmission line clock 1.
Since the clock is delayed by the clock, the frequency dividing ratio of the variable frequency dividing circuit 217 is set to a predetermined number of times (n + 1) at a predetermined interval so as to follow this.
Is controlled so that Similarly, when the negative stuff is performed, the phase of the write counter 207 advances, so that the frequency division ratio of the variable frequency dividing circuit 217 is controlled to be (n-1) so as to follow this. As a result, the phase of the reference counter 221 gradually follows the phase of the write counter 207 in units of frequency-divided transmission line clocks. Therefore, the amount of phase fluctuation detected by the phase comparison circuit 210 is also in the unit of the frequency-divided transmission line clock, and the amount of phase fluctuation is smoothed by the low-pass filter 211. Can be reduced.

In the second embodiment, the variable frequency dividing circuit 21
7, the amount of phase fluctuation is corrected in units of frequency-divided transmission line clocks and smoothed by the low-pass filter 211, so that the jitter can be reduced.

Embodiment 3 Next, the embodiment of the present invention will be described.
Mode 3 will be described. First, FIG. 6 shows, for example, ITU-
As shown in TG.975, in addition to the addition of the OH
To add an additional FEC area,
Error correction, and compensates for transmission line quality degradation
It is a figure showing an example of the transmission frame made in this way. This
Mapping of asynchronous signals using such transmission frames
When demapping, delete the FEC area on the receiving side
It is necessary to perform
Jitter occurs in the tributary clock that is reproduced in step (1). An example
For example, from the parallel signal shown in FIG.
If removed, phase fluctuation smoothed by low-pass filter
The amount is 16 low-speed divided transmission line clocks.
You.

FIG. 7 is a block diagram showing a configuration of an asynchronous signal mapping unit of the asynchronous signal transmission apparatus according to the third embodiment of the present invention. That can be achieved. This asynchronous signal mapping unit further includes a variable frequency dividing circuit 113, a frame counter 114, a phase comparing circuit 115, a write counter 116, a memory 117, and a read counter 118 in the configuration shown in FIG.

In FIG. 7, a variable frequency dividing circuit 113 has a variable frequency dividing ratio under the control of a phase comparing circuit 115, divides a frequency dividing transmission line clock to generate a low-speed variable frequency dividing clock, and generates a frame counter. 111, the read counter 105, the write counter 116, and the register array 108. The frame counter 114 counts the OH area, the tributary signal area, and the FEC area shown in FIG. 6B based on the low-speed frequency-divided transmission line clock output from the frequency dividing circuit 110.

The phase comparison circuit 115 includes a write counter 1
16 is compared with the phase of the read counter 118, and from this phase difference, the variable frequency divider 11
3 is controlled. The write counter 116 generates a write address of the memory 117 based on the low-speed variable frequency-divided clock. The memory 117 has a write counter 116.
Selector 109 according to the write address output from
, And outputs a stored signal in accordance with the read address output from read counter 118. The read counter 118 stores the memory 117 based on the low-speed frequency-divided transmission line clock output from the frequency divider 110.
To generate a read address.

As in the first embodiment, the output signal of the selector 109 is added with the OH area shown in FIG. 6B, the tributary signal is mapped to the tributary area, and the OH area and the tributary signal area Are stored, and an FEC area is added to the output of the memory 117. The phase comparison circuit 115 compares the phases of the write counter 116 and the read counter 118, and based on the phase difference, controls the frequency division ratio of the variable frequency division counter 113 in accordance with the phase advance / delay. For example, normally, assuming that the dividing ratio is n, (n + 1) or (n−
Since the control is performed so as to satisfy 1), the signal stored in the memory 117 can be read without any loss or duplication. As described above, the FEC area is added after the positive / negative stuff is controlled in the same manner as in the first embodiment. Done.

FIG. 8 is a block diagram showing a configuration of an asynchronous signal demapping unit of the asynchronous signal transmission device according to the third embodiment of the present invention. This asynchronous signal demapping unit includes the asynchronous signal demapping unit shown in FIG.
A variable frequency dividing circuit 217, a frame counter 220, a phase comparing circuit 219, a write counter 215, a memory 216, and a read counter 218 are further provided.

In FIG. 8, a variable frequency dividing circuit 217 has a frequency dividing ratio variable under the control of a phase comparing circuit 219, divides a frequency dividing transmission line clock to generate a low-speed variable frequency dividing clock, and generates a frame counter. 205, the read counter 218, the write counter 207, and the register array 203. The frame counter 220 counts the OH area, the tributary signal area, and the FEC area in FIG. The phase comparing circuit 219 compares the phases of the write counter 215 and the read counter 218, and controls the frequency division ratio of the variable frequency dividing circuit 217 according to the phase lead / lag based on the phase difference.

The write counter 215 generates a write address of the memory 216 based on the low-speed transmission line frequency-divided clock. The memory 216 stores the serial / parallel conversion circuit 201 according to the write address output from the write counter 215.
, And outputs the stored signal in accordance with the read address output from the read counter 218. The read counter 218 generates a read address of the memory 216 based on the variable frequency dividing circuit 217.

The output signal of the serial / parallel conversion circuit 201 is the transmission frame shown in FIG. 6B, and the memory 216 stores an OH area and a tributary signal area.
Delete area C. The phase of the write counter 215 and the phase of the read counter 218 are compared by the phase comparison circuit 219, and the frequency division ratio of the variable frequency division circuit 217 is controlled based on the phase difference in accordance with the lead / lag of the phase. For example, assuming that the frequency division ratio is n, (n + 1) or (n−
Since control is performed so as to satisfy 1), the signal stored in the memory 216 can be read without any loss or duplication. The output signal of the memory 216 is the transmission frame shown in FIG. 2B, and in the subsequent processing, the same processing as the processing shown in Embodiment 1 is performed. Therefore, regardless of the presence or absence of the FEC area, Demapping of the tributary signal to the transmission frame is performed.

In the third embodiment, the asynchronous signal mapping section maps the asynchronous signal to the transmission frame regardless of the FEC area, and the asynchronous signal demapping section converts the asynchronous signal from the transmission frame regardless of the FEC area. Since the data is demapped, the influence of the phase fluctuation due to the addition / deletion of the FEC area to the tributary clock reproduced on the receiving side is eliminated, and the jitter can be reduced.

Embodiment 4 Next, a fourth embodiment of the present invention will be described. In Embodiment 3 described above,
For the components of the asynchronous signal demapping unit shown in FIG. 4, the variable frequency divider 217, the frame counter 220,
Phase comparison circuit 219, write counter 215, memory 2
Although the 16 and the read counter 218 are additionally provided, the same components may be additionally provided for the asynchronous signal demapping unit shown in FIG. In the fourth embodiment, the same operation and effect as those of the third embodiment can be obtained.

[0050]

As described above, according to the present invention, in the transmitting apparatus, the tributary receiving means performs reception conversion of the input asynchronous tributary input signal, outputs the tributary signal, and outputs the tributary signal. A clock is extracted from an input signal and output as a tributary clock. First clock divider divides the first tributary clock output by the tributary receiver and divides the divided clock. Output as a tributary clock, and the first serial / parallel conversion means outputs
The tributary signal output by the tributary receiving means is serial-to-parallel converted based on the frequency-divided tributary clock and output as a parallel tributary signal, and the second clock frequency dividing means transmits the signal asynchronously with the tributary clock. Divides the parallel tributary signal into a predetermined transmission frame based on the divided tributary clock, and divides the divided tributary signal into a predetermined transmission frame based on the divided tributary clock. The parallel tributary signal is output as a mapped parallel tributary signal based on the transmission line input clock. To parallel-to-serial conversion and output as a serial tributary signal. The serial tributary signals output from the second parallel-serial conversion means for transmitting output to the transmission path as a transmission path signal. On the other hand, in the receiving device, the transmission path receiving means performs reception conversion of the transmission path signal input via the transmission path, outputs this reception-converted serial tributary signal, and The transmission line input clock is extracted and output, and the third clock dividing means
The transmission line input clock is frequency-divided, and the divided frequency-divided transmission line input clock is output. The second serial / parallel conversion means outputs the frequency-divided transmission path input clock output from the third clock frequency division means. Based on the clock, the serial tributary signal output from the transmission path receiving unit is serial-to-parallel converted and output as a parallel tributary signal, and the asynchronous signal demapping unit is output from the third clock frequency dividing unit. The parallel tributary signal output from the second serial-to-parallel converter is demapped based on the frequency-divided transmission path clock, and the demapped parallel tributary signal is output, and the demapped parallel tributary signal is output. And outputs the tributary clock from the tributary clock, and the clock multiplying means outputs the tributary clock output from the asynchronous signal demapping means. Multiplies the reclocked outputs a clock the multiplication as multiplication tributary clock,
A second parallel-to-serial conversion unit, based on the multiplied tributary clock, performs parallel-to-serial conversion of the parallel tributary signal output from the asynchronous signal demapping unit, and outputs the parallel tributary signal as a serial tributary signal; Based on the multiplied tributary clock, the second
Since the serial tributary signal output from the parallel-to-serial conversion means is transmitted and output, mapping and demapping can be performed at a low speed, and even when the tributary signal speeds up, the size and size of the device can be reduced. There is an effect that low power consumption can be maintained.

According to the next invention, the tributary receiving means performs a receiving conversion of the input asynchronous tributary input signal, outputs a tributary signal, extracts a clock from the tributary input signal, and extracts the clock as a tributary clock. The first clock dividing means divides the first tributary clock output by the tributary receiving means, outputs the divided clock as a divided tributary clock, and outputs the first serial parallel clock. The converting means converts the tributary signal output from the tributary receiving means from serial to parallel based on the frequency-divided tributary clock, and outputs a parallel tributary signal, and the second clock frequency dividing means outputs the tributary clock and Divides the asynchronous transmission line input clock and outputs it as the divided transmission line input clock. And, asynchronous signal mapping unit, the parallel tributary signals are mapped to predetermined transmission frame on the basis of the divided tributary clock,
The divided parallel transmission line input clock is output as a parallel tributary signal after mapping based on the divided transmission line input clock, and the second parallel / serial conversion means converts the parallel tributary signal output from the asynchronous signal mapping means to the divided transmission line input clock. And outputs the serial tributary signal as a serial tributary signal, and the transmission path transmitting means transmits and outputs the serial tributary signal output from the second parallel / serial conversion means to the transmission path as a transmission path signal. Therefore, the mapping can be performed at a low speed, and even when the tributary signal is speeded up, an effect that the device can be kept small and low power consumption can be maintained.

According to the next invention, the transmission path receiving means comprises:
The transmission line signal input via the transmission line is received and converted, and the received and converted serial tributary signal is output, and the transmission line input clock is extracted from the transmission line signal and output. Clock frequency dividing means divides the transmission line input clock, outputs the divided frequency divided transmission line input clock, and outputs the divided serial / parallel conversion means from the third clock frequency dividing means. A serial tributary signal output from the transmission line receiving means is converted into a serial-to-parallel signal based on the divided frequency-divided transmission path input clock, and output as a parallel tributary signal. The asynchronous signal demapping means outputs the third clock signal. Demapping the parallel tributary signal output from the second serial-parallel conversion means based on the frequency-divided transmission line clock output from the frequency dividing means,
A parallel tributary signal after the demapping is output, and a tributary clock is extracted and output from the demapped parallel tributary signal, and the clock multiplying means converts the tributary clock output from the asynchronous signal demapping means. The multiplied clock is output as a multiplied tributary clock, and the second parallel / serial conversion means parallelizes the parallel tributary signal output from the asynchronous signal demapping means based on the multiplied tributary clock. The serial tributary signal is converted and output as a serial tributary signal, and the tributary transmission means transmits and outputs the serial tributary signal output from the second parallel-serial conversion means based on the multiplied tributary clock. , The demapping can be done at low speed, Even Ribyutari signal in a case where the speed, an effect that it is possible to maintain a small size and low power consumption of the device.

According to the next invention, in the asynchronous signal mapping means, the serial-to-parallel conversion circuit further performs serial-to-parallel conversion on the input parallel tributary signal, and outputs it as a low-speed parallel tributary signal. A circuit further divides the divided tributary clock, outputs the divided clock as a low-speed tributary clock, and a write counter generates a write address using the low-speed tributary clock. The frequency divider further divides the frequency-divided transmission line input clock, outputs the frequency-divided clock as the low-speed transmission line input clock, and the read counter reads the read address using the low-speed transmission line input clock. The memory generates a low-speed parallel tributary output from the serial-to-parallel conversion circuit based on the write address. And outputs the stored low-speed parallel tributary signal based on the read address. A phase comparison circuit detects a phase difference between the write address and the read address. If the value exceeds the value, a stuff request signal indicating insertion / deletion of stuff is output in accordance with the phase difference, and the frame counter outputs the stuff request signal based on the low-speed frequency-divided transmission line input clock output from the second frequency divider. The stuff control circuit counts the number of bits of the transmission frame and outputs the control timing of the insertion / deletion of the stuff, and the stuff control circuit generates a dummy signal based on the stuff request signal and the control timing from the frame counter. An insert control instruction is output to the read counter, and the register array reads the low-speed frequency read from the memory based on the low-speed frequency-divided transmission line clock. Parallel tributary signal by a predetermined bit shifted output, selector,
Based on a dummy signal insertion control instruction output from the stuff control circuit, a low-speed parallel tributary signal output from the register array is selectively output, and a parallel-serial conversion circuit converts the low-speed frequency-divided transmission line input clock. Originally, the low-speed parallel tributary signal output from the selector is subjected to parallel-to-serial conversion and output as a high-speed parallel tributary signal. Even in this case, there is an effect that the size and power consumption of the device can be maintained.

According to the next invention, in the asynchronous signal mapping means, a second memory is provided between the selector and the parallel / serial conversion circuit, and a second write counter is provided in the second memory. And a variable frequency dividing circuit variably frequency-divides the frequency-divided transmission line input clock, and variably frequency-divides the low-speed variable frequency-divided transmission line input clock into the frame counter, the read counter and Output to the second write counter, wherein the second frame counter counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock output from the second frequency divider; Counting the overhead area, tributary area and FEC area of the transmission frame,
Generates a read address for reading the low-speed parallel tributary signal stored in the second memory based on the count value of the second frame counter.
Detects the phase difference between the second write counter and the second read counter,
Since the frequency dividing ratio of the variable frequency dividing circuit is controlled according to the delay, the mapping can be performed at a low speed.
In addition, it is possible to maintain the small size and low power consumption of the device irrespective of the addition or deletion of the FEC area in the transmission frame.

According to the next invention, in the asynchronous signal demapping means, the third frequency dividing circuit further divides the frequency of the divided transmission line input clock and outputs the low-speed divided transmission line input clock. A third frame counter counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock, and a second serial-to-parallel converter outputs the second serial-to-parallel converter. The parallel tributary signal is further serial-to-parallel converted to a low-speed parallel tributary signal, and the destuff control circuit determines whether or not there is a stuff stored in the transmission frame from the low-speed parallel tributary signal output from the second serial-parallel conversion circuit. Is detected and destuff control is performed.
Based on the low-speed divided transmission path input clock, the low-speed parallel tributary signal output from the second serial-to-parallel conversion circuit is shifted by a predetermined bit and output, and a second selector is provided for the destuff control circuit. Under control, the second
The stuff is selected and deleted from the low-speed parallel tributary signal output from the register array, and the second write counter calculates the stuff based on the low-speed frequency-divided transmission line input clock and a control instruction from the destuff control circuit. A write address is generated, a second read counter generates a read address, and a third memory outputs from the second selector based on the write address generated by the second write counter. The low-speed parallel tributary signal thus stored is stored in the second
And outputting a stored low-speed parallel tributary signal based on the read address generated by the read counter. The third phase comparison circuit outputs the write address generated by the second write counter and the second read Detecting a phase difference from the read address generated by the counter; a low-pass filter smoothing the value of the phase difference detected by the third phase comparison circuit;
A voltage controlled oscillator outputs a frequency-divided tributary clock having a frequency corresponding to the value smoothed by the low-pass filter, and a fourth frequency divider divides the frequency-divided tributary clock output by the voltage controlled oscillator. Then, the divided clock is output to the second read counter as a low-speed divided tributary clock, and the second parallel / serial conversion circuit converts the low-speed divided tributary clock output from the fourth frequency dividing circuit. Originally, the low-speed parallel tributary signal read from the third memory is parallel-to-serial converted and a high-speed parallel tributary signal is output, so that demapping can be performed at a low speed. Even if the speed of the signal is increased, an effect that the device can be kept small and low power consumption can be maintained.

According to the next invention, in the asynchronous signal demapping means, the second variable frequency divider variably frequency-divides the frequency-divided transmission line input clock, and variably frequency-divides the low-speed variable frequency division transmission. And a reference counter counts the number of clocks of the second variable frequency dividing circuit. In the third phase comparing circuit, a fourth phase comparing circuit includes the second write counter. A phase difference between the second read counter and the reference counter, and a frequency division ratio of the second variable frequency divider is controlled based on the detected phase difference. And the detected phase difference is output to the low-pass filter, so that demapping can be performed at a low speed. There even when at high speed. In addition, the addition of FEC region in the transmission frame, regardless of the deletion, an effect that it is possible to maintain the size and power consumption of the device.

According to the next invention, in the asynchronous signal demapping means, a fourth memory is provided between the second serial-parallel conversion circuit and the second register array, and A counter counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock output from the third frequency divider, and counts an overhead area, a tributary area, and an FEC area of the transmission frame. A third write counter for generating a write address for the fourth memory based on the low-speed frequency-divided transmission line input clock and the count value of the fourth frame counter; A frequency dividing circuit variably dividing the frequency-divided transmission line input clock to generate a variable-frequency-divided low-speed variable frequency-divided transmission line input clock; 3 generates a read address of the low-speed parallel tributary signal stored in the fourth memory based on the low-speed variable frequency-divided transmission line input clock output from the third variable frequency circuit, and the sixth phase comparison circuit A phase difference between the third write counter and the third read counter is detected, and a frequency division ratio of the third variable frequency dividing circuit is controlled based on the phase difference. Counting the number of bits of a transmission frame based on the low-speed variable frequency-divided transmission line input clock output by the third variable frequency-dividing circuit;
Since the second write counter generates the write address based on the low-speed variable frequency division transmission line input clock output from the third variable frequency dividing circuit, the demapping is performed at a low speed. Therefore, even when the speed of the tributary signal is increased, it is possible to maintain the size and power consumption of the device irrespective of the addition or deletion of the FEC area in the transmission frame.

According to the next invention, in the asynchronous signal demapping means, the reference counter counts the number of clocks of the third variable frequency dividing circuit, and the seventh phase in the sixth phase comparing circuit. The comparison circuit is configured to perform the third
The phase difference between the write counter and the reference counter is detected, and the frequency division ratio of the third variable frequency divider is controlled based on the detected phase difference. Since the phase difference between the read counter and the reference counter is detected and the value of the detected phase difference is output from the low-pass filter, the demapping can be performed at a low speed, so that the tributary signal is speeded up. Even if F
There is an effect that the size and power consumption of the device can be maintained regardless of the addition or deletion of the EC area.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an asynchronous signal transmission device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a transmission frame used in the asynchronous signal transmission device shown in FIG.

FIG. 3 is a block diagram illustrating a detailed configuration of an asynchronous signal mapping unit of the asynchronous signal transmission device illustrated in FIG. 1;

FIG. 4 is a block diagram showing a detailed configuration of an asynchronous signal demapping unit of the asynchronous signal transmission device shown in FIG.

FIG. 5 is a block diagram illustrating a detailed configuration of an asynchronous signal demapping unit of the asynchronous signal transmission device according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a transmission frame to which an FEC area has been added.

FIG. 7 is a block diagram illustrating a detailed configuration of an asynchronous signal mapping unit of the asynchronous signal transmission device according to the third embodiment of the present invention.

FIG. 8 is a block diagram showing a detailed configuration of an asynchronous signal demapping unit of the asynchronous signal transmission device according to the third embodiment of the present invention.

FIG. 9 is a block diagram illustrating a detailed configuration of an asynchronous signal mapping unit of a conventional asynchronous signal transmission device.

FIG. 10 is a block diagram illustrating a detailed configuration of an asynchronous signal demapping unit of a conventional asynchronous signal transmission device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 Tributary receiving unit, 2, 5, 9 clock frequency dividing unit, 3, 10 serial / parallel conversion unit, 4 asynchronous signal mapping unit, 6, 13 parallel / serial conversion unit, 7 transmission line transmission unit, 8 transmission line reception unit, 11 Asynchronous signal demapping unit, 12 clock multiplication unit, 14 tributary transmission unit, 101, 201 serial / parallel conversion circuit, 102, 11
0, 202, 213 divider circuit, 103, 116, 20
7,215, write counter, 104,117,20
8,216 memory, 105,118,209,218
Read counter, 106, 113, 115, 210,
219, 210 Phase comparison circuit, 107 stack control circuit, 108, 203 register array, 109, 20
6 selector, 111, 114, 205, 220 frame counter, 112, 214 parallel / serial conversion circuit, 2
04 destuff control circuit, 211 low-pass filter, 212 voltage-controlled oscillator, 217 variable frequency divider,
221 Reference counter.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K028 AA07 NN32 NN51 SS06 SS16 5K047 AA16 GG08 GG47 LL04 LL05 MM02 MM11 MM24 MM33 MM55 MM56

Claims (9)

[Claims] 1. An asynchronous signal transmission device for mapping / demapping and transmitting an asynchronous tributary signal with respect to a transmission rate of a transmission frame and transmitting the received tributary signal, performing a receiving conversion of the input asynchronous tributary input signal and outputting a tributary signal. A tributary receiving means for extracting a clock from the tributary input signal and outputting the clock as a tributary clock; dividing the first tributary clock output by the tributary receiving means; First clock frequency dividing means for outputting as a tributary clock; and first serial frequency converting means for serially / parallel-converting the tributary signal output from the tributary receiving means based on the frequency-divided tributary clock and outputting as a parallel tributary signal. Parallel conversion means; and the tributary Second clock frequency dividing means for dividing a transmission line input clock asynchronous with the lock and outputting the divided clock as a divided transmission line input clock; and transmitting the parallel tributary signal based on the divided tributary clock in a predetermined manner. An asynchronous signal mapping unit that maps the frame onto a frame and outputs it as a parallel tributary signal after mapping based on the divided transmission line input clock; and inputs the parallel tributary signal output from the asynchronous signal mapping unit to the divided transmission line input. A second parallel-to-serial conversion unit that performs parallel-to-serial conversion on the basis of a clock and outputs a serial tributary signal; A transmission-side device having: Transmission line receiving means for outputting the reception-converted serial tributary signal, extracting and outputting the transmission line input clock from the transmission line signal, and dividing the transmission line input clock. Third clock dividing means for outputting the divided frequency-divided transmission line input clock; and receiving the transmission line based on the frequency-divided transmission line input clock output from the third clock frequency dividing means. A second serial-to-parallel converter for serial-to-parallel conversion of the serial tributary signal output from the means, and outputting as a parallel tributary signal; and a frequency-divided transmission line clock output from the third clock frequency divider. , Demapping the parallel tributary signal output from the second serial / parallel conversion means, outputting the demapped parallel tributary signal, Asynchronous signal demapping means for extracting and outputting a tributary clock from the paralleled tributary signal which has been tapped; Clock multiplying means for outputting, and second parallel-serial converting means for performing parallel-to-serial conversion of the parallel tributary signal output from the asynchronous signal demapping means based on the multiplied tributary clock, and outputting as a serial tributary signal. A tributary transmission unit for transmitting and outputting a serial tributary signal output from the second parallel-serial conversion unit based on the multiplied tributary clock, and a receiving-side device having: Asynchronous signal transmission device. 2. An asynchronous signal transmission device for mapping and transmitting an asynchronous tributary signal with respect to a transmission rate of a transmission frame, performing a receiving conversion of the input asynchronous tributary input signal and outputting a tributary signal. A tributary receiving means for extracting a clock from the tributary input signal and outputting the extracted clock as a tributary clock; dividing the first tributary clock output by the tributary receiving means, and dividing the divided clock by a divided tributary clock And a first serial-to-parallel converter for converting the tributary signal output by the tributary receiving unit from serial to parallel based on the frequency-divided tributary clock, and outputting as a parallel tributary signal. And the tributary clock is not Clock dividing means for dividing the transmission line input clock of the first stage and outputting the divided clock as the divided transmission line input clock, and mapping the parallel tributary signal to a predetermined transmission frame based on the divided tributary clock. An asynchronous signal mapping means for outputting as a parallel tributary signal after mapping based on the frequency-divided transmission line input clock; and a parallel tributary signal output from the asynchronous signal mapping means for the frequency-divided transmission line input clock. A second parallel-to-serial conversion means for performing parallel-to-serial conversion to output as a serial tributary signal, and a transmission path for transmitting and outputting the serial tributary signal output from the second parallel-to-serial conversion means as a transmission path signal to a transmission path An asynchronous signal transmission device, comprising: transmission means. 3. An asynchronous signal transmission device for demapping and transmitting a tributary signal that is asynchronous with respect to the transmission rate of a transmission frame. A transmission line receiving means for outputting the converted serial tributary signal and extracting and outputting the transmission line input clock from the transmission line signal; dividing the transmission line input clock; Third clock dividing means for outputting a line input clock, and a serial tributary signal output from the transmission line receiving means based on the frequency-divided transmission line input clock output from the third clock frequency dividing means. Serial-to-parallel conversion means for serially / parallel-converting the data and outputting the result as a parallel tributary signal; Based on the lock, the parallel tributary signal output from the second serial / parallel conversion means is demapped, and the demapped parallel tributary signal is output, and the tributary clock is output from the demapped parallel tributary signal. An asynchronous signal demapping means for extracting and outputting the same; a clock multiplying means for multiplying the tributary clock output from the asynchronous signal demapping means and outputting the multiplied clock as a multiplied tributary clock; A second parallel-to-serial conversion unit that performs parallel-to-serial conversion of the parallel tributary signal output from the asynchronous signal demapping unit based on the tally clock, and outputs the serial tributary signal as a serial tributary signal; The second parallel-serial conversion means And a tributary transmission means for transmitting and outputting the serial tributary signal output from the asynchronous signal transmission device. 4. The asynchronous signal mapping means further performs serial-to-parallel conversion on the input parallel tributary signal, and outputs a low-speed parallel tributary signal as a serial-to-parallel conversion circuit; and further divides the frequency-divided tributary clock. A first frequency divider that outputs the frequency-divided clock as a low-speed tributary clock; a write counter that generates a write address using the low-speed tributary clock; A second frequency dividing circuit that outputs the divided clock as a low-speed transmission line input clock; a read counter that generates a read address using the low-speed transmission line input clock; And stores the low-speed parallel tributary signal output from the serial-to-parallel conversion circuit. A memory for outputting a parallel tributary signal based on the read address, a phase difference between the write address and the read address, and a stuff corresponding to the phase difference when the phase difference exceeds a predetermined value. A phase comparison circuit that outputs a stuff request signal indicating insertion / deletion of the signal; and a low-speed frequency-divided transmission line input clock output from the second frequency divider. A frame counter for outputting a control timing for insertion / deletion of stuff; a stuff control circuit for outputting a dummy signal insertion control instruction to the read counter based on the stuff request signal and control timing from the frame counter A low-speed parallel tributary signal read from the memory based on the low-speed divided transmission line clock, A register array for outputting a low-speed parallel tributary signal output from the register array based on a dummy signal insertion control instruction output from the stuff control circuit; and 2. A parallel-serial conversion circuit for converting a low-speed parallel tributary signal output from the selector into a parallel-to-serial signal based on a transmission line input clock, and outputting the parallel low-speed tributary signal as a high-speed parallel tributary signal. Or the asynchronous signal transmission device according to 2. 5. The asynchronous signal mapping means comprises: a second memory provided between the selector and the parallel-to-serial conversion circuit; and a second write counter for generating a write address of the second memory. And a variable frequency divider for variably dividing the frequency-divided transmission line input clock and outputting the variably divided low-speed variable frequency-divided transmission line input clock to the frame counter, the read counter, and the second write counter. Circuit, and counts the number of bits of the transmission frame based on the low-speed frequency-divided transmission line input clock output from the second frequency dividing circuit, and counts the overhead area, tributary area, and FEC area of the transmission frame. A second frame counter; and a second frame counter based on a count value of the second frame counter.
A second read counter for generating a read address for reading the low-speed parallel tributary signal stored in the memory, detecting a phase difference between the second write counter and the second read counter, and leading / lagging the phase 5. The asynchronous signal transmission device according to claim 4, further comprising: a second phase comparator that controls a frequency division ratio of the variable frequency divider according to 6. The asynchronous signal demapping means further comprises: a third frequency divider for further dividing the frequency-divided transmission line input clock and outputting a low-speed frequency-divided transmission line input clock; A third frame counter for counting the number of bits of the transmission frame based on the input clock; and a low-speed parallel tributary signal obtained by further serial-to-parallel conversion of the parallel tributary signal output from the second serial-parallel conversion means. A second serial-to-parallel conversion circuit, and a destuffing control circuit that detects the presence or absence of stuff stored in the transmission frame from the low-speed parallel tributary signal output from the second serial-to-parallel conversion circuit, and performs destuffing control. A low-speed parallel tributary signal output from the second serial-to-parallel conversion circuit based on the low-speed frequency-divided transmission path input clock; A second register array for shifting and outputting, and a second selector for selecting and deleting stuff from low-speed parallel tributary signals output from the second register array under the control of the destuff control circuit A second write counter that generates a write address based on the low-speed divided transmission path input clock and a control instruction from the destuff control circuit; a second read counter that generates a read address; The low-speed parallel tributary signal output from the second selector is stored based on the write address generated by the second write counter, and based on the read address generated by the second read counter. A third memory that outputs the stored low-speed parallel tributary signal, a write address generated by the second write counter, and the second read A third phase comparison circuit that detects a phase difference from the read address generated by the counter, a low-pass filter that smoothes a value of the phase difference detected by the third phase comparison circuit, and a value that is smoothed by the low-pass filter. A voltage-controlled oscillator that outputs a frequency-divided tributary clock having a frequency corresponding to the frequency-divided tributary clock output from the voltage-controlled oscillator, and uses the frequency-divided clock as a low-speed frequency-divided tributary clock. And a low-speed parallel tributary signal read from the third memory based on a low-speed frequency-divided tributary clock output from the fourth frequency divider circuit. 7. A second parallel-serial conversion circuit that performs parallel-to-serial conversion and outputs a high-speed parallel tributary signal. Asynchronous signal transmission apparatus according to one or misalignment. 7. A second variable frequency dividing circuit for variably dividing the frequency-divided transmission path input clock and outputting a variable-frequency-divided low-speed variable frequency division transmission path input clock; A reference counter for counting the number of clocks of the second variable frequency dividing circuit; and a third phase comparing circuit for detecting a phase difference between the second write counter and the reference counter. And a fifth phase comparison circuit that detects a phase difference between the second read counter and the reference counter. The fourth phase comparison circuit is configured to calculate a phase difference based on the detected phase difference. 7. The frequency division ratio of the second variable frequency divider circuit is controlled, and the fifth phase comparator circuit outputs the value of the detected phase difference to the low-pass filter.
2. The asynchronous signal transmission device according to item 1. 8. The asynchronous signal demapping means includes: a fourth memory provided between the second serial-to-parallel conversion circuit and the second register array; and an output from the third frequency dividing circuit. A fourth frame counter that counts the number of bits of the transmission frame and counts an overhead area, a tributary area, and an FEC area of the transmission frame based on the input low-speed frequency-divided transmission path input clock; A third write counter for generating a write address for the fourth memory based on a transmission line input clock and a count value of the fourth frame counter; and a variable frequency divider for dividing the frequency-divided transmission line input clock. A third variable frequency dividing circuit that generates a variable frequency-divided low-speed variable frequency dividing transmission line input clock; and a low speed variable frequency dividing transmission line that is output by the third variable frequency dividing circuit. A third read counter for generating a read address of the low-speed parallel tributary signal stored in the fourth memory based on the input clock, and a phase difference between the third write counter and the third read counter. A sixth phase comparator circuit for detecting and controlling a frequency division ratio of the third variable frequency divider circuit based on the phase difference, wherein the third frame counter comprises: The second write counter counts the number of bits of the transmission frame based on the low-speed variable frequency division transmission line input clock output by the frequency dividing circuit. The second write counter outputs the low speed variable frequency division transmission output by the third variable frequency dividing circuit. 7. The asynchronous signal transmission device according to claim 6, wherein a write address is generated based on a path input clock. 9. The asynchronous signal demapping unit includes a reference counter that counts the number of clocks of the third variable frequency dividing circuit, and the sixth phase comparison circuit includes a third write counter and the reference A seventh phase comparison circuit for detecting a phase difference between the third read counter and the reference counter, and a seventh phase comparison circuit for detecting a phase difference between the third read counter and the reference counter. The circuit controls a dividing ratio of the third variable frequency dividing circuit based on the detected phase difference, and the eighth phase comparing circuit outputs a value of the detected phase difference to the low-pass filter. 9. The method according to claim 8, wherein
2. The asynchronous signal transmission device according to item 1.