JP2002261043A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a fine pattern exceeding the limit of the conventional fine processing by slightly modifying an etching technique by inheriting an already established i-line exposure technique. I will provide a. A method for manufacturing a semiconductor device, comprising: forming a material to be etched on one main surface of a semiconductor substrate;
A step of forming a mask pattern on the material to be etched, and a step other than the mask pattern of the material to be etched by a dry etching method using an etchant gas and a polymer deposition gas in a state where an etching suppression wall is formed on the upper side of the mask pattern. Etching the region. The material to be etched after the etching is a gate electrode or a wiring pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor device,
The present invention relates to a semiconductor device such as a memory element and a method of manufacturing the same, and more particularly to a technique effective in forming a fine pattern gate electrode or a wiring pattern.

[0002]

2. Description of the Related Art Ultra-large-scale integrated circuits (ULSI: Ultra-La)
(rge Scale Integrated Circuits) has increased its integration density twice as fast as in three years, achieving higher performance and higher functionality. As a result, the minimum line width of ULSI is 2000
It is expected to reach the range of 0.18 μm to 0.15 μm in the year and the sub-0.1 μm region after 2005.
As an example of a semiconductor device having a fine conductive pattern, a field-effect transistor (TFT) having a gate electrode of a fine pattern is disclosed in, for example, the following documents (a) and (b).
(C). (A) “Stacked diffusion layer type 0.1 μm-MOSFE”
T ", Shinichiro Kimura and Eiji Takeda: Applied Physics, vol.
1, No. 11, p. 1143 (1992) (b) “30 nm gate InAlAs / InGaAs”
HEMT and its High Frequency Characteristics ", Tetsuya Suemitsu, Tetsuyoshi Ishii, Haruki Yokoyama, et al .: IEICE Technical Report ED98-1
85, p. 15 (1999) (c) “InP-based high electron mobility transistor (HEM)
T) ", Tetsuya Suemitsu: Applied Physics, vol.
2, p. 141 (2000)

In the aforementioned document (a), a diffusion layer is stacked on a substrate in order to effectively suppress punch-through.
The gate electrode of the OSFET is formed by i-line exposure and a phase shift method. Here, the gate length is 0.1 μm, and the gate electrode is formed of polycrystalline silicon by utilizing the self-alignment forming technology of the sidewall insulating film. In the above-mentioned documents (b) and (c), the fine gate pattern of 0.03 μm uses an electron beam drawing and a nano-composite resist, and prevents a decrease in high-frequency characteristics with a two-stage recess gate structure, thereby reducing the current gain cutoff frequency. ft = 350 GHz has been achieved. Previous reports (October 7, 1999 Accepted applied physics vo
l. 69 No. In 2), ft = 350 GHz is one of the highest values.

[0004]

A technique which has been developed mainly for high integration of semiconductor integrated circuits is a fine processing technique.
Among these fine processing techniques, a lithography technique for forming a pattern on a semiconductor substrate plays a central role. In order to make the pattern finer, it is necessary to increase the resolution to ensure dimensional accuracy. At present, lithography techniques in the submicron region include a light exposure method, an X-ray exposure method, and an electron beam drawing method. In the light exposure method, miniaturization of the design rule is supported by shortening the exposure wavelength and increasing the NA (numerical aperture) of the projection lens. As a method of exposing a pattern smaller than the wavelength, there are super-resolution techniques such as a phase shift method, a modified illumination method, and a pupil filter method. When using super-resolution technology, 300 to 200 n with a mercury lamp i-line of wavelength 365 nm
m, a pattern of 200 to 180 nm can be formed with a KrF excimer laser having a wavelength of 248 nm, and a pattern of 180 to 130 nm can be formed with an ArF excimer laser having a wavelength of 193 nm. Since shortening the wavelength and increasing the numerical aperture increase the depth of focus, chemical mechanical polishing (CMP: Chemical Mechanica)
l Polishin) to reduce the device step. Conventionally, in the case of a positive resist, the line width can be reduced by increasing the exposure amount as a method of simply reducing the pattern width.
If the thickness is less than 50 nm, the subsequent processing will be hindered due to a decrease in the film thickness of the resist and deterioration of the profile.

[0005] As described above, it is extremely difficult to cope with the minimum processing dimension of 200 nm or less without using the conventional technology in the light exposure method. The benzene ring compound of the resist material is 19
It cannot be used because of its large absorption at 3 nm. High transparency of the high-sensitivity resist with respect to the light source wavelength is achieved by shortening the exposure wavelength, and the standing wave effect and halation are prominent due to the increase in the reflectance from the underlying substrate with the shortening of the wavelength. A problem is a reduction in process margin such as deterioration of the resist shape and dimensional variation due to an increase in the base reflectance. As a representative of the high-sensitivity resist, there is a problem in that a chemically amplified single-layer resist, when left after exposure, diffuses acid and cannot obtain a rectangular etched shape. Further, when the required dimensional control accuracy becomes severe, the fluctuation at the resist molecule level becomes a level that cannot be ignored.

In the case of an ArF excimer laser having a wavelength of 193 nm, a lens is the biggest problem. It is difficult to put a transparent lens into practical use. Lens materials that can transmit ArF excimer laser include fluorite and quartz. Fluorite is excellent in optical performance, but is difficult to handle because it is soft, sensitive to temperature changes, easily scratched, and difficult to polish. Quartz has a small amount of absorptivity to the ArF excimer laser and has transparency until the initial stage, but a color center is formed in the lens with the passage of time, and the transmittance changes. As described above, both fluorite and quartz have problems with the materials themselves, and the bottleneck is that the durability of the lens does not increase. Attention has been paid to a method using a reflection mirror system as a method for reducing the influence of a lens having poor durability. However, at present, not all lenses can be replaced with a reflection system.

[0007] Even if the light exposure system is a stepper type or a scan type, reliability around the light source is important. In particular,
It is necessary to suppress the length of downtime and cost increase during maintenance. In the case of the i-line, the mercury lamp should have been replaced, but the excimer laser light source is one system, which requires a long maintenance time and significantly increases the cost. Further, countermeasures for reaction products are required. The impurities are ionized by the short wavelength light and are deposited on the optical system components.
This causes a photo-CVD effect and contaminates the optical system components even if nitrogen purge is performed. In addition, there is a concern that the operating rate and cost increase are all low, such as deterioration of the mirror inside the laser resonator. In order to use shorter light, we must simultaneously solve many technical issues such as development of high-sensitivity resist, selection of anti-reflection film, pattern dimensional accuracy of resist, durability of optical system, and reliability around light source. No.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which inherit the already established i-line exposure technology. It is an object of the present invention to provide a technique capable of forming a fine pattern exceeding the limit of the conventional fine processing by slightly modifying the etching technique. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention is a semiconductor device having a pattern layer provided on one main surface of a semiconductor substrate, wherein the pattern width of the pattern layer on the semiconductor substrate side is b,
When the height of the pattern layer is h, b ≦ 200 nm
Where h / b ≧ 3 is satisfied. Further, the present invention is a semiconductor device having a pattern layer provided on one main surface of a semiconductor substrate, wherein the pattern width of the pattern layer on the semiconductor substrate side is b, and the pattern layer is located farthest from the semiconductor substrate on the side farthest from the semiconductor substrate. When the pattern width is a, b ≦ 20
It is characterized by satisfying 0.97 ≦ b / a ≦ 1.03 at 0 nm. Further, in a preferred embodiment of the present invention, when the height of the pattern layer is h, the hook portion of the pattern layer is a portion having a height of approximately h / 3 from one side of the semiconductor substrate side. It is characterized by the following.

The present invention is also a method of manufacturing a semiconductor device, comprising: forming a material to be etched on one principal surface of a semiconductor substrate; and forming a mask pattern on the material to be etched. Etching a region other than the mask pattern of the material to be etched by a dry etching method using an etchant gas and a polymer deposition gas in a state where an etching suppression wall is formed on the upper side of the mask pattern. . In a preferred embodiment of the present invention, the material to be etched after the etching is a gate electrode. In a preferred embodiment of the present invention, the material to be etched after the etching is a wiring pattern.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. [Embodiment 1] The present invention relates to an excimer radar light exposure,
No special equipment such as X-ray (SOR) exposure and electron beam lithography is required, and a general i-line stepper and Electron Cyclotron Resonance (ECR)
This is to perform fine processing with a line width of 200 nm or less, which was almost impossible in the past, using a dry etching apparatus. FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Hereinafter, FIG.
The method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. (1) First, a resist pattern sample 3 having a line width of 250 nm is formed on a material layer of a pattern layer (for example, an electrode wiring metal film) 2 formed on a semiconductor substrate 1 by an i-line stepper device and a phase shift method. Is formed (see FIG. 1A). (2) Next, as a first step, in the ECR apparatus, the resist pattern sample 3 is reduced to a desired width by oxygen plasma to form an etching mask (FIG. 1).
(B)). In the subsequent etching process, continuous and continuous processing is performed in the ECR apparatus.

In the pattern forming method of the first step, the range of the ECR device control parameters is as follows. The substrate temperature is 15 ° C. to 40 ° C., the flow rate is 50 to 200 sccm using oxygen, and the gas pressure is 0.005.
From 0.1 torr, the microwave frequency 2.
This is performed by applying a power of 560 W ± 20% at 45 GHz and a power of 2 to 15 W at a bias frequency of 2 MHz. Since the oxygen plasma in this step has a strong tendency for isotropic etching, low-pressure and high-ion-density plasma is required to limit the anisotropy of the resist shape. The conditions are a long mean free path for the ions to guarantee directionality, a high ion-to-neutral radical ratio to minimize isotropic etching, and a high reactivity to maintain high etching rates. It is derived from seed density.

In order to lengthen the mean free path, lowering the pressure is advantageous. However, there is a problem that low pressure is accompanied by a decrease in the particle density in the reaction chamber, which makes it difficult to generate plasma, and that the etching rate is reduced as compared with the conventional method due to a decrease in active species. In the ECR method, when a microwave and a magnetic field are combined in a reaction chamber into which an etching gas is introduced and a magnetic field is applied in the same direction as the propagation direction of the microwave, the Lorentz force of the magnetic field and charged particles (electrons and ions) dissociated by the microwave Generates a circular motion, and the microwave frequency is 2.45 GHz.
When the condition of the magnetic field strength of 875 G is set for z, frequency resonance occurs and electrons are accelerated to increase the degree of ionization of the etching gas, and charged particles and active particles (radicals) are efficiently generated to form high-density plasma. These charged particles and active particles suppress collision scattering under a long mean free path in the molecular flow region, and etching with good uniformity is performed.

On the other hand, when a bias is applied to the sample stage electrode, charged particles (mainly ions) are given kinetic energy by the bias potential, and an ion-assisted reaction system in which the supply of ions with uniform direction is a rate-determining step may be assembled. it can. This reaction system can perpendicularly enter the wafer sample and can realize high-speed and anisotropic etching. The reaction system is capable of high-speed, low-damage etching and control of the etching profile even with a variable bias. In addition, ECR plasma is considered to be a promising multi-charged ion source because it has a high density and an extremely high electron temperature and has sufficient energy to cause inner-shell ionization. Multivalent ionization more chemically activates or increases or decreases the thin film polymer forming function or chemical reaction effect. Examples of high-density plasma sources that require the principle of the plasma source of the ECR method and chemical / physical mechanisms include helicon wave excited plasma, magnetron plasma, magnetic neutral plasma, inductively coupled plasma, narrow electrode parallel plate plasma, The effect can be obtained by using UHF plasma, surface wave plasma, or the like.

(3) Next, as a second step, ECR
In the apparatus, using the etching mask 4 as a mask,
Under the condition that an etching suppression wall (hereinafter referred to as “Rabbit ear”) is generated on the shoulder portion of the resist on the processing side surface, a one-step etching of the pattern layer (for example, the electrode wiring metal film) 2 has Center of gravity ±
Work to about 10% of the way (see FIG. 1 (c)). Here, as shown in FIG. 2, the rabbit ear 5 is a wall-shaped member formed on the processing side surface of the resist shoulder, and is also called alias, fence, burr, and fluff. Often seen are the products of Au and Pt, a malleable metal and a resist, formed on the shoulder of the metal. 2 (a) is a cross-sectional photograph, and FIG. 2 (b) is a perspective view schematically showing FIG. 2 (a). The center of gravity of the kaname portion means a portion whose depth from the surface of the pattern layer 2 is 2/3 (that is, the height from the semiconductor substrate 1 is 1/3) (FIG. 1C).
reference). Here, the conditions under which the rabbit-ear effect occurs due to plasma control are extremely narrow, and gas types, gas flow rates, gas pressures, and gas compositions are excluded, excluding device-specific parameters such as reaction chamber volume and surface area, electrode spacing, and pumping speed. In each setting range such as substrate temperature, microwave power supply power, microwave frequency, bias power, bias frequency, etc., it is adapted with each external parameter depending on the resist material, the underlying substrate structure and the target processing metal.

On the other hand, internal parameters in plasma are described, for example, in Applied Physics Vol. 56, No. 8, 978, 1987.
As reported on the page: Potential (electric field) distribution between electrodes and its time change (specifically, sheath voltage, sheath length, electric field in bulk plasma, etc.), electron energy distribution function and its time change, electron density and spatial / temporal Changes, spatial and temporal changes in the amount of RF power injected, selectivity of the primary reaction of the raw material molecules, ie, dependence on the electron energy distribution function, optimization of the secondary reaction in the gas phase (physical quantities involved are gas temperature, gas Pressure), optimization of surface reaction process (flux and composition of ions and radicals from gas phase, rate constant of surface process,
This is related to the substrate temperature). That is, how to control the internal parameters by the external parameters. Since one external parameter interacts with many internal parameters, a great many factors can be considered as etching parameters. In the current etching apparatus with mass productivity, the radical species having the isotropic etching characteristics which cannot completely align the direction of the ion species incident on the substrate only by the ECR method and have the isotropic etching characteristics exist before. In order to prevent these etchings in the horizontal direction and achieve a vertical shape, it is necessary to focus on the etching gas for forming the sidewall protective film, and to perform the etching while forming the sidewall protective film by the ECR method and the ion assist reaction. is there.

A gas for depositing a polymer in forming a side wall protective film.
Halogen (A), carbon (C) and hydrogen (H)
CxHyAz system (eg, CHF_Three, CH_TwoF_Two,
C_ThreeH _TwoF₆, CH_TwoCl_Two, H_Two+ CF_Four, H_Two+ C_TwoF₆, C
H_Four+ CF_Four, H_Two+ C_ThreeF₈Etc.). Fluorocarbo
As a method of forming gas-based deposits, the hydrogen
Increase the amount, consume the fluorine of the etchant, and
Methods for increasing the nitrogen / fluorine ratio are empirically known. C
In xHyAz-based etching, mainly -C-H
Group or polymer film consisting of -CF group protects side wall
Think of it as a membrane. Etchant gas contains carbon element
Halogen-free gas (eg, F_Two, HF, C
l_Two, HCl, NF_Three, SF₆, BCl_Three, HBr, SiF
_Four, SiCl_FourEtc.) are better for etching and polymer
This is convenient because the deposition ratio can be controlled independently.
You. The combination of gas types depends on the number of
It greatly affects the selectivity and damage of the substrate and the underlying substrate. Compound
When etching the electrode wiring metal on the semiconductor crystal,
As a chant gas, a non-chlorine gas such as SF₆
With CHF as polymer deposition gas_ThreeWhen using
Compound semiconductor with high selectivity to compound semiconductor crystal and low damage
The characteristics of the device can be significantly improved.

FIG. 3 shows an example of the etching rate and selectivity of the resist and WSi when the gas composition of the external parameter is changed, and FIGS. 2 and 4 show examples of the processing shape. FIG. 4 is a cross-sectional photograph having a large pattern shape because it is relatively easy to illustrate with a characteristic shape. FIG. 3 shows the etching rate and selectivity of WSi and resist when the composition ratio of SF ₆ and CHF ₃ as the etchant gas and the polymer deposition gas is changed. The condition of FIG. 3 is that the semiconductor substrate is Ga
Using As, a substrate temperature of 25 ° C. and a pattern width of 250 n
m, microwave power 560 W, bias high frequency power 10
W, gas pressure 0.01 torr. As the SF ₆ concentration increases, the etching rate of both WSi and the resist increases. However, when the concentration of SF ₆ is 30% or more, the resist tends to be slightly saturated. The selection ratio is about 1 when the SF ₆ concentration is around 30% and about 2 when the SF ₆ concentration is around 100%. Normally, processing is performed under the condition that the selectivity between resist and WSi is greater than 1 and the SF ₆ concentration is high in consideration of resist resistance. W
Si is easily etched isotropically by fluorine.

As shown in FIG. 4A, the pattern width 40
0 nm, SF ₆ concentration of 80% in about selectivity of 1.9, side etching is generated between the resist and the WSi the processing conditions shown in Fig. Side etching, the tendency increases as SF ₆ concentration is increased. On the other hand, the SF ₆ concentration was reduced so that the pattern width was 700 nm and the SF ₆ concentration was 2
At 0% and a substrate temperature of −40 ° C., a remaining side wall re-adhesion film is formed as shown in FIG.
This means that the shoulder of the resist pattern is tapered during the etching. As a result, the height of the vertical side surface is reduced, and the vehicle moves while moving backward. Therefore,
WSi is etched while applying tape. As a result, the bottom surface becomes larger and trapezoidal than the upper surface, resulting in poor anisotropy. The same tendency as in FIG. 4B is obtained even when the SF ₆ concentration is 10%. Further, when the SF ₆ concentration is 0%, the polymer is deposited without etching.

Here, the characteristic feature is that the etching rate of WSi and the resist intersect at a SF ₆ concentration of about 30%, and the etching rate of WSi is reversed below that, and the etching rate of WSi starts to rapidly decrease. Under the conditions of FIG. 3, the rabbit ear effect occurs in a concentration range of about 10% to 30% of SF ₆ concentration. Using this effect, by optimizing the concentration of SF ₆ and other external parameters, the apparent side by barrier regression of the resist pattern at the end of the WSi etched with Rabbit ear effect, and verticalization sidewall redeposited film Can be etched without leaving any residue. FIG. 2 shows an example of the result of etching by this method. In the photograph shown in FIG. 2A, the etching shape of WSi is slightly wedge-shaped, but good processing without a sidewall re-adhesion film residue can be realized. In FIG. 2A, the size of the neck portion is 50 nm, a rabbit ear effect is observed at the shoulder of the resist, and the tapered shape is suppressed from acting as a fence. In order to realize the rabbit ear effect, it is important to optimize not only the gas composition but also other external parameters.

An example of the bias power dependence under the condition where the rabbit ear effect is observed will be described. FIG. 4C shows an electric power of 10
In FIG. 4D, the electric power is 20 W. Here, the pattern width is 300 nm, the SF6 concentration is 20%, and the gas pressure is 0.1 torr. At high power, there is a problem in resist resistance, but a shape close to a vertical shape including a neck portion is obtained. FIG. 4B shows a condition in which a rabbit ear occurs at a substrate temperature of 25 ° C., but when the substrate temperature becomes about −45 ° C., a side wall re-adhesion film is observed. Also, if the gas pressure affected by the gas pressure is high, the resist resistance is improved, but the shape shows an isotropic tendency, the skirt portion on the side of the WSi largely recedes, and even if excessive overetching is performed, the pattern becomes vertical. And dimensional control are not improved. In addition to the above, it is considered that the rabbit ear effect is also affected by the microwave frequency, the bias frequency, the pumping speed, and the like. However, the configuration of the present invention required the following step condition range.

In the pattern forming method of the second step, E
The range of the CR device external control condition is as follows. The substrate temperature is 15 ° C. to 40 ° C., the composition ratio of SF ₆ concentration and CHF ₃ is 10% to 30%, and the total flow rate of the mixed gas is 25% to 1%.
00 sccm, gas pressure from 0.005 to 0.3 torr
r, the microwave power needs to be 560 W ± 20% and the bias high frequency power needs to be 2 to 15 W. The external control conditions are delicate because each has a control range specific to the apparatus. However, if conditions for obtaining the rabbit ear effect are selected, vertical and fine processing can be realized. Actually, it is empirically known that there are delicate and appropriate conditions for generating a plasma and processing a desired product. 100n
For a fine isolated pattern of m or less, pattern collapse due to mechanical factors such as resist peeling, surface tension at the time of cleaning, and impact is often experienced, and is a consideration when the aspect ratio becomes 4 to 5 or more. As for the mechanical strength of the fine isolated pattern, the center of gravity is like a sword. Regarding the correlation between the center of gravity and the vertical shape in the rabbit ear effect,
In a range lower than the position of the center of gravity, the shape of the pattern is a tapered trapezoid, and in a higher range, the side etching is dominant and tends to be undercut. In the case of performing fine gate processing, controllability of the gate length is hindered in a tapered state and an undercut state. Therefore, in order to realize vertical and fine processing with small dimensional shift, it is important to optimize the rabbit ear effect and the position of the center of gravity of kaname.

(4) Next, as a third step, EC
In the R apparatus, the gas pressure in the reaction chamber is lower than that in the second step, the output level of the high frequency bias power is lowered, and the rabbit ear effect is further proliferated. Wiring metal film)
2 is formed by final processing by two-step etching (FIG. 1D)
reference). EC in the pattern formation method of the third step
The range of the R device external control parameters is as follows. The substrate temperature is 15 ° C. to 40 ° C., the SF ₆ concentration is about 10% to 30% using CHF ₃ , and the gas pressure is 0.1%.
005 to 0.2 torr, total flow rate of mixed gas is 25 to 100 sccm, microwave power is 560 W ± 20%
And the bias high frequency power is 2 to 15 W. The change in gas pressure depends on the collision frequency of electrons or radicals, or Pm
(Average free path, primary reaction of raw material gas molecules, secondary reaction of radicals). The change in the collision frequency is related to the electron energy distribution and the electron density, and affects the selectivity of the primary reaction. Further, it is involved in the generation and loss of ions and electrons, and changes the discharge maintenance mechanism, that is, the form of the potential electric field distribution. on the other hand,
Changes in Pm directly affect the frequency of secondary reactions and change the relative weight of secondary reactions. Also, the speed of transport of the generated active species to the substrate is changed through the diffusion constant.

The low gas pressure conditions in this step make the anisotropic etching action more intense due to the more activated ions. Changes in high-frequency power change plasma parameters such as electron energy distribution, electron density, and potential distribution, but due to differences in other external parameter settings, if the power consumption is mainly in the sheath, the electron energy distribution will be changed to the bulk plasma. If it is in the middle, it greatly affects the electron density. The low electron potential distribution under the low power condition enables a low-damage etching action, and is suitable for a gate metal of a surface device such as an FET in which damage may be introduced into a substrate crystal. This step can be said to be a condition under which the effect of ions becomes apparent in a plasma source having a low electron energy distribution while maintaining a high density under a low pressure. Further, low gas pressure is effective for reducing the side wall re-adhesion film, and low power is effective for maintaining the etching resistance of the resist. Therefore, in order to make the etching shape nearly vertical, it is necessary to form a polymer film on the side wall of the resist pattern, prevent the receding by the rabbit ear effect, and increase the area of the vertical side surface of the polymer film.

(5) Finally, as a fourth step, E
In the CR device, all the remaining resist is ashed by oxygen plasma. The range of the ECR device external control parameters in the fourth step ashing is as follows. Using oxygen, the flow rate is 25 to 100 sccm, the gas pressure is 0.005 to 0.05 torr, the microwave power is 560 W ± 20%, the bias high frequency power is 5 to 25 W, and the ashing time is about 1 to 5 minutes. Etching is originally a clean surface forming technique, and requires a continuous process to maintain the original cleanliness after processing. In microfabrication as well, when the processed metal, resist and reaction products are exposed to air, they are affected by oxidation reaction, adsorbed water and the like. To avoid effects and increase reproducibility,
(2) to (5) need to be continuously and continuously processed in a single etching apparatus. In a process of forming a gate electrode and an ohmic electrode of a semiconductor device, a process of performing wiring, and the like, a multilayer thin film having various multilayer structures requires an etching step condition capable of improving a selectivity with respect to a resist or a base layer thin film and a substrate, For that purpose, multi-step sequence etching that can perform continuous and consistent processing suitable for the laminated thin film is effective.

FIG. 5 is a diagram for explaining a pattern layer manufactured by the manufacturing method of the present embodiment, and is a schematic cross-sectional view showing a cross-sectional shape of the pattern layer. As described above, since the etching of the pattern layer 2 is performed in two stages, the pattern layer manufactured by the manufacturing method of the present embodiment faces one side of the semiconductor substrate and one side of the semiconductor substrate. The portion c in FIG. The portion c is the center of gravity of the above-mentioned kaname. On the other hand, from another point of view, as shown in FIG. 5D, it can be said that the pattern is qualitatively etched while the sidewall shape of the pattern is exponentially attenuated. The time constant or lifetime of the decay curve is 1 / e ≒ 0.368. The center of gravity (1/3 ≒ 0.333) and the life are relatively near the above-mentioned portion c. As described above, the life and the center of gravity are distorted in pattern formation. Its range is between 0.3 and 0.4. Therefore, the one-step pattern is
At this point (part c), the two-stage patterning is started. As described above, in the present embodiment, as shown in FIG.
When the pattern width of one side of the semiconductor substrate side is b and the pattern width of the other side facing the one side of the semiconductor substrate is a,
FIG. 5B shows b / a ≧ 0.97, and FIG. 5C shows b / a
= 1.00, and FIG. 5D shows b / a ≦ 1.03. Therefore, a pattern layer 2 satisfying 0.97 ≦ b / a ≦ 1.03 can be obtained. Further, when the height of the pattern layer 2 is h, h / b (that is, the aspect ratio) can be 3 or more. When a fine pattern having a pattern width of 200 nm or less is formed on the pattern layer 2, an X-ray exposure method or an electron beam drawing method is used. In these methods, the pattern width and the aspect ratio as described above are used. Has not yet been realized.

[Second Embodiment] FIG. 6 is a view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention. (1) First, an electrode wiring metal layer 52 is deposited on a semiconductor substrate 51 by a sputtering method. In the present embodiment, a GaAs wafer having a flat surface is used for the semiconductor substrate 51, and WSi is used for the electrode wiring metal layer 52. The thickness of WSi is 700 nm. (2) Next, a positive photoresist (for example, THMR-ip-1800 manufactured by Tokyo Ohka) is formed on the electrode wiring metal layer 52.
Is applied. The thickness of the positive photoresist is 2000n
m, the post-bake temperature is 120 ° C. (3) Next, by the i-line stepper device and the phase shift method,
A resist pattern sample 53 having a line width of 250 nm is formed (see FIG. 6A).

(4) This sample is placed in a microwave etching (ECR) apparatus (for example, Model M-206 manufactured by Hitachi) and the following etching is performed. This device (Hitachi M-2
Type 06) can eliminate metal contamination because the plasma is surrounded by a quartz dielectric, and the temperature of the substrate is controlled by flowing a cooling gas to the back surface of the substrate, and He gas is introduced into the reaction chamber at 5 sccm. It is known that He dissociates in plasma to cause a photoexcitation reaction. From this point of view, there is a possibility that etching, ashing reaction, polymer formation, and the like are affected. Initially, a reaction chamber pressure 5 × 10 ^-6 to
After the pressure was adjusted to rr or less, the resist pattern sample 53 was adjusted to a gas temperature of 0.015 torr by introducing a substrate temperature of 25 ° C. and an oxygen gas flow rate of 200 sccm. Microwave (oscillation frequency 2.45 GHz) power 560 W, bias high frequency (oscillation frequency 2 MHz) power 3 W
The first processing is completed by narrowing the resist pattern sample 53 to 100 nm in an etching time of 35 seconds (FIG. 6B).
reference). This resist pattern sample functions as an etching mask 54 in FIG. 6B.

At this time, in order to prevent processing failure due to deformation of the resist, it is necessary to leave a resist thickness in which the ratio of the remaining resist pattern film thickness to the electrode wiring metal film thickness is about 3 or more in accordance with the design rule. There is. The etching by oxygen plasma in this step may be omitted when a desired target pattern dimension is obtained. (5) Next, the condition for generating the rabbit ear 55, S
The WSi is etched with 10 sccm of F ₆ gas, 40 sccm of CHF ₃ gas, a gas pressure of 0.05 torr, a microwave power of 560 W, and a bias high frequency power of 10 W (see FIG. 6C). The etching depth at this time is about 467 nm, which corresponds to で は of the total film thickness of 700 nm.
The degree is removed by etching, and the second processing of the kaname is stopped. Subsequently, about 233 nm corresponding to the remaining 1/3 is processed in the next step.

(6) Next, as a third process, the gas pressure is set to 0.01 to
rr, the high frequency power is switched to 3 W, and the operation is performed while the rabbit ear effect is continued (see FIG. 6D). The overetching time is 5 seconds in consideration of the tailing of the neck portion and the film thickness distribution of the electrode metal wiring film 52 of the wafer. This over-etching is also effective in removing foreign substances and metal residues. Precise control of the etching amount is automated by a dedicated CPU using a sharp end point detection method for detecting a plasma emission spectrum, thereby enabling fine processing with excellent dimensional accuracy and improving reproducibility. For example, WS
In the case of i, the wavelength of W (4008.753 °) is detected.

(7) Next, in the fourth processing, all the remaining resist is ashed by oxygen plasma. The conditions are as follows: the flow rate of oxygen is set to 50 sccm, the pressure is set to 0.01 torr, the microwave power is set to 560 W, the bias high frequency power is set to 10 W, and the ashing is performed for 5 minutes. (8) Next, after etching, the sample was taken out, and the cross section of the pattern was observed with a scanning electron microscope. The result shown in FIG. 2 was obtained. The resist height is 400n
m, height of WSi is 700 nm, neck is 50 n
m. Although the shape is a wedge type, when applied to a gate, the surface of the head can be enlarged to reduce the contact resistance. In order to make the wedge shape vertical, in this case, the apparent center of gravity may be set in a low range. In addition,
In this embodiment, SF ₆ is used as an etchant gas. However, similar effects can be obtained by using another etchant gas. In addition, a mixed gas of a polymer deposition gas and an etchant gas may be used as oxygen, nitrogen, argon, or the like. May be introduced.

[0032] Similarly, the polymer deposition gas is not limited to only CHF _3. In the present embodiment, a semiconductor substrate is used as the substrate (51). However, the electrode wiring metal layer 52 can be coated on the insulating film and the dielectric substrate by vapor deposition, sputtering, CVD, or plating. Further, in the embodiment, WSi is used for the electrode wiring metal layer 52, but other silicide such as MgSi, CaSi, TiSi,
VSi, CrSi, MnSi, FeSi, CoSi, N
iSi, ZrSi, NbSi, MoSi, RuSi, R
hSi, PdSi, HfSi, TaSi, ReSi, O
sSi, IrSi, PtSi, etc. can also be used. In addition, as a salicide, for example, a Ti-based or Co-based metal, for example, as a metal, for example, Al, Mo, Ti, Ta,
W, Pt, Pd, Au, Ag, Cu, Cr, Fe, etc.
Undoped polysilicon or doped polysilicon and barrier metal include Ti, TiN, TiSi
N, Ta, TaN, TaC, TaSiN, TaCe
O ₂ , Ir ₄₆ Ta ₅₄ , W, WN, W ₂ N, W ₆₄ B ₂₀ N ₁₆ ,
Such as _{W 23 B 49 N 28, W} 47 Si 9 N 44 can be used.
Among these, one or more single-layer films or multilayer films can be used.

In the embodiment, the photoresist THMR-ip-1800 is used as the organic photosensitive material thin film. However, the present invention can be applied to a general organic photosensitive polymer thin film, or Organic photosensitive material thin film (main) and transfer etching mask (sub), for example, SiO ₂ , S
The same effect can be obtained by applying a multilayer thin film of i, Si ₃ N ₄ and an inorganic material thin film such as Al, Si, W, WSi, Cr, or another organic polymer, or an inorganic photosensitive material thin film. it can. Here, the main and sub are masks transferred from main to sub. The process of reducing the width of the mask pattern by the phase shift method or the oxygen plasma described in this embodiment can be omitted. In this embodiment, the etching mask is formed by using a resist mask formed by an i-line reduction phase shift method, but other resists such as an excimer laser method, an X-ray exposure method, an ion beam method, and an electron beam drawing method are used. A mask can be used, and the present invention is not limited to this embodiment. As described above, according to the present embodiment, fine and high aspect ratio dry etching can be performed by etching using the rabbit ear effect that occurs during dry etching of the organic photosensitive material thin film and the electrode wiring metal. . Therefore, this invention is
If applied to the gate and wiring of T, 200 nm for i-line
This is useful because the following fine processing can be formed with high precision.

[Third Embodiment] FIG. 7 is a diagram for illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. (1) First, on a semi-insulating gallium arsenide (GaAs) substrate 10, an undoped gallium arsenide (i-GaAs) layer 11 having a thickness of about 300 nm as a buffer layer, and indium gallium having a thickness of 20 nm as a channel layer. Arsenic (i-InGaAs) layer 12 and electron supply layer 15
n-type indium gallium phosphide (n-In)
GaP) layer 13 and 5 nm as an etching stopper layer
Gallium arsenide (i-GaAs) layer 14 and an n-conductivity type gallium arsenide (n-GaAs) layer 15 having a thickness of at least 20 nm or more as a cap layer are sequentially laminated by epitaxial growth (see FIG. 7A). ).

(2) Next, to form a gate electrode
Next, select a predetermined area of the laminate with a photoresist pattern
Is etched away, and the air exposed from the opening 16 is removed.
Isotropic wet etching on the etching stopper layer 14
I do. Subsequently, the remaining etching stopper layer 14 is
Select up to the depth to reach the n-InGaP layer 13 immediately below
The connection hole 17 is formed by performing anisotropic dry etching
(See FIG. 7B). (3) Next, the gate is formed in the same process as in the first embodiment.
A gate made of WSi having a length of 50 nm and a gate height of 200 nm
A gate lower electrode 18 is formed (see FIG. 7C). (4) Next, as the first passivation film, a film thickness of 75
nm of silicon oxide (SiO_Two) Layer 19 and moisture blocking film
15 nm thick silicon nitride (Si_ThreeN_Four) Layer 20
And a 60 nm-thick oxidation film as a second passivation film.
Silicon (SiO _Two) Layer 21 is formed by CVD.
After that, the upper layer SiO_TwoEtch back the membrane 21 or
Planarization and gate electrode exposure are performed by CMP (FIG. 7).
(D)).

In this embodiment, since the insulating film is deposited after the gate electrode is processed, there is no crack or void, the gate electrode can be formed thick without changing the gate length, and the parasitic resistance can be reduced. Can be reduced. (5) Next, a silicon oxide (SiO ₂₎ layer 19 and a silicon nitride (Si ₃ N ₄₎ layer 20 and silicon oxide (SiO
₂ ) A predetermined area of the layer 21 is selectively dry-etched and removed by a photoresist pattern, and after the resist is stripped, titanium / platinum / gold (Ti / Pt / A
After the ohmic electrode made of u) is deposited, a heat treatment is performed at 450 ° C. for 1 minute to selectively remove a predetermined region by a photoresist pattern by milling, and the source electrode 22, the gate upper electrode 23, and the drain electrode 24 are formed. Is formed (see FIG. 7E). In this embodiment, the distance between the substrate and the upper electrode is long, so that the fringing capacitance can be reduced.

[Fourth Embodiment] A method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described below. (1) First, a semi-insulating indum phosphorus (InP) substrate 1
Undoped indium aluminum arsenide (i-InAlA) having a thickness of about 200 nm as a buffer layer on
s) layer 11, an indium gallium arsenide (i-InGaAs) layer 12 having a thickness of 15 nm as a channel layer,
An n-conductivity type indium aluminum arsenide (n-InAlAs) layer 13 having a thickness of 15 nm as an electron supply layer, and a 5 nm indium phosphorus (i-I) as an etching stopper layer.
nP) layer 14 and at least 15 nm as cap layer
The n-conductivity type indium gallium arsenide (n-I
An nGaAs) layer 15 is sequentially formed by an epitaxial growth method (see FIG. 7A). This embodiment is a typical InP-based HEMT structure. Hereinafter, a semiconductor device is manufactured in the same steps as in the third embodiment.

According to the present invention, excimer radar light exposure,
No special equipment such as X-ray (SOR) exposure and electron beam lithography is required, and a general i-line stepper apparatus and an ECR dry etching apparatus are used.
Fine processing of 0 nm or less can be performed with a high aspect ratio, and the throughput can be improved.
In addition, the present invention simplifies the structure and process, improves reliability,
The reproducibility can be improved, and it is very effective in the manufacture of semiconductor devices such as semiconductor devices and memory elements, and other electrode wirings. Hereinafter, main functions and effects of the present invention will be described. (1) Fine processing with a line width of about 200 nm or less, which was almost impossible in the past. The limit of the line width is 130 n by the ArF excimer laser light exposure method.
m, 10 nm by X-ray contact exposure method, 10 n by electron beam lithography
m. In the light exposure method, this value (50 nm or less) of the example of the present invention is not yet known. HEM with a gate length of 30 nm
Since the operation of MOSFETs of T and 40 nm has been confirmed, it is possible to miniaturize the device itself. However, when considering the technology for mass production, the microfabrication technology of 100 nm or less has not seen the light of day.

(2) High Aspect Ratio by Microfabrication The increase in the layer thickness of the electrode wiring structure along with the miniaturization of patterns involves a reduction in dimensions and an accompanying increase in aspect ratio. The electron beam writing method most used for miniaturization has an aspect ratio of about 2, whereas the present invention has a height of 700 nm.
/ Width 50 nm = 14. (3) Special Apparatus According to the present invention, submicron electrode wiring processing can be performed using only an i-line stepper apparatus and an electron cyclotron resonance (ECR) etching apparatus, and excimer laser exposure, X-ray (SO
R) No special equipment and operation and maintenance such as development technology such as exposure and electron beam drawing, and price are required. If the operation speed of the LSI is increased along with the miniaturization and the cost per unit function and the power consumption are not reduced, they cannot be accepted in the market. If the design rule becomes smaller than about 100 nm, many of the currently widely used processing apparatuses cannot be used, and it is necessary to introduce new technologies and new materials.

(4) Throughput Throughput is the biggest issue in electron beam lithography, which is the most advanced in fine processing, and it is said that there is no breakthrough at present. A variable rectangular beam or batch exposure is considered as a method of improving the light exposure. However, if the light exposure time is 1 second, it takes 1 hour with the variable rectangular beam and 1 minute even with the batch exposure. Batch exposure makes it difficult to realize a mask. Since electrons do not pass through the glass due to charged particles, a mask must be made with a hole in the portion where the electrons are to be transmitted. The mask needs to be approximately 100 times the size.

In electron beam drawing, it is necessary to correct the proximity effect for a pattern of 1000 nm or less. As the pattern becomes finer, its correction becomes rapidly difficult, and as a method of reducing the proximity effect, the pattern shape is corrected by a computer, the dose is corrected by a computer, the low acceleration voltage drawing, the high acceleration voltage drawing, and the pattern is connected. It is necessary to process a large amount of alignment for moving at high speed. These methods are effective for a pattern of 1000 to 500 nm, and for a pattern of about 250 nm or less, the time required for correction becomes enormous and is not always effective.
If there is a lot of software, it will take time to execute and the throughput will decrease. On the other hand, according to the present invention, a pattern layer having a pattern width of 200 nm or less and a high aspect ratio can be formed with improved throughput.

(5) Simplification Excimer laser, X-ray, electron beam drawing, etc. have many development issues, but the established i-ray exposure technology can be inherited as it is. Complex structures such as embedding and two-step recesses and their advanced manufacturing processes have many disadvantages from a technical viewpoint such as elimination of factors that lower the reliability yield, and are not preferable from an economic viewpoint such as productivity cost. . Therefore, a simple structure and a simple process are required to simplify the manufacturing process. In the present invention, since the established i-line exposure technology can be inherited as it is, the manufacturing process can be simplified.

(6) Reliability When the pattern layer of the present invention is used for wiring, it is effective for scaling by increasing the density of wiring, and the reliability is improved by reducing the interaction between wiring such as wiring capacitance and crosstalk. Can be achieved. For the electrode wiring metal, a high melting point metal, a metal with low specific resistance, or a barrier metal is uniformly bonded to Schottky junction, ohmic junction, wiring, etc.
Since it is a continuous laminated structure without cracks and voids, problems such as low resistance of metal, adhesion, oxidation prevention, peeling due to poor interface characteristics, electromigration resistance, wettability, metal diffusion and contact failure etc. A highly reliable electrode wiring metal can be obtained without occurrence.

(7) Reproducibility According to the present invention, precise control of the etching amount is performed by using a sensitive end point detection method for detecting a plasma emission spectrum.
The automation by the CPU enables fine processing with excellent dimensional accuracy and reliability, thereby improving reproducibility. (8) In the case where the miniaturization of the present invention is used for a semiconductor device The device structure has been miniaturized with the increase in the degree of integration and density of the device.
When used for manufacturing a gate electrode of an FET, an increase in transconductance and a reduction in gate capacitance due to a shortened gate length can be the most effective means for improving a cutoff frequency.

(9) When the present invention is used for a buried T-shaped gate: A buried method using a combination of a conventional lift-off method using a multilayer electron beam resist, a method using a self-alignment forming technique of a side wall insulating film, etc. Cracks and voids cause defects such as poor performance due to poor insulation and poor shape of the semiconductor device.Furthermore, in the sub-half micron generation, low resistance between gate wiring and no It is difficult to avoid generation of cracks and voids. The present invention can solve these problems and can manufacture a highly reliable semiconductor device having a fine pattern with a vertical cross-sectional shape and high performance at a high yield. In order to improve the high frequency characteristics of the FET, it is important to reduce the gate parasitic resistance and the gate fringing capacitance while shortening the channel. When a T-shaped gate electrode is manufactured according to the present invention, the effective gate length is shortened in the lower shape, and the gate cross-sectional area is increased in the upper shape.
In order to reduce the parasitic resistance and increase the gate fringing capacitance, the aspect ratio between the upper gate electrode and the substrate can be increased.
Higher speed of T can be achieved.

(10) Self-Aligned Gate According to the present invention, a T-shaped gate can be provided by a self-alignment method preceding the gate without using an unstable burying method having a small gate resistance even with a small gate length. Since the gate is formed by processing the gate metal of a single-layer film or a laminated film deposited on the entire surface of the semiconductor substrate, the effective gate length can be shortened with higher reliability and accuracy than the buried structure, so that the speed of the FET can be increased. . The upper gate wiring can be overlapped with the lower gate in a self-aligned manner by etching back, so that the mask can be easily aligned and formed without displacement. In addition, the distance between the gate and the drain and the distance between the gate and the source can be set independently, and the width of the pattern created by lithography is reduced to the design dimension or less. Each can be set to the required value. Therefore, it is possible to electrically form a defect-free pattern with reasonable throughput and dimensional accuracy / overlay accuracy in mass production.

(11) Accuracy If the linearity of the transfer pattern dimension with respect to the design dimension is not degraded, the i-line reduced projection exposure is more advantageous than the same-size X-ray exposure because it is a 5-fold mask. In the case of 100 nm on a mask, even a pattern transfer using a 5 × mask has an accuracy of about 20 nm on a wafer. Further, when the transfer processing of the present invention is employed, the mask accuracy on the wafer is about 10 nm or less.

(12) Causes of fine processing The causes of the excellent fine processing characteristics of the present invention as described above can be inferred as follows. Side etching is considered to be caused by active species that react in the horizontal direction, such as fluorine radicals. In the present invention, by mixing hydrocarbons, these active species react with carbon, hydrogen, and sulfur to reduce the amount of carbon. Hydrogen / fluorine / sulfur compounds selectively repeat the formation and disappearance of the plasma polymerized film on the side surface of the organic material thin film, and suppress the side etching at that rate,
This is thought to be due to a unique phenomenon that has the three effects of preventing the occurrence of rabbit ears from retreating. As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Of course, it is.

[0049]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, the pattern width is 200
It is possible to form a pattern layer having a high aspect ratio of not more than nm with an improved throughput.

[Brief description of the drawings]

FIG. 1 is a view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a view for explaining an etching suppressing wall in the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a graph showing the etching rate and selectivity of WSi and resist when the composition ratio of SF ₆ and CHF ₃ as an etchant gas and a polymer deposition gas is changed.

FIG. 4 is a photograph showing an example of a processed shape of WSi and a resist when the composition ratio of SF ₆ and CHF ₃ as an etchant gas and a polymer deposition gas is changed.

FIG. 5 is a diagram for explaining a pattern layer manufactured by the manufacturing method according to the first embodiment of the present invention;

FIG. 6 is a view illustrating a method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a view illustrating a method for manufacturing the semiconductor device according to the third embodiment of the present invention.

[Explanation of symbols]

1, 10, 51: semiconductor substrate, 2: pattern layer, 3, 5
3, resist pattern sample, 4, 54 etching mask, 5, 55 etching suppression wall (rabbit ear), 10 semi-insulating gallium arsenide (GaAs) substrate,
11: buffer (i-GaAs) layer, 12: channel (i-InGaAs) layer, 13: electron supply layer (n-In)
GaP) layer, 14 ... etching stopper (i-GaAs)
s) layer, 15: cap (n-GaAs) layer, 16: opening, 17: connection hole, 18: gate lower electrode, 19, 2
1 ... silicon oxide (SiO ₂₎ layer, 20 ... silicon nitride (Si ₃ N ₄₎ layer, 22 ... Source electrode, 23 ... upper gate electrode, 24 ... drain electrode, 52 ... electrode wiring metal layer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/812 H01L 29/80 F 29/778 H F term (Reference) 4M104 AA04 AA05 BB01 BB02 BB04 BB06 BB07 BB08 BB09 BB13 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB32 BB33 BB34 BB35 BB36 DD04 DD34 DD37 DD43 DD52 DD53 DD62 DD66 DD67 FF06 FF08 AFF16A14H16 FF18 A EA40 EB02 5F033 GG02 HH07 HH08 HH11 HH13 HH14 HH17 HH18 HH19 HH20 HH25 HH26 HH27 HH28 HH29 HH30 HH32 HH33 HH34 HH35 MM08 MM17 MM19 PP06 PP15 PP19 PP27 PP28 QQ01 QQ08 QQ10 QQ12 QQ16 QQ25 QQ27 QQ28 QQ48 VV06 XX03 XX10 5F102 FA03 GB01 GC01 GD01 GJ05 GJ06 GK04 GK05 GL04 GM04 GN04 GN05 GN08 GQ01 GS04 GT03 GT05 GV06 GV07 GV08 HC01 HC17

Claims (6)

[Claims] 1. A semiconductor device having a pattern layer provided on one main surface of a semiconductor substrate, wherein a pattern width of the pattern layer on the semiconductor substrate side is b, and a height of the pattern layer is h. b ≦ 200 nm,
A semiconductor device satisfying h / b ≧ 3. 2. A semiconductor device having a pattern layer provided on one main surface of a semiconductor substrate, wherein a pattern width of the pattern layer on the semiconductor substrate side is b, and a pattern of the pattern layer farthest from the semiconductor substrate is provided. When the width is a, b ≦ 200 nm and 0.97 ≦ b / a ≦
A semiconductor device satisfying 1.03. 3. When the height of the pattern layer is h,
3. The semiconductor device according to claim 2, wherein the kaname portion of the pattern layer is a portion having a height of about h / 3 from one side of the semiconductor substrate. 4. 4. A step of forming a material to be etched on one main surface of a semiconductor substrate; a step of forming a mask pattern on the material to be etched; Etching a region other than the mask pattern of the material to be etched by a dry etching method using an etchant gas and a polymer deposition gas. 5. The material to be etched after the etching,
5. The method according to claim 4, wherein the method is a gate electrode. 6. The material to be etched after the etching,
The method according to claim 4, wherein the method is a wiring pattern.