JP2002279798A - Semiconductor integrated circuit and method for measuring transistor thereof - Google Patents

Abstract

[PROBLEMS] To measure a transistor itself in an actual device, instead of using a measurement TEG in measuring transistor characteristics of a differential sense amplifier built in a DRAM or the like. SOLUTION: Transistors N6 to N interposed between a bit line pair equalizing circuit 2 and bit lines BL and / BL are provided.
9, means for turning off the transistors P3 and N3 for controlling the voltages of the sense amplifier drive lines 106 and 107, and the transistor N10 for equalizing the sense amplifier drive lines, and applying a voltage to the data line pair DQ, / DQ and the sense amplifier drive lines. External input / output terminal PAT that can forcibly apply
By using 1 to PAT4, it is possible to directly measure the transistor characteristics of the semiconductor integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to measurement of characteristics of transistors on a semiconductor integrated circuit, and more particularly to measurement of transistors forming a differential sense amplifier in a semiconductor memory device.

[0002]

2. Description of the Related Art With the rapid progress in miniaturization of transistors, transistor characteristics between chips vary, and even between adjacent transistors having the same shape, transistor characteristics may vary due to manufacturing variations. is there.

For this reason, it is important to measure the characteristics of adjacent transistors on an actual device so that the characteristics can be evaluated.

In particular, in a differential sense amplifier which amplifies a small potential difference read by a memory cell array of a DRAM or an SRAM and transfers a signal to a data line buffer via a data line, the characteristic of the transistor is used. Is very important.

[0005] Generally when measuring the characteristics of the transistors, for example, the source voltage V _s and a back bias V _b to VSS in the NMOS transistor as shown in FIG. 3, applying an external potential of VCC and the like to the drain potential V _d, the gate potential V the _g by applying a potential V _g from VSS to VCC, the drain - measuring the drain current I _d flowing between the source can be obtained characteristics of the transistor.

In order to measure such transistor characteristics on an actual device, measurement is performed using a TEG dedicated to measurement.

[0007]

However, in consideration of the fact that manufacturing variations occur even between adjacent transistors having the same shape as described above, it is necessary to measure the transistor characteristics of a TEG other than the device to be measured used as a product. Even if it is performed, there is a very high possibility that the characteristic is not exactly what is desired.

In addition, the situation of peripheral circuits, manufacturing conditions, and the like may differ between a transistor formed as a TEG and a transistor formed on a product, so that the pairing of a sense amplifier transistor in an actual device is not measured. It is difficult to determine the actual transistor characteristics.

Therefore, the object of the present invention is not to measure the transistor characteristics by TEG but to directly measure the actual device used as a product, so that the transistor characteristics can be measured by using the external input / output terminals of the actual device. An object of the present invention is to provide a method for measuring a semiconductor integrated circuit and a transistor thereof.

[0010]

[MEANS FOR SOLVING THE PROBLEMS] A differential sense amplifier, first and second bit lines connected to the differential sense amplifier, and a first bit line for transmitting and receiving signals to and from the first bit line. A data line, a second data line for transmitting and receiving signals to and from the second bit line, a first external input / output terminal connected to a high potential power supply node of the differential sense amplifier, Connected to the low potential power supply node of the sense amplifier
An external input / output terminal, a third external input / output terminal connected to the first data line, a fourth external input / output terminal connected to the second data line, and the first data input / output terminal. Line and the first
A first column select gate transistor interposed between the second data line and the second bit line; and a second column select gate transistor interposed between the second data line and the second bit line. In measuring the transistor of the dynamic sense amplifier, the first and second column select gate transistors are turned on, and the potential supply to the gate, drain and source of the transistor other than the first to fourth external input / output terminals is performed. The problem is solved by a semiconductor integrated circuit having a test circuit for interrupting a path.

In the semiconductor integrated circuit, the test circuit is controlled, and a gate potential and a drain potential are applied to a transistor to be measured by the differential sense amplifier from the first to fourth external input / output terminals. And a step of applying a source potential to the semiconductor integrated circuit.

According to the present invention, it is possible to measure the characteristics of a transistor constituting a sense amplifier circuit directly on an actual device via an external input / output terminal, and to determine the characteristics of a transistor of a semiconductor integrated circuit. It can be measured accurately.

[0013]

[First Embodiment] FIG. 1 shows a first embodiment of the present invention.

The bit line pairs BL and BL in the sense amplifier region
/ BL is connected to the bit line pair BLL, / BLL in the memory cell array region on the left side in FIG. 1 via NMOS transistors N6, N7 driven by the signal line MUXL (the control signal line 101 controlled by the test circuit 1). Each is connected. An equalizing circuit 2 controlled by a signal line EQLL is connected to the bit line pair BLL and / BLL.

The bit line pair BL and / BL is connected to a signal line MUXR (a control signal line 1 controlled by the test circuit 1).
01) driven by the NMOS transistors N8, N
9 are connected to bit line pairs BLR and / BLR in the memory cell array region on the right side in FIG.
Then, like the left bit line pair, the right bit line pair BLR,
The equalizing circuit 2 controlled by the signal line EQLR is also connected to / BLR.

Further, a bit line pair BL, / BL is connected to a column selection line CSL (a control signal line 1 controlled by the test circuit 1).
05) are connected to the data line pair DQ and / DQ via NMOS transistors N4 and N5 driven by N5, respectively, and the minute potential difference on the data line pair DQ and / DQ is amplified to a logical amplitude by a data line amplifier circuit (not shown). Is done.

The differential sense amplifier of this embodiment is an NMO
It comprises an N-channel sense amplifier composed of S transistors N1 and N2, and a P-channel sense amplifier composed of PMOS transistors P1 and P2.

Here, the drive line 107 of the N-channel sense amplifier is connected to a low-potential-side power supply via an NMOS transistor N3 driven by a signal line SEN (the control signal line 104 controlled by the test circuit 1). .

The driving line 1 of the P-channel sense amplifier
06 is a PMOS transistor P driven by the signal line SEP (the control signal line 102 controlled by the test circuit 1).
3, a high-potential-side power supply is connected.

Further, the drive line 107 of the N-channel sense amplifier and the drive line 106 of the P-channel sense amplifier are equalized. To control the equalization, a sense amplifier equalize is provided between the drive lines 107 and 106. The NMOS transistor N10 is controlled by a signal line EQLSA (the control signal line 103 controlled by the test circuit 1).

The drive line 106 for the P-channel sense amplifier, the drive line 107 for the N-channel sense amplifier, and the data line pair DQ, / DQ are connected to external input / output terminals PAT1 to PAT4, respectively.

The signal line MUXL and the column selection line CS
L, signal line MUXR, sense amplifier equalize signal line E
The QLSA, the signal line SEN, and the signal line SEP are controlled by the test circuit 1.

Next, a method of measuring the transistors used in the differential sense amplifier of the semiconductor integrated circuit of FIG. 1 will be described.

In order to make the NMOS transistors N6 to N9 non-conductive, the test signal 1
(The signal line MUXL and the signal line MUXR) are set to VSS, and the bit line pair BL, / BL and the left and right bit line pair BL
L, / BLL and BLR, / BLR and these bit line pairs are separated from the equalizing circuit.

In order to make the NMOS transistor N10 non-conductive, the test signal 1
(Signal line EQLSA) is set to VSS.

The PMOS transistor P3 and the NMO
To make the S transistor N3 non-conductive, the test circuit 1
, The control signal line 102 (signal line SEP) is connected to VCC,
With the control signal line 104 (signal line SEN) set to VSS, power supplied to drive the differential sense amplifier is cut off.

The NMOS transistors N4 and N5
In order to turn on the control signal line 1 in the test circuit 1,
05 (signal line CSL) as VCC and the data line pair DQ
And / DQ to the bit line pair BL and / BL.

As described above, by cutting off the potential supply path not related to the measurement of the transistor characteristics of the semiconductor integrated circuit, the transistor characteristics can be directly measured using the external input / output terminals.

Next, a specific example of measuring the transistor characteristics of the NMOS transistor N2 forming the differential sense amplifier in the semiconductor integrated circuit of FIG. 1 will be exemplified.

In the NMOS transistor N2, the external input / output terminal PAT2 is connected to the drain of N2 and the external input / output terminal PA.
T4 is the source of N2, and external input / output terminal PAT3 is N
2 corresponds to the gate.

Therefore, a drain potential (eg, VCC) is applied to the external input / output terminal PAT2, and a source potential (eg, VSS) is applied to the external input / output terminal PAT4.
Varying the gate potential V _g which gives to AT3, by measuring the external input and output terminals PAT2 the drain current I _d displaced with it, it is possible to measure the V _g -I _d characteristics of the transistors N2. Here, VSS is applied to the external input / output terminal PAT1.

Here, as for the MOS transistors N1, P1 and P2 other than the NMOS transistor N2 to be measured, the gate potentials of the NMOS transistor N1 and the PMOS transistor P2 are such that the respective transistors are turned off. , N2 are not affected. The PMOS transistor P1 is NM
Although turned on when measuring the OS transistor N2, VSS is applied to the external input / output terminal PAT1, so that the measurement near the most important threshold value is not affected.
It does not particularly affect the measurement of N2.

Next, when measuring another NMOS transistor N1 constituting the N-channel sense amplifier, the drain potential (for example, V
CC), a source potential (for example, V
SS) giving, varying the gate potential V _g which gives to the external input and output terminals PAT4, the drain current I _d displaced with it
By measuring the external input and output ends PAT2, it is possible to measure the V _g -I _d characteristics of the transistors N1.

The measurement of the P-channel sense amplifier is the same as that of the N-channel transistor.

When measuring the PMOS transistor P2, the drain potential (for example, V
SS), and a source potential (for example, V
CC) give, varying the gate potential V _g which gives to the external input and output terminals PAT3, the drain current I _d displaced with it
Is measured at the external input / output terminal PAT1, so that it can be measured similarly to the N-channel transistor. Another PMOS transistor P1 constituting the P-channel sense amplifier can be measured in the same manner.

The external input / output terminals PAT1 to PAT4
Is bonded to the lead electrodes, so that the transistors of these semiconductor integrated circuits can be measured even in a package state after assembly.

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.

The bit lines BL and BL in the sense amplifier area
/ BL is connected to a pair of bit lines BLL and / BLL in the memory cell array region on the left side in FIG. 2 via NMOS transistors N6 and N7 driven by a signal line MUXL. Then, the bit line pair BLL, / B
The equalizer circuit 2 controlled by the signal line EQLL is connected to LL.

The bit line pair BL, / BL is connected to the signal line M
NMOS transistors N8 and N driven by UXR
9 are connected to the bit line pairs BLR and / BLR in the memory cell array region on the right side in FIG.
Then, like the left bit line pair, the right bit line pair BLR,
The equalizing circuit 2 controlled by the signal line EQLR is also connected to / BLR.

Further, the bit line pair BL, / BL is an NMOS transistor N driven by a column selection line CSL.
4 and N5 are connected to the data line pair DQ and / DQ, respectively, and a minute potential difference on the data line pair DQ and / DQ is amplified to a logical amplitude by a data line amplifier circuit (not shown).

The differential sense amplifier of the present embodiment is an NMO
It comprises an N-channel sense amplifier composed of S transistors N1 and N2, and a P-channel sense amplifier composed of PMOS transistors P1 and P2.

Here, the drive line 107 of the N-channel sense amplifier is connected to a low potential side power supply via an NMOS transistor N3 driven by the signal line SEN.

The driving line 1 of the P-channel sense amplifier
Reference numeral 06 is connected to a high-potential-side power supply via a PMOS transistor P3 driven by a signal line SEP.

Further, the drive line 107 of the N-channel sense amplifier and the drive line 106 of the P-channel sense amplifier are equalized. In order to control the equalization, a sense amplifier equalizer is provided between the drive lines 107 and 106. This is via an NMOS transistor N10 controlled by the signal line EQLSA.

The drive line 106 of the P-channel sense amplifier, the drive line 107 of the N-channel sense amplifier, and the pair of data lines DQ and / DQ are connected to external input / output terminals PAT1 to PAT4, respectively.

The signal line MUXL and the column selection line CS
L, signal line MUXR, sense amplifier equalize signal line E
The QLSA, the signal line SEN, and the signal line SEP are connected to external input terminals PAT5 to PAT10, respectively.

Next, a method of measuring the transistors used in the differential sense amplifier of the semiconductor integrated circuit of FIG. 2 will be described.

VSS is applied to the external input terminals PAT5 and PAT7.
Is applied to make the NMOS transistors N6 to N9 non-conductive, and the bit line pair BL, / BL and the left and right bit line pair BL
L, / BLL and BLR, / BLR and these bit line pairs are separated from the equalizing circuit.

Further, VSS is applied to the external input terminal PAT8 to turn off the NMOS transistor N10.

Further, VCC is applied to the external input terminal PAT10 to make the PMOS transistor P3 non-conductive.
VSS is applied to the external input terminal PAT9 to turn off the NMOS transistor N3 and cut off the power supplied to drive the differential sense amplifier.

Further, VCC is applied to the external input terminal PAT6 to turn on the NMOS transistors N4 and N5, thereby making the data line pairs DQ and / DQ and the bit line pairs BL and / BL conductive.

As described above, the transistor characteristics can be directly measured using the external input / output terminals PAT1 to PAT4 by cutting off the potential supply path not related to the transistor characteristic measurement of the semiconductor integrated circuit.

In the first embodiment, the control signal for cutting off the potential supply path not related to the transistor measurement is controlled by the test circuit 1, whereas in the second embodiment, these control signals are also transmitted from the external input terminals PAT5 to PAT10. The transistor characteristics of the semiconductor integrated circuit can be measured by forcibly applying a potential from the outside.

The specific method of measuring the transistor thereafter is the same as in the first embodiment.

In this embodiment, the external input / output terminal P
AT1 to PAT4 and external input terminals PAT5 to PA
By bonding T10 to the lead electrode, it is possible to measure the transistors of the semiconductor integrated circuit even in the package state after assembly.

Further, external input / output terminals PAT3 and PAT3
NMO to prevent the threshold of the potential supplied from 4 from dropping
By applying a voltage higher than the power supply voltage to the external input terminal PAT6 connected to the gates of the S transistors N4 and N5, it is possible to measure the transistor characteristics with higher accuracy.

In the above description, the V _g -I _d characteristic is taken as an example of measurement of a transistor. However, the V _d -I _d characteristic can be naturally measured by the present invention.

In the first and second embodiments,
The sense amplifier circuit is configured to be sandwiched between two memory cell arrays in the entire configuration of the DRAM as shown in FIG. 4, and an example in which one differential sense amplifier functions for two memory cell arrays on both sides. Explained.

However, the present invention can be naturally applied to a sense amplifier circuit configured so that one differential sense amplifier functions only for one memory cell array.

Further, in the first embodiment, all the control signals used to cut off the potential supply paths which are not related when measuring the transistor characteristics of the differential sense amplifier are controlled by the test circuit 1, and in the second embodiment, Although all of the control signals are forcibly applied from the external input terminal, a part of these control signals is controlled by the test circuit, and a part of the control signals can be forcibly applied from the external input terminal. .

Therefore, the present invention is not limited to the embodiment, and various modifications and changes can be made within the scope of the claims.

[0062]

As described above, according to the present invention, it is possible to forcibly input / output a potential from the outside to a drain, a source, and a gate of a transistor of a semiconductor integrated circuit, and supply a potential not related to measurement. By blocking the path, the transistor characteristics of the semiconductor integrated circuit on the actual device can be directly measured.

As a result, the transistor characteristics of the semiconductor integrated circuit on the device as a product can be measured accurately.
The present invention is suitable for device analysis.

Further, since the external input / output terminal connected to the transistor of the semiconductor integrated circuit can be measured after assembly by bonding the lead electrode to the external input / output terminal, the measurement of the present invention can be effectively used even in the analysis of product reversion.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing an NMOS transistor.

FIG. 4 is a block diagram showing an overall schematic configuration in reading from a semiconductor memory device (DRAM).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Test circuit, 2 ... Equalization circuit, PAT1-PAT4 ... External input / output terminal, PAT5-PAT10 ...
External input terminals, N1 to N10 NMOS transistors, P1 to P3 PMOS transistors, 101 to 105 control signal lines, 106 drive lines for P-channel sense amplifiers, 107 drive lines for N-channel sense amplifiers, BL and / BL ... bit line pairs in the sense amplifier area, BLL, / BLL ... bit line pairs in the left memory cell area, BLR, / BLR ... bit line pairs in the right memory cell area, DQ, / DQ ... data line pairs

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G132 AA08 AE22 AG09 AK11 AK22 AL11 5F083 GA30 LA03 LA10 ZA20 5L106 AA01 AA02 DD00 DD31 EE02

Claims (4)

[Claims] A differential sense amplifier; first and second bit lines connected to the differential sense amplifier; a first data line for transmitting and receiving signals to and from the first bit line; A second data line for transmitting and receiving signals to and from the second bit line; a first external input / output terminal connected to a high potential power supply node of the differential sense amplifier; A second external input / output terminal connected to the low potential power supply node; a third external input / output terminal connected to the first data line; and a fourth external input / output terminal connected to the second data line. An external input / output terminal, a first column selection gate transistor interposed between the first data line and the first bit line, and a second data line and the second bit line. A second column select gate transistor interposed therebetween, and the differential sense amplifier In the measurement of the transistor, the first and second column selection gate transistors are turned on, and the potential supply paths other than the first to fourth external input / output terminals to the gate, drain and source of the transistor are cut off. A semiconductor integrated circuit, comprising: a test circuit. 2. A differential sense amplifier, first and second bit lines connected to the differential sense amplifier, a first data line for transmitting and receiving signals to and from the first bit line, A second data line for transmitting and receiving a signal to and from the second bit line; a first external input / output terminal connected to a high potential power supply node of the differential sense amplifier; A second external input / output terminal connected to the low potential power supply node; a third external input / output terminal connected to the first data line; and a fourth external input / output terminal connected to the second data line. An external input / output terminal, a first column select gate transistor interposed between the first data line and the first bit line, and a second data line and the second bit line. A second column select gate transistor interposed between the first and second transistors; A transfer gate provided on each of the first and second bit lines in a region between an equalizing circuit for equalizing a read line and the differential sense amplifier; and a first control signal line for driving the transfer gate. A second control signal line for driving a first sense amplifier activating transistor interposed between a high-potential power supply node of the differential sense amplifier and a high-potential power supply; and the differential sense amplifier A third control signal line for driving a second sense amplifier activating transistor interposed between the low potential power supply node and the low potential side power supply, and a high potential power supply node of the differential sense amplifier. A fourth control signal line interposed between the low-potential power supply node and driving a sense amplifier equalizing transistor for equalizing the two power supply nodes; The semiconductor integrated circuit characterized by comprising a fifth control signal line for driving the first and second column selection gate transistors, and a test circuit for controlling the first to fifth control signal line. 3. The first test circuit for forcibly applying a potential to turn off the transfer gate, the first and second sense amplifier activating transistors, and the sense amplifier equalize transistor, respectively, by the test circuit. Controlling a fifth control signal line to forcibly apply a potential for turning on the first and second column select gate transistors; and controlling the fifth control signal line to forcibly apply a potential for turning on the first and second column selection gate transistors. 3. The semiconductor integrated circuit according to claim 2, further comprising a step of applying a gate potential, a drain potential, and a source potential to a transistor to be measured of said differential sense amplifier from first to fourth external input / output terminals. How to measure transistors in a circuit. 4. A differential sense amplifier; first and second bit lines connected to the differential sense amplifier; a first data line for transmitting and receiving signals to and from the first bit line; A second data line for transmitting and receiving signals to and from the second bit line; a first external input / output terminal connected to a high potential power supply node of the differential sense amplifier; A second external input / output terminal connected to the low potential power supply node; a third external input / output terminal connected to the first data line; and a fourth external input / output terminal connected to the second data line. An external input / output terminal, a first column selection gate transistor interposed between the first data line and the first bit line, and a second data line and the second bit line. A second column select gate transistor interposed between the first and second transistors; A transfer gate provided on each of the first and second bit lines in a region between the equalizing circuit for equalizing the read line and the differential sense amplifier; and a first control signal line for driving the transfer gate. A second control for driving a first sense amplifier activation transistor interposed between a fifth external input terminal connected thereto and a high-potential power supply node of the differential sense amplifier and a high-potential power supply; A sixth external input terminal connected to the signal line, and a second drive terminal for driving a second sense amplifier activating transistor interposed between a low potential power supply node of the differential sense amplifier and a low potential power supply. A third external input terminal connected to the control signal line No. 3 and a high potential power supply node and a low potential power supply node of the differential sense amplifier. An eighth external input terminal connected to a fourth control signal line for driving a sense amplifier equalizing transistor for equalizing a gate, a fifth control signal line for driving the first and second column selection gate transistors, In measuring a transistor of a semiconductor integrated circuit having a ninth external input terminal connected thereto, the transfer gate, the first and second sense amplifier activation transistors, and the sense amplifier equalize transistor are each turned off. To forcibly apply a potential from the fifth to eighth external input terminals, and forcibly apply a potential from the ninth external input terminal to turn on the first and second column select gate transistors. Providing a transistor to be measured by the differential sense amplifier from the first to fourth external input / output terminals. The gate potential, the drain potential and the transistor measuring method of a semiconductor integrated circuit, characterized by comprising the steps of providing a source potential.