JP2002203859A - Wiring forming method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form embedded wiring consisting of conductive material having integrity without any defect in a recess even when the recess part with a high aspect ratio exists. SOLUTION: When a conductive metal 20 is embedded by wet plating on a fine recess part 14 provided on the surface of a board W to form the wiring, a substrate film 18 constituted of two kinds of metals is formed on the surface of the board, and the wet plating is performed on the surface of the substrate film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring and a semiconductor device, and more particularly to a method for embedding a conductive metal such as copper (Cu) in fine recesses for wiring provided on the surface of a substrate such as a semiconductor substrate. The present invention relates to a wiring forming method for forming a wiring, and a semiconductor device having a wiring formed by the method.

[0002]

2. Description of the Related Art Aluminum or an aluminum alloy is generally used as a metal material for forming a wiring circuit on a semiconductor substrate. In recent years, however, the use of copper has become remarkable. This means that the electrical resistivity of copper is 1.
Since it is 72 μΩcm, which is about 40% lower than the electrical resistivity of aluminum, it is not only advantageous for the signal delay phenomenon, but also has a much higher electromigration resistance of copper than the current aluminum, and has a dual damascene more than aluminum. This is because the process is easy to adopt, and there is a high possibility that a complicated and fine multilayer wiring structure can be manufactured relatively inexpensively.

Here, there are three methods of embedding a metal such as copper in a wiring groove and a via hole at the same time by a dual damascene method: CVD, sputtering, and plating. Among these methods, the plating method has a relatively good embedding property into a fine concave portion, and has a strong tendency to form a conductive line with a relatively easy and inexpensive process. It is becoming common sense to incorporate this into a semiconductor mass production line with a design rule generation of 18 μm.

FIG. 7 shows the basic steps of a wiring forming method used to obtain a semiconductor device in which a copper wiring is formed by plating a surface of a semiconductor substrate with copper. That is, as shown in FIG. 7A, a SiO.sub.2 is formed on the conductive layer 1a on the semiconductor substrate 1 on which the semiconductor element is formed, as shown in FIG.
₂ is deposited, and a fine concave portion 5 composed of a contact hole 3 and a wiring groove 4 is formed inside the insulating film 2 by lithography and etching technology.
A diffusion suppression (barrier) layer 6 made of TaN or the like is formed thereon.

[0005] Then, as shown in FIG. 7 (b), copper 7 is filled in the recesses (holes) 5 of the semiconductor substrate 1 by applying copper plating to the surface of the semiconductor substrate W.
Copper 7 is deposited on the diffusion suppressing (barrier) layer 6. afterwards,
The copper 7 on the diffusion suppression (barrier) layer 6 and the diffusion suppression (barrier) layer 6 are removed by chemical mechanical polishing (CMP),
Copper 7 filled in contact hole 3 and wiring groove 4
And the surface of the insulating film 2 are made substantially flush with each other. As a result, an embedded wiring made of copper 7 is formed as shown in FIG.

Here, when copper 7 is buried in the fine concave portion 5 provided on the surface of the semiconductor substrate W by, for example, an electrolytic plating method, as shown in FIG. It is widely practiced to form a base film 8 made of copper or the like to be a power supply (seed) layer on the surface of the diffusion suppressing layer 6 formed on W by, for example, sputtering or CVD.
The main purpose of the underlayer (seed layer) 8 is to reduce metal ions in the liquid by using the surface of the seed layer as an electric cathode,
The purpose is to supply a current sufficient to precipitate as a metallic solid. In the electroless plating method, a catalyst layer is widely provided instead of a power supply layer.

[0007]

By the way, the underlying film 8
Is generally formed by sputtering or CVD,
As the density of the wiring increases, the buried wiring becomes finer, and the aspect ratio of the contact hole and the via hole increases. For example, a recess (hole) 5 having a diameter of 0.15 μm and an aspect ratio of about 6, and a lower portion made of copper, for example, are formed. When the ground film 8 is formed, as shown in FIG. 8, the ratio B ₁ / A ₁ (side coverage) of the film thickness B _{1 on} the side surface of the concave portion 5 of the base film 8 to the film thickness A ₁ on the surface of the substrate W is 5. -10%
In addition, the formation of the continuous underlayer 8 becomes difficult. This is considered to be because, for example, sputtered copper atoms aggregate during film formation.

When copper wiring is formed by performing wet plating such as electrolytic plating or electroless plating in this state, the seed layer disappears due to etching with a plating solution. There was a problem that copper could not be electrodeposited because it could not be secured, and the yield was reduced. When the thickness A of the seed layer corresponding to the base film 8 in FIG. 8 is increased for the purpose of securing the side coverage,
The substantial aspect ratio is increased, so that the hole entrance is closed at the time of filling, voids are generated in the holes, and the yield decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. Even in a recess having a high aspect ratio, a wiring capable of forming a buried wiring made of a sound conductive material having no defect in the recess. It is an object to provide a formation method and a semiconductor device having a wiring formed by the method.

[0010]

Means for Solving the Problems In order to achieve the above object, a method for forming a wiring according to the present invention provides a method for forming wiring by embedding a conductive metal by wet plating in fine recesses provided on the surface of a substrate. A base film made of two or more metals is formed on the surface of the substrate, and wet plating is performed on the surface of the base film.

As a result, even if the recess has a high aspect ratio, a buried wiring made of a healthy conductive material having no defect can be formed in the recess. This improves the side coverage characteristics by utilizing the re-sputtering action at the top and bottom of the concave portion of the metal particles having a large atomic weight and the action of suppressing the cohesive force of the metal particles having a small atomic weight. It is considered that the inclusion of particles can improve the etching resistance.

According to the present invention, the metal constituting the base film is preferably
A combination of a first metal that is the same as the metal forming the buried wiring and a second metal made of a noble metal having an atomic weight larger than that of the first metal. For example, when copper is used for the wiring material, copper is used as the first metal and second metal is used.
Palladium, silver, platinum, or gold are used as the metals for, respectively. Thus, even in a concave portion having a high aspect ratio, copper can be buried in the concave portion by wet plating to form a sound copper wiring without defects.

[0013] The present invention is characterized in that the first metal is gold, silver or copper. This makes it possible to form a wiring made of gold, silver or copper, which has smaller wiring resistance than aluminum and has excellent electromigration resistance.

According to the present invention, the first metal is copper, and the second metal is palladium, silver, platinum or gold.

The present invention is characterized in that the base film is formed by sputtering or CVD.

According to the semiconductor device of the present invention, there is provided a base film made of two or more kinds of metals in a fine concave portion provided on the surface of a substrate, and a conductive metal deposited on the surface of the base film by wet plating. Characterized in that a buried wiring made of

A wiring forming apparatus according to the present invention comprises: a film forming apparatus for forming a base film made of two or more metals on a surface of a substrate provided with fine recesses for wiring; And a plating device for embedding a conductive metal in the recess.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a wiring forming method according to an embodiment of the present invention in the order of steps. In this example, as shown in FIG. 1A, a semiconductor substrate 10 on which a semiconductor element is formed and an insulating film 12 made of SiO ₂ is deposited on a substrate W by, for example, a lithography / etching technique. .1
A fine concave portion (hole) 14 for wiring having a thickness of 5 μm and an aspect ratio of about 6 is formed, and copper is buried in the concave portion 14 by wet plating (electrolytic plating or electroless plating) to form a copper wiring. It was done. First, FIG.
As shown in (a), for example, by sputtering,
A diffusion suppression (barrier) layer 16 made of, for example, TaN is formed on the surface of the substrate W.

Next, as shown in FIG. 1B, a base film 18 serving as a power supply (seed) layer or a catalyst layer is formed on the surface of the diffusion suppressing layer 16 formed on the semiconductor substrate W by, for example, sputtering or CVD. I do. As the material of the base film 18, an alloy of copper, which is the same material as the wiring forming material, and a noble metal having an atomic weight larger than that of copper, for example, palladium, silver, platinum, or gold is used. As this alloy, for example, a copper alloy containing 10 at% palladium (Cu-Pd (1
0 at%)). The content of palladium, silver, platinum or gold in the copper alloy is preferably
0.001 at% to 30 at%, more preferably 0.1 to 30 at%.
001 at% to 10 at%.

As described above, when the base film 18 is formed of a Cu—Pd (10 at%) alloy, the film thickness A _{2 on} the surface of the substrate W having a film thickness B _{2 on} the side surface of the concave portion 14 of the base film 18 made of this alloy. The ratio of B ₂ / A ₂ (side coverage) to the film thickness A _{1 on} the surface of the substrate W having the film thickness B _{1 on} the side surface of the concave portion 5 of the conventional copper-made base film 8 shown in FIG. To B ₁ / A ₁ to improve coverage characteristics, and to provide a continuous base film 18
Is formed.

This is because, in the concave portion (contact hole or peer hole) 14 having a high aspect ratio, palladium particles having an atomic weight larger than that of copper are rounded by the re-sputtering action at the upper portion of the concave portion 14 and at the bottom of the hole. This is considered to be because palladium particles having an improved atomic weight have a function of suppressing the cohesive force of copper particles having a small atomic weight.

Next, as shown in FIG. 1C, the surface of the semiconductor substrate W is subjected to wet copper plating (electrolytic plating or electroless plating) to fill the recesses 14 with copper 20 and to diffuse the copper. Copper 20 is deposited on the suppression (barrier) layer 16. As a result, the copper 20 is buried in the recess 14 without causing defects such as voids and seals.

This is because, as described above, the coverage characteristics of the base film 18 are improved, and the base film 18 contains palladium having an atomic weight larger than that of copper.
This is considered to be because the etching resistance is improved as compared with the conventional base film 8 made of copper, and the etching by the plating solution is suppressed.

Thereafter, as shown in FIG. 1D, the diffusion suppressing (barrier) layer 16 is formed by chemical mechanical polishing (CMP).
The upper copper 20 and the diffusion suppressing (barrier) layer 16 are removed, and the surface of the copper 20 filled in the concave portion 14 and the surface of the insulating film 12 are made substantially flush with each other to form an embedded wiring made of the copper 20. . As a result, even if the recess 14 has a high aspect ratio,
Even in this concave portion 14, a sound copper 20 having no defect is provided.
Is formed.

FIG. 2 is a plan view showing a wiring forming apparatus according to an embodiment of the present invention. This wiring forming apparatus includes two load / unload units 30 accommodating a plurality of substrates W therein, two sputtering apparatuses 32 for forming a base film, and an electrolytic plating apparatus for embedding in the same facility. 34,
A cleaning device 36 and a transfer robot 38 for transferring the substrate W between the cleaning devices 36 are housed therein.

Then, the diffusion suppressing layer 16 (FIG. 1) is formed on the surface.
The substrate W on which (a) is formed is taken out from the loading / unloading section 30 by the transfer robot 38 and is transferred to the sputtering device 32 for forming the base film, and the base film 18 is formed on the surface of the diffusion suppressing layer 16 by sputtering. The formation is performed (see FIG. 1B). As described above, in the case of copper wiring, for example, copper, which is the same material as the wiring forming material, and a noble metal having an atomic weight larger than copper, for example, palladium, silver, platinum, gold, or the like, as described above. Alloy, for example, a copper alloy containing 10 at% palladium (Cu-Pd (1
0 at%)). Then, the substrate W is transported to the first cleaning device 36, the surface thereof is cleaned and dried, and then transported to the electrolytic plating device 34 for embedding, where copper is embedded (see FIG. 1C). . Thereafter, the substrate is washed and dried inside the embedding electrolytic plating apparatus 34 and then returned to the loading / unloading section 30.

In this example, an example is shown in which the sputtering device 32 is used for forming the underlayer, but a CVD device may be used instead of the sputtering device 32. Also, an electrolytic plating apparatus 3 for embedding copper
Instead of 4, an electroless plating apparatus may be used.

FIG. 9 shows another embodiment of the present invention. As shown in the drawing, the present plating apparatus includes a loading / unloading area 520 for transferring a wafer cassette containing semiconductor wafers,
The semiconductor device includes a process area 530 for performing a process, and a cleaning / drying area 540 for cleaning and drying the semiconductor wafer after the process. The cleaning / drying area 540 is arranged between the carry-in / out area 520 and the process area 530. A partition 521 is provided in the loading / unloading area 520 and the washing / drying area 540, and the washing / drying area 5 is provided.
A partition 523 is provided between 40 and the process area 530.

The partition 521 is provided with a passage (not shown) for transferring the semiconductor wafer between the carry-in / out area 520 and the cleaning / drying area 540, and a shutter 522 for opening and closing the passage. I have. In addition, the partition 523
A passage (not shown) for transferring a semiconductor wafer between the cleaning / drying area 540 and the process area 530
, And a shutter 524 for opening and closing the passage. Cleaning / drying area 540 and process area 5
30 is designed to supply and exhaust air independently.

The plating apparatus for wiring a semiconductor wafer having the above configuration is installed in a clean room.
(Pressure of loading / unloading area 520)> (pressure of cleaning / drying area 540)> (pressure of process area 530), and pressure of loading / unloading area 520 is set lower than pressure in the clean room. This prevents air from flowing out of the process area 530 to the cleaning / drying area 540, prevents air from flowing out of the cleaning / drying area 540 to the loading / unloading area 520, and further reduces air from the loading / unloading area 520 into the clean room. To prevent spills.

In the loading / unloading area 520, a load unit 520a for storing a semiconductor wafer storage cassette and an unload unit 520b are arranged. The washing / drying area 540 is provided with two water washing units 541 and two drying units 542 each of which performs a process after the plating process, and is provided with a transfer unit (transfer robot) 543 for transferring a semiconductor wafer. Here, as the water washing section 541, for example, a pencil type with a sponge at the front end or a roller type with a sponge is used. As the drying unit 542, for example, a type in which a semiconductor wafer is spun at a high speed to dehydrate and dry the semiconductor wafer is used.

In the process area 530, a sputtering apparatus 531 for forming a base film of a semiconductor wafer and a plating tank 532 for performing copper plating are arranged.
A transfer unit (transfer robot) 54 for transferring a semiconductor wafer
3 are provided.

FIG. 10 shows the flow of air flow in a plating apparatus for wiring semiconductor wafers. In the washing / drying area 540, fresh external air is taken in from the pipe 546, pushed in by a fan through the high-performance filter 544, and supplied as down-flow clean air from the ceiling 540a around the washing section 541 and the drying section 542. Is done. Most of the supplied clean air is supplied from the floor 540b to the circulation pipe 545.
To the ceiling 540a side, and again the high-performance filter 5
It is pushed by a fan through 44 and circulates in the washing / drying area 540. Part of the airflow is exhausted from inside the washing unit 541 and the drying unit 542 through the duct 552.

Although the process area 530 is referred to as a wet zone, particles are not allowed to adhere to the surface of the semiconductor wafer. Therefore, the process area 53
Particles are prevented from adhering to the semiconductor wafer by flowing down-flow clean air through the high-performance filter 533 by being pushed into the inside of the ceiling 530 by the fan from the ceiling 530a.

However, if the total flow rate of the clean air forming the down flow depends on the supply and exhaust from the outside,
A huge supply and exhaust volume is required. For this reason, only the exhaust that keeps the room at a negative pressure is used as the external exhaust from the duct 553, and most of the downflow airflow is transferred to the pipes 534 and 535.
Through the circulating airflow.

When a circulating air flow is used, the process area 5
The clean air that has passed through 30 contains a chemical mist or gas, and is thus passed through scrubber 536 and mit separator 53.
7,538. This allows the ceiling 530a
The air returned to the circulation duct 534 on the side does not contain a chemical mist or gas, is pushed again by the fan, passes through the high-performance filter 533, and circulates as clean air into the process area 530.

A part of the air passing through the process area 530 from the floor 530b is discharged outside through the pipe 553, and the air containing the chemical mist and gas is discharged outside through the duct 553. From the duct 539 of the ceiling 530a, fresh air corresponding to these displacements is supplied into the process area 530 to such an extent that a negative pressure is maintained.

As described above, the respective pressures of the carry-in / carry-out area 520, the washing / drying area 540, and the process area 530 are (pressure of the carry-in / carry-out area 520)>
(Pressure in the cleaning / drying area 540)> (pressure in the process area 530). Therefore, when the shutters 522 and 524 (see FIG. 9) are opened, the flow of air between these areas flows in the order of the carry-in / out area 520, the cleaning / drying area 540, and the process area 530 as shown in FIG. Further, the exhaust gas passes through the ducts 552 and 553 and is collected in the collective exhaust duct 554 as shown in FIG.

FIG. 12 is an external view showing an example in which a plating apparatus for wiring a semiconductor wafer according to the present invention is disposed in a clean room. The side with the cassette transfer port 555 and the operation panel 556 of the loading / unloading area 520 is the partition wall 5.
It is exposed to the clean working zone 558 of the clean room partitioned by 57, and the other side surface is accommodated in the low clean utility zone 559.

As described above, the cleaning / drying area 540 is disposed between the loading / unloading area 520 and the process area 530, and the loading / unloading area 520 and the cleaning / drying area 5
Since the partition walls 521 are provided between the cleaning zone 40 and the cleaning / drying area 540 and the process area 530, the partition 521 is transported in a dry state from the working zone 558 through the cassette transfer port 555 into the plating apparatus for semiconductor wafer wiring. The semiconductor wafer is plated in a plating apparatus for wiring a semiconductor wafer, and carried out to the working zone 558 in a washed and dried state, so that particles and mist do not adhere to the surface of the semiconductor wafer, and the semiconductor wafer is placed in a clean room. Working zone 5 with high cleanliness
58 is not contaminated with particles, chemicals, or cleaning liquid mist.

In FIGS. 9 and 10, the plating apparatus for wiring semiconductor wafers has a carry-in / carry-out area 520, a cleaning / carrying area, and
Although the example in which the drying area 540 and the process area 530 are provided is shown, an area where a CMP apparatus is arranged in the process area 530 or adjacent to the process area 530 is provided, and an area where the process area 530 or the CMP apparatus is arranged is provided. The cleaning / drying area 540 may be arranged between the loading / unloading area 520. In short, any configuration may be used as long as the semiconductor wafer is carried in a dry state into the plating apparatus for semiconductor wafer wiring, and the semiconductor wafer after the plating process is washed and carried out in a dry state.

In the above example, the substrate plating apparatus is described as an example of a plating apparatus for wiring a semiconductor wafer. However, the substrate is not limited to a semiconductor wafer, and a portion to be plated is also formed on a wiring surface formed on the substrate surface. It is not limited to a department. In the above example, Cu plating was described as an example,
It is not limited to Cu plating.

(Example 1) As a substrate W shown in FIG. 1A, an insulating film 12 made of SiO _{2 is} formed on a semiconductor base material 10.
The insulating film 12 has a diameter of 0.15 μm and a depth of 0.15 μm.
A 9 μm (aspect ratio: 6) concave portion (hole) 14 is prepared, and a 30 nm-thick diffusion suppressing (barrier) layer 16 made of TaN is formed on the surface by sputtering. -Pd (10 at%)
A sample was prepared by forming a 90-nm-thick base film (seed layer) 18 made of an alloy by sputtering (FIG. 1).
(B)). Then, the surface of this sample was subjected to electrolytic copper plating, and copper 20 was embedded in the concave portion 14 (FIG. 1).
(C)). The plating solution composition and plating conditions at this time are as follows. (Plating solution _{composition) CuSO 4 · 5H 2 O 200} g / L H 2 SO 4 55 g / L Cl - 60 mg / L additives Some (plating ^{conditions) 2.5 A / dm 2, 2min} , 25 ℃

FIG. 3 schematically shows a cross-sectional SEM (scanning electron microscope) photograph after the plating process. From this figure,
It can be seen that the copper 20 is uniformly embedded in the concave portion 14 and a sound copper wiring without defects is formed.

(Embodiment 2) As in Embodiment 1, Cu
A sample in which a 90-nm-thick base film (seed layer) 18 made of a -Pd (10 at%) alloy is formed by sputtering, and the surface of this sample is subjected to electroless copper plating to form a base film (seed layer) 18 were reinforced. The plating solution composition and plating conditions at this time are as follows. (Plating solution composition) CuSO ₄ .5H ₂ O 2.5 g / L EDTA.2Na 20 g / L NaOH 4 g / L HCHO (37%) 5 ml / L (Plating conditions) 65 ° C., 60 sec

FIG. 4 schematically shows a cross-sectional SEM (scanning electron microscope) photograph after plating. From this figure,
It can be seen that the seed layer is uniformly and uniformly reinforced, and a sound seed layer 18 without defects is formed.

[0047] As the substrate shown in (Comparative Example 1) FIG. 8, an insulating film 2 made of SiO ₂ is formed on the semiconductor substrate 1, the insulating film 2 in diameter 0.15 [mu] m, depth 0.9 .mu.m (Aspect A recess (hole) 5 having a ratio of 6) is prepared, a 30 nm-thick diffusion suppressing (barrier) layer 6 made of TaN is formed on the surface by sputtering, and a copper thickness is formed on the surface. 90 nm underlayer (seed layer)
8 was formed by sputtering to prepare a sample. Then, the surface of this sample was subjected to electrolytic copper plating under the same conditions as in Example 1, and copper 7 was embedded in the recess 5.

FIG. 5 schematically shows a cross-sectional SEM (scanning electron microscope) photograph after plating. From this figure,
It can be seen that cavities (devoid of plating) C are formed in about 2/3 of the lower part of the copper 7 embedded in the recess 5.

(Comparative Example 2) As in Comparative Example 1, a 90 nm-thick underlayer (seed layer) 8 was formed by sputtering to form a sample, and the surface of this sample was formed in the same manner as in Example 2 above. Under the conditions, electroless copper plating was performed to reinforce the base film (seed layer) 8. Cross section SEM after plating
(Scanning Electron Microscope) FIG. 6 is a schematic drawing of a photograph. From this figure, it can be seen that the seed layer is chipped in about ／ of the lower portion of the seed layer 8 in the concave portion (hole) 5.

[0050]

As described above, according to the present invention,
Even in the case of a fine wiring structure having a contact hole, a peer hole, or the like having a high aspect ratio, the embedded wiring can be formed with good yield by inexpensive wet plating.

Thus, the conventional underlayer (seed layer)
Then, it is necessary to satisfy both the side coverage property and the bottom-up property, and therefore, there is a large restriction in determining the composition of the plating solution, but according to the present invention,
Since the base film (seed layer) has good side coverage characteristics, in the plating step, the composition of the plating solution can be optimized by focusing only on the bottom-up characteristics of the wiring, and this is a factor that affects, for example, the bottom-up characteristics. It is possible to increase the concentration of the carrier (brightener).

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a wiring forming method according to an embodiment of the present invention in the order of steps.

FIG. 2 is a plan view showing a layout of the wiring forming apparatus according to the embodiment of the present invention;

FIG. 3 is a schematic view of a cross-sectional SEM photograph of a substrate plated with electrolytic copper according to Example 1.

FIG. 4 is a diagram schematically illustrating a cross-sectional SEM photograph of a substrate on which electroless copper plating is performed according to Example 2.

FIG. 5 is a diagram schematically illustrating a cross-sectional SEM photograph of a substrate plated with electrolytic copper according to Comparative Example 1.

6 is a diagram schematically illustrating a cross-sectional SEM photograph of a substrate on which electroless copper plating has been performed according to Comparative Example 2. FIG.

FIG. 7 is a sectional view illustrating a basic wiring forming method of a semiconductor device in which wiring is formed on a surface of a semiconductor substrate by plating, in a process order.

FIG. 8 shows a recess (hole) having a high aspect ratio by a conventional method.
FIG. 5 is a cross-sectional view showing a state when a base film (seed layer) is formed on the surface of FIG.

FIG. 9 is a diagram showing a plan configuration of a plating apparatus for wiring a semiconductor wafer of the present invention.

FIG. 10 is a diagram showing a flow of an airflow in a plating apparatus for wiring a semiconductor wafer according to the present invention.

FIG. 11 is a view showing a flow of air between respective areas of the plating apparatus for semiconductor wafer wiring of the present invention.

FIG. 12 is an external view showing an example in which the plating apparatus for wiring a semiconductor wafer of the present invention is disposed in a clean room.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor base material 12 Insulating film 14 Depression 16 Diffusion suppression (barrier) layer 18 Base film 20 Copper

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Takao Kato, Inventor 11-11 Haneda Asahimachi, Ota-ku, Tokyo Ebara Corporation (72) Inventor Kenji Nakamura 1-1-6 Yoshiyukizaka, Fujisawa-shi, Kanagawa Prefecture Yu Yu Ebara (72) Inventor Moruji Matsumoto 1-1-6 Yoshiyukizaka, Fujisawa-shi, Kanagawa Prefecture FF13 FF18 FF22 5F033 JJ11 JJ12 JJ13 JJ14 JJ32 KK01 NN06 NN07 PP06 PP15 PP27 PP28 QQ09 QQ37 QQ48

Claims (15)

[Claims] In forming a wiring by embedding a conductive metal in a fine recess provided on a surface of a substrate by wet plating, a base film made of two or more metals is formed on the surface of the substrate. A wiring forming method, wherein wet plating is performed on a surface of a base film. 2. A metal forming the base film is a combination of a first metal same as a metal forming the buried wiring and a second metal made of a noble metal having an atomic weight larger than that of the first metal. The method according to claim 1, wherein: 3. The wiring forming method according to claim 2, wherein said first metal is gold, silver or copper. 4. The method according to claim 3, wherein the first metal is copper, and the second metal is palladium, silver, platinum, or gold. 5. The method according to claim 5, wherein the base film is formed by sputtering or C
2. The wiring forming method according to claim 1, wherein the wiring is formed by VD. 6. A base film made of two or more kinds of metals and a wiring made of a conductive metal deposited on the surface of the base film by wet plating are formed inside a fine concave portion provided on the surface of the substrate. A semiconductor device characterized by the following. 7. The metal forming the base film is a combination of a first metal same as the metal forming the wiring and a second metal composed of a noble metal having an atomic weight larger than that of the first metal. 7. The semiconductor device according to claim 6, wherein: 8. The semiconductor device according to claim 7, wherein said first metal is gold, silver or copper. 9. The semiconductor device according to claim 8, wherein said first metal is copper, and said second metal is palladium, silver, platinum or gold. 10. The semiconductor device according to claim 6, wherein said base film is formed by sputtering or CVD. 11. A film forming apparatus for forming a base film made of two or more kinds of metals on a surface of a substrate provided with fine recesses for wiring, and wet-plating the surface of the base film to form a base film in the recess. And a plating apparatus for embedding a conductive metal in the wiring. 12. A metal forming the base film, the first metal being the same as a conductive metal embedded in the recess, and the first metal being the same as the first metal.
The wiring forming apparatus according to claim 11, wherein the combination is a combination with a second metal made of a noble metal having an atomic weight larger than that of the metal. 13. The apparatus according to claim 12, wherein the first metal is gold, silver, or copper. 14. The wiring forming apparatus according to claim 13, wherein said first metal is copper, and said second metal is palladium, silver, platinum or gold. 15. The wiring forming apparatus according to claim 11, wherein said film forming apparatus is a sputtering apparatus or a CVD apparatus.