JP2002223065A - Method for manufacturing printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board which can efficiently manufacture the printed wiring board with superior connectivity with mounted electronic components. SOLUTION: Solder paste 30 is printed at desired positions on the wiring board 10 and made to reflow and thus solder bumps 2 are formed on the wiring board 10. While a flat surface 41 of a fluttering jig 4 are made to abut against the solder paste 30 from above, the solder paste 30 is made to reflow. Consequently, the peak parts 31 of the solder bumps 3 are flattened and formed almost on the same plane.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a printed wiring board provided with a plurality of solder bumps.

[0002]

2. Description of the Related Art Conventionally, there is a printed wiring board in which solder bumps are formed on a surface layer for mounting electronic components such as an IC chip. In order to improve the connectivity with the electronic component, the solder bumps are flattened at the top, and the tops of the plurality of solder bumps are formed on substantially the same plane. For example, Japanese Patent Application Laid-Open No. 2000-244101 discloses a method of manufacturing a printed wiring board in which after forming a solder bump on a wiring board, the top of the solder bump is flattened by heating, pressing, or heating and pressing. A method is disclosed.

That is, in the above-mentioned manufacturing method, first, after a solder paste is printed on a wiring board, the solder paste is reflowed to form a plurality of solder bumps on the wiring board. Next, the sheet-like wiring board is singulated. Next, the top of the solder bump is flattened by heating, pressing, or heating and pressing.

[0004]

However, in the above-mentioned conventional method for manufacturing a printed wiring board, it is necessary to provide a step of flattening the top of the solder bump after reflowing the solder paste. The efficiency may decrease. Further, even if the solder bumps are formed on a sheet-shaped wiring board, it is difficult to parallelly set a jig for mounting the wiring board and a flattening head that presses the top of the solder bumps. It is necessary to flatten the tops of the solder bumps after singulating the wiring board. Therefore, the tops of the solder bumps must be individually flattened for each piece, and it is difficult to improve the production efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and a method of manufacturing a printed wiring board capable of efficiently manufacturing a printed wiring board having excellent connectivity with electronic components to be mounted. It is intended to provide.

[0006]

According to a first aspect of the present invention, after a solder paste is printed at a plurality of desired positions on a wiring board, the solder paste is reflowed to form a plurality of solder bumps on the wiring board. In forming the solder bump, the top of the solder bump is flattened by reflowing the solder paste while the flat surface of the flattening jig having a flat surface is in contact with the solder paste. In addition, there is provided a method of manufacturing a printed wiring board, wherein the tops of the plurality of solder bumps are formed on substantially the same plane.

What is most notable in the present invention is that the solder paste is reflowed with the flat surface of the flattening jig abutting from above the solder paste.

Next, the function and effect of the present invention will be described.
According to the present manufacturing method, since the tops of the solder bumps are flattened, the connection area with the electronic components mounted on the printed wiring board is increased, and the connection can be reliably performed.
Further, since the tops of the plurality of solder bumps can be formed on substantially the same plane, it is possible to prevent the electronic components to be mounted from being disconnected from the connection pads.

In the method of manufacturing a printed wiring board, the solder paste is reflowed from above the solder paste while the flat surface of the flattening jig is in contact with the solder paste. As a result, the top of the softened solder paste is flattened along the flat surface, and a solder bump having a flat top is formed.

In this way, during the reflow, the tops of the solder bumps can be flattened and the tops of the plurality of solder bumps can be formed on substantially the same plane. Therefore, a step of flattening the tops of the solder bumps and forming the tops of the plurality of solder bumps on substantially the same plane is performed.
No special provision is required. Therefore, a method for manufacturing a printed wiring board having excellent production efficiency can be obtained.

Further, according to the above-described manufacturing method, the flattening of the tops of the solder bumps formed on the sheet-like wiring board is performed collectively without dividing the sheet-like wiring board into individual pieces. Can be. Therefore, the production efficiency of the printed wiring board can be greatly improved.

As described above, according to the present invention, it is possible to provide a method for manufacturing a printed wiring board which can efficiently manufacture a printed wiring board having excellent connectivity with electronic components to be mounted.

Next, as in the second aspect of the present invention, the flattening jig may be placed on the solder paste during reflow. In this case,
Due to the weight of the flattening jig, the solder paste can be pressed through the flat surface of the flattening jig. Thereby, the top of the solder paste softened by the reflow is flattened along the flat surface,
The tops of the plurality of solder bumps are formed on substantially the same plane.
For example, the flattening jig can be placed on the solder paste in a state where the flat surface is in contact with the solder paste before the reflow, and the reflow can be performed in that state. Therefore, the top of the solder bump can be easily flattened.

Next, the flattening jig may be pressed in the direction of the solder paste during reflow.
For example, the pressing can be performed by mechanically driving the flattening jig in the direction of the solder paste. As a result, the top of the solder bump can be reliably flattened.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A method for manufacturing a printed wiring board according to an embodiment of the present invention will be described with reference to FIGS. In the method of manufacturing the printed wiring board 1 of the present embodiment, as shown in FIGS. 1 and 2, after solder paste 30 is printed at a plurality of desired positions on the wiring board 10, the solder paste 30 is reflowed. A plurality of solder bumps 3 are formed on the wiring board 10.

In forming the solder bump 3, FIG.
As shown in (C) and (D), the solder paste 3 is placed in a state where the flat surface 41 of the flattening jig 4 having the flat surface 41 is brought into contact with the solder paste 30 from above.
Reflow 0. Thereby, as shown in FIG. 2E, the top 31 of the solder bump 3 is flattened,
The tops 31 of the plurality of solder bumps 3 are formed on substantially the same plane.

First, as shown in FIG. 1A, a mask 2 having an opening 21 for printing is formed on a wiring board 10.
Is positioned and placed. Next, a creamy solder paste 30 is supplied to the upper surface 22 of the mask 2, and the solder paste 30 is filled in the opening 21 while being pressed by a squeegee. Next, as shown in FIG. 1B, the mask 2 is separated from the wiring board 10. As described above, the solder paste 30 is printed on the wiring board 10.

Next, as shown in FIGS. 2C and 2D, the fluttering jig 4 is placed on the solder paste 30 and reflow is performed. At this time, the wiring board 10
Is mounted and transported on a reflow transport jig 51 made of a metal plate such as aluminum or stainless steel. This prevents the occurrence of warpage of the wiring board 10 during reflow. Then, after the reflow, the fluttering jig 4 is removed as shown in FIG. As a result, a plurality of solder bumps 3 having the top portions 31 which are flattened on substantially the same plane are obtained. Further, the flattening jig 4 has a protruding portion 42 protruding from the flat surface 41 by a predetermined length at a peripheral end portion. The protrusion 42 contacts the wiring board 10 after the flat surface 41 presses the solder paste 30.

Hereinafter, a more specific method for manufacturing the printed wiring board 1 of the present embodiment will be described in detail with reference to FIGS. A. Preparation of Resin Film for Interlayer Resin Insulation Layer Bisphenol A type epoxy resin (Epoxy equivalent 46
9. Yuka Shell Epoxy Co., Epicoat 1001) 3
0 parts by weight, 40 parts by weight of a cresol novolak type epoxy resin (epoxy equivalent: 215, manufactured by Dainippon Ink and Chemicals, Inc., Epicron N-673), triazine structure-containing phenol novolak resin (phenolic hydroxyl group equivalent: 120,
FENOLITE KA-705 manufactured by Dainippon Ink and Chemicals, Inc.
2) 30 parts by weight were dissolved by heating in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha while stirring, and epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) was added thereto.
15 parts by weight, 1.5 parts by weight of a pulverized product of 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely divided silica, and 0.5 part by weight of a silicone-based antifoaming agent were added to the epoxy resin composition. Was prepared. The obtained epoxy resin composition is applied on a 38 μm-thick PET film using a roll coater so that the thickness after drying becomes 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to obtain an interlayer resin. A resin film for an insulating layer was produced.

B. Preparation of Resin Composition for Filling Through Holes 100 parts by weight of a bisphenol F-type epoxy monomer (manufactured by Yuka Shell Co., molecular weight: 310, YL983U), an average particle diameter of which surface is coated with a silane coupling agent is 1.6 μm, S whose maximum particle diameter is 15 μm or less
iO ₂ spherical particles (Atotech Co., Ltd., CRS1101-C
E) 72 parts by weight and a leveling agent (manufactured by San Nopco,
Perenol S4) Put 1.5 parts by weight in a container, and stir and mix the mixture so that its viscosity is 30-80P at 25 ± 1 ° C.
a · s resin filler was prepared. In addition, as a curing agent,
Imidazole curing agent (2E4MZ-C manufactured by Shikoku Kasei Co., Ltd.)
N) 6.5 parts by weight were used.

C. Method for manufacturing printed wiring board (1) 0.8 mm thick glass epoxy resin or BT
A starting material is a copper-clad laminate in which 18 μm copper foils 118 are laminated on both surfaces of a sheet-shaped resin substrate 11 made of (bismaleimide triazine) resin (FIG. 3A).
reference). First, the copper-clad laminate was drilled, subjected to an electroless plating treatment, and etched in a pattern to form a lower conductor circuit 14 and a through hole 19 on both surfaces of the resin substrate 11. In the following, the term “substrate” refers to an intermediate product obtained at that time unless otherwise indicated.

(2) The substrate on which the through hole 19 and the lower conductor circuit 14 are formed is washed with water and dried,
H (10 g / l), NaClO ₂ (40 g / l), Na ₈
A blackening treatment using an aqueous solution containing PO ₄ (6 g / l) as a blackening bath (oxidizing bath), NaOH (10 g / l), Na
A reduction treatment is performed using an aqueous solution containing BH ₄ (6 g / l) as a reduction bath, and the lower conductor circuit 1 including the through hole 19 is subjected to a reduction treatment.
Roughened surfaces 14a and 19a were formed on the entire surface of FIG.
(B)).

(3) Next, after preparing the resin composition for filling through holes described in B above, the resin composition was adjusted by the following method.
Within four hours, a layer of the resin filler 18 was formed in the through-hole 19 and on the non-conductive-circuit-formed portion on one side of the substrate 11 and the outer edge of the conductive circuit 14. That is, first, the resin composition for filling the through hole was pushed into the through hole using a squeegee, and then dried at 100 ° C. for 20 minutes. Next, a mask having an opening corresponding to the portion where the conductive circuit is not formed is placed on the substrate, and a layer of the resin filler 18 is formed in the portion where the conductive circuit is not formed using the squeegee.
It was dried at 0 ° C. for 20 minutes (see FIG. 3C).

(4) One surface of the substrate after the treatment of the above (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the surface of the lower conductor circuit 14 and the through hole 19. Polishing was performed so that the resin filler 18 did not remain on the land surface, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Next, a heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to cure the resin filler 18.

In this manner, the surface layer of the resin filler 18 formed in the through-hole 19 and the portion where the conductor circuit is not formed and the surface of the lower-layer conductor circuit 14 are flattened.
And an insulating substrate in which the inner wall surface of the through hole 19 and the resin filler 18 are firmly adhered to each other through the roughened surface 19a. (See FIG. 3 (d)). That is, by this step, the surface of the resin filler 18 and the surface of the lower conductive circuit 14 become flush with each other.

(5) After the above substrate is washed with water and acid degreased,
Soft etching is performed, and then an etching solution is sprayed onto both surfaces of the substrate to etch the surface of the lower conductor circuit 14 and the land surface and the inner wall of the through hole 19, so that the entire surface of the lower conductor circuit 14 is roughened. Surface 14
a, 19a were formed (see FIG. 4A). As an etching solution, an etching solution (Mec etch bond, manufactured by Mec Co.) consisting of 10 parts by weight of imidazole steel (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.

(6) The resin film for the interlayer resin insulating layer slightly larger than the substrate prepared in the above A was placed on both sides of the substrate, and the pressure was 0.4 MPa, the temperature was 80 ° C., and the pressing time was 10 minutes.
The sheet was temporarily pressed and cut under the condition of seconds. Further, the interlayer resin insulating layer film was adhered to the substrate using a vacuum laminator apparatus by the following method, and then thermally cured to form an interlayer resin insulating layer 12 (see FIG. 4B). . That is, a resin film for an interlayer resin insulation layer is placed on a substrate, with a degree of vacuum of 67 Pa, a pressure of 0.4 MPa,
At the temperature of 80 ° C. and the pressing time of 60 seconds, the main bonding was performed, followed by bonding, followed by thermosetting at 170 ° C. for 30 minutes.

(7) Next, through a mask having a through hole having a thickness of 1.2 mm formed on the interlayer resin insulating layer 12, a CO ₈ gas laser having a wavelength of 10.4 μm is used.
Via hole 16 having a diameter of 75 μm was formed in interlayer resin insulation layer 12 under the conditions of 0 mm, top hat mode, pulse width of 8.0 μsec, diameter of through hole of mask of 1.0 mm, and one shot (FIG. 4 ( c)).

(8) Further, the substrate in which the via hole opening 16 is formed is washed with 80 g of permanganic acid containing 60 g / l.
The substrate was immersed in a solution at 10 ° C. for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 12. Thereby, the surface of the interlayer resin insulating layer 12 including the inner wall of the via hole opening 16 was roughened (see FIG. 4D).

(9) Next, the substrate after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and washed with water. Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment (roughening depth: 3 μm), the surface of the interlayer resin insulating layer 12 and the inner wall surface of the via hole opening 16 are formed. Catalyst nuclei were deposited.

(10) Next, the substrate is immersed in an aqueous solution of electroless copper plating having the following composition, and a thickness of 0.6 to
A 3.0 μm electroless copper plating layer 112 was formed (FIG. 5).
(A)). [Aqueous electroless plating solution] NiS04 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyridyl 40 mg / L Polyethylene glycol (PEG) 0.10 g / l [Electroless plating conditions] 40 minutes at a liquid temperature of 35 ° C

(11) A commercially available photosensitive dry film is attached to the electroless copper plating layer 112, and a mask is placed thereon.
Exposure was performed at 100 mJ / cm ² , and development processing was performed with a 0.8% aqueous sodium carbonate solution to provide a plating resist 13 having a thickness of 20 μm (see FIG. 5B).

(12) Next, the substrate is washed with 50 ° C. water.
Degreased, washed with water at 25 ° C, and further washed with sulfuric acid.
And then apply electrolytic plating under the following conditions to
A layer 113 was formed (see FIG. 5C). [Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive 19.5 ml / l (Atotech Japan, Capparaside HL) [Electroplating conditions] Current density 1 A / dm^Two  Time 65 minutes Temperature 22 ± 2 ℃

(13) Further, the plating resist 13 is
Then, the electroless plating layer 112 under the plating resist 13 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the electroless plating layer 112 is removed from the electroless copper plating layer 112 and the electrolytic plating layer 113. 18μm thick
Independent upper layer conductor circuit 15 (including via hole 17)
(See FIG. 5D).

(14) By repeating the above steps (5) to (13), the upper interlayer resin insulation layer 12
And the upper layer conductive circuit 15 (including the via hole 17) was formed (see FIGS. 6A to 7A). Thereafter, a roughened surface was formed on the surface of the upper conductive circuit 15 using an etchant. As an etchant, Mech etch bond manufactured by Mec Co. was used (see FIG. 7B).

(15) Next, diethylene glycol dime
60% by weight in chill ether (DMDG)
Cresol novolak type epoxy resin
(Nippon Kayaku Co., Ltd.) acrylated 50% of epoxy groups
Oligomers for imparting photosensitivity (molecular weight: 4000) 46.6
7 parts by weight, 80% by weight dissolved in methyl ethyl ketone
Bisphenol A type epoxy resin (Yukaka Shell Co., Ltd.
Product name: Epicoat 1001) 15.0 parts by weight, Imida
Sol curing agent (Shikoku Chemicals, trade name: 2E4MZ-C
N) 1.6 parts by weight, polyvalent acrylic which is a photosensitive monomer
Monomer (Nippon Kayaku Co., Ltd., trade name: R604) 3.0
Amount, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd.
Product name: DPE6A) 1.5 parts by weight, dispersion defoamer (Sun
0.71 part by weight of Nopco, S-65)
The mixture was stirred and mixed to prepare a mixed composition. This mixed composition
Benzophenone (Kanto Chemical)
2.0 parts by weight, Michler's ketone as photosensitizer
Add 0.2 parts by weight (manufactured by Kanto Chemical Co.) and adjust the viscosity at 25 ° C.
Obtain solder resist composition adjusted to 2.0 Pa · s
Was. The viscosity was measured using a B-type viscometer (Tokyo Keiki Co., Ltd., D
VL-B type) 60 min ^-1(Rpm) for rotor
-No. 4,6min^-1(Rpm) for rotor N
o. According to 3.

(16) Next, on both surfaces of the multilayer substrate 100 (FIG. 7B) obtained by the steps up to (14),
The solder resist composition was applied in a thickness of 20 μm, and dried at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes. After that, a 5 mm-thick photomask on which the pattern of the solder pad is drawn is brought into close contact with the solder resist layer, and is exposed to ultraviolet light of 1000 mJ / cm ^2.
The film was developed with an MTG solution to form an opening having a diameter of 90 μm. Further, the solder resist layer was cured by performing heat treatment at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. Thus, a solder resist layer 114 having an opening for forming a solder bump and having a thickness of 20 μm was formed. In addition, a commercially available solder resist composition can be used as the solder resist composition.

(17) Next, an etching solution containing sodium persulfate as a main component was used, and its etching ability was 2 μm / min.
The substrate on which the solder resist layer 114 has been formed is immersed in this etching solution for 1 minute.
A roughened surface having an average roughness (Ra) of 1 μm or less was formed on the surface of the conductor circuit. Further, this substrate was coated with nickel chloride (2.
3 × 10 ^-1 mol / l), sodium hypophosphite (2.
8 × 10 ^-1 mol / l), sodium citrate (1.6
× 10 ^-1 mol / l) and immersed in an electroless nickel plating solution having a pH of 4.5 and having a pH of 4.5 for 20 minutes.
A μm nickel plating layer 115 was formed. Further, the substrate was treated with potassium potassium cyanide (7.6 × 10 ⁻³ mol / mol).
l), ammonium chloride (1.9 × 10 ⁻¹ mol /
l), sodium citrate (1.2 × 10 ^-1 mol /
l), sodium hypophosphite (1.7 × 10 ⁻¹ mol /
1) is immersed for 7.5 minutes at 80 ° C. in an electroless gold plating solution containing
A 3 μm gold plating layer 116 was formed to form a solder pad. Thus, a sheet-shaped multilayer wiring board 10 having solder pads was obtained.

(18) Thereafter, the solder resist layer 11
4, a mask having an opening having a diameter of 100 μm is placed on a portion opposed to all the openings for forming solder bumps, and the solder paste is inserted into the concave openings for forming solder bumps by using a press-fit type press. Was completely filled. The solder paste filled here was Sn: Ag in a weight ratio of 96.
5: 3.5 mainly containing solder having a particle size of 5 to 20 μm, the viscosity of which was adjusted to 200 Pa · s.

(19) Next, of the solder paste filled in the step (18), a portion of the solder paste which is raised from the surface of the solder resist layer 114 is replaced with a stainless steel squeegee or a 90 ° hardness flat rubber squeegee. Then, the surface of the filled solder paste was flattened, and the surface of the solder paste and the surface of the solder resist layer were made flush with each other.

(20) Next, the solder resist layer 114
A mask similar to the mask used in the step (18) was placed on the top, and solder paste was printed. The solder paste filled here was Sn: Ag in a weight ratio of 96.5:
It mainly contains solder having a particle size of 5 to 20 μm and is adjusted to have a viscosity of 250 Pa · s.

(21) Thereafter, the flat surface of the flattening jig is brought into contact with the solder paste from above,
The solder paste printed in the steps (18) to (20) was reflowed at about 250 ° C. (see FIGS. 2C and 2D), and further, flux cleaning was performed. This gives
The tops 31 of the solder bumps 3 were flattened, and the tops 31 of the plurality of solder bumps 3 were formed on substantially the same plane. Thus, a multilayer printed wiring board 1 provided with the solder bumps 3 was obtained (see FIG. 7C). Then, the printed wiring board 1 was divided into individual pieces to obtain a large number of piece-shaped printed wiring boards.

Next, the operation and effect of this embodiment will be described. According to this manufacturing method, since the top portions 31 of the solder bumps 3 are flattened, the connection area with the electronic component mounted on the printed wiring board 1 is increased, and the connection can be reliably performed. Further, since the top portions 31 of the plurality of solder bumps 3 can be formed on substantially the same plane, it is possible to prevent the electronic components to be mounted from being disconnected from connection pads.

In the method of manufacturing the printed wiring board 1, the solder paste 30 is reflowed from above the solder paste 30 while the flat surface 41 of the flattening jig 4 is in contact with the solder paste 30 (FIG. 2 (C),
(D)). As a result, as shown in FIG. 2D, the top 31 of the softened solder paste 30 is
2E, the solder bumps 3 having a flat top 31 are formed as shown in FIG.

In this way, during reflow, the tops 31 of the solder bumps 3 can be flattened and the tops 31 of the plurality of solder bumps 3 can be formed on substantially the same plane. Therefore, there is no need to provide a special step of flattening the tops 31 of the solder bumps 3 and forming the tops 31 of the plurality of solder bumps 3 on substantially the same plane. Therefore, a method for manufacturing the printed wiring board 1 having excellent production efficiency can be obtained.

Further, according to the above-described manufacturing method, the flattening of the top portions 31 of the solder bumps 3 formed on the sheet-like wiring board 10 is performed without dividing the sheet-like wiring board 10 into individual pieces. You can do it. Therefore, the production efficiency of the printed wiring board 1 can be greatly improved.

As shown in FIG. 2C, the fluttering jig 4 is placed on the solder paste 30 during reflow. Accordingly, the solder paste 30 can be pressed by the weight of the flattening jig 4 via the flat surface 41 of the flattening jig 4. Therefore, the top 310 of the solder paste 30 softened by reflow is flattened along the flat surface 41, and the tops 31 of the plurality of solder bumps 3 are formed on substantially the same plane (FIGS. 2D and 2D). E)). In addition, since the flattening jig 4 may be placed on the solder paste 30 before reflow, the top 31 of the solder bump 3 can be easily flattened.

As shown in FIG. 2D, the projection 42 provided on the flattening jig 4 comes into contact with the wiring board 10 after the flat surface 41 presses the solder paste 30. The length of the protrusion 42 is constant. Therefore, the flat surface 41 and the wiring board 10
A space with a certain width is secured between the two. Therefore, the top 31 of the solder bump 3 is securely connected to the wiring board 10.
And formed on a plane parallel to

As described above, according to this embodiment, it is possible to provide a method of manufacturing a printed wiring board, which can efficiently manufacture a printed wiring board having excellent connectivity with electronic components to be mounted.

Embodiment 2 In this embodiment, as shown in FIG.
This is an example of a method for manufacturing a printed wiring board in which the solder is pressed toward the solder paste 30 during reflow. That is, as shown in FIGS. 8A and 8B, at the time of reflow, the flattening jig 40 is mechanically driven in the direction of the solder paste 30 (arrow A in FIG. 8A).

The flattening jig 40 is made of a stainless steel plate having a chromium plating formed on the surface. In addition, the flattening jig 40 has no protrusion. The wiring board 10 is placed on a support jig 52 made of stainless steel. Other configurations are the same as those of the first embodiment. This ensures that
The top 31 of the solder bump 3 can be flattened. In addition, the third embodiment has the same functions and effects as the first embodiment.

In the first embodiment, the fluttering jig 4 may be pressed at the time of reflow in the same manner as in the second embodiment. That is, the fluttering jig 4 having the protrusion 42 (see FIGS. 2C and 2D) may be mechanically pressed until the protrusion 42 comes into contact with the wiring board 10. Thereby, the top portion 31 of the solder bump 3 can be more reliably flattened.

[0053]

As described above, according to the present invention, it is possible to provide a method for manufacturing a printed wiring board which can efficiently manufacture a printed wiring board having excellent connectivity with electronic components to be mounted. it can.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for printing a solder paste according to a first embodiment.

FIG. 2 is an explanatory diagram of flattening of solder bumps in the first embodiment.

FIG. 3 is a cross-sectional view showing a part of the steps of the method for manufacturing a printed wiring board in the first embodiment.

FIG. 4 is a cross-sectional view showing a part of the steps of the method for manufacturing a printed wiring board in the first embodiment.

FIG. 5 is a cross-sectional view showing a part of the steps of the method for manufacturing the printed wiring board in the first embodiment.

FIG. 6 is a cross-sectional view showing a part of the steps of the method for manufacturing a printed wiring board in the first embodiment.

FIG. 7 is a cross-sectional view showing a part of the steps of the method for manufacturing the printed wiring board in the first embodiment.

FIG. 8 is a diagram illustrating flattening of solder bumps according to a second embodiment.

[Explanation of symbols]

 1. . . Printed wiring board, 10. . . Wiring board, 2. . . Mask, 3. . . Solder bumps, 31. . . Top, 30. . . 3. solder paste; . . Fluttering jig, 41. . . Flat surface,

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E319 AA03 AC01 BB04 BB05 CC33 CD13 CD29 GG15 5E346 AA15 AA32 BB16 CC40 FF45 GG25 HH31

Claims (3)

[Claims] After printing a solder paste on a plurality of desired positions on a wiring board, the solder paste is reflowed to form a plurality of solder bumps on the wiring board. By flattening the tops of the solder bumps by reflowing the solder paste in a state where the flat surfaces of the flattening jig having flat surfaces are in contact with each other, the tops of the plurality of solder bumps are flattened. A method for manufacturing a printed wiring board, wherein the printed wiring board is formed on substantially the same plane. 2. The method according to claim 1, wherein the flattening jig is placed on the solder paste during reflow. 3. The method according to claim 1, wherein the flattening jig is pressed toward the solder paste during reflow.