JP2002231505A - Chip resistor and its manufacturing method - Google Patents
Chip resistor and its manufacturing methodInfo
- Publication number
- JP2002231505A JP2002231505A JP2001029322A JP2001029322A JP2002231505A JP 2002231505 A JP2002231505 A JP 2002231505A JP 2001029322 A JP2001029322 A JP 2001029322A JP 2001029322 A JP2001029322 A JP 2001029322A JP 2002231505 A JP2002231505 A JP 2002231505A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- insulating substrate
- resistor
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 18
- 238000009966 trimming Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 69
- 229920005989 resin Polymers 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 9
- 239000002344 surface layer Substances 0.000 claims 2
- 239000010408 film Substances 0.000 description 173
- 238000007650 screen-printing Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 8
- 238000007639 printing Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000005388 borosilicate glass Substances 0.000 description 4
- 239000003973 paint Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000005355 lead glass Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052573 porcelain Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、抵抗体膜を配置し
た絶縁基板を分割して形成されるチップ形抵抗器および
そのチップ形抵抗器の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip resistor formed by dividing an insulating substrate on which a resistor film is arranged, and a method of manufacturing the chip resistor.
【0002】[0002]
【従来の技術】昨今、携帯端末等の小形化と普及に伴っ
て極小寸法を有するチップ形抵抗器の供給が要請される
ようになった。そして、この極小寸法を有するチップ形
抵抗器の、小形電子機器の回路基板への採用と実装に際
しては、実装の効率化とはんだ接合の信頼性の確保に向
けて、部品メーカおよび機器メーカが協力することが望
まれる。2. Description of the Related Art In recent years, with the miniaturization and spread of portable terminals and the like, the supply of chip type resistors having extremely small dimensions has been demanded. When adopting and mounting this extremely small chip-type resistor on the circuit board of small electronic devices, the parts and equipment manufacturers work together to increase the efficiency of mounting and ensure the reliability of solder joints. It is desired to do.
【0003】一方、部品メーカ等における前記チップ形
抵抗器の製造方法は、例えば下記の手順にて形成され
る。すなわち、まず、表裏両面に分割スリッド入りの絶
縁基板(アルミナ96%以上含有の磁器からなる)を用
意し、これにメタルグレーズ(AgまたはAg・Pd系
グレーズ)でスクリーン印刷し、これを例えば約850
℃で焼成し、膜厚が8〜12μmの裏面電極を形成す
る。この裏面電極は二次方向分割スリッドから離間して
形成する。On the other hand, a method of manufacturing the chip-type resistor in a part maker or the like is formed by, for example, the following procedure. That is, first, an insulating substrate (made of porcelain containing 96% or more alumina) is prepared on both the front and back surfaces, and is screen-printed with a metal glaze (Ag or Ag / Pd-based glaze). 850
C. to form a back electrode having a thickness of 8 to 12 .mu.m. This back surface electrode is formed apart from the secondary direction split slip.
【0004】次に、絶縁基板にメタルグレーズ(Ag・
Pd系グレーズ)でスクリーン印刷し、これを例えば8
50℃で焼成し、膜圧が8〜12μmの表電極膜を形成
する。このときの焼成は前記裏面電極形成のための焼成
と同時に行ってもよい。この表電極膜は二次方向分割ス
リッドから離間して形成する。続いて、一対の表電極膜
間に、RuO2 系グレーズの抵抗体膜の両端を載せた
(スクリーン印刷した)後、これを850℃で焼成し、
その抵抗体膜上にアンダーコート膜を形成する。Next, a metal glaze (Ag.
Screen printing with Pd-based glaze)
Baking is performed at 50 ° C. to form a front electrode film having a film pressure of 8 to 12 μm. The firing at this time may be performed simultaneously with the firing for forming the back electrode. This front electrode film is formed apart from the secondary direction split slip. Subsequently, both ends of a RuO 2 -based glaze resistor film are placed (screen printed) between a pair of front electrode films, and then fired at 850 ° C.
An undercoat film is formed on the resistor film.
【0005】このアンダーコート膜は硼珪酸鉛ガラスで
二次方向の分割スリッドを跨いでスクリーン印刷をし、
約600℃で焼成して、膜厚が8〜12μmの膜とした
ものである。そして、レーザ工法による抵抗値調整のた
めのトリミング溝の刻設が、そのアンダーコート膜上か
ら行われる。続いて、前記アンダーコート膜上に硼珪酸
鉛ガラスのスクリーン分割印刷を行い、さらに約600
℃で焼成してオーバーコート膜を形成する。続いて絶縁
基板の一次方向の分割スリッドに沿って短冊状に一次ブ
レークをする。[0005] This undercoat film is screen-printed with lead borosilicate glass across a split in the secondary direction,
This was fired at about 600 ° C. to form a film having a thickness of 8 to 12 μm. Then, a trimming groove for adjusting the resistance value is formed by the laser method from the undercoat film. Subsequently, screen division printing of lead borosilicate glass is performed on the undercoat film,
Firing at ℃ to form an overcoat film. Subsequently, a primary break is made in a strip shape along the divided slit in the primary direction of the insulating substrate.
【0006】さらに、Ag系またはAg・Pd系グレー
ズで印刷し、600℃で焼成して、膜厚が10〜12μ
mの端面電極膜を形成し、その後二次ブレークにより個
々のチップに分割し、Niめっき膜とSnめっき膜また
はSn・Pbめっき膜をそれぞれ電極めっき膜として形
成する。Further, printing is performed with an Ag-based or Ag / Pd-based glaze, and baked at 600 ° C.
Then, an end face electrode film having a thickness of m is formed and then divided into individual chips by a secondary break, and a Ni plating film and a Sn plating film or a Sn · Pb plating film are formed as electrode plating films.
【0007】図4は従来技術におけるチップ形抵抗器の
製造工程の実施態様の概説図である。このチップ形抵抗
器は一次方向および二次方向に形成された分割スリット
で絶縁基板を分割して、矩形のチップに形成される。図
4(a)乃至図4(i)はそのチップ単位で見たチップ
抵抗器の製造工程を示す。まず、図4(a)に示すよう
に、矩形状に区画された絶縁基板1の裏側の左右両端部
に位置するように、該絶縁基板1の前後両端から所定距
離だけ離間した領域に、すなわち二次方向の分割スリッ
ドから離間した領域に裏電極膜2を形成する。一方、前
記絶縁基板1の表側の左右両端部に位置するように、該
絶縁基板1の前後両端からそれぞれ所定距離離間した位
置までの領域に図4(b)に示すような表電極膜下層3
を形成する。そして、図4(c)に示すように、前記の
左右両端部の表電極膜下層3どうしを、これらの一部に
重なるように抵抗体膜4により接続し、さらにその抵抗
体膜4を前記絶縁基板1の前後両端までアンダーコート
膜5にて、図4(d)に示すように覆う。また、このア
ンダーコート膜5の上から前記抵抗体膜4の抵抗値調整
のために、図4(d)に示すようにトリミング溝6を刻
設し、前記絶縁基板1の一部を除いて前後両端まで、図
4(e)に示すように、前記アンダーコート膜5および
トリミング溝6をオーバーコート膜7にて覆う。FIG. 4 is a schematic view showing an embodiment of a manufacturing process of a chip-type resistor according to the prior art. This chip-type resistor is formed into a rectangular chip by dividing an insulating substrate by dividing slits formed in a primary direction and a secondary direction. 4 (a) to 4 (i) show the steps of manufacturing a chip resistor as viewed on a chip-by-chip basis. First, as shown in FIG. 4 (a), a region separated by a predetermined distance from both front and rear ends of the insulating substrate 1 so as to be located on both left and right ends on the back side of the insulating substrate 1 partitioned into a rectangular shape, The back electrode film 2 is formed in a region separated from the secondary sliding slit. On the other hand, as shown in FIG. 4 (b), a region between the front and rear ends of the insulating substrate 1 and a position separated by a predetermined distance from the front and rear ends of the insulating substrate 1 so as to be located at the left and right ends of the front surface of the insulating substrate 1.
To form Then, as shown in FIG. 4 (c), the lower surface electrode layers 3 at the left and right end portions are connected to each other by a resistor film 4 so as to overlap a part thereof, and the resistor film 4 is further connected to the lower layer. The front and rear ends of the insulating substrate 1 are covered with the undercoat film 5 as shown in FIG. Further, a trimming groove 6 is cut out from above the undercoat film 5 to adjust the resistance value of the resistor film 4 as shown in FIG. 4D, and a part of the insulating substrate 1 is removed. As shown in FIG. 4E, the undercoat film 5 and the trimming groove 6 are covered with an overcoat film 7 up to the front and rear ends.
【0008】次に、前記絶縁基板1の左右端面を覆うよ
うに、また、この左右端面を覆い、かつ前記裏電極膜2
および表電極膜3の一部に重畳するように、図4(f)
および図4(g)に示すような端面電極膜8を形成し、
最後に、図4(h)および図4(i)に示すように、前
記裏電極膜2、表電極膜3および端面電極膜8を電極め
っき膜9にて覆うようにして、チップ形抵抗器を完成す
る。図5はこのような工程を経て製造されたチップ形抵
抗器の正面断面図である。Next, the left and right end surfaces of the insulating substrate 1 are covered and the back electrode film 2 is covered with the left and right end surfaces.
4 (f) so as to overlap with part of the front electrode film 3.
And forming an end face electrode film 8 as shown in FIG.
Finally, as shown in FIGS. 4 (h) and 4 (i), the back electrode film 2, the front electrode film 3 and the end face electrode film 8 are covered with an electrode plating film 9, so that a chip type resistor is formed. To complete. FIG. 5 is a front sectional view of a chip-type resistor manufactured through such a process.
【0009】[0009]
【発明が解決しようとする課題】しかしながら、前記の
ようなチップ形抵抗器の製造方法にあっては、膜厚の厚
いメタルグレーズの裏電極膜2と表電極膜3の一部に、
膜厚の厚いメタルグレーズの端面電極8が一部重畳する
構造を有するので、これらの重畳部分に段差が形成さ
れ、回路基板ランドへのはんだ付け実装の際に、はんだ
溶融時の濡れ応力の影響受け易く、つまり、ツームスト
ンが発生し易くなるという問題があった。また、端面電
極8が膜厚の厚いメタルグレーズで形成されているの
で、絶縁基板の2次方向の分割スリットに沿ってブレー
クする際のブレーク性が悪く、且つ端面電極の膜厚が厚
く、バラツキを有するが為にチップ形抵抗器の長さ方向
の仕上がり寸法精度の安定性に乏しく、小型のチップ抵
抗器ではこのように分割のブレーク性及び寸法精度の悪
さが顕著となっていた。However, in the above-described method of manufacturing a chip-type resistor, a part of the back electrode film 2 and the front electrode film 3 made of a thick metal glaze is formed.
Since the end face electrode 8 of a thick metal glaze partially overlaps, a step is formed in these overlapped portions, and when soldering and mounting on a circuit board land, the influence of the wetting stress at the time of solder melting is applied. However, there is a problem that tombstones are easily generated. Further, since the end face electrode 8 is formed of a thick metal glaze, the breakability at the time of breaking along the split slit in the secondary direction of the insulating substrate is poor, and the thickness of the end face electrode is large and uneven. Therefore, the stability of the finished dimensional accuracy in the longitudinal direction of the chip resistor is poor, and the breakability of the division and the poor dimensional accuracy are remarkable in a small chip resistor.
【0010】さらに、裏電極膜2が二次分割スリットか
ら離間して形成されているため、裏電極膜2における二
次分割スリットからの離間距離が均等に保つことができ
ず、左右何れかに偏る結果、回路基板ランドへのはんだ
付けの際のセルフアライメント効果が期待できず、回路
基板ランドに対して位置ずれが生じた状態で実装されて
しまうという問題があった。また、製品として、オーバ
ーコート膜7の面が表電極面より突き出ることにより、
また、回路基板への実装に対して裏電極膜側だけの片面
実装のためにTp(テーピング)による供給に限定され
ることにより、回路基板への実装効率が悪いという問題
があった。Further, since the back electrode film 2 is formed so as to be separated from the secondary division slit, the distance between the back electrode film 2 and the secondary division slit cannot be kept uniform, and either the left or right As a result, the self-alignment effect at the time of soldering to the circuit board land cannot be expected, and there is a problem that the semiconductor device is mounted in a state of being displaced with respect to the circuit board land. Further, as a product, the surface of the overcoat film 7 protrudes from the surface of the front electrode,
Further, since the mounting on the circuit board is limited to the supply by Tp (taping) for single-side mounting only on the back electrode film side, there is a problem that mounting efficiency on the circuit board is low.
【0011】本発明は前記のような問題を解決するもの
であり、その目的とするところは、表側または裏側のい
ずれの状態でも回路基板への実装とTpまたはバルクに
よる供給とをそれぞれ可能にし、分割スリッドにおける
分割時の絶縁基板や表裏電極膜のバリ、欠けの発生を抑
制でき、さらにチップ抵抗器の長さ方向寸法および幅方
向寸法の仕上がり精度の安定化と小形化に対応でき、加
えてツームストン現象を抑制でき、セルフアライメント
効果が良好となるチップ形抵抗器およびその製造方法を
提供することにある。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to enable mounting on a circuit board and supply by Tp or bulk, regardless of the state of the front side or the back side, respectively. It is possible to suppress the occurrence of burrs and chipping of the insulating substrate and front and back electrode films at the time of division in the divided sliding, and it is also possible to respond to the stabilization and miniaturization of the finishing accuracy of the length and width dimensions of the chip resistor. An object of the present invention is to provide a chip-type resistor capable of suppressing the tombstone phenomenon and having a good self-alignment effect, and a method of manufacturing the same.
【0012】[0012]
【課題を解決するための手段】前記目的達成のために、
請求項1の発明にかかるチップ形抵抗器は、矩形状に区
画された絶縁基板の裏側の左右両端部に位置するよう
に、該絶縁基板の左右の両端および前後両端までの領域
に形成された裏電極膜と、前記絶縁基板の表側の左右両
端部に位置するように、該絶縁基板の前後両端からそれ
ぞれ所定距離離間した位置までの領域に形成された表電
極膜下層と、該表電極膜下層どうしを接続し、これらの
一部を覆う抵抗体膜と、該抵抗体膜を覆うアンダーコー
ト膜と、該アンダーコート膜の上から前記抵抗体膜の抵
抗値調整のために刻設されたトリミング溝と、一部が前
記絶縁基板の前後両端まで、前記アンダーコート膜およ
びトリミング溝を覆うオーバーコート膜と、前記表電極
膜下層上において、前記絶縁基板の前後両端までを覆う
表電極膜上層とを有し、前記絶縁基板の左右端面を覆う
ように、または該左右端面を覆い前記裏電極膜および表
電極膜上層の各一部に重畳するように前記左右端面にス
パッタ工法により端面電極膜を形成し、前記裏電極膜、
表電極膜上層および端面電極膜を電極めっき膜により覆
うようにしたものである。To achieve the above object,
The chip-type resistor according to the first aspect of the present invention is formed at the left and right ends and at the front and rear ends of the insulating substrate so as to be located at the left and right ends on the back side of the rectangularly partitioned insulating substrate. A back electrode film, a lower layer of the front electrode film formed in a region from the front and rear ends of the insulating substrate to positions at predetermined distances from the front and rear ends of the insulating substrate so as to be located at both left and right ends of the front side of the insulating substrate; The lower layers are connected to each other, a resistor film covering a part thereof, an undercoat film covering the resistor film, and a resistor film formed on the undercoat film to adjust the resistance value of the resistor film. A trimming groove, a part of which extends to the front and rear ends of the insulating substrate, an overcoat film that covers the undercoat film and the trimming groove, and an upper layer of the front electrode film covering the front and rear ends of the insulating substrate on the lower surface of the front electrode film. With An end face electrode film is formed on the left and right end faces by a sputtering method so as to cover the left and right end faces of the insulating substrate, or to cover the left and right end faces and overlap each part of the back electrode film and the front electrode film upper layer, The back electrode film,
The upper layer of the front electrode film and the end face electrode film are covered with an electrode plating film.
【0013】また、請求項2の発明にかかるチップ形抵
抗器は、前記裏電極膜を8μm以下の膜厚を有するメタ
ルグレーズ系の膜、または10μm以下の膜厚を有する
銀レジン系の導電膜、あるいは金属有機物の導電膜と
し、前記表電極膜上層を8μm以下の膜厚を有するメタ
ルグレーズ系の導電膜、または10μm以下の膜厚を有
する銀レジン系の導電膜であり、前記オーバーコート膜
をレジン系またはガラス系の膜としたものである。Further, in the chip type resistor according to the present invention, the back electrode film may be a metal glaze-based film having a thickness of 8 μm or less, or a silver resin-based conductive film having a thickness of 10 μm or less. A metal glaze-based conductive film having a film thickness of 8 μm or less, or a silver resin-based conductive film having a film thickness of 10 μm or less; Is a resin-based or glass-based film.
【0014】また、請求項3の発明にかかるチップ形抵
抗器の製造方法は、矩形状に区画するように一次方向お
よび二次方向の分割スリッドが表裏面に刻設された絶縁
基板の裏面に、前記一次方向および二次方向の分割スリ
ッドを跨いで裏電極膜を形成する裏電極膜形成工程と、
前記絶縁基板の表面に、前記一次方向の分割スリッドを
跨ぎ、かつ前記二次方向の分割スリッドから離間するよ
うに表電極膜下層を形成する表電極膜下層形成工程と、
該表電極膜下層どうしを接続し、これらの一部を覆う抵
抗体膜を形成する抵抗体膜形成工程と、前記抵抗体膜を
覆うようにアンダーコート膜を形成するアンダーコート
膜形成工程と、前記アンダーコート膜上から前記抵抗体
膜の抵抗値調整のためのトリミング溝を刻設するトリミ
ング溝刻設工程と、前記アンダーコート膜とトリミング
溝を覆うように、前記絶縁基板の二次方向の分割スリッ
ドの一部を回避し、および前記絶縁基板の二次方向の分
割スリッドの一部を跨ぐようにオーバーコート膜を形成
するオーバーコート膜形成工程と、前記表電極膜下層上
において、前記絶縁基板の二次方向の分割スリッドを跨
ぐように表面電極膜上層を形成する表面電極膜上層形成
工程と、前記絶縁基板を一次方向の分割スリッドに沿っ
て、機械敵応力を利用して短冊状に分割する絶縁基板分
割工程と、前記絶縁基板の左右端面を覆うように、また
は該左右端面を覆い裏電極膜および表電極膜上層の各一
部に重畳するように、スパッタ工法により端面電極膜を
形成する端面電極膜形成工程と、前記絶縁基板を二次方
向の分割スリッドに沿って機械的応力を利用してチップ
状に分割するチップ状分割工程とを実施し、最後の電気
めっき膜形成工程にて、前記裏電極膜、表電極膜上層お
よび端面電極膜を覆うように電極めっき膜を形成するこ
とを特徴とする。According to a third aspect of the present invention, there is provided a method of manufacturing a chip-type resistor, wherein a divided slit in a primary direction and a secondary direction is formed on a front surface and a rear surface of an insulating substrate so as to be divided into a rectangular shape. A back electrode film forming step of forming a back electrode film over the split in the primary direction and the secondary direction,
On the surface of the insulating substrate, straddle the split in the primary direction, and form a lower layer of the front electrode film so as to be separated from the split in the secondary direction,
Connecting the lower layer of the front electrode film to each other, forming a resistor film covering a part thereof; and forming an undercoat film so as to cover the resistor film, A trimming groove engraving step of engraving a trimming groove for adjusting the resistance value of the resistor film from above the undercoat film, and a secondary direction of the insulating substrate so as to cover the undercoat film and the trimming groove. An overcoat film forming step of forming an overcoat film so as to avoid a part of the divisional slit and to straddle a part of the divisional slip in the secondary direction of the insulating substrate; A surface electrode film upper layer forming step of forming a surface electrode film upper layer so as to straddle the split in the secondary direction of the substrate, and the insulating substrate is subjected to mechanical enemy stress along the split in the primary direction. An insulating substrate dividing step of dividing the insulating substrate into strips by using a sputtering method so as to cover the left and right end surfaces of the insulating substrate, or to cover the left and right end surfaces and overlap the back electrode film and the upper surface of the front electrode film. Performing an end face electrode film forming step of forming an end face electrode film by a construction method, and a chip-shaped dividing step of dividing the insulating substrate into chips using mechanical stress along a secondary sliding slit in a secondary direction. In the electroplating film forming step, an electrode plating film is formed so as to cover the back electrode film, the upper layer of the front electrode film, and the end face electrode film.
【0015】また、請求項4の発明にかかるチップ形抵
抗器の製造方法は、前記裏電極膜形成工程を、レジン形
のオーバーコート膜を形成する前記オーバーコート膜形
成工程に続いてAgレジン系の裏電極膜を形成する工程
とすることを特徴とする。According to a fourth aspect of the present invention, in the method of manufacturing a chip-type resistor, the step of forming the back electrode film includes the step of forming the resin-type overcoat film followed by the step of forming an Ag resin. Forming the back electrode film.
【0016】[0016]
【発明の実施の形態】以下、本発明の実施の一形態を詳
細に説明する。まず、本発明の抵抗チップの製造方法を
述べる。まず、96%以上のアルミナを含有し、表裏面
に一次方向および二次方向の分割スリッドが入った絶縁
基板を用意し、これの裏面に、一次方向および二次方向
の分割スリッドを跨いで、AuまたはAgまたはPtの
レジネートでスクリーン印刷を行い、約850℃で焼成
して膜厚が数1000・の裏面電極を形成し、あるいは
一次方向および二次方向の分割スリッドを跨いで、Ag
またはAg・Pd系のグレーズでスクリーン印刷を行
い、これを約850℃で焼成して4〜8μmの膜厚の裏
面電極を形成する。ここでは、膜厚が制御されているた
めに、一次方向および二次方向の分割スリッドを跨ぐス
クリーン印刷でも、絶縁基板の一次ブレーク時の分割が
容易となり、分割面のバリ、欠けが抑えられるほか、は
んだ付けに供する電極膜面が広く活用でき、はんだ結合
面積が広く、セルフアライメント効果を発揮できる。ま
た、一次ブレークによる分割仕上がり精度が良好とな
り、抵抗器の幅方向の精度が向上し、小形化に寄与す
る。また、この裏面電極を、Agレジンを一次方向およ
び二次方向の分割スリッドを跨ぐようにスクリーン印刷
し約200℃で硬化させて5〜10μmの膜厚とするこ
ともできる。次に、Ag・Pd系グレーズで印刷をし、
約850℃で焼成して膜厚が8〜12μmの表電極膜下
層を形成する。表電極膜は二層構造であり、前記表電極
膜下層は一次方向の分割スリッドを跨ぎ、二次方向分割
スリッドから離間するように形成し、表電極膜上層は膜
厚制御して、さらに表電極膜下層上に一次方向および二
次方向の分割スリッドを跨ぐように印刷して形成するこ
とにより、表電極膜上層をオーバーコート膜面と面一ま
たはやや高めにでき、従って表電極膜での実装が可能と
なる。また、一次方向の分割スリッドは絶縁基板に矩形
に分割された左右両端部に位置し、二次分割スリッドは
前後両端に位置する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail. First, a method for manufacturing a resistor chip according to the present invention will be described. First, an insulating substrate containing 96% or more of alumina and having splits in the primary and secondary directions on its front and back surfaces is prepared. On the back surface, the split slits in the primary and secondary directions are straddled. Screen printing is performed with a resinate of Au, Ag, or Pt, and baked at about 850 ° C. to form a back electrode having a thickness of several thousand ·, or Ag across a split in the primary and secondary directions.
Alternatively, screen printing is performed with an Ag / Pd glaze, which is baked at about 850 ° C. to form a back electrode having a thickness of 4 to 8 μm. Here, since the film thickness is controlled, even in the screen printing across the divided slits in the primary direction and the secondary direction, division at the time of the primary break of the insulating substrate becomes easy, and burrs and chipping of the divided surface are suppressed. In addition, the electrode film surface used for soldering can be widely used, the solder bonding area is large, and the self-alignment effect can be exhibited. Further, the accuracy of the division finish by the primary break is improved, and the accuracy in the width direction of the resistor is improved, which contributes to downsizing. Alternatively, the back electrode may be screen-printed with Ag resin so as to straddle the divided slits in the primary direction and the secondary direction, and cured at about 200 ° C. to have a film thickness of 5 to 10 μm. Next, print with Ag / Pd glaze,
By baking at about 850 ° C., a surface electrode film lower layer having a thickness of 8 to 12 μm is formed. The surface electrode film has a two-layer structure, the lower layer of the surface electrode film is formed so as to straddle the split in the primary direction and to be separated from the split slit in the secondary direction. By printing on the lower layer of the electrode film so as to straddle the splits in the primary and secondary directions, the upper layer of the front electrode film can be flush with or slightly higher than the surface of the overcoat film. Implementation becomes possible. The primary divided slits are located at the left and right ends of the insulating substrate divided into rectangles, and the secondary divided slips are located at the front and rear ends.
【0017】次に、一対の表電極膜下層間にRuO2 系
グレーズでスクリーン印刷を行い、これを約850℃で
焼成して抵抗体膜を形成し、その抵抗体膜の上に、硼珪
酸鉛ガラスをスクリーン分割印刷または二次方向の分割
スリッドを跨ぐようにスクリーン印刷して、これを約6
00℃で焼成することにより、膜厚8〜12μmのアン
ダーコート膜を形成する。続いて、このアンダーコート
膜上からレーザ工法により抵抗値調整のためのトリミン
グを行い、その上にエポキシ系塗料で、二次方向の分割
スリットの一部を回避するようにしてアンダーコート膜
を覆うようにスクリーン印刷を行った後、約200℃で
硬化させてオーバーコート膜とする。また、この他のオ
ーバーコート膜として、硼珪酸鉛ガラスをスクリーン印
刷し、約600℃で焼成したものとしてもよい。Next, screen printing is performed with a RuO 2 -based glaze between the lower layers of the pair of front electrode films, and the resultant is fired at about 850 ° C. to form a resistor film. Screen printing of lead glass or screen printing across the split slits in the secondary direction,
By baking at 00 ° C., an undercoat film having a thickness of 8 to 12 μm is formed. Subsequently, trimming for resistance value adjustment is performed by a laser method from above the undercoat film, and the undercoat film is covered with an epoxy-based paint so as to avoid a part of the secondary slit in the secondary direction. After performing the screen printing as described above, it is cured at about 200 ° C. to form an overcoat film. As another overcoat film, lead borosilicate glass may be screen-printed and fired at about 600 ° C.
【0018】続いて、オーバーコート膜として、前記エ
ポキシ系塗料を用いた場合には、前記のように形成され
た表電極膜下層に重なるように、かつ二次方向の分割ス
リッドを跨ぐように、Agレジンでスクリーン印刷して
約200℃で硬化させ、膜厚5〜10μmの表電極膜上
層を形成する。一方、前記オーバーコート膜として硼珪
酸鉛ガラスを用いた場合には、この表電極膜上層をAg
系またはAg・Pd系グレーズを用い、二次方向の分割
スリッドを跨ぐようにして、表電極膜下層上からスクリ
ーン印刷をし、これを600℃で焼成して、膜厚8〜1
2μmの表電極膜上層を形成する。Subsequently, when the above-mentioned epoxy-based paint is used as the overcoat film, the epoxy-based paint is formed so as to overlap the lower layer of the front electrode film formed as described above and to straddle the split in the secondary direction. Screen printing with an Ag resin is performed and cured at about 200 ° C. to form an upper layer of the front electrode film having a thickness of 5 to 10 μm. On the other hand, when lead borosilicate glass was used as the overcoat film, the upper layer of the front electrode film was made of Ag.
System or an Ag / Pd-based glaze, screen printing is performed over the lower layer of the front electrode film so as to straddle the split in the secondary direction, and is baked at 600 ° C. to obtain a film thickness of 8 to 1
An upper layer of the front electrode film of 2 μm is formed.
【0019】このような表電極膜上層の形成後は、必要
に応じ、二次方向の分割スリッドを跨ぐようにして、A
g含有エポキシ樹脂塗料のスクリーン印刷を行って、約
200℃で硬化させて膜厚5〜10μmの裏電極膜を形
成し、さらにマスキングレジストのスクリーン印刷を行
って、これを硬化させた後、絶縁基板の一次方向の分割
スリッドに沿って短冊状にブレークする。そして、絶縁
基板の端面を覆うように、またはこの端面を覆い、かつ
表電極膜上層および裏電極膜の一部に重なるように、ス
パッタ法によって、膜厚が数千ÅのCr薄膜およびNi
膜を形成し、前記マスキングレジストを除去し、絶縁基
板を二次方向の分割スリッドでブレークして、個々のチ
ップ状に分割し、最後にNiめっき膜とSn系めっきま
たはSn・Pbめっき膜を電極めっき膜として施すこと
により、チップ形抵抗器が得られる。After the formation of the upper layer of the front electrode film, if necessary, the A
g-containing epoxy resin paint is screen-printed, cured at about 200 ° C. to form a back electrode film having a thickness of 5 to 10 μm, and further screen-printed with a masking resist. A break occurs in a strip shape along the divided slit in the primary direction of the substrate. Then, a Cr thin film and a Ni thin film having a thickness of several thousand 数 are formed by a sputtering method so as to cover the end face of the insulating substrate or to cover the end face and partially overlap the upper layer of the front electrode film and the back electrode film.
A film is formed, the masking resist is removed, the insulating substrate is broken by a secondary sliding slit, divided into individual chips, and finally a Ni plating film and a Sn-based plating or Sn · Pb plating film are formed. By applying it as an electrode plating film, a chip-type resistor can be obtained.
【0020】なお、前記表電極膜上層の膜厚が制御され
ているため、二次方向の分割スリッドを跨いで印刷され
ても、絶縁基板の一次ブレークでの分割が容易であり、
分割面のバリ、欠けを抑えることができる。また、はん
だ付けに供する電極膜を広く活用でき、結合面積が広く
なり、セルフアラメント効果に寄与できる。さらに、一
次ブレークにおける分割仕上がり精度が良好となり、抵
抗器の幅方向の精度が向上し、小形化に寄与する。Since the thickness of the upper layer of the front electrode film is controlled, even if the printing is performed across the split in the secondary direction, the insulating substrate can be easily split at the primary break.
Burrs and chips on the divided surface can be suppressed. Further, the electrode film to be used for soldering can be widely used, the bonding area can be widened, and the self-alignment effect can be contributed. Further, the accuracy of the division finish in the primary break is improved, and the accuracy in the width direction of the resistor is improved, which contributes to downsizing.
【0021】続いて、チップ単位で見た本発明のチップ
抵抗器およびその製造工程を図1(a)〜(j)につい
て説明する。まず、図1(a)に示すように、矩形状に
区画された絶縁基板1の裏側の左右両端部に位置するよ
うに、該絶縁基板1の左右の両端および前後両端までの
領域に、すなわち一次方向および二次方向の分割スリッ
ドを跨ぐように、裏電極膜2を形成し、一方、前記絶縁
基板1の表側の左右両端部に位置するように、該絶縁基
板1の左右両端および前後両端からそれぞれ所定距離離
間した位置までの領域に、図1(b)に示すような表電
極膜下層3を形成する。そして、図1(c)に示すよう
に、前記の左右両端部の表電極膜下層3どうしを抵抗体
膜4により接続し、さらにその抵抗体膜4をアンダーコ
ート膜5にて図1(d)に示すように覆う。また、この
アンダーコート膜5の上から前記抵抗体膜4の抵抗値調
整のために、図1(d)に示すようなトリミング溝6を
刻設し、図1(f)に示すように前記絶縁基板1の前後
両端から一部を回避するように、前記アンダーコート膜
5とトリミング溝6をオーバーコート膜7により覆う。Next, the chip resistor according to the present invention viewed from a chip unit and a manufacturing process thereof will be described with reference to FIGS. 1 (a) to 1 (j). First, as shown in FIG. 1 (a), the insulating substrate 1 is positioned at the left and right ends and the front and rear ends of the insulating substrate 1 so as to be located on the right and left ends on the back side of the rectangularly divided insulating substrate 1, A back electrode film 2 is formed so as to straddle the divided slits in the primary direction and the secondary direction, and on both sides of the insulating substrate 1 so as to be located at the left and right ends on the front side of the insulating substrate 1. 1B, a surface electrode film lower layer 3 as shown in FIG. Then, as shown in FIG. 1C, the lower layer 3 of the front electrode film at the left and right ends is connected to each other by a resistor film 4, and the resistor film 4 is further connected by an undercoat film 5 in FIG. Cover as shown in). Further, a trimming groove 6 as shown in FIG. 1D is cut out from above the undercoat film 5 in order to adjust the resistance value of the resistor film 4, and as shown in FIG. The undercoat film 5 and the trimming groove 6 are covered with an overcoat film 7 so as to partially avoid the front and rear ends of the insulating substrate 1.
【0022】さらに、図1(f)に示すように前記絶縁
基板1の左右両端および前後両端まで、前記表電極膜下
層3を表電極膜上層10により覆い、前記絶縁基板1の
左右端面を覆うように、または該左右端面を覆うととも
に前記裏電極膜2および表電極膜上層10の一部に重畳
するように、図1(g)または図1(h)に示すように
スパッタ工法による端面電極膜8を形成し、最後に、図
1(i)または(j)に示すように、前記裏電極膜2、
表電極膜上層10および端面電極膜8を電極めっき膜9
で覆うようにして、チップ抵抗器を形成する。図2はこ
のような工程を経て製造されたチップ抵抗器の正面断面
図である。Further, as shown in FIG. 1F, the front electrode film lower layer 3 is covered with the front electrode film upper layer 10 to the left and right ends and the front and rear ends of the insulating substrate 1, and the left and right end faces of the insulating substrate 1 are covered. 1 (g) or 1 (h) so as to cover the left and right end faces and overlap the back electrode film 2 and part of the front electrode film upper layer 10 as shown in FIG. A film 8 is formed, and finally, as shown in FIG. 1 (i) or (j), the back electrode film 2,
The upper electrode layer 10 and the end face electrode film 8 are coated with the electrode plating film 9.
To form a chip resistor. FIG. 2 is a front sectional view of the chip resistor manufactured through the above steps.
【0023】従って、このようにして製造されるチップ
形抵抗器は、裏電極膜2および表電極膜上層10の一部
に重畳されたスパッタ膜としての端面電極膜8が、これ
らの各電極膜上で不均一な段差の発生を抑制し、特に微
小寸法を有するチップ形抵抗器にあっては、回路基板1
上のランドとのはんだ溶融の際に、はんだの濡れ応力に
よって生じるツームストン現象(チップ立ち)の発生を
抑えることができる。また、端面電極膜9の膜厚が薄い
ので、抵抗器の長さ方向の寸法精度が向上し、小形化に
寄与できる。Accordingly, in the chip resistor manufactured in this manner, the end face electrode film 8 as a sputtered film superimposed on a part of the back electrode film 2 and a part of the front electrode film upper layer 10 is formed by each of these electrode films. The occurrence of uneven steps is suppressed, and especially in the case of chip resistors having minute dimensions, the circuit board 1
When the solder is melted with the upper land, the occurrence of the tombstone phenomenon (tip standing) caused by the wetting stress of the solder can be suppressed. Further, since the thickness of the end face electrode film 9 is small, the dimensional accuracy in the length direction of the resistor is improved, which can contribute to downsizing.
【0024】また、前記二次ブレークで分割スリッドの
一部を回避するようなオーバーコート(レジンまたはガ
ラス、表電極膜上層とオーバーコート膜の組み合わせお
よび裏電極膜とオーバーコート膜の組み合わせがある)
が形成されているため、電極めっき膜形成時に二次ブレ
ーク方向へのめっき成長を阻止でき、オーバーコート膜
のバリ、欠けが抑えられる。Also, an overcoat that avoids a part of the split slip in the secondary break (resin or glass, a combination of the upper layer of the front electrode film and the overcoat film, and a combination of the back electrode film and the overcoat film)
Is formed, plating growth in the secondary break direction can be prevented during formation of the electrode plating film, and burrs and chipping of the overcoat film can be suppressed.
【0025】図3は表電極膜上層10の印刷と裏電極膜
2の印刷の組み合わせにおいて、メタルグレーズおよび
またはAgレジンで形成したときの一次ブレーク時およ
び二次ブレーク時の分割仕上がり性を観察した結果を示
す。ここではチップ形抵抗器の公称長さ寸法が1.6m
mで、公称幅寸法が0.8mmのものを試料として作成
し、一次ブレーク時および二次ブレーク時の分割仕上が
り性を、倍率10の拡大鏡を用いて、各要因100個を
目視検査して良否判定した。これによれば、本実施例は
好適範囲を十分に満たすことが分かる。なお、本実施例
ではチップ形抵抗器の公称長さ寸法が1.6mmで、公
称幅寸法が0.8mmのものを試料としたが、前記公称
寸法以外の様々な公称寸法を有する小型化したチップ形
抵抗器にも応用できる。FIG. 3 shows the division finish at the time of the primary break and the secondary break when formed of metal glaze and / or Ag resin in the combination of printing of the upper electrode layer 10 and printing of the rear electrode film 2. The results are shown. Here, the nominal length of the chip resistor is 1.6 m
m, a sample having a nominal width of 0.8 mm was prepared as a sample, and the finished finish at the time of the primary break and the secondary break was visually inspected using a magnifying glass with a magnification of 10 for 100 factors. Pass / fail was determined. According to this, it is understood that the present example sufficiently satisfies the preferable range. In this embodiment, the chip-type resistor has a nominal length dimension of 1.6 mm and a nominal width dimension of 0.8 mm. However, the chip resistor is reduced in size to have various nominal dimensions other than the nominal dimensions. It can also be applied to chip type resistors.
【0026】[0026]
【発明の効果】以上のように、本発明によれば、チップ
形抵抗器の表側または裏側のいずれも回路基板の実装が
可能であり、Tpおよびバルクのいずれによる供給も可
能になるほか、抵抗器メーカ側の標準化推進および生産
性向上に寄与する。また、一次方向および二次方向のブ
レーク時における絶縁基板、表裏電極膜およびコート膜
およびコート膜のバリや欠けが抑制されて分割精度が向
上し、かつ、チップ形抵抗器の長さ方向、幅方向の仕上
がり精度が安定化し、小形化が可能になるという効果が
得られる。また、表裏電極膜の面積を広くでき、段差を
なくして平坦化にできるため、ツームストンの発生を抑
制でき、セルフアライメント効果が期待できる。As described above, according to the present invention, the circuit board can be mounted on either the front side or the back side of the chip-type resistor, the supply can be made by either Tp or bulk, and the resistance can be increased. It contributes to the promotion of standardization and productivity improvement for equipment manufacturers. In addition, the burrs and chipping of the insulating substrate, the front and back electrode films and the coating film and the coating film at the time of the break in the primary direction and the secondary direction are suppressed, and the division accuracy is improved. The effect of stabilizing the finishing accuracy in the direction and enabling downsizing can be obtained. In addition, since the area of the front and back electrode films can be increased and flattened without steps, the occurrence of tombstones can be suppressed and a self-alignment effect can be expected.
【0027】また、表裏電極膜の領域の厚みの均一性が
確保できて、セルファライメント効果が発揮でき、ま
た、平坦性が確保されることで、ツームストン現象の発
生を抑制できるという効果が得られる。さらに、各製造
工程におけるチップ形抵抗器の供給シュートでの流れが
円滑になるとともに、Tp供給方式でのキャビティから
のチップ形抵器を実装機のノズルによる吸着取り出しが
容易になるという効果が得られる。Further, the uniformity of the thickness of the region of the front and back electrode films can be ensured, the self-alignment effect can be exhibited, and the effect of ensuring the flatness can suppress the occurrence of the tombstone phenomenon. . Furthermore, in each manufacturing process, the flow in the supply chute of the chip-type resistor is smoothed, and the chip-type resistor from the cavity in the Tp supply system is easily attracted and taken out by the nozzle of the mounting machine. Can be
【図1】本発明の実施の一形態によるチップ形抵抗器の
製造工程を示す説明図である。FIG. 1 is an explanatory diagram showing a manufacturing process of a chip-type resistor according to an embodiment of the present invention.
【図2】図1に示すチップ抵抗器の縦断面図である。FIG. 2 is a longitudinal sectional view of the chip resistor shown in FIG.
【図3】本発明における表電極膜上層と裏電極膜を持っ
た絶縁基板の分割仕上がり結果を示す説明図である。FIG. 3 is an explanatory diagram showing the results of division of an insulating substrate having an upper layer of a front electrode film and a back electrode film in the present invention.
【図4】従来のチップ形抵抗器の製造工程を示す説明図
である。FIG. 4 is an explanatory view showing a manufacturing process of a conventional chip-type resistor.
【図5】従来のチップ形抵抗器を示す縦断面図である。FIG. 5 is a longitudinal sectional view showing a conventional chip-type resistor.
1 絶縁基板 2 裏電極膜 3 表電極膜下層 4 抵抗体膜 5 アンダーコート膜 6 トリミング溝 7 オーバーコート膜 8 端面電極膜 9 電極めっき膜 10 表電極膜上層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Back electrode film 3 Lower layer of front electrode film 4 Resistor film 5 Undercoat film 6 Trimming groove 7 Overcoat film 8 Edge electrode film 9 Electrode plating film 10 Upper layer of front electrode film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 平野 立樹 北海道空知郡奈井江町字奈井江955−1 釜屋電機株式会社内 Fターム(参考) 5E028 BA03 BB01 CA02 DA01 EA01 EB05 JC02 JC12 5E032 BA03 BB01 CA02 CC14 CC16 CC18 DA01 TA11 TB02 5E033 AA01 BB02 BC01 BE02 BE04 BH02 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tatsuki Hirano 955-1 Naie, Naie-cho, Sorachi-gun, Hokkaido F-term (reference) in Kamaya Electric Co., Ltd. CC18 DA01 TA11 TB02 5E033 AA01 BB02 BC01 BE02 BE04 BH02
Claims (4)
右両端部に位置するように、該絶縁基板の左右の両端お
よび前後両端までの領域に形成された裏電極膜と、前記
絶縁基板の表側の左右両端部に位置するように、該絶縁
基板の前後両端からそれぞれ所定距離離間した位置まで
の領域に形成された表電極膜下層と、該表電極膜下層ど
うしを接続し、これらの一部を覆う抵抗体膜と、該抵抗
体膜を覆うアンダーコート膜と、該アンダーコート膜上
から前記抵抗体膜の抵抗値調整のために刻設されたトリ
ミング溝と、一部が前記絶縁基板の前後両端まで、前記
アンダーコート膜およびトリミング溝を覆うオーバーコ
ート膜と、前記表電極膜下層上において、前記絶縁基板
の前後両端までを覆う表電極膜上層と、前記絶縁基板の
左右端面を覆うように、または該左右端面を覆い前記裏
電極膜および表電極膜上層の各一部に重畳するようにス
パッタ工法により形成した端面電極膜と、前記裏電極
膜、表電極膜上層および端面電極膜を覆う電極めっき膜
とを備えたことを特徴とするチップ形抵抗器。1. A back electrode film formed at left and right ends and front and rear ends of an insulating substrate so as to be located at left and right ends on the back side of an insulating substrate partitioned into a rectangular shape. The lower surface electrode layer formed in the region from the front and rear ends of the insulating substrate to a position separated by a predetermined distance from each of the front and rear ends of the insulating substrate so as to be located at both left and right ends of the front surface of the insulating substrate, and the lower surface of the front electrode film are connected to each other. A resistor film covering a part of the resistor film, an undercoat film covering the resistor film, a trimming groove engraved from above the undercoat film for adjusting a resistance value of the resistor film, and a part of the insulating film; To the front and rear ends of the substrate, the overcoat film covering the undercoat film and the trimming groove, and on the lower surface of the front electrode film, the upper surface of the front electrode film covering the front and rear ends of the insulating substrate, and the left and right end faces of the insulating substrate. To cover Or an end face electrode film formed by a sputtering method so as to cover the left and right end faces and overlap with each part of the back electrode film and the upper surface layer of the front electrode film, and the back electrode film, the upper surface layer of the front electrode film and the end face electrode film. A chip-type resistor comprising: a covering electrode plating film.
るメタルグレーズ系の膜、または10μm以下の膜厚を
有する銀レジン系の導電膜、あるいは金属有機物の導電
膜であり、前記表電極膜上層が8μm以下の膜厚を有す
るメタルグレーズ系の導電膜、または10μm以下の膜
厚を有する銀レジン系の導電膜で、前記オーバーコート
膜がレジン系またはガラス系の膜であることを特徴とす
る請求項1に記載のチップ形抵抗器。2. The front electrode, wherein the back electrode film is a metal glaze-based film having a thickness of 8 μm or less, a silver resin-based conductive film having a thickness of 10 μm or less, or a metal-organic conductive film. The upper layer is a metal glaze-based conductive film having a thickness of 8 μm or less, or a silver resin-based conductive film having a thickness of 10 μm or less, and the overcoat film is a resin-based or glass-based film. The chip-type resistor according to claim 1, wherein
二次方向の分割スリッドが表裏面に刻設された絶縁基板
の裏面に、前記一次方向および二次方向の分割スリッド
を跨いで裏電極膜を形成する裏電極膜形成工程と、前記
絶縁基板の表面に、前記一次方向の分割スリッドを跨
ぎ、かつ前記二次方向の分割スリッドから離間するよう
に表電極膜下層を形成する表電極膜下層形成工程と、該
表電極膜下層どうしを接続し、これらの一部を覆う抵抗
体膜を形成する抵抗体膜形成工程と、前記抵抗体膜を覆
うようにアンダーコート膜を形成するアンダーコート膜
形成工程と、前記アンダーコート膜上から前記抵抗体膜
の抵抗値調整のためのトリミング溝を刻設するトリミン
グ溝刻設工程と、前記アンダーコート膜とトリミング溝
を覆うように、前記絶縁基板の二次方向の分割スリッド
の一部を回避し、および前記絶縁基板の二次方向の分割
スリッドの一部を跨ぐようにオーバーコート膜を形成す
るオーバーコート膜形成工程と、前記表電極膜下層上に
おいて前記絶縁基板の二次方向の分割スリッドを跨ぐよ
うに表面電極膜上層を形成する表面電極膜上層形成工程
と、前記絶縁基板を一次方向の分割スリッドに沿って、
機械敵応力を利用して短冊状に分割する絶縁基板分割工
程と、前記絶縁基板の左右端面を覆うように、または該
左右端面を覆い裏電極膜および表電極膜上層の各一部に
重畳するように、スパッタ工法により端面電極膜を形成
する端面電極膜形成工程と、前記絶縁基板を二次方向の
分割スリッドに沿って機械的応力を利用してチップ状に
分割するチップ状分割工程と、前記裏電極膜、表電極膜
上層および端面電極膜を覆うように電極めっき膜を形成
する電極めっき膜形成工程とを実行することを特徴とす
るチップ形抵抗器の製造方法。3. A back electrode straddling the primary and secondary divisional slits on the back surface of an insulating substrate in which primary and secondary divisional slits are engraved on the front and back sides so as to be divided into a rectangular shape. A back electrode film forming step of forming a film, and a front electrode film that forms a lower layer of the front electrode film on the surface of the insulating substrate so as to straddle the primary sliding slit and to be separated from the secondary sliding slit. A lower layer forming step, a resistor film forming step of connecting the lower layers of the front electrode film and forming a resistor film covering a part thereof, and an undercoat forming an undercoat film so as to cover the resistor film A film forming step, a trimming groove engraving step of engraving a trimming groove for adjusting the resistance value of the resistor film from above the undercoat film, and the insulating step so as to cover the undercoat film and the trimming groove. An overcoat film forming step of forming a overcoat film so as to avoid a part of the secondary substrate in the secondary substrate and cover a part of the secondary substrate in the insulating substrate; and A surface electrode film upper layer forming step of forming a surface electrode film upper layer so as to straddle a secondary slit of the insulating substrate on the film lower layer, and the insulating substrate along the primary direction split slit,
An insulating substrate dividing step of dividing into strips by using mechanical enemy stress, and covering the left and right end surfaces of the insulating substrate, or covering the left and right end surfaces and superimposing on the back electrode film and each part of the upper layer of the front electrode film. As described above, an end face electrode film forming step of forming an end face electrode film by a sputtering method, and a chip-shaped dividing step of dividing the insulating substrate into chips using mechanical stress along a secondary sliding slit, Forming an electrode plating film so as to cover the back electrode film, the upper electrode film, and the end surface electrode film.
ーバーコート膜を形成する前記オーバーコート膜形成工
程に続いてAgレジン系の裏電極膜を形成する工程であ
ることを特徴とする請求項3に記載のチップ形抵抗器の
製造方法。4. The back electrode film forming step is a step of forming an Ag resin-based back electrode film subsequent to the overcoat film forming step of forming a resin-type overcoat film. Item 4. A method for manufacturing a chip-type resistor according to Item 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001029322A JP2002231505A (en) | 2001-02-06 | 2001-02-06 | Chip resistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001029322A JP2002231505A (en) | 2001-02-06 | 2001-02-06 | Chip resistor and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002231505A true JP2002231505A (en) | 2002-08-16 |
Family
ID=18893684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001029322A Pending JP2002231505A (en) | 2001-02-06 | 2001-02-06 | Chip resistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002231505A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088368A (en) * | 2007-10-02 | 2009-04-23 | Kamaya Denki Kk | Method of manufacturing low-resistance chip resistor |
| JP2010161135A (en) * | 2009-01-07 | 2010-07-22 | Rohm Co Ltd | Chip resistor, and method of making the same |
| JP2013110304A (en) * | 2011-11-22 | 2013-06-06 | Rohm Co Ltd | Chip resistor and manufacturing method of the same |
-
2001
- 2001-02-06 JP JP2001029322A patent/JP2002231505A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009088368A (en) * | 2007-10-02 | 2009-04-23 | Kamaya Denki Kk | Method of manufacturing low-resistance chip resistor |
| JP2010161135A (en) * | 2009-01-07 | 2010-07-22 | Rohm Co Ltd | Chip resistor, and method of making the same |
| JP2013110304A (en) * | 2011-11-22 | 2013-06-06 | Rohm Co Ltd | Chip resistor and manufacturing method of the same |
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