JP2002344145A - Multilayer wiring board and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] (Problem corrected) [PROBLEMS] To realize a thin and lightweight multilayer wiring board having a built-in bypass capacitor and to arrange a dielectric layer forming the bypass capacitor on the outermost layer of the board.
To reduce the adverse effect of via hole inductance by reducing the length of the via hole that electrically connects the bypass capacitor and the mounted component. SOLUTION: The insulating layer 13 and the dielectric layer 1 are made of the same kind of resin material to reduce the warpage of the substrate and to reduce the thickness. Further, the dielectric layer 1 is formed on an arbitrary layer, and is preferably formed on the outermost layer of the multilayer wiring board. This makes it possible to shorten the connection of the via 5 to the capacitor layer and reduce the influence of the inductance of the via 5. In addition, by providing the via 5 that passes through the capacitor layer and is connected to the lower layer, wiring connection with a high degree of freedom becomes possible, and the wiring design is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a bypass capacitor formed inside the board and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, digitalization of electronic equipment has progressed, and high-speed information processing, miniaturization and multifunctional integration have been remarkable. Along with this, the circuit board is required to have high-density wiring accommodability and high-density component mounting in order to cope with the increasing number of semiconductor components.

[0003] In response to the demand for high-density wiring accommodability, in recent years, a multilayer wiring board or a build-up wiring board having an all-layer IVH structure has been developed and has been put to practical use. In order to increase the density of component mounting, BGA
(Ball grid array) and CSP (chip size package) have been developed, and it has become possible to reduce the mounting area and to significantly reduce the space between components. In order to further increase the component mounting density, a technique for forming a bypass capacitor necessary for operating a semiconductor in a substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 5-36857.

In a multilayer wiring board disclosed in Japanese Patent Application Laid-Open No. 5-36857, a first conductive electrode layer and a second conductive electrode are formed on a substrate made of silicon (Si) or aluminum nitride (AIN) or the like. A bypass capacitor including a layer and a dielectric layer sandwiched between these two layers is formed, and a multilayer wiring layer including a wiring layer and an insulating layer is stacked thereon. The multilayer wiring board thus configured includes:
A semiconductor element is mounted on the multilayer wiring layer, and the semiconductor element and the bypass capacitor are electrically connected via via holes provided in the multilayer wiring board. A multilayer wiring board with bypass capacitors formed in the inner layer eliminates the need to place chip capacitors on the chip mounting surface and eliminates the need for wiring to connect chip capacitors.
The degree of freedom in the arrangement and wiring of mounted components has been greatly improved, enabling high-density mounting. As described above, using a wiring board in which a bypass capacitor is built in a board has been a very effective means for high-density mounting.

[0005]

However, the multilayer wiring board disclosed in Japanese Patent Application Laid-Open No. 5-36857 has a structure in which wiring layers and insulating layers made of different materials are laminated, and heat treatment is performed in a mounting process. In this case, the substrate is likely to be warped due to the difference in thermal expansion coefficient between the two. Therefore,
In order to secure the rigidity of the substrate, a certain thickness is required, and there is a problem that the weight of the substrate increases. Further, in this multilayer wiring substrate, a hard substrate made of heat-resistant silicon (Si) or aluminum nitride (AIN) is used, and a dielectric layer is sintered on the hard substrate to form a bypass capacitor. . Therefore, between the surface on which the semiconductor element is mounted and the bypass capacitor layer, there are several layers of insulating layers and wiring layers, and the electrical connection between the semiconductor element and the bypass capacitor is made of these several insulating layers and This must be done via vias that penetrate the wiring layer. As described above, if the bypass capacitor and the semiconductor element connected to the bypass capacitor are arranged at a distance from each other and the length of the via connecting the both becomes long, there is a concern that the inductance of the via adversely affects the stabilization of power supply. is there.

An object of the present invention is to realize a thin and lightweight multilayer wiring board having a built-in bypass capacitor, and to arrange a dielectric layer forming the bypass capacitor on the outermost layer of the board, so that the bypass capacitor and the mounting parts can be mounted. The purpose of the present invention is to reduce the adverse effect of the via hole inductance by making the length of the via hole that electrically connects the via holes short.

[0007]

A multilayer wiring board according to the present invention is a multilayer wiring board in which a wiring layer and an insulating resin layer are laminated, wherein at least one of the insulating resin layers is formed of a dielectric resin layer. A first electrode formed adjacent to the dielectric resin layer; and a first electrode formed adjacent to an opposite side of the dielectric resin layer with the dielectric resin layer interposed therebetween. First
And a second electrode opposed to the first electrode, wherein the dielectric resin layer is disposed on an arbitrary layer of the multilayer wiring board. In the capacitor layer, the first electrode is electrically connected to one terminal of a power supply circuit of the mounted component, and the second electrode is another terminal having a different potential from one terminal of the power supply circuit of the mounted component. And electrically function as a capacitor.

[0008] At least one of the first electrode and the second electrode connected to the one terminal on the high potential side of the dielectric resin layer is oriented in a direction perpendicular to the outermost layer of the multilayer wiring board. It is characterized in that it is formed in the same surface shape and the same area as the projection surface of the mounting component, and is arranged in the projection surface of the mounting component in a direction perpendicular to the outermost layer. As a result, it is possible to prevent the power supply noises of the capacitors formed on the same dielectric resin layer from affecting each other, resulting in worse noise.

[0009] The dielectric resin layer is disposed on the outermost layer of the multilayer wiring board. This makes it possible to shorten the via-hole conductor that electrically connects the mounted component with the capacitor layer including the dielectric resin layer, the first electrode, and the second electrode.

[0010] The multilayer wiring board has an all-layer interstitial via hole structure. Thereby, a via hole can be provided at an arbitrary position to electrically connect the mounted component with the capacitor layer including the dielectric resin layer, the first electrode, and the second electrode. Design can be facilitated.

[0011] By making the thickness of the dielectric resin layer larger than the surface roughness of the first electrode and the second electrode and smaller than the thickness of the insulating resin layer, the thickness of the substrate by pressurizing and heating in the manufacturing process is increased. Warpage can be reduced.

The dielectric resin layer and the insulating resin layer are made of a compressible material.
Thereby, the conductive paste used as the via-hole conductor can be compressed, and the electrical connection can be made more stable.

[0013] The dielectric resin layer is a polymer film. Thereby, the dielectric resin layer can be arranged on an arbitrary layer of the multilayer wiring board.

The polymer film is made of any one of polypropylene, polyethylene terephthalate, polyethylene naphthalate, and polyphenylene sulfide.

The dielectric resin layer is a resin mixed with at least one of a polymer organic filler and an inorganic filler. Thereby, the capacitance of the capacitor layer made of the dielectric resin layer can be increased.

[0016] The polymer organic filler comprises at least one of polypropylene, polyethylene terephthalate, polyethylene naphthalate, and polyphenylene sulfide.

[0017] The inorganic filler is aluminum nitride. The resin is a modified epoxy resin.

The insulating resin layer includes a base material in which a non-woven fabric made of aramid fiber is impregnated with an uncured epoxy resin, a base material in which a woven fabric of glass fiber is impregnated with an uncured epoxy resin,
It is characterized by comprising at least one of a base material in which an adhesive is applied to both surfaces of a polymer film such as polyimide. In accordance with this, the material of the dielectric resin layer is selected from those described above, and the same type of organic material having a molecular structure similar to the insulating resin layer and the dielectric resin layer is used. This makes it possible to reduce the warpage of the substrate.

At least one metal selected from the group consisting of Ni, Zn, and Cr can be electrically connected to a conductor connected to the wiring layer on the surface of the wiring layer, and the surface of the wiring layer can be oxidized. It is characterized in that it is metal-treated in an extremely small amount so as to be able to prevent the occurrence of metallization.

A conductive paste is used as means for connecting the insulating resin layers. The thermal expansion coefficient difference between the insulating resin layer and the dielectric resin layer is small.

According to the method of manufacturing a multilayer wiring board of the present invention, a step of forming a conductor layer made of a metal foil or a metal film on both sides of a dielectric resin layer, and a step of forming a conductor layer formed on both sides of the dielectric resin layer Forming a desired pattern on one side and forming one of the opposing electrodes; providing an insulating resin layer on the conductor layer formed with the desired pattern; and penetrating until the conductor layer is exposed from the insulating resin layer side A step of forming a via hole, a step of providing a conductive material in the via hole, a step of providing a conductive layer patterned so as to block the via hole in an insulating resin layer, and a step of curing the insulating resin layer; Forming a desired pattern on the other of the conductor layers formed on both surfaces of the resin layer, and forming the other of the counter electrodes.

Further, the step of forming conductor layers on both surfaces of the dielectric resin layer includes a step of forming a via hole for conducting between layers of the dielectric resin layer.

The step of providing the insulating resin layer includes a step of temporarily bonding the insulating resin layer to the conductor layer by lamination.

In the step of curing the insulating resin layer, the conductor layer formed in a desired pattern, the insulating resin layer having via holes formed therein, and the conductor layer closing the via holes are subjected to vacuum hot pressing. Bonding, and curing the conductive material filled in the via hole by the vacuum hot press.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The multilayer wiring board of the present invention has a built-in capacitor in which a dielectric layer is sandwiched between opposed electrodes.
In the multilayer wiring board of the present invention, unlike the conventional multilayer wiring board in which a sintered dielectric layer is formed on a ceramic substrate, a polymer film or a resin in which a polymer organic filler or an inorganic filler is mixed in the dielectric layer. Use materials. This makes it possible to provide the dielectric layer on any layer of the multilayer wiring board, for example, on the outermost layer of the multilayer wiring board. Therefore, it is possible to shorten the via, which is an electrical connection means between the mounted component and the built-in capacitor layer, and it is possible to reduce the adverse effect of the via inductance.

As described above, the technique of using a polymer film for the dielectric layer of a capacitor has already been established in the field of film capacitors, and the present invention applies this technique to the formation of a capacitor built in a multilayer wiring board. It was done. Techniques for forming a film capacitor using a polymer film are disclosed in, for example, JP-A-6-251992 and JP-A-8-102427.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. (Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
FIG. 3 is a cross-sectional view illustrating a structure of a multilayer wiring board of FIG.

In FIG. 1, a multilayer wiring board according to the present embodiment includes an insulating resin layer 13, a dielectric resin layer 1,
5a, 15b, 21 and 23 and opposing electrodes 3a and 3b opposing each other with the dielectric resin layer 1 interposed therebetween. Furthermore,
The multilayer wiring board according to the present embodiment enables conduction between wiring layers provided with an insulator interposed therebetween, and includes a conductive paste 17 filled in a via hole penetrating the insulator, and a dielectric resin layer 1. And a via-hole conductor filled in a via-hole penetrating through the dielectric resin layer.
Reference numeral 7 denotes a mounting component mounted on the multilayer wiring board according to the present embodiment, for example, a semiconductor element or a semiconductor integrated circuit. The mounting component 7 has a Vc of the power supply circuit of the mounting component 7.
A c terminal 9, a GND terminal 11 of the power supply circuit, and signal lines 19a and 19b are provided.

The dielectric resin layer 1 is a dielectric used for forming a capacitor. On one surface of the dielectric resin layer 1, a counter electrode 3b and a wiring layer 23 are formed. Further, on the other surface of the dielectric resin layer 1, a counter electrode 3 is provided.
a is formed. The counter electrodes 3a and 3b are provided to face each other so as to sandwich the dielectric resin layer 1. The counter electrode 3b is connected to the GND terminal 11, and the counter electrode 3a
Is connected to the Vcc terminal 9 via the via-hole conductor 5 and the wiring layer 23. Thereby, the dielectric resin layer 1 and the counter electrodes 3a and 3b function as capacitors. This capacitor is referred to as a built-in capacitor layer 10. The counter electrode 3a is provided with the same surface shape and area as the shape of the projection surface of the mounting component 7 in the direction perpendicular to the outermost layer of the multilayer wiring board, and in the direction perpendicular to the outermost layer of the multilayer wiring board. Are arranged so as to fit within the projection plane of the mounting component 7. On the surface of the dielectric resin layer 1 on the side where the counter electrode 3b is formed, wiring layers 15a and 15b connected to the signal lines 19a and 19b are further provided.

Below the built-in capacitor layer 10, an insulating resin layer 13 and a wiring layer 21 formed on the lower surface of the insulating resin layer 13 and connected to the wiring of the mounted component 7 are further provided. The wiring layers 15 a and 15 b and the wiring layer 21 are electrically connected by the conductive paste 17. Further, the counter electrode 3a is connected to the wiring layer 21 via the conductive paste 17. In the lower layer,
An insulating resin layer 13 and a wiring layer 21 are provided.
The wiring layers 21 disposed on both sides of the substrate 3 are electrically connected to each other by the conductive paste 17.

The features of the multilayer wiring board of the present embodiment thus configured will be described below.

In the multilayer wiring board of the present embodiment, the built-in capacitor layer 10 is arranged on the outermost layer of the multilayer wiring board. In order to realize such a configuration, in the present embodiment, a polymer film or a modified epoxy resin mixed with a filler is used as the material of the dielectric resin layer 1.

As the polymer film, at least polypropylene (PP), polyethylene terephthalate (PE)
T), polyethylene naphthalate (PEN), or polyphenylene sulfide (PPS). The filler mixed into the modified epoxy resin may be an inorganic filler such as aluminum nitride (AlN), or polypropylene (PP), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyphenylene sulfide (PP).
One of the high molecular organic fillers such as S) is used.

Preferably, a modified epoxy resin in which either an inorganic filler or a high molecular weight organic filler is mixed in the dielectric resin layer 1 is used. This is because the dielectric constant of the dielectric resin layer 1 can be adjusted by adjusting the mixing amount of the inorganic filler or the polymer organic filler, and the circuit constant can be easily adjusted as necessary. It is.

By using a resin material for the dielectric resin layer 1 as described above, the dielectric resin layer 1 can be disposed on an arbitrary layer of the multilayer wiring board, and the built-in capacitor layer 1 can be formed.
0 can be arranged on the outermost layer. Therefore, the via hole 5 a for electrically connecting the built-in capacitor layer 10 and the mounted component 7 only needs to penetrate the dielectric resin layer 1. Therefore, it is possible to make the via hole 5a very short as compared with a conventional multilayer wiring board which requires via holes penetrating several layers of insulators for electrical connection between the mounted components and the built-in capacitor. it can. As a result, the influence of the inductance of the via-hole conductor 5 can be minimized, and stabilization of power supply can be more effectively realized.

In addition, the built-in capacitor layer 10 is disposed on the outermost layer, and the opposing electrode 3a connected to at least the higher potential side of the opposing electrodes 3a, 3b is moved in a direction perpendicular to the outermost layer of the multilayer wiring board. It is formed in the same shape and area as the projection surface of the mounting component 7 and is disposed immediately below the mounting component 7 so as to be within the projection surface of the mounting component 7 in a direction perpendicular to the outermost layer of the multilayer wiring board. . Thereby, even when the power supply circuits of a plurality of mounted components are connected, the same dielectric resin layer 1
It is possible to prevent the power supply noises of the plurality of built-in capacitor layers 10 formed on each other from affecting each other, resulting in inferior noise. Further, with such a configuration, the connection by the via-hole conductor 5 for electrically connecting the built-in capacitor layer 10 and the mounted component 7 can be further shortened, so that the power supply can be further stabilized. Can be realized in a practical manner. On the other hand, the counter electrode 3b, which is the other counter electrode, is connected to the GND terminal 11 of the mounted component 7 and is formed so as to cover almost the entire surface of the substrate. Therefore, the counter electrode 3b has a shielding effect against electromagnetic wave noise generated from a circuit in the substrate.

In this embodiment, since the built-in capacitor layer 10 is provided on the outermost layer of the substrate, the signal lines 19a and 19b need to be wired below the built-in capacitor layer 10. For this reason, the signal line 19 a provided on the mounted component 7 is connected to the wiring layer 21 below the built-in capacitor layer 10 via the via hole conductor 17 filled in the via hole 18 b penetrating the dielectric resin layer 1. . Further, the signal line 19b located on the outer peripheral portion of the mounted component 7 is drawn out to the outside of the counter electrodes 3a and 3b by the wiring layer 15b, and then the via hole conductor 17 filled in the via hole 18a penetrating the dielectric resin layer 1 is formed. Through this, it is connected to the wiring layer 21 below the built-in capacitor layer 10. With this configuration, even if the built-in capacitor layer 10 is provided on the outermost layer, the degree of freedom in wiring design of the signal line is not impaired.

Further, the same type of organic material having a molecular structure similar to the material of the dielectric resin layer 1 and the material of the insulating resin layer 13 is used. The insulating resin layer 13 includes a nonwoven fabric made of aramid fiber impregnated with an uncured epoxy resin, a woven glass fiber fabric impregnated with an uncured epoxy resin, and both surfaces of a polymer film such as polyimide. And at least one of a base material coated with an adhesive. In accordance with this, the above-described materials are used for the dielectric resin layer 1. This makes it possible to suppress the warpage of the entire substrate. Therefore, since it is not necessary to increase the thickness of each layer in order to secure the rigidity of the substrate, it is possible to suppress an increase in the weight of the multilayer wiring substrate.

From the viewpoint of reducing the warpage of the entire substrate, it is preferable to use a material having a coefficient of thermal expansion as close as possible to the material of the dielectric resin layer 1 and the material of the insulating resin layer 13. This is because if the difference between the two coefficients of thermal expansion is large,
During solder reflow (at high temperature) or afterwards, the board warps,
This is because a mounting defect occurs. If a material having a coefficient of thermal expansion close to both materials is used, it is possible to reduce the warpage of the substrate. In addition, this eliminates the need to increase the thickness of each layer in order to secure the rigidity of the substrate, thereby suppressing an increase in the weight of the multilayer wiring substrate.

Further, by making the dielectric resin layer 1 thinner than the insulating resin layer 13, it is possible to suppress the warpage of the entire substrate even if both have different thermal expansion coefficients. In the present embodiment, the dielectric resin layer 1 has a thickness of 0.1
The insulating resin layer 13 has a thickness of 20 to 10 μm.
It is formed with a thickness of １００100 μm.

The thickness of the dielectric resin layer 1 is 0.1 to
It may be 3 μm. More preferably, the thickness of the dielectric resin layer 1 may be set to 0.1 to 1 μm. By forming the thickness of the dielectric resin layer 1 as thin as possible, the warpage of the substrate can be further suppressed, and the capacity of the built-in capacitor layer 10 can be increased. In consideration of both the productivity and the performance of the multilayer wiring board, the thickness of the dielectric resin layer 1 is preferably set to 1 μm.

In the present embodiment, all-layer interstitial via holes (hereinafter referred to as IV
Abbreviated as H. ) A substrate having a structure is used. The substrate having the all-layer IVH structure is preferable because a via hole can be formed at an arbitrary position in an arbitrary layer. In addition, with the use of a substrate having an all-layer IVH structure, a conductive paste 17 is used for a via-hole conductor. The conductive paste is, for example, a paste obtained by kneading one of copper powder, silver powder, copper-silver alloy powder, and powder obtained by plating copper powder with silver, and a thermosetting resin. When the conductive paste 17 is compressed, the metal powder contained in the paste is densified, and a more stable electrical connection can be obtained.
Therefore, it is preferable to use a material having compressibility for the dielectric resin layer 1 and the insulating resin layer 13. By using such a material having compressibility, the dielectric resin layer 1 and the insulating resin layer 13 shrink during the pressing process,
The conductive paste can be more compressed. As a result, stable electrical connection can be realized.
In the present embodiment, the multilayer wiring substrate is a substrate having an all-layer IVH structure. However, the present invention is not limited to this. Any substrate may be used as long as a via hole can be formed at an arbitrary position in an arbitrary layer.

Further, in the present embodiment, the wiring layer 1
Metal plating is applied to the surfaces 5a, 15b, 21, and 23 so that the surfaces are not completely covered. This is because the copper foil surface is prevented from being oxidized, the adhesion with the organic material is improved, and the copper foil and the conductive paste 17 are prevented.
And stable electrical connection with the same. For the wiring layers 15a, 15b, 21, 23, electrolytic copper foil is generally used. In order to prevent oxidation of the copper foil surface, a metal made of at least one of Ni, Zn, and Cr is plated. Metals such as Ni, Zn, and Cr are easily bonded to oxygen and form a stable metal oxide film. By forming this metal oxide film, oxidation of the copper foil surface can be prevented. Further, the metal oxide film has excellent adhesion to an organic material. However, on the other hand, since the metal oxide film is a non-conductor, it adversely affects the electrical connection with the conductor connected to the copper foil surface. Therefore, the amount of metal plated on the copper foil surface is extremely small. When a very small amount of metal is thinly plated on the surface of the copper foil as described above, the plated metal does not uniformly cover the surface of the copper foil, and minute gaps are formed in the plating layer. The copper foil surface and the conductor connected thereto come into contact with each other through this gap, and both can be conducted. Such metal plating makes it possible to prevent oxidation of the copper foil surface, improve the adhesion to the organic material, and achieve stable electrical connection between the copper foil and the conductive paste 17.

Next, the manufacturing method of the present embodiment configured as described above will be described in detail below. FIG.
FIG. 7 is a cross-sectional view sequentially showing the steps of manufacturing the multilayer wiring board of the present embodiment.

As shown in FIG. 2A, the counter electrode 3
a, 3b and the base material of the wiring layers 15a, 15b, and the dielectric resin layer 1
To form The thickness of the dielectric resin layer 1 formed at this time is preferably larger than the surface roughness of the metal foil 12 and smaller than the thickness of the metal foil 12. The dielectric resin layer 1 is formed thin using an ED method (electrodeposition) which is a kind of a coating method or a plating method. Alternatively, a method in which the metal film 12 is formed on one surface of the dielectric resin layer 1 made of a thin polymer film by using vacuum evaporation, sputtering, or plating.

Subsequently, as shown in FIG. 2B, a via hole 5a is formed to enable conduction between the front and back surfaces of the dielectric resin layer 1. The processing of the via hole 5a uses a laser processing method in the present embodiment. The processing method is not limited to laser processing.

Further, as shown in FIG. 2C, on the other surface of the dielectric resin layer 1 where the metal foil 12 is not formed,
The metal film 16 which is a conductor layer is formed by using vacuum evaporation, sputtering, or plating. The dielectric resin layer 1
As described above, the metal film 1 is formed to be very thin.
At the time of forming 6, metal is deposited also in the via hole 5a, and the via hole conductor 5 is formed. Thereby, the layers between the metal foil 12 and the metal film 16 can be electrically connected. That is, conduction between the conductor layers becomes possible.

Next, as shown in FIG. 2D, a counter electrode 3a is formed on the metal film 16 in a desired wiring pattern.

Thereafter, as shown in FIG. 2E, the insulating resin layer 13 is temporarily bonded by a laminating method. Temporary bonding is 8
It is performed by applying a pressure of approximately 3 kg / cm at a temperature of 0 to 100 ° C.

Further, as shown in FIG. 2F, via holes are formed from the insulating resin layer 13 side by using a laser processing method. What is important in this step is that the counter electrode 3a
The via holes 18a to be processed on the upper side and the via holes 18b to be processed on the metal foil 12 are processed at the same time to form via holes having different depths. The laser used for the processing is an ultraviolet laser having a wavelength of 355 nm, and it is possible to process via holes having different depths by weighting the processing data for each via hole by a weight corresponding to the number of processing pulses. The via hole 18a is formed in the dielectric resin layer 1
Is formed so that the surface of the metal foil 12 is exposed.

Next, as shown in FIG. 2G, the conductive paste 17 is filled in the via holes 18a and 18b by repeating squeezing several times. Note that a vacuum defoaming step may be inserted in the middle of squeezing. Thereby, bubbles can be prevented from being mixed into the conductive paste 17 to be filled, so that the filling property of the conductive paste 17 is improved. In addition, the filling property of the conductive paste 17 is also improved by the resin component of the conductive paste 17 exuding from a small gap between the via holes 18a and 18b and the metal foil 12 at the time of filling.

Next, as shown in FIG. 2 (h), a supporting base material 22 in which the wiring layer 21 is formed by patterning in advance.
Are superposed on the insulating resin layer 13 while aligning the wiring layers 21 so as to block the corresponding via holes 18a and 18b. After being overlapped in this manner, the metal foil 12, the insulating resin layer 13, and the supporting base material 22 are bonded and integrated by heating and pressing with a vacuum hot press to completely cure the insulating resin layer 13. Let it. Further, the conductive paste 17 filled in the via holes 18a and 18b is compressed by the heating and pressing at this time. As a result, the metal powder contained in the conductive paste 17 is densified, and an electrical connection between the metal foil 12 and the wiring layer 21 provided with an insulator therebetween and between the counter electrode 3a and the wiring layer 21 is provided. Connection is possible.

Subsequently, as shown in FIG. 2I, the supporting base material 22 is removed. A metal foil made of Al or the like that can be selectively etched with the wiring layer 21 is used as the material of the support base material 22. However, the material is not limited to a metal foil as long as it is a material that can be peeled off after vacuum hot pressing. .

Subsequently, as shown in FIG. 2 (j), the steps (e) to (i) of FIG.
And a wiring layer 21 are formed. Thus, (e) of FIG.
By repeating (i) to (i) a desired number of times, it is possible to form a multilayer.

Finally, as shown in FIG. 2 (k), the counter electrode 3b and the wiring layers 15a, 15b and 23 are formed on the metal foil 12 in a desired wiring pattern, and the multilayer wiring board according to the present embodiment is formed. Is completed.

(Embodiment 2) FIG. 3 is a sectional view showing a structure of a multilayer wiring board according to Embodiment 2 of the present invention.

In FIG. 3, the multilayer wiring board according to the present embodiment includes an insulating resin layer 13, a dielectric resin layer 1, opposing electrodes 3a and 3b opposed to each other with the dielectric resin layer 1 interposed therebetween, and a wiring layer 21. , 15a, 15b, 23, and 25.
Further, the multilayer wiring board according to the present embodiment has conductive paste 17 that enables conduction between wiring layers provided with an insulator therebetween and is filled in via holes penetrating the insulator. Reference numeral 7 denotes a mounting component mounted on the multilayer wiring board according to the present embodiment, for example, a semiconductor element or a semiconductor integrated circuit. The mounted component 7 is provided with a Vcc terminal 9 of a power supply circuit of the mounted component 7, a GND terminal 11 of the power supply circuit, and signal lines 19a and 19b.

The dielectric resin layer 1 is a dielectric used for forming a capacitor. On one surface of the dielectric resin layer 1, a counter electrode 3a is formed. Further, on the other surface of the dielectric resin layer 1, a counter electrode 3b is formed. The counter electrodes 3a and 3b are provided to face each other so as to sandwich the dielectric resin layer 1. Thereby, the dielectric resin layer 1 and the counter electrodes 3a and 3b function as capacitors. This capacitor is referred to as a built-in capacitor layer 20.
Further, the counter electrode 3b is formed by connecting the via hole conductor 17 and the wiring layer 2 to each other.
3 is connected to the GND terminal 11 via the counter electrode 3a.
Is Vcc via the via-hole conductor 17 and the wiring layer 25.
Connected to terminal 9. Thereby, the built-in capacitor 20 and the mounting component 7 can be electrically connected. The counter electrodes 3a, 3b are provided in the same shape and area as the shape of the projection surface of the mounting component 7 in the direction perpendicular to the outermost layer of the multilayer wiring board, and in the direction perpendicular to the outermost layer of the multilayer wiring board. Are arranged so as to fit within the projection plane of the mounted component 7 to the camera.

The insulating resin layer 13 and the wiring layers 15a, 15b, 23, 25 are provided above the built-in capacitor layer 20. The wiring layer 15 is provided on the upper surface of the insulating resin layer 13.
a, 15b, 23 and 25 are formed. Wiring layer 15
a is provided for connection to the signal line 19a of the mounted component 7. The wiring layer 15b is provided to connect to the signal line 19b of the mounted component 7. Wiring layer 2
Reference numeral 3 is provided for connection to the GND terminal 11 of the power supply circuit of the mounted component 7. The wiring layer 25 is provided to connect to the Vcc terminal 9 of the power supply circuit of the mounted component 7.

Under the built-in capacitor layer 20, an insulating resin layer 13 and a wiring layer 21 are provided. The wiring layer 21 is formed on the upper surface of the insulating resin layer 13. The wiring layer 21 includes a wiring layer 15 a via the via-hole conductor 17,
15b is electrically connected. Further, an insulating resin layer 13 and a wiring layer 21 are provided below the wiring layer 21, and the wiring layers 21 disposed on both sides of the insulating resin layer 13 are electrically connected to each other by the conductive paste 17. .

The features of the multilayer wiring board of the present embodiment thus configured will be described below. The detailed description of the same points as in the first embodiment is omitted.

In FIG. 3, the multilayer wiring board of the present embodiment according to the present invention uses a polymer film for the dielectric resin layer 1 or uses an inorganic filler or a polymer organic filler as in the first embodiment. Is used. Therefore, the dielectric resin layer 1 can be provided on an arbitrary layer of the multilayer wiring board. In the present embodiment, the dielectric resin layer 1 is disposed on the inner layer of the multilayer wiring board.
That is, the dielectric resin layer 1 is disposed between the insulating resin layers 13.

In the multilayer wiring board on which the dielectric resin layer 1 is disposed as described above, the signal lines 19a and 19b are drawn out to the outer peripheral portion of the mounted component 7 on the board surface by the wiring layers 15a and 15b, respectively, via the via hole conductor 17. Wiring in the lower layer. That is, there is no need to pass the via-hole conductor 17 connected to the signal line to the built-in capacitor layer 20, and it is easy to secure the necessary area for the opposing electrodes 3a and 3b by not penetrating the via-hole. Therefore,
It becomes possible to make the projection area of the counter electrodes 3a, 3b smaller than the projection area of the mounting component 4.

Further, at least the counter electrode 3a on the high potential side of the counter electrode is formed in the same shape and the same area or the same shape and the small area on the projection surface of the mounting component 7, and the multilayer It is better to arrange them so as to fit within the projection plane of the mounting component 7 in a direction perpendicular to the outermost layer of the wiring board. Preferably, both of the counter electrodes 3a and 3b have the same shape and the same area as the projection surface shape of the mounted component 7,
Alternatively, it is better to be formed in the same shape and with a small area, and to be arranged so as to fit within the projection plane of the mounting component 7 in a direction perpendicular to the outermost layer of the multilayer wiring board. With such a configuration, even when the power supply circuits of a plurality of mounted components are connected, the power supply noises of the built-in capacitor layers 20 formed on the same dielectric resin layer 1 affect each other, resulting in further deterioration. Noise can be prevented. Further, since the via connection for connecting to the built-in capacitor layer 20 can be shortened, the power supply can be more effectively stabilized.

In addition, the configuration shown in FIG.
By providing the built-in capacitor layer 20 as in the present embodiment, the built-in capacitor layer can be multi-layered and the capacity of the inner capacitor layer connected to the mounted component 7 can be further increased.

Next, a method for manufacturing the multilayer wiring board of the present embodiment configured as described above will be described in detail. The detailed description of the same points as in the first embodiment is omitted. FIG. 4 is a cross-sectional view sequentially showing the steps of manufacturing the multilayer wiring board of the present embodiment.

As shown in FIG. 4A, the counter electrode 3b
The dielectric resin layer 1 is formed on one of the surfaces of the metal foil 12 serving as a conductor layer and serving as a base material of the wiring layer 21. The dielectric resin layer 1 is formed thin using an ED method which is a kind of a coating method or a plating method. Alternatively, a vacuum evaporation or sputtering method may be applied to one of the surfaces of the dielectric resin layer 1 in the form of a thin film.
Alternatively, a method of forming the metal foil 12 using a plating method may be used. Further, if necessary, via holes may be provided in order to establish conduction between the dielectric resin layers 1.

As shown in FIG. 4B, a conductor layer is formed on the other surface of the dielectric resin layer 1 on which the metal foil 12 is not formed by using vacuum deposition, sputtering, or plating. A metal film 16 is formed.

As shown in FIG. 4C, the counter electrode 3a is formed by forming the metal film 16 in a desired pattern.

Next, as shown in FIG. 4D, an insulating resin layer 13 is temporarily bonded to the surface of the metal foil 12 on which the counter electrode 3a is formed by a laminating method. Temporary bonding is 80-1
It is performed by applying a pressure of about 3 kg / cm at a temperature of 00 ° C.

Further, as shown in FIG. 4E, via hole processing is performed from the insulating resin layer 13 side by using a laser method. What is important in this step is, as in the first embodiment, a via hole 18a to be processed on the counter electrode 3a and a metal foil 12a.
This is to simultaneously process via holes 18b having different depths. Also, via hole 18b
Is processed until the surface of the metal foil 11 is exposed through the dielectric resin layer 1.

Next, as shown in FIG. 4F, the conductive paste 17 is filled in the via holes 18a and 18b. Filling is performed by repeating squeezing several times. Further, the vacuum defoaming step may be inserted in the middle of several times of squeezing.

Next, as shown in FIG. 4 (g), the supporting base material 22, in which the wiring layers 15a, 15b, 23 and 25 are formed by previously performing wiring patterning on the conductor layer, is moved to the wiring layer 1 as shown in FIG.
Via holes 18 corresponding to 5a, 15b, 23, 25
While being aligned with a and 18b, it is superposed on the insulating resin layer 13.

Subsequently, as shown in FIG. 4 (h), the metal foil 12, the insulating resin layer 13, and the supporting base material 22 are heated and pressed by a vacuum hot press to completely cure the insulating resin layer 13. And are integrated. At the same time, via holes 18a,
The conductive paste 17 in 18b is compressed, and the metal powder contained in the conductive paste 17 is densified. This allows
Electrical connection is possible between the metal foil 12 and the wiring layers 15a, 15b, and 23, and between the wiring layer 25 and the counter electrode 3a.

Subsequently, as shown in FIG.
2 is patterned into a desired wiring pattern shape to form a wiring layer 21 and a counter electrode 3b.

Further, as shown in FIG. 4 (j), the steps shown in FIGS. 4 (d) to 4 (i) are repeated, and the insulating resin layer 13 is formed.
And a wiring layer 21 are formed.

Finally, as shown in FIG. 4 (k), the supporting base material 22 is removed, and a multilayer wiring board according to the second embodiment as shown in FIG. 3 is completed.

In the present embodiment, the support base material 22
Used a metal foil such as Al that can be selectively etched with the wiring layers 15a, 15b, 23, and 25. However, the material is not limited to a metal foil as long as it is a material that can be peeled off after vacuum hot pressing.

[0079]

According to the multilayer wiring board of the present invention, in a multilayer wiring board having an all-layer IVH structure, the same type of resin material is used for all of the insulating resin layers and the dielectric resin layers constituting the board. In response to the demand for thinner, it is possible to realize thinner and lighter and to reduce warpage in a mounting process. Further, since the dielectric resin layer can be arranged on an arbitrary layer of the multilayer wiring board, the inner capacitor layer can be formed immediately below the mounted component, that is, on the outermost layer of the multilayer circuit board. . Thereby, the via connection for connecting the inner capacitor layer and the mounted component can be shortened, and the influence of the via inductance can be minimized. Therefore, stabilization of power supply can be realized more effectively. Further, by providing a via that passes through the inner capacitor layer and is connected to the lower layer, wiring connection with a high degree of freedom in the inner layer can be performed, thereby simplifying the wiring design.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a multilayer wiring board according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing the method for manufacturing the multilayer wiring board according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing a multilayer wiring board according to a second embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a multilayer wiring board according to Embodiment 2 of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dielectric resin layer 3a, 3b Counter electrode 5 Via hole conductor 5a Via hole 7 Mounting component 9 Vcc terminal 11 GND terminal 12 Metal foil 13 Insulating resin layer 15a, 15b, 21, 23, 25 Wiring layer 17 Conductive paste 19a, 19b Signal Line 16 Metal film 18a, 18b Via hole 22 Support base material 35, 45, 55 Support base material

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[Procedure amendment]

[Submission Date] May 16, 2001 (2001.5.1)
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 19

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 20

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claim 21

[Correction method] Change

[Correction contents]

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) C08L 23/10 C08L 23/10 63/00 63/00 C 67/02 67/02 81/02 81/02 H01L 23 / 12 H05K 1/11 N H05K 1/11 3/24 A 3/24 H01L 23/12 BE (72) Inventor Daizo Ando 1006 Odakadoma, Kadoma City, Osaka Prefecture F-term (reference) 4J002 BB122 CD001 CF062 CF082 CN012 DF016 FD012 FD016 GQ01 5E317 AA24 BB12 CC25 CD27 CD32 GG11 GG14 5E343 AA02 AA13 AA15 AA16 AA17 BB16 BB24 BB38 BB44 BB71 DD02 EE60 GG01 GG08 A13A33 A13 A33 A13 A33 A13 A33 A13 A33 A13 A33 A13 A33 A13 A33 A33 A13 A33 A13 A33 A13 A33 A13 A33 A31 A33 A31 A33 A CC08 CC16 CC21 CC32 CC37 DD02 DD07 DD22 DD32 EE06 EE07 EE09 EE13 EE18 EE33 EE38 FF04 FF18 FF45 GG17 GG19 GG28 HH01 HH02 HH06 HH25

Claims (21)

[Claims] 1. A multilayer wiring board in which a wiring layer and an insulating resin layer are laminated, wherein at least one of the insulating resin layers is made of a dielectric resin layer, and the dielectric resin layer is made of a dielectric resin. A first electrode formed adjacent to the layer, and a second electrode formed adjacent to the opposite side of the dielectric resin layer with the dielectric resin layer interposed therebetween and facing the first electrode; Wherein the dielectric resin layer is disposed on an arbitrary layer of the multilayer wiring board. 2. The device of claim 1, wherein the first electrode is electrically connected to one terminal of a power supply circuit of the mounted component, and the second electrode is connected to another terminal having a different potential from one terminal of the power supply circuit of the mounted component. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is electrically connected to one terminal. 3. One of the first electrode and the second electrode connected to at least the one terminal on the high potential side,
3. The multi-layer wiring board according to claim 2, which is formed in the same surface shape and the same area as a projection surface of the mounting component in a direction perpendicular to the outermost layer of the multilayer wiring board, and is arranged in the projection surface. The described multilayer wiring board. 4. The multilayer wiring board according to claim 1, wherein the dielectric resin layer is disposed on an outermost layer of the multilayer wiring board. 5. The multilayer wiring board according to claim 1, wherein the multilayer wiring board has an all-layer interstitial via hole structure. 6. The method according to claim 1, wherein the thickness of the dielectric resin layer is larger than the surface roughness of the first electrode and the second electrode and smaller than the thickness of the insulating resin layer. Multilayer wiring board. 7. The multilayer wiring board according to claim 1, wherein the dielectric resin layer and the insulating resin layer are made of a material having compressibility. 8. The multilayer wiring board according to claim 1, wherein the dielectric resin layer is a polymer film. 9. The multilayer wiring according to claim 8, wherein the polymer film is made of any one of polypropylene, polyethylene terephthalate, polyethylene naphthalate, and polyphenylene sulfide. substrate. 10. The multilayer wiring board according to claim 1, wherein the dielectric resin layer is a resin mixed with at least one of a polymer organic filler and an inorganic filler. 11. The organic polymer filler according to claim 1, wherein the organic filler comprises at least one of polypropylene, polyethylene terephthalate, polyethylene naphthalate, and polyphenylene sulfide.
2. The multilayer wiring board according to item 0. 12. The multilayer wiring board according to claim 10, wherein the inorganic filler is aluminum nitride. 13. The multilayer wiring board according to claim 10, wherein the resin is a modified epoxy resin. 14. The insulating resin layer includes a base material obtained by impregnating an uncured epoxy resin into a nonwoven fabric made of aramid fiber, a base material obtained by impregnating a woven glass fiber fabric with an uncured epoxy resin, and a resin such as polyimide. 2. The multilayer wiring board according to claim 1, comprising at least one of a base material having an adhesive applied to both surfaces of the polymer film. 15. The method according to claim 15, wherein Ni, Zn, C
At least one kind of metal of r is metal-treated in a trace amount capable of electrically connecting to a conductor connected to the wiring layer and preventing oxidation of the surface of the wiring layer. 2. The multilayer wiring board according to claim 1, wherein: 16. The multilayer wiring board according to claim 1, wherein a conductive paste is used as a means for connecting the insulating resin layers. 17. The multilayer wiring board according to claim 1, wherein a difference in thermal expansion coefficient between the insulating resin layer and the dielectric resin layer is small. 18. A step of forming conductor layers on both sides of a dielectric resin layer, forming a desired pattern on one of the conductor layers formed on both sides of the dielectric resin layer, and forming one of the counter electrodes. A step of providing an insulating resin layer on a conductor layer formed in a desired pattern; a step of forming a via hole penetrating from the insulating resin layer side until the conductor layer is exposed; and a step of providing a conductive material in the via hole. Providing a conductor layer patterned and formed on the insulating resin layer so as to block the via hole, and curing the insulating resin layer; and forming a desired pattern on the other of the conductor layers formed on both surfaces of the dielectric resin layer. Forming the other of the opposed electrodes, and the method of manufacturing a multilayer wiring board. 19. The method according to claim 17, wherein the step of forming a conductor layer on both surfaces of the dielectric resin layer includes a step of forming a via hole for conducting between layers of the dielectric resin layer. Of manufacturing a multi-layer wiring board. 20. The method according to claim 17, wherein the step of providing the insulating resin layer includes a step of temporarily bonding the insulating resin layer to the conductor layer by lamination. 21. The step of curing the insulating resin layer includes bonding a conductive layer formed in a desired pattern, an insulating resin layer formed with a via hole, and a conductive layer closing the via hole by a vacuum hot press. 18. The method for manufacturing a multilayer wiring board according to claim 17, further comprising: performing a step of curing the conductive material filled in the via hole by the vacuum hot pressing.