JP2002353763A - Method for manufacturing piezoelectric element device - Google Patents
Method for manufacturing piezoelectric element deviceInfo
- Publication number
- JP2002353763A JP2002353763A JP2001160714A JP2001160714A JP2002353763A JP 2002353763 A JP2002353763 A JP 2002353763A JP 2001160714 A JP2001160714 A JP 2001160714A JP 2001160714 A JP2001160714 A JP 2001160714A JP 2002353763 A JP2002353763 A JP 2002353763A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- piezoelectric element
- acoustic wave
- surface acoustic
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01045—Rhodium [Rh]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
(57)【要約】
【課題】 ヒートサイクルにより圧電素子と基板との電
気的接続部のクラックの発生を防止し、かつ機械的強度
の低下が防止された圧電素子デバイス（表面弾性波素子
デバイス）の製造方法を得る。
【解決手段】 配線基板２０に表面弾性波素子１０をフ
リップチップ実装する。表面弾性波素子１０の周囲を囲
う様に、第１の樹脂からなる枠部３を形成する。枠部３
で囲まれた領域を上記第１の樹脂より低い弾性率を有す
る第２の樹脂からなる封止樹脂５により充填し、励起電
極２と基板６の間を中空状態に保持して表面弾性波素子
１０を封止する。
(57) Abstract: A piezoelectric element device (surface acoustic wave element device) that prevents cracks in an electrical connection between a piezoelectric element and a substrate due to a heat cycle and prevents a decrease in mechanical strength. Is obtained. SOLUTION: A surface acoustic wave element 10 is flip-chip mounted on a wiring board 20. The frame portion 3 made of the first resin is formed so as to surround the surface acoustic wave device 10. Frame part 3
Is filled with a sealing resin 5 made of a second resin having a lower elastic modulus than that of the first resin, and a space between the excitation electrode 2 and the substrate 6 is held in a hollow state. 10 is sealed.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、圧電素子デバイス
の製造方法、特に高周波フィルタとして、電気通信機器
等に用いられる表面弾性波素子を圧電素子として用いた
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a piezoelectric element device, and more particularly to a method of manufacturing a piezoelectric element using a surface acoustic wave element used for a telecommunication device or the like as a high frequency filter.
【０００２】[0002]
【従来の技術】図３は、特開平４―３０１９１０号公報
に記載された従来の表面弾性波素子デバイスを示す断面
図である。この図において、１は圧電体基板であり、こ
の圧電体基板１の一方の主面（図において下面）には、
圧電体基板１表面の所定方向に励振される表面波の伝搬
路となるすだれ状電極（Ｉｎｔｅｒｄｉｇｉｔａｌ Ｔ
ｒａｎｓｄｕｃｅｒ、以下ＩＤＴと称する）によって形
成された励振電極２とこの励振電極２から延設されて機
能部の外部への接続端子となる電極パッド（図示せず）
とが形成され、以上により表面弾性波素子１０を構成す
る。１１はパッケージで、１１ｃは上記チップを保持す
るパッケージ保持部、１１ａおよび１１ｂは上記チップ
を取り囲むように設けられ、上記チップの収容部を形成
するパッケージ周壁部で、１１ａの一部には外部への接
続部となる端子部１２が形成されている。９は金属製の
カバーで、パッケージ周壁部１１ｂの上面に設けた封止
部１３に接合させ、上記表面弾性波素子１０の機能部を
気密封止して保護している。2. Description of the Related Art FIG. 3 is a sectional view showing a conventional surface acoustic wave device described in Japanese Patent Application Laid-Open No. 4-301910. In this figure, reference numeral 1 denotes a piezoelectric substrate, and one main surface (a lower surface in the figure) of the piezoelectric substrate 1 has:
Interdigital T (interdigital T) serving as a propagation path of a surface wave excited in a predetermined direction on the surface of the piezoelectric substrate 1.
and an electrode pad (not shown) extending from the excitation electrode 2 and serving as a connection terminal to the outside of the functional unit.
Are formed, and the surface acoustic wave device 10 is constituted as described above. 11 is a package, 11c is a package holding portion for holding the chip, 11a and 11b are provided so as to surround the chip, and is a package peripheral wall portion which forms a receiving portion for the chip. A terminal portion 12 serving as a connection portion is formed. Reference numeral 9 denotes a metal cover, which is joined to a sealing portion 13 provided on the upper surface of the package peripheral wall portion 11b, and hermetically seals and protects the functional portion of the surface acoustic wave device 10.
【０００３】表面弾性波素子１０と端子部１２との接続
はバンプ電極４で行っている。即ち、チップ１の図示し
ない電極パッド上に形成したバンプ電極４を端子部１２
に接合して電気的接続を得ている。パッケージ周壁部１
１ａにより、パッケージ保持部１１ｃの励振電極２に対
応する部分に段差を形成して中空部１４を確保し、これ
によって励振電極２の保護並びにその表面部の空隙確保
が図られている。即ち、図３に示すように、励振電極２
をチップ１の下面に設け、励振電極２とパッケージ保持
部１１ｃとの対向部に中空部１４を形成することによ
り、励振電極２により励振される表面波とその伝搬路を
弾性的に開放するための中空部を確保することができる
とともに、励振電極２の破損を防止するための保護対策
もできる。The connection between the surface acoustic wave device 10 and the terminal portion 12 is made by the bump electrode 4. That is, the bump electrodes 4 formed on the electrode pads (not shown) of the chip 1 are connected to the terminal portions 12.
To obtain an electrical connection. Package wall 1
By 1a, a step is formed in a portion of the package holding portion 11c corresponding to the excitation electrode 2 to secure the hollow portion 14, thereby protecting the excitation electrode 2 and securing a void in the surface portion thereof. That is, as shown in FIG.
Is provided on the lower surface of the chip 1 and a hollow portion 14 is formed at a portion opposite to the excitation electrode 2 and the package holding portion 11c to elastically open the surface wave excited by the excitation electrode 2 and its propagation path. And a protective measure for preventing the excitation electrode 2 from being damaged.
【０００４】しかし、金属製カバー９による気密封止
は、製造コストが高くなり、さらに、表面弾性波素子を
収容するパッケージ１１は、予め、１つまたは複数個の
表面弾性波素子１０を収容するよう個々に用意されてい
るので、大量生産に不向きであるという課題があった。[0004] However, the hermetic sealing with the metal cover 9 increases the manufacturing cost, and the package 11 accommodating the surface acoustic wave element previously accommodates one or more surface acoustic wave elements 10. There is a problem that it is not suitable for mass production because it is prepared individually.
【０００５】それに対して、セラミックパッケージや金
属製カバーを使用せず、樹脂封止により製造工程を簡易
化し、生産性を上げるために、例えば特開平１０―３２
１６６６号公報には、安価な絶縁樹脂等で表面弾性波素
子等の圧電素子全体を封止するという方法が記載されて
いる。On the other hand, in order to simplify the manufacturing process and increase the productivity by resin sealing without using a ceramic package or a metal cover, for example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Publication No. 1666 discloses a method of sealing the entire piezoelectric element such as a surface acoustic wave element with an inexpensive insulating resin or the like.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、圧電素
子全体を樹脂で封止した場合、圧電素子に対する応力に
よる特性劣化や圧電素子の電気的接合部の破損や、封止
樹脂の圧電素子界面にクラックが発生するという課題が
あった。また、上記課題を解決するために、封止樹脂に
低弾性率の樹脂を用いると、機械的強度に劣り、製造時
には、ダイシングソーによる切断性に劣るという課題が
あった。However, when the entire piezoelectric element is sealed with a resin, deterioration of characteristics due to stress on the piezoelectric element, breakage of an electrical joint of the piezoelectric element, and cracks at the interface of the sealing resin with the piezoelectric element. There was a problem that occurs. In addition, when a resin having a low elastic modulus is used as the sealing resin to solve the above-mentioned problem, there is a problem that the mechanical strength is inferior, and the cutting property with a dicing saw is inferior in manufacturing.
【０００７】本発明はかかる課題を解消するためになさ
れたもので、圧電素子に対する応力による特性劣化や圧
電素子との接合部の破損や、封止樹脂の圧電素子界面に
クラックが発生することを防止し、かつ機械的強度の低
下が防止された圧電素子デバイスを得ることを目的とす
る。また、ダイシングソーによる切断性が向上すること
により、生産性の向上した圧電素子デバイスの製造方法
を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is intended to prevent deterioration of characteristics due to stress on a piezoelectric element, breakage of a joint with the piezoelectric element, and generation of cracks at the interface of the sealing resin with the piezoelectric element. It is an object of the present invention to obtain a piezoelectric element device in which a reduction in mechanical strength is prevented. Another object of the present invention is to obtain a method for manufacturing a piezoelectric element device with improved productivity by improving the cutting performance of a dicing saw.
【０００８】[0008]
【課題を解決するための手段】本発明に係る第１の圧電
素子デバイスの製造方法は、配線基板に圧電素子を実装
し、上記圧電素子を樹脂封止した圧電素子デバイスの製
造方法であって、上記配線基板に、圧電素子をフリップ
チップ実装する工程、上記圧電素子を囲むように第１の
樹脂からなる枠部を上記配線基板に設ける工程、上記枠
部で囲まれた領域に上記第１の樹脂より低い弾性率を有
する第２の樹脂を充填し、上記圧電素子を樹脂封止する
工程、並びにダイシングソーにより樹脂パッケージ毎に
上記枠部を切断する工程を備えた方法である。A first method of manufacturing a piezoelectric element device according to the present invention is a method of manufacturing a piezoelectric element device in which a piezoelectric element is mounted on a wiring board and the piezoelectric element is sealed with a resin. A step of flip-chip mounting a piezoelectric element on the wiring board, a step of providing a frame made of a first resin on the wiring board so as to surround the piezoelectric element, and a step of forming a first frame in a region surrounded by the frame. A step of filling a second resin having a lower elastic modulus than the above resin, sealing the piezoelectric element with a resin, and cutting the frame portion for each resin package with a dicing saw.
【０００９】本発明に係る第２の圧電素子デバイスの製
造方法は、上記第１の圧電素子デバイスの製造方法にお
いて、第２の樹脂の硬化物の弾性率が１０〜５００ｋｇ
／ｍｍ２の方法である。According to a second method for manufacturing a piezoelectric element device according to the present invention, in the first method for manufacturing a piezoelectric element device, the cured product of the second resin has an elastic modulus of 10 to 500 kg.
/ Mm 2 .
【００１０】本発明に係る第３の圧電素子デバイスの製
造方法は、上記第１または第２の圧電素子デバイスの製
造方法において、圧電素子が表面弾性波素子であり、表
面弾性波素子の機能面を配線基板側にしてフリップチッ
プ実装し、表面弾性波素子と配線基板間に空間が形成さ
れるようにする方法である。A third method for manufacturing a piezoelectric element device according to the present invention is the method according to the first or second piezoelectric element device, wherein the piezoelectric element is a surface acoustic wave element, and the functional surface of the surface acoustic wave element is Is mounted on the wiring board side by flip-chip mounting so that a space is formed between the surface acoustic wave element and the wiring board.
【００１１】[0011]
【発明の実施の形態】以下、本発明を、圧電素子として
表面弾性波素子を用い、表面弾性波素子デバイスを製造
する場合を説明するが、本発明はこれに限定されるもの
ではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described for a case where a surface acoustic wave device is manufactured using a surface acoustic wave device as a piezoelectric element, but the present invention is not limited to this.
【００１２】実施の形態１．図１（ａ）〜（ｆ）は本発
明の第１の実施の形態の圧電素子デバイス（表面弾性波
素子デバイス）の製造方法を工程順に示す工程図で、図
中、１は圧電体基板（チップ）であり、この圧電体基板
１の一方の主面（図において下面）には圧電体基板１表
面の所定方向に励振される表面波の伝搬路となる、すだ
れ状電極（Ｉｎｔｅｒｄｉｇｉｔａｌ Ｔｒａｎｓｄｕ
ｃｅｒ、以下ＩＤＴと称する）によって形成された励振
電極２とこの励振電極２から延設されて機能部の外部へ
の接続端子となる電極パッド（図示せず）とが形成さ
れ、以上により表面弾性波素子１０を構成する。３は第
１の樹脂（高剛性樹脂）により形成された枠部、４は例
えば金製のバンプ、５は第１の樹脂より低い弾性率を有
する第２の樹脂（低弾性率樹脂）からなる封止樹脂、６
は基板、７は基板６に形成された配線電極で、基板６と
配線電極７により配線基板２０を構成する。５０はダイ
シングにより切断される位置である。Embodiment 1 FIGS. 1A to 1F are process diagrams showing a method of manufacturing a piezoelectric element device (surface acoustic wave device device) according to a first embodiment of the present invention in the order of steps. Chip), and on one main surface (lower surface in the figure) of the piezoelectric substrate 1, there is provided an interdigital transducer, which serves as a propagation path of a surface wave excited in a predetermined direction on the surface of the piezoelectric substrate 1.
and an electrode pad (not shown) extending from the excitation electrode 2 and serving as a connection terminal to the outside of the functional unit. The wave element 10 is constituted. Reference numeral 3 denotes a frame portion formed of a first resin (high-rigidity resin), 4 denotes a bump made of, for example, gold, and 5 denotes a second resin (low-elasticity resin) having a lower elastic modulus than the first resin. Sealing resin, 6
Denotes a substrate, and 7 denotes a wiring electrode formed on the substrate 6. The substrate 6 and the wiring electrode 7 constitute a wiring substrate 20. Reference numeral 50 denotes a position to be cut by dicing.
【００１３】まず、１つの平板基板６上に複数組の配線
電極７を設けて配線基板２０を得る｛図１（ａ）｝。本
実施の形態において、平板状配線基板の材質は、ガラス
基材エポキシ樹脂基板などの有機系基板材料や、アルミ
ナなどのセラミック基板が用いられ、製造工程の自由度
を向上させる事ができる。First, a plurality of sets of wiring electrodes 7 are provided on one flat substrate 6 to obtain a wiring substrate 20 (FIG. 1A). In the present embodiment, as the material of the flat wiring substrate, an organic substrate material such as a glass base epoxy resin substrate or a ceramic substrate such as alumina is used, and the degree of freedom of the manufacturing process can be improved.
【００１４】予めバンプ４が形成された表面弾性波素子
１０を、バンプ４が設けられた面と平板状基板６の配線
電極７が向かい合うようにしてそれぞれ接続する｛図１
（ｂ）｝。本実施の形態において、表面弾性波素子１０
と配線電極７との接続をバンプ４で構成したが、電気的
な接続ができる手段であればその他、導電性樹脂のエス
トラマパッド、半田ペーストもしくはシルバーペースト
を利用することができる。The surface acoustic wave devices 10 on which the bumps 4 are formed in advance are connected so that the surface on which the bumps 4 are provided and the wiring electrodes 7 of the flat substrate 6 face each other.
(B)｝. In the present embodiment, the surface acoustic wave device 10
Although the connection between the electrode and the wiring electrode 7 is made up of the bumps 4, any other means capable of making an electrical connection may be used, such as an elastomer pad of conductive resin, a solder paste or a silver paste.
【００１５】そして、表面弾性波素子１０の周囲を囲う
様に、例えばメタルマスクを用いたスクリーン印刷また
はディスペンス法により、第１の樹脂（高剛性樹脂）を
配置して枠部３を形成する｛図１（ｃ）｝。その際、枠
部３の高さは表面弾性波素子１０より高いと、機械的に
脆い圧電基板１が表面に露出しないためハンドリング性
が良好となる。第１の樹脂としては、硬化物の弾性率が
６００ｋｇ／ｍｍ２以上であると、得られた圧電素子デ
バイスの機械強度が高く、また第１の樹脂からなる枠部
３での切断が容易となり望ましい。また、硬化前のペー
スト特性として、粘度または揺変性の高い樹脂が所望の
形状に保持しやすいため望ましい。上記のように第１の
樹脂を配置後、例えばオーブン内で硬化させるが、完全
に硬化させる必要はなく、所望の形状を保持できる程度
に硬化させてもよい。Then, the first resin (high-rigidity resin) is arranged so as to surround the surface acoustic wave element 10 by, for example, screen printing or dispensing using a metal mask, thereby forming the frame portion 3. FIG. 1 (c)｝. At this time, if the height of the frame portion 3 is higher than the surface acoustic wave element 10, the mechanically fragile piezoelectric substrate 1 is not exposed on the surface, so that the handleability is improved. When the elastic modulus of the cured product of the first resin is 600 kg / mm 2 or more, the mechanical strength of the obtained piezoelectric element device is high, and the cutting at the frame 3 made of the first resin becomes easy. desirable. Further, as a paste characteristic before curing, a resin having high viscosity or thixotropic property is desirable because it is easy to maintain a desired shape. After disposing the first resin as described above, the first resin is cured, for example, in an oven. However, it is not necessary to completely cure the first resin, and the first resin may be cured to such an extent that a desired shape can be maintained.
【００１６】その後、上記第１の樹脂より低い弾性率の
第２の樹脂（低弾性率樹脂）からなる封止樹脂５で表面
弾性波素子１０の圧電体基板１の機能領域の裏面と側面
から平板状基板６にかけてを覆い硬化することで表面弾
性波素子１０を樹脂封止する｛図１（ｄ）｝。第２の樹
脂の供給はスクリーン印刷法、ディスペンス法またはポ
ッティング法により行われるが、量産性の面ではスクリ
ーン印刷法が好ましい。Thereafter, the sealing resin 5 made of a second resin (low elastic modulus resin) having an elastic modulus lower than that of the first resin is applied to the surface acoustic wave element 10 from the back and side surfaces of the functional area of the piezoelectric substrate 1. The surface acoustic wave element 10 is sealed with a resin by covering and curing the flat substrate 6 (FIG. 1D). The supply of the second resin is performed by a screen printing method, a dispensing method, or a potting method, but the screen printing method is preferable in terms of mass productivity.
【００１７】樹脂封止の後、枠部３をダイシングソーに
よりダイシング位置５０で切断して｛図１（ｅ）｝、樹
脂パッケージ毎に切り離して表面弾性波素子デバイスを
得る｛図１（ｆ）｝が、比較的高剛性である第１の樹脂
からなる枠部３を切断するため、ダイシング性に優れ生
産速度が向上する。なお、図１（ｅ）は、切断前、隣り
合った表面弾性波素子デバイスはスルーホールを共用
し、そのスルーホール部で切断する場合を示す。この場
合、ダイシングラインを共用しているので一度の切断で
隣り合った表面弾性波素子デバイスを分離できダイシン
グ工程が簡素化され、プロセスコスト低減の効果があ
る。しかし、上記のようにダイシングラインをスルーホ
ール部等に精度よく設定する必要があり、ダイシング精
度が要求される。従って、切断前隣り合った表面弾性波
素子デバイス間に余白領域を設けて各表面弾性波素子デ
バイス毎にダイシングする方法を採用しても良い。After resin sealing, the frame portion 3 is cut at a dicing position 50 by a dicing saw {FIG. 1 (e)}, and cut into individual resin packages to obtain a surface acoustic wave device {FIG. 1 (f)]. ｝ Cuts the frame portion 3 made of the first resin having relatively high rigidity, so that the dicing property is excellent and the production speed is improved. FIG. 1E shows a case where adjacent surface acoustic wave device devices share a through hole before cutting, and cut at the through hole portion. In this case, since the dicing line is shared, adjacent surface acoustic wave device devices can be separated by one cut, so that the dicing process is simplified and the process cost is reduced. However, as described above, it is necessary to set the dicing line in the through-hole portion or the like with high accuracy, and dicing accuracy is required. Therefore, a method of providing a blank area between adjacent surface acoustic wave device devices before cutting and dicing each surface acoustic wave device device may be adopted.
【００１８】上記のようにして得られる図１（ｆ）に示
される表面弾性波素子デバイスは、平板状基板６とこれ
に設けた配線電極部７とからなる配線基板２０に表面弾
性波素子１０を実装したものである。表面弾性波素子１
０表面の励振電極２から延設される電極パッドに形成さ
れたバンプ４と上記配線電極７とがフリップチップ方式
で接続され、表面弾性波素子１０の周囲を囲う様に、第
１の樹脂からなる枠部３が形成され、枠部３で囲まれた
領域が上記第１の樹脂より低い弾性率を有する第２の樹
脂からなる封止樹脂により充填されることにより、表面
弾性波素子１０が封止されたもので、励起電極２と基板
６の間を中空状態に保持する。The surface acoustic wave device device shown in FIG. 1 (f) obtained as described above has a surface acoustic wave device 10 on a wiring board 20 comprising a flat substrate 6 and a wiring electrode portion 7 provided thereon. Is implemented. Surface acoustic wave device 1
The bump 4 formed on the electrode pad extending from the excitation electrode 2 on the surface 0 and the wiring electrode 7 are connected in a flip-chip manner, and the first resin is formed so as to surround the surface acoustic wave element 10. The surface acoustic wave element 10 is formed by forming a frame portion 3 formed by filling a region surrounded by the frame portion 3 with a sealing resin made of a second resin having a lower elastic modulus than the first resin. It is sealed and holds the space between the excitation electrode 2 and the substrate 6 in a hollow state.
【００１９】即ち、本実施の形態において、表面弾性波
素子１０を枠部３を形成する第１の樹脂より低い弾性率
を有する第２の樹脂（低弾性率樹脂）で封止しているの
は、表面弾性波素子１０への応力を緩和するためであ
る。また、弾性率が低いために、機械的強度に劣ること
を防止するために、表面弾性波素子１０の周囲を囲む様
に、第１の樹脂（高剛性樹脂）により枠部３を配置した
ものである。従って、本実施の形態により、高価なセラ
ミックや金属を用いず、安価なエポキシ樹脂などの材料
で樹脂封止したものでも、ヒートサイクル等による電気
特性の劣化を防止し、かつ機械的強度の低下が防止され
た圧電素子デバイスを得ることができる。また、ダイシ
ングは比較的高剛性の第１の樹脂からなる枠部３を切断
するので、生産性が向上する。That is, in this embodiment, the surface acoustic wave device 10 is sealed with a second resin (low elastic modulus resin) having a lower elastic modulus than the first resin forming the frame portion 3. This is for relaxing the stress on the surface acoustic wave device 10. Further, in order to prevent the mechanical strength from being inferior due to the low elastic modulus, the frame portion 3 is arranged by a first resin (high rigid resin) so as to surround the surface acoustic wave element 10. It is. Therefore, according to the present embodiment, even if the resin is sealed with a material such as an inexpensive epoxy resin without using expensive ceramics and metals, deterioration of electrical characteristics due to heat cycles and the like can be prevented, and mechanical strength can be reduced. Can be obtained. In addition, since the dicing cuts the frame 3 made of the first resin having relatively high rigidity, the productivity is improved.
【００２０】本実施の形態において、上記第２の樹脂と
して、表１に示す各弾性率（ｋｇ／ｍｍ２）を有する樹
脂を用いて、上記製造方法により表面弾性波素子１０を
樹脂封止した表面弾性波素子デバイスを製造し、下記試
験を施した。In the present embodiment, the surface acoustic wave device 10 is resin-sealed by the above-described manufacturing method using a resin having each elastic modulus (kg / mm 2 ) shown in Table 1 as the second resin. A surface acoustic wave device was manufactured and subjected to the following tests.
【００２１】[0021]
【表１】 [Table 1]
【００２２】なお、表中、ヒートサイクル試験は、−４
０℃―８５℃間のヒートサイクルを行い、上記表面弾性
波素子デバイスの電気特性が５％以上劣化するまでのヒ
ートサイクル回数を測定することにより行う。表中、耐
湿試験は、８５℃で８５％ＲＨの雰囲気中に放置し、上
記表面弾性波素子デバイスの電気特性が５％以上劣化す
るまでのヒートサイクル回数を測定することにより行
う。表中、吸湿リフロー試験とは、吸湿リフロー試験
（ＪＥＤＥＣ Ｌｅｂｅｌ―３）を施し、２６０℃リフ
ローを３回施した後、電気特性が５％以上劣化したもの
をＮＧ、電気特性の劣化が５％未満のものをＯＫとす
る。表中、衝撃試験は、衝撃試験機で５００〜５０００
Ｈｚの正弦パルス（加速度１０００Ｇ）を０．５ｍｓｅ
ｃ印加した後、電気特性が５％以上劣化したものをＮ
Ｇ、電気特性の劣化が５％未満のものをＯＫとする。In the table, the heat cycle test was -4.
The heat cycle is performed between 0 ° C. and 85 ° C., and the number of heat cycles until the electrical characteristics of the surface acoustic wave device degrades by 5% or more is measured. In the table, the moisture resistance test is performed by leaving the device in an atmosphere of 85% RH at 85 ° C. and measuring the number of heat cycles until the electrical characteristics of the surface acoustic wave device degrades by 5% or more. In the table, the moisture absorption reflow test means that when the moisture absorption reflow test (JEDEC Level-3) is performed, the reflow is performed at 260 ° C. three times, and the electrical characteristics are degraded by 5% or more, NG, and the electrical characteristics are degraded by 5% Those less than are OK. In the table, the impact test was performed using an impact tester at 500 to 5000.
Hz sine pulse (acceleration 1000G) for 0.5mse
c, after the electric characteristics have been deteriorated by 5% or more,
G: If the deterioration of the electrical characteristics is less than 5%, it is OK.
【００２３】表１からわかるように、第２の樹脂の弾性
率が８００ｋｇ／ｍｍ２であると、ヒートサイクルが重
なると、封止樹脂に起因する熱応力が大きくなり、ヒー
トサイクルやリフロー試験において、表面弾性波素子お
よび素子と基板との接合部にダメージが生じて電気特性
が劣化したり、封止樹脂と表面波素子間および封止樹脂
と配線基板の界面で剥離や樹脂クラックが生じやすくな
る。一方、弾性率が、１０ｋｇ／ｍｍ2未満の場合、表
面弾性波素子に与える応力・歪みは小さいものの、機械
的強度が低くなるために、例えば、取り扱いにおいて、
不具合を起こしやすく、また衝撃試験では樹脂の変形が
大きくなり、素子および基板との接合部にダメージが生
じやすくなる。以上のように、弾性率が１０〜５００ｋ
ｇ／ｍｍ２であるのが好ましいのがわかる。As can be seen from Table 1, when the elastic modulus of the second resin is 800 kg / mm 2 , when the heat cycle is overlapped, the thermal stress caused by the sealing resin increases, and in the heat cycle and the reflow test, The surface acoustic wave element and the junction between the element and the substrate are damaged, and the electrical characteristics are deteriorated, and peeling and resin cracks are easily generated between the sealing resin and the surface acoustic wave element and at the interface between the sealing resin and the wiring board. Become. On the other hand, when the elastic modulus is less than 10 kg / mm 2, although the stress / strain applied to the surface acoustic wave element is small, the mechanical strength is low.
Failures are likely to occur, and in the impact test, the resin is greatly deformed, and the junction between the element and the substrate is likely to be damaged. As described above, the elastic modulus is 10 to 500 k
g / mm 2 is preferred.
【００２４】なお、本実施の形態では、圧電素子として
表面弾性波素子を載置する装置について述べたが、その
他マイクロウエーブ整合素子、インピーダンス整合素子
を載置する装置にも利用できる。In this embodiment, an apparatus for mounting a surface acoustic wave element as a piezoelectric element has been described. However, the present invention can also be applied to an apparatus for mounting a microwave matching element and an impedance matching element.
【００２５】実施の形態２．図２（ａ）〜（ｆ）は本発
明の第２の実施の形態の圧電素子デバイスの製造方法を
工程順に示す工程図であり、実施の形態１において、第
２の樹脂（低弾性率樹脂）からなる封止樹脂５で表面弾
性波素子１０を封止する際に、圧電体基板１の機能領域
の裏面は覆わず、側面から平板状基板６にわたって覆い
硬化する｛図２（ｄ）｝他は実施の形態１と同様にして
表面弾性波素子デバイスを得る｛図２（ｆ）｝。したが
って、上記実施の形態１に対して、表面弾性波素子１の
裏面にエポキシ樹脂などの材料で樹脂封止する必要がな
く、封止材料の節約ができる。また、表面弾性波素子１
の裏面と封止用樹脂８間に亀裂が生じることも防止する
ことができる。即ち、本実施の形態のように構成すれ
ば、所定の機械的強度を得ると共に、装置の低背化と材
料費の低減による低コスト化が可能になる。Embodiment 2 FIGS. 2A to 2F are process diagrams showing a method of manufacturing a piezoelectric element device according to a second embodiment of the present invention in the order of steps. In the first embodiment, a second resin (low elastic modulus resin) is used. When the surface acoustic wave device 10 is sealed with the sealing resin 5 made of (1), the back surface of the functional region of the piezoelectric substrate 1 is not covered, but is covered and hardened over the side surface of the flat substrate 6 {FIG. 2 (d)}. Otherwise, a surface acoustic wave device is obtained in the same manner as in the first embodiment {FIG. 2 (f)}. Therefore, unlike the first embodiment, it is not necessary to seal the back surface of the surface acoustic wave element 1 with a material such as an epoxy resin, so that the sealing material can be saved. Also, the surface acoustic wave device 1
Cracking between the back surface of the substrate and the sealing resin 8 can also be prevented. That is, with the configuration as in the present embodiment, it is possible to obtain a predetermined mechanical strength and to reduce the cost by reducing the height of the apparatus and the material cost.
【００２６】[0026]
【発明の効果】本発明の第１の圧電素子デバイスの製造
方法は、配線基板に圧電素子を実装し、上記圧電素子を
樹脂封止した圧電素子デバイスの製造方法であって、上
記配線基板に、圧電素子をフリップチップ実装する工
程、上記圧電素子を囲むように第１の樹脂からなる枠部
を上記配線基板に設ける工程、上記枠部で囲まれた領域
に上記第１の樹脂より低い弾性率を有する第２の樹脂を
充填し、上記圧電素子を樹脂封止する工程、並びにダイ
シングソーにより樹脂パッケージ毎に上記枠部を切断す
る工程を備えた方法で、生産性が向上し、電気特性の劣
化と機械的強度の低下が防止されるという効果がある。The first method of manufacturing a piezoelectric device according to the present invention is a method of manufacturing a piezoelectric device in which a piezoelectric element is mounted on a wiring board and the piezoelectric element is sealed with a resin. A step of flip-chip mounting the piezoelectric element, a step of providing a frame portion made of a first resin on the wiring substrate so as to surround the piezoelectric element, and an elasticity lower than that of the first resin in a region surrounded by the frame portion. The method includes a step of filling the second resin having a specific ratio and sealing the piezoelectric element with a resin, and a step of cutting the frame portion for each resin package with a dicing saw, thereby improving the productivity and improving the electrical characteristics. This has the effect of preventing deterioration of mechanical strength and reduction of mechanical strength.
【００２７】本発明の第２の圧電素子デバイスの製造方
法は、上記第１の圧電素子デバイスの製造方法におい
て、第２の樹脂の硬化物の弾性率が１０〜５００ｋｇ／
ｍｍ２の方法で、生産性が向上し、電気特性の劣化と機
械的強度の低下が防止されるという効果がある。According to a second method for manufacturing a piezoelectric element device of the present invention, in the first method for manufacturing a piezoelectric element device, the cured product of the second resin has an elastic modulus of 10 to 500 kg / kg.
With the method of mm 2 , there is an effect that the productivity is improved, and the deterioration of the electric characteristics and the decrease in the mechanical strength are prevented.
【００２８】本発明の第３の圧電素子デバイスの製造方
法は、上記第１または第２の圧電素子デバイスの製造方
法において、圧電素子が表面弾性波素子であり、表面弾
性波素子の機能面を配線基板側にしてフリップチップ実
装し、表面弾性波素子と配線基板間に空間が形成される
ようにする方法で、生産性が向上し、電気特性の劣化と
機械的強度の低下が防止された表面弾性波素子デバイス
を得るという効果がある。According to a third method of manufacturing a piezoelectric element device of the present invention, in the first or second method of manufacturing a piezoelectric element device, the piezoelectric element is a surface acoustic wave element, and the functional surface of the surface acoustic wave element is changed. A method of flip-chip mounting on the wiring board side so that a space is formed between the surface acoustic wave element and the wiring board, thereby improving productivity, preventing deterioration of electrical characteristics and reduction of mechanical strength. There is an effect of obtaining a surface acoustic wave device.
【図１】 本発明の第１の実施の形態の圧電素子デバイ
スの製造方法を工程順に示す工程図である。FIG. 1 is a process chart showing a method of manufacturing a piezoelectric element device according to a first embodiment of the present invention in the order of steps.
【図２】 本発明の第２の実施の形態の圧電素子デバイ
スの製造方法を工程順に示す工程図である。FIG. 2 is a process chart showing a method of manufacturing a piezoelectric element device according to a second embodiment of the present invention in the order of steps.
【図３】 従来の表面弾性波素子デバイスを示す断面図
である。FIG. 3 is a cross-sectional view showing a conventional surface acoustic wave device.
１ 圧電体基板、２ 励振電極、１０ 表面弾性波素
子、３ 枠部（第１の樹脂）、４ バンプ、５ 封止樹
脂（第２の樹脂）、６ 基板、７ 配線電極、２０ 配
線基板、５０ ダイシングにより切断される位置。REFERENCE SIGNS LIST 1 piezoelectric substrate, 2 excitation electrode, 10 surface acoustic wave element, 3 frame portion (first resin), 4 bump, 5 sealing resin (second resin), 6 substrate, 7 wiring electrode, 20 wiring substrate, 50 Position to be cut by dicing.
フロントページの続き Ｆターム(参考） 5F061 AA01 BA03 CA04 CA06 CA12 CB13 FA06 5J097 AA25 AA31 AA34 HA04 HA07 HA08 HB07 HB08 JJ03 JJ09 KK10 Continued on the front page F term (reference) 5F061 AA01 BA03 CA04 CA06 CA12 CB13 FA06 5J097 AA25 AA31 AA34 HA04 HA07 HA08 HB07 HB08 JJ03 JJ09 KK10
Claims (3)
素子を樹脂封止した圧電素子デバイスの製造方法であっ
て、上記配線基板に、圧電素子をフリップチップ実装す
る工程、上記圧電素子を囲むように第１の樹脂からなる
枠部を上記配線基板に設ける工程、上記枠部で囲まれた
領域に上記第１の樹脂より低い弾性率を有する第２の樹
脂を充填し、上記圧電素子を樹脂封止する工程、並びに
ダイシングソーにより樹脂パッケージ毎に上記枠部を切
断する工程を備えた圧電素子デバイスの製造方法。1. A method of manufacturing a piezoelectric element device in which a piezoelectric element is mounted on a wiring board and the piezoelectric element is sealed with a resin, wherein a step of flip-chip mounting the piezoelectric element on the wiring board is provided. Providing a frame portion made of a first resin so as to surround the wiring substrate; filling a region surrounded by the frame portion with a second resin having a lower elastic modulus than the first resin; And a step of cutting the frame portion for each resin package with a dicing saw.
００ｋｇ／ｍｍ２であることを特徴とする請求項１に記
載の圧電素子デバイスの製造方法。2. The cured product of the second resin has an elastic modulus of 10 to 5
Method for manufacturing a piezoelectric element device according to claim 1, characterized in that a 00kg / mm 2.
弾性波素子の機能面を配線基板側にしてフリップチップ
実装し、表面弾性波素子と配線基板間に空間が形成され
るようにすることを特徴とする請求項１または請求項２
に記載の圧電素子デバイスの製造方法。3. The piezoelectric element is a surface acoustic wave element, and flip chip mounting is performed with the functional surface of the surface acoustic wave element facing the wiring board so that a space is formed between the surface acoustic wave element and the wiring board. 3. The method according to claim 1, wherein
3. The method for manufacturing a piezoelectric element device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001160714A JP2002353763A (en) | 2001-05-29 | 2001-05-29 | Method for manufacturing piezoelectric element device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001160714A JP2002353763A (en) | 2001-05-29 | 2001-05-29 | Method for manufacturing piezoelectric element device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1569276A1 (en) * | 2004-02-27 | 2005-08-31 | Heptagon OY | Micro-optics on optoelectronics |
| EP1473776A3 (en) * | 2003-04-28 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
| WO2006123478A1 (en) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
| US7247509B2 (en) | 2003-09-03 | 2007-07-24 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing solid-state imaging devices |
| JP2010147453A (en) * | 2008-12-19 | 2010-07-01 | Samsung Electro-Mechanics Co Ltd | Manufacturing method of wafer level package |
| CN112335179A (en) * | 2018-07-30 | 2021-02-05 | 京瓷株式会社 | Composite substrate |
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2001
- 2001-05-29 JP JP2001160714A patent/JP2002353763A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1473776A3 (en) * | 2003-04-28 | 2006-04-05 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
| US7273765B2 (en) | 2003-04-28 | 2007-09-25 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
| US7247509B2 (en) | 2003-09-03 | 2007-07-24 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing solid-state imaging devices |
| EP1569276A1 (en) * | 2004-02-27 | 2005-08-31 | Heptagon OY | Micro-optics on optoelectronics |
| US7457490B2 (en) | 2004-02-27 | 2008-11-25 | Heptagon Oy | Micro-optics on optoelectronics |
| WO2006123478A1 (en) * | 2005-05-17 | 2006-11-23 | Matsushita Electric Industrial Co., Ltd. | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
| US7875496B2 (en) | 2005-05-17 | 2011-01-25 | Panasonic Corporation | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
| JP2010147453A (en) * | 2008-12-19 | 2010-07-01 | Samsung Electro-Mechanics Co Ltd | Manufacturing method of wafer level package |
| CN112335179A (en) * | 2018-07-30 | 2021-02-05 | 京瓷株式会社 | Composite substrate |
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