JP2002359321A - Power amplifying module, circuit element aggregate substrate and method for regulating circuit element characteristics - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small-sized power amplifying module. SOLUTION: An impedance matching circuit 211 or 215 has capacitors C1 to C6, and is connected to an input side or an output side of an MMIC 20. A multilayer substrate 7 has a dielectric layer 72 or 73 and supports the MMIC 20 and the matching circuit 211 or 215. At least, one of the capacitors C1 to C6 included in the matching circuit 211 or 215 is constituted of a pair of capacitor electrodes disposed on both surfaces of the layer 72 or 73.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier module mainly used for a transmission circuit section, a circuit element assembly substrate used for manufacturing the same, and a method of adjusting circuit element characteristics in communication equipment utilizing a microwave band. About.

[0002]

2. Description of the Related Art In recent years, with the spread of digital mobile communication devices such as portable telephones, demand for a power amplification module used for a transmitter in a microwave band has been increased. The power amplification module is a component of mobile communication devices. In recent years, demands for low voltage operation, high efficiency, and light weight have been increasing along with the miniaturization and high functionality of communication devices, particularly mobile phones. I have.

In a digital mobile communication device, a signal received by an antenna is transmitted to a low noise amplifier, supplied from the low noise amplifier to a mixer, modulated, and further transmitted to a baseband through an IF. . The transmission signal generated in the baseband unit is modulated by the mixer unit, transmitted to the power amplification module, and the signal amplified by the power amplification module is converted into a duplexer (Dupl).
exer) and transmitted to the transmitting antenna. The power amplification module amplifies a signal supplied from the mixer unit to a required power level. The signal output from the power amplification module is supplied to the non-reciprocal circuit unit.

A signal output from the non-reciprocal circuit section normally passes through a power detection section, and the power level is detected. Then, automatic power control (AP) is performed so that the power transmitted from the power control unit to the power amplification module is always constant.
C, Auto Power Contro1) is added. For this reason, the output signal from the power amplification module may increase more than necessary,
It is constantly controlled at the required power level without diminishing below the need. The high-order harmonic component of the signal that has passed through the power detection unit is removed by a low-pass filter, transmitted to a duplexer, and further transmitted to a transmission antenna.

As a general configuration, a power amplification module includes an input impedance matching circuit, an MMIC (Microwav
e Monolithic IC), DC bias circuit and output impedance matching circuit. The MMIC forms an amplification circuit, and the DC bias circuit applies a DC bias to the MMIC.

[0006] The input impedance matching circuit is composed of an LC circuit composed of a capacitor and an inductor.
, And impedance matching between the MMIC and the circuit on the input side.

[0007] The output impedance matching circuit is composed of an LC circuit composed of a capacitor and an inductor.
To provide impedance matching between the MMIC and the load.

An input impedance matching circuit, an MMIC,
DC bias circuit and output impedance matching circuit,
It is supported by a multilayer substrate. In the input impedance matching circuit, for example, one ground capacitor is used, and in the output impedance matching circuit, for example, three ground capacitors are used.

A ground capacitor used in an input impedance matching circuit and an output impedance matching circuit has a large capacitance. Therefore, conventionally, a multilayer ceramic capacitor has been used and mounted on the surface of a multilayer substrate.

A digital mobile communication device such as a cellular phone using this type of power amplification module is a high-density integrated device, and the occupied space allowed for the power amplification module is extremely small and will be further reduced in the future. Is inevitable. Therefore, the power amplification module must have a particularly small planar shape.

However, the surface of the multi-layer substrate already has M
An MIC and the like are mounted, and further, an inductor of an input impedance matching circuit, an inductor of an output impedance matching circuit, a capacitor of a DC bias circuit, an input / output coupling capacitor, and the like are mounted.

For this reason, in the conventional structure in which a multilayer ceramic capacitor is used as the ground capacitor of the input / output impedance matching circuit and mounted on the surface of the multilayer substrate, it is difficult to reduce the plane area of the surface of the multilayer substrate. ,
It is becoming impossible to meet the demand for miniaturization.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a small power amplifier module.

Another object of the present invention is to provide a circuit element assembly board suitable for manufacturing the power amplification module described above.

Still another object of the present invention is to provide a circuit element characteristic adjusting method suitable for adjusting characteristics of individual circuit paths included in the circuit element assembly board described above.

[0016]

In order to solve the above-mentioned problems, a power amplification module according to the present invention comprises an MMIC (M
icrowave Monolithic IC), impedance matching circuit, and multilayer substrate. The MMIC constitutes an amplifier circuit. The impedance matching circuit includes a capacitor, and is connected to at least one of an input side and an output side of the MMIC.

The multi-layer substrate includes a dielectric layer,
The MIC and the impedance matching circuit are supported. At least one of the capacitors included in the impedance matching circuit is constituted by a pair of capacitor electrodes disposed on both surfaces of the dielectric layer.

In the power amplification module according to the present invention, the MMIC constitutes an amplification circuit, and an impedance matching circuit connected to an input side or an output side of the MMIC performs impedance matching between the MMIC and the load. Therefore, the signal input to the MMIC and the MMIC
Signal transmission from the load to the load can be performed with high efficiency.

The MMIC and the impedance matching circuit are supported by a multilayer substrate.
A power amplification module in which the MIC and the impedance matching circuit are integrated can be obtained.

[0020] The multilayer substrate includes a dielectric layer. At least one of the capacitors included in the impedance matching circuit is constituted by a pair of capacitor electrodes disposed on both surfaces of the dielectric layer. For this reason, the number of circuit elements mounted on the surface of the multilayer substrate can be reduced, and the plane area of the power amplification module can be reduced. Alternatively, it is possible to increase the space for other circuit components to be mounted on the surface of the multilayer substrate.

Next, the present invention discloses a circuit element assembly board suitable for manufacturing the above-described power amplification module. This circuit element assembly substrate includes a dielectric layer, a number of capacitor electrodes, and measurement electrodes.

The capacitor electrodes are provided at opposing positions on both surfaces of the dielectric layer, and are arranged at intervals on the both surfaces.

The measuring electrode includes a first measuring electrode and a second measuring electrode.
And a measuring electrode. The first measurement electrode is provided on one surface of the dielectric layer. The second measurement electrode is provided on the other surface of the dielectric layer, is opposed to the first measurement electrode, and is led out to the one surface of the dielectric layer by a lead conductor penetrating the dielectric layer. ing.

According to the circuit element assembly board described above, the first
A characteristic adjustment method of measuring the capacitance generated between the measurement electrode and the second measurement electrode and determining the trimming amount of the capacitor electrode based on the measured value can be adopted.

That is, since the first and second measurement electrodes are provided on the front surface and the back surface of the dielectric layer, the capacitance generated between the first measurement electrode and the second measurement electrode is measured. The thickness of the dielectric layer can be calculated from the areas of the first and second measurement electrodes and the dielectric constant of the dielectric layer, which are known in advance.

From the calculated thickness of the dielectric layer, the area of the capacitor electrode and the dielectric constant of the dielectric layer which are known in advance, the capacitance obtained by the current electrode area (design value) is calculated and calculated. By trimming the capacitor electrode provided on the surface of the dielectric layer so that the capacitance value becomes equal to the design capacitance value, the capacitance value can be adjusted to a predetermined value.

[0027]

FIG. 1 is a block diagram showing the configuration of a high-frequency circuit section in a digital mobile communication device (compatible with W-CDMA). The signal received by the receiving antenna ANT2 is transmitted to the low noise amplifier AMP, modulated by the mixer MIXR, and sent to the baseband BSB via the IF.

The transmission signal generated by the baseband section BSB is modulated by the mixer section MIXT. Modulation by the mixer MIXT is performed based on a signal supplied from the phase locked loop PLL to the mixer MIXT. After the transmission signal is modulated by the mixer section MIXT, it is supplied to the power amplification section circuit section PWA. The power amplifier circuit unit PWA plays a role of amplifying the transmission signal output from the transmission antenna ANT1 until the power reaches the receiver. The signal amplified by the power amplifier circuit unit PWA is transmitted to the transmitting antenna ANT1 via the duplexer DUP, and is radiated from the transmitting antenna ANT1 into the air.

FIG. 2 is a block diagram showing details of the power amplifier circuit section PWA. Illustrated power amplifier circuit section PW
A is a bandpass filter 1, a power amplification module 2,
It includes a power detection unit 31, a low-pass filter 32, and a non-reciprocal circuit unit 33. From the modulation signal supplied from the mixer section MIXT to the power amplification section circuit section PWA, only necessary frequency components are extracted by the band-pass filter 1,
The power is transmitted to the power amplification module 2. The signal that has passed through the bandpass filter 1 is supplied to the power amplification module 2.

The power amplification module 2 amplifies the signal passing through the band-pass filter 1. The signal output from the power amplification module 2 is supplied to the power detection unit 31. Then, when passing through the power detection unit 31, the power level of the signal is detected. The power detection signal is transmitted to the power control unit 3
4 is supplied. The power control section 34 applies APC control to the power amplification module 2 based on the power detection signal supplied from the power detection section 31 to make the output power constant.

The high-order harmonic component of the signal that has passed through the power detection unit 31 is removed by a low-pass filter 32 and supplied to a nonreciprocal circuit unit 33.

The non-reciprocal circuit section 33 constitutes an isolator, and transmits the signal supplied from the power amplification module 2 to the transmitting antenna ANT1.
The signal returning from the NT1 to the power amplification module 2 is cut. Without the non-reciprocal circuit section 33, when the output-side load impedance changes due to the operating environment or the like, the power amplified by the power amplification module 2 is reflected, returned to the power amplification module 2, and returned from the power amplification module 2. Output signal quality degradation (noise level increase), efficiency degradation,
The internal circuit of the power amplification module 2 may be destroyed. The non-reciprocal circuit section 33 is provided to prevent such a problem due to reflection.

The signal passing through the nonreciprocal circuit section 33 is transmitted to a duplexer DUP, and further transmitted to a transmitting antenna AN.
It is transmitted to T1. Then, a signal is radiated from the transmitting antenna ANT1 into the air.

The examples shown in FIGS. 1 and 2 are compatible with W-CDMA, and the main characteristics required of the power amplification module 2 are as follows.

Frequency (fin) = 1920 to 1980 MHz Output power (Pout) = 27 dBm Power added efficiency (PAE) = 40% or more Adjacent channel leakage power ratio (ACPR) ACPR1 = −38 dBc or less (at 5 MHz) ACPR2 = −48d8c or less (At 10 MHz) The adjacent channel power ratio (ACPR) is 5.0 MHz or 10.0 MHz from the center frequency of the transmission signal.
This is a value representing the noise level at a frequency z away from the power level of the center frequency as a relative ratio. The power added efficiency (PAE) is a ratio of output power to power consumption expressed as a percentage, and a higher value is more preferable.

The power amplifier module 2 is designed so that the above characteristics can be obtained when the output load impedance ZIo is 50Ω. Actually, the state of 50 Ω does not constantly remain, and the value of about 30 to 70 Ω can sufficiently change depending on the angle of the antenna, temperature conditions, and the like. The power amplification module 2 can include a non-reciprocal circuit unit.

FIG. 3 shows a block diagram of the power amplification module 2. In the illustrated embodiment, the power amplification module 2 includes an input impedance matching circuit 211, a previous-stage power amplification element 212, a rear-stage power amplification element 214, an output impedance matching circuit 215, and a DC bias circuit 21.
6 is included. The power amplifier module 2 has additional or additional circuit parts in addition to the power amplifier module 2.

The power amplifying elements 212 and 214 are, for example, HB
It is composed of T (heterojunction bipolar transistor) and FET (field effect transistor).

The DC bias circuit 216 applies a DC bias to the power amplifier 212 based on the DC voltage Vcc supplied to the Vcc terminal and the signal Vreg supplied to the Vreg terminal.

From the Pin terminal connected to the band-pass filter 1 (see FIG. 2), the input impedance matching circuit 2
11, the signal supplied to the power amplification element 212 is
The power is amplified by the power amplification element 212. The signal whose power has been amplified by the power amplifying element 212 is supplied to the power amplifying element 214 and further subjected to a power amplifying operation.

The signal amplified by the power amplifying element 214 is supplied to the Pout terminal via the output impedance matching circuit 215. The output impedance matching circuit 215 converts the output impedance of the MMIC 20 to the input impedance (10 to 30) of the non-reciprocal circuit unit 33.
Ω).

In the circuit shown in FIG. 3, the power amplifying element 212 and the power amplifying element 214 constitute the MMIC 20 packaged in one package. The output impedance of the MMIC 20 is converted into a load impedance of 50Ω by the output impedance matching circuit 215 and the non-reciprocal circuit unit 33.

The input impedance matching circuit 211
The impedance of 50Ω when the side of the bandpass filter 1 (see FIG. 2) is viewed from the in terminal is matched with the input impedance of the MMIC 20.
And an LC circuit including capacitors C1 and C2. The signal supplied to the Pin terminal is ideally input to the MMIC 20 without reflection.

The signal input to the MMIC 20 is amplified to a desired power by the power amplifier 212 and the power amplifier 214.

An output impedance matching circuit 215 provided on the output side of the MMIC 20 includes an L-type circuit including an inductor L2 and a capacitor C3, a π-type circuit including a capacitor C4, an inductor L3 and a capacitor C5, and a DC blocking capacitor C6. Contains.

The DC bias circuit 216 has a function of applying a DC bias for operating the power amplifying elements 212 and 214 and preventing leakage of the amplified power to the outside. Therefore, the inductors L5 and L6 included in the DC bias circuit 216 are ideally required to have an infinite impedance so that the signals amplified by the power amplifying elements 212 and 214 do not leak to the Vcc terminal. For this reason, the inductors L5 and L6 are configured by an inductor element having an impedance corresponding to the (λ / 4) length pattern or the (λ / 4) length pattern with respect to the wavelength λ.

FIG. 4 is a partial cross-sectional view showing an example of the layer configuration of the power amplification module according to the present invention. The illustrated power amplification module includes a multilayer substrate 7 and an MMIC 20. The MMIC 20 includes the power amplification element 212 and the power amplification element 214 as described above (see FIGS. 2 and 3).

The MMIC 20 and the output impedance matching circuit 215 are supported by the multilayer substrate 7, and the multilayer substrate 7 provides a power amplification module in which the MMIC 20 and the output impedance matching circuit 215 are integrated. In the embodiment, the input impedance circuit 211 and the DC bias circuit 216 are also supported by the multilayer substrate 7.

The multilayer substrate 7 has a structure in which dielectric layers 71 to 73, a core layer 74, and dielectric layers 75 to 77 are laminated. These layers 71 to 77 are formed by a sheet laminating method or a coating method.

FIG. 5 is a diagram schematically showing a laminated structure of a multilayer substrate used in the power amplification module shown in FIG.
6 to 13 are diagrams showing patterns on adjacent surfaces of the multilayer substrate 7. FIG. Next, referring to FIG. 5 and FIGS.
The laminated structure of the multilayer substrate 7 will be described in detail.

First, FIG. 6 is a plan view of the dielectric layer 71 constituting the uppermost layer of the multilayer substrate 7 as viewed from the surface. An input impedance matching circuit 211 is provided on the surface of the dielectric layer 71.
And a capacitor C2. The capacitors C7 to C9 of the DC bias circuit 216 and the inductor L4
And the capacitor C6 and the inductors L2 and L3 of the output impedance circuit 215.
Is provided.

FIG. 7 shows the dielectric layer 71 adjacent to the dielectric layer 71.
FIG. 4 is a plan view showing a surface of a second example. The ground pattern GND1 is formed on the dielectric layer 72.

FIG. 8 is a plan view showing the surface of the dielectric layer 73 which is adjacent to the dielectric layer 72. FIG. The dielectric layer 73 includes a capacitor C of the input impedance matching circuit 211.
1 and the capacitor electrodes C31, C41, 51 forming the capacitors C3, C4, C5 of the output impedance circuit 215 are formed.

FIG. 9 is a plan view showing the surface of the core layer 74 which is adjacent to the dielectric layer 73. A ground pattern GND2 is formed on the core layer 74. Core layer 74
Is an organic layer containing glass fibers. Core layer 74
Is a glass fiber-containing core substrate having a thickness of, for example, 160 μm and a relative permittivity εr of about 10.

As described above, the multilayer substrate 7 includes two dielectric layers 72 and 73 adjacent to each other, and the two dielectric layers 72 and 73 are respectively provided on the surface opposite to the adjacent surface to the ground electrode GND1. , GND2. Among the capacitors C3 to C6 included in the output impedance matching circuit 215, the capacitors C3 to C5 whose one ends are grounded are the capacitor electrodes C3 provided on the adjacent surfaces of the dielectric layers 72 and 73.
1, C41, C51, and capacitors Ca1, Ca2, Cb between the capacitor electrodes C31, C41, C51 and the first and second ground electrodes GND1, GND2.
1 and Cb2 (see FIG. 5).

Therefore, in comparison with the related art, the area of the capacitor electrodes C31, C41, C51 and the dielectric layer 7
If the thicknesses of the electrodes 2 and 73 are the same, approximately twice the capacity can be obtained. If the capacities are the same, the capacitor electrodes C31 and C4
1. The plane area of C51 can be halved.

Therefore, the output impedance matching circuit 2
15 are connected to the multilayer substrate 7
And the number of circuit elements mounted on the surface of the multilayer substrate 7 can be reduced, and the plane area of the power amplification module can be reduced. If the plane area of the power amplification module is kept as it is, the space for circuit elements mounted on the surface of the multilayer substrate 7, for example, conductor patterns constituting the inductors L1 to L3 can be increased.

In the embodiment, an input impedance matching circuit 211 (see FIG. 3) is provided on the adjacent surfaces of the dielectric layers 72 and 73.
Electrode C constituting capacitor C1 included in
11 is also provided. The capacitor electrode C11 also faces the ground electrodes GND1 and GND2, so that a large capacitance can be obtained and the plane area of the multilayer substrate 7 can be reduced.

Further, as shown in FIGS. 5 and 8, the capacitor electrode C31 is formed so as to have an area S1 larger than an area required to obtain a required capacitance value, and trimming is performed. Thereby, it is possible to accurately adjust to a predetermined capacitance value. Other capacitor electrode C1
The same applies to 1, C41 and C51.

FIG. 10 is a plan view showing the surface of the dielectric layer 75 which is adjacent to the core layer 74. The dielectric layers 75 include inductors L5 and L6 of the DC bias circuit 216.
Are formed. The other ends of the inductors L5 and L6 are connected to each other and guided to the Vcc terminal.

FIG. 11 is a plan view showing the surface of a dielectric layer 76 adjacent to the dielectric layer 75, and FIG.
FIG. 13 is a plan view showing the surface of the dielectric layer 77 which is adjacent to the dielectric layer 77. FIG. On the back surface of the dielectric layer 77, a ground pattern GND3 is formed.

The dielectric layers 71 to 73 are preferably made of a mixed material obtained by mixing an organic resin material and a dielectric powder. Unlike the core layer 74, the dielectric layers 71 to 73 do not include glass fibers, and are composed of a mixed layer of a selected organic resin material and a dielectric powder. In the dielectric layers 71 to 73, as an example, the dielectric layer 71 located at the uppermost layer
Has a thickness of 40 μm or less, a relative dielectric constant εr of about 3, a middle dielectric layer 72 has a thickness of 40 μm or less, a relative dielectric constant of about 10 and a lowermost dielectric layer 73 has a thickness of It is selected to be 40 μm or less and the relative dielectric constant εr to be about 10. The relative dielectric constant εr can be set to a desired value by selecting the organic resin material and the dielectric powder and controlling their contents.

The dielectric layers 75 to 77 are also preferably made of a mixed material obtained by mixing an organic resin material and a dielectric powder. In the dielectric layers 75 to 77, as an example, the dielectric layer 75 has a thickness of 40 μm or less and a relative dielectric constant εr of about 10, and the intermediate dielectric layer 76 has a thickness of 40 μm or less and a relative dielectric constant εr of The dielectric layer 77 located at the lowermost layer is selected to have a thickness of about 40 μm or less and a relative dielectric constant εr of about 3. The relative permittivity εr can be set to a desired relative value by selecting the organic resin material and the dielectric powder and controlling the contents thereof as in the case of the dielectric layers 71 to 73.

In the case of the above-described embodiment, the overall thickness of the multilayer board 7 is at most 0.5 mm, which can be made thinner than the conventional 0.7 mm.

The dielectric layers 71 to 73 and the dielectric layers 75 to 7
Reference numeral 7 is made of a mixed material in which an organic resin material and a dielectric powder are mixed, and does not include a reinforcing component such as glass fiber. Therefore, the thickness of each layer can be remarkably reduced to 40 μm or less, for example. Dielectric layers 71-73 and dielectric layers 75-7
7 includes a ceramic powder, so that a dielectric ceramic powder having a high dielectric constant can be selected, and excellent electrical characteristics can be secured as compared with the organic resin multilayer substrate 7.

In the case of the embodiment, the dielectric layers 71 to 73, 75
Since No. 77 are made of a mixed material in which an organic resin material and a dielectric powder are mixed, unlike a ceramic multilayer substrate, they do not generate warpage, have high bending strength, and are unlikely to cause breakage, cracking, and the like. Therefore, the thickness can be reduced, and the reliability can be improved.

The multilayer substrate 7 has a core layer 74 which is an organic layer containing glass fibers.
Since the dielectric layers 71 to 73 are adjacent to one surface and the dielectric layers 75 to 77 are adjacent to the other surface of the core layer 74, the thicknesses of the dielectric layers 71 to 73 and the dielectric layers 75 to 77 are reduced. The mechanical strength is ensured by the core layer 74 while the thickness is reduced and the thickness is reduced, so that a highly reliable power amplifier module which is thin and has a large mechanical strength can be obtained as a whole.

For example, taking the bending strength as an example, in the case of a ceramic multilayer substrate, the bending strength is 30 to 40 kg / mm.
² , but the bending strength of the glass epoxy multilayer substrate is 45.
５２52 kg / mm ² . The multilayer substrate according to the present invention,
Since the hybrid dielectric layers 71 to 73 and 75 to 77 in which the organic resin material and the dielectric powder are mixed and the core layer 74 containing the glass fiber are combined, about a middle of the ceramic multilayer substrate and the glass epoxy multilayer substrate. Bending strength can be ensured.

The dielectric powder used to form the dielectric layers 71 to 73 and 75 to 77 has a relative dielectric constant of 5 to 100.
0, and the dielectric loss tangent is 0.00002 to 0.01.
Can be selected from ceramic materials in the range of Specific examples include titanium-barium-neodymium-based ceramics and titanium-barium-tin-based ceramics.

The organic resin material can be appropriately selected from materials having excellent moldability, workability, lamination adhesiveness, and electrical properties. Organic resin material content is 20 ~
It is preferably in the range of 70 vol%. Specific examples of the organic resin material include a thermosetting resin and a thermoplastic resin. More specifically, examples thereof include an epoxy resin, a phenol resin, a low dielectric constant epoxy resin, a polybutadiene resin, and a BT resin. These resins may be used alone or as a mixture of two or more. When two or more kinds are used as a mixture, the mixing ratio is arbitrary.

One preferred example of the organic resin material is a polyvinyl benzyl ether compound. In the laminated structure shown in FIGS. 6 to 13, the dielectric layers 71 to 73 are capacitor forming layers, and preferably have a high dielectric constant and a low dielectric loss tangent. The dielectric layers 75 to 77 are inductor forming layers and preferably have a low dielectric loss tangent. Dielectric layer 75-
77 does not need to have a high dielectric constant, but may have a high dielectric constant in order to shorten the wavelength.

As the organic resin material constituting these layers, a polyvinyl benzyl ether compound can be used. As a polyvinyl benzyl ether compound,
It is preferable to use one having a relative dielectric constant in the range of 2.5 to 3.5 and a dielectric loss tangent in the range of 0.0025 to 0.005.

In this case, when the content of the polyvinyl benzyl ether compound is a (vol%) and the content of the ceramic powder is b (vol%), a + b = 100
(Vol%), 40 (vol%) ≦ b ≦ 60 (v
ol%). According to this mixed material, the relative dielectric constant is 7 to 14, and the dielectric loss tangent is 0.01 to 0.002.
Can be realized.

In the dielectric layers 71 to 73 and 75 to 77, a flame retardant may be further added. Specific examples of the flame retardant include a tetrabromodiphenol A modified polyvinyl benzyl ether compound.

Next, the glass cloth material used for the core layer 74 is mainly composed of SiO _2.
Plays a role in forming the skeleton. The core layer 74 can be configured by using the glass cloth material as a core and impregnating the core with the above-described organic resin material. Examples of glass cloth compositions that can be used are shown below.

<Example of Composition of Glass Cloth> SiO ₂ : 56 vol% MgB ₂ O ₃ : 10 vol% Al ₂ O ₃ : 17 vol% CaO: 17 vol% A flame retardant can also be added to the core layer 74. Specific examples of the flame retardant include the above-mentioned tetrabromodiphenol A-modified polyvinyl benzyl ether compound.

FIG. 14 is a perspective view of a circuit element assembly board suitable for manufacturing the above-described power amplification module, and FIG.
FIG. 16 is a plan view of the circuit element assembly substrate shown in FIG.
FIG. 17 is a partial sectional view taken along line 16-16 of FIG. In the drawings, the same components as those shown in the drawings previously described are denoted by the same reference numerals.

The illustrated circuit element assembly substrate comprises a dielectric layer 73 and a number of capacitor electrodes C11, C31, C4.
1, C51 (see FIGS. 15 and 16) and the measurement electrode 8.

In FIG. 5, the dielectric layer 73 is
A fourth dielectric layer, under which a core layer 74 and a fourth dielectric layer 75 are sequentially laminated. The details of the laminated structure are as described with reference to FIGS. As a finished product of the multilayer substrate, two
Since the fifth dielectric layer 72 and the uppermost dielectric layer 71 are laminated, and the fifth and sixth dielectric layers 76 and 77 are sequentially laminated on the fourth dielectric layer 75, FIGS. FIG.
The circuit element assembly board shown in FIG. 6 has a character as an intermediate product.

The dielectric layer 73 constitutes a surface layer,
The capacitor electrodes (C11, C31, C41, C51) are formed on the surface of the dielectric layer 73. On the back surface of the dielectric layer 73, the capacitor electrodes C11, C31, C41, C
51, a ground electrode GN serving as a pair of capacitor electrodes
D2 are arranged at intervals. As described above, the back surface of the dielectric layer 73 is adjacent to the front surface of the core layer 74.

The capacitor electrodes (C11, C31, C4
1, C51) and the ground electrode GND2 constitute a set of opposed electrode groups as shown in FIGS. 5, 8, and 9, and each set includes one set of one power amplification module. Configure circuit elements. In the illustrated embodiment, the capacitor electrode (C1
1, C31, C41, C51) and the ground electrode GND2. The circuit elements Q11 to Q58 are arranged in a matrix.

The measuring electrode 8 includes a first measuring electrode 81 and a second measuring electrode 82 (see FIG. 16). A plurality of measurement electrodes 8 are arranged at appropriate intervals so as to surround the region Q in a space outside the region Q where the circuit elements Q11 to Q58 are arranged.

FIG. 17 is an enlarged plan view showing one of the measurement electrodes 8, and FIG. 18 is a partial sectional view taken along the line 18-18 in FIG. 17 and 18 also show the measuring method.

The first measurement electrode 81 is provided on the surface of the dielectric layer 73. The second measurement electrode 82 is provided on the dielectric layer 7.
3, that is, on the surface adjacent to the dielectric layer 73 and the core layer 74, facing the first measurement electrode 81,
3 is led out to the surface of the dielectric layer 73 by a lead conductor 85 penetrating through the third dielectric layer 73.

In the illustrated embodiment, a first measuring terminal 83 and
And a second measuring terminal 84. First measurement terminal 8
3 is provided on the surface of the dielectric layer 73, and the first measurement electrode 8
Conducted with 1. The second measurement terminal 84 is connected to the dielectric layer 7.
3 and is electrically connected to the second measurement electrode 82 via the lead conductor 85.

According to the above-described circuit element assembly board, the first
The probes 91 and 92 of the capacitance measuring device 9 are applied to the measurement terminal 83 and the second measurement terminal 84 of the first measurement electrode 81, respectively.
And the second measurement electrode 82 are measured for a capacitance generated therebetween, and based on the measured value, the capacitance of the capacitor electrode (C1) is measured.
1, C31, C41, C51) can be employed.

That is, the first and second measurement electrodes 81 and 82
Are provided on the front and back surfaces of the dielectric layer 73,
By measuring the capacitance generated between the first measurement electrode 81 and the second measurement electrode 82, the areas of the first and second measurement electrodes 81 and 82, which are known in advance, and the permittivity of the dielectric layer 73 are known. From this, the thickness of the dielectric layer 73 can be calculated.

Then, the calculated thickness of the dielectric layer 73 and the capacitor electrodes (C11, C31,
The capacitance obtained at the current electrode area (design value) is calculated from the area of C41, C51) and the dielectric constant of the dielectric layer 73 so that the capacitance value becomes equal to the design capacitance value as shown in FIG. Next, the capacitor electrodes (C11, C31, C41, C51) provided on the surface of the dielectric layer 73 are trimmed.

FIG. 19 is a diagram showing a specific example of the trimming method. As shown in the figure, capacitor electrodes (C11, C31, C
41, C51) are imaged, processed by the computer 13, projected on the monitor screen 14, and instructed by the computer 13 so as to have a predetermined area corresponding to the change amount of the area ratio viewed on the monitor screen 14. Trimming means 10
Is driven to adjust the capacitance value to a predetermined value.

According to this characteristic adjusting method, the characteristics of the individual circuit elements included in the circuit element assembly board can be easily and accurately adjusted.

FIG. 20 is a perspective view showing another embodiment of the circuit element assembly board according to the present invention, FIG. 21 is a plan view of the circuit element assembly board shown in FIG. 20, and FIG. It is the fragmentary sectional view which met. The illustrated embodiment shows an example in which the capacitors C1, C3, C4, and C5 have a multilayer structure. In the drawings, the same components as those shown in the drawings previously described are denoted by the same reference numerals.

The illustrated circuit element assembly substrate includes a dielectric layer 72, a number of ground electrodes GND1, and a measurement electrode 80.

In FIG. 5, the dielectric layer 72 is
The third dielectric layer is provided on the third dielectric layer 73. The third dielectric layer 73 is shown in FIGS.
The capacity adjustment work shown in FIG. 19 has been completed.
The third dielectric layer 73 is laminated on one surface of the core layer 74, and a fourth dielectric layer 75 and a fifth dielectric layer 76 are formed on the other surface of the core layer 74. They are sequentially stacked. The details of the laminated structure are as described with reference to FIGS.

The dielectric layer 72 constitutes a surface layer,
The ground electrode GND1 is formed on the surface of the dielectric layer 72. A trimming process is performed on the back surface of the dielectric layer 72 (FIG. 14).
To FIG. 19), the finished capacitor electrodes C11 and C3
1, C41 and C51 are arranged.

Each of the ground electrodes GND1 is opposed to the capacitor electrodes (C11, C31, C41, C51) in common and constitutes a set of opposed electrodes. Each set includes one circuit for each power amplification module. Make up the element. In the illustrated embodiment, the ground electrode GND1 and the capacitor electrodes (C11, C
31, C41, and C51).
Q58 is arranged in a matrix.

The measuring electrode 80 is a third measuring electrode 801.
14 to 19, a fourth measurement electrode constituted by a first measurement electrode 81 provided on the dielectric layer 73 is included. Hereinafter, the reference numeral 81 is assigned to the fourth measurement electrode of the measurement electrode 80. A plurality of measurement electrodes 80 are arranged at appropriate intervals in a space outside the area Q where the circuit elements Q11 to Q58 are arranged so as to surround the area Q.

FIG. 23 is an enlarged plan view showing one of the measuring electrodes 80, and FIG. 24 is a partial sectional view taken along line 24-24 in FIG. 23 and 24 also show the measurement method.

[0098] The third measurement electrode 801 is provided on the surface of the dielectric layer 72. The fourth measurement electrode 81 is provided on the adjacent surface between the dielectric layer 73 and the dielectric layer 72, and is opposed to the third measurement electrode 801 by the lead conductor 805 penetrating through the dielectric layer 72. 72 surface.

In the illustrated embodiment, the third measuring terminal 803
And a fourth measurement terminal 804. The third measurement terminal 803 is provided on the surface of the dielectric layer 72 and is electrically connected to the third measurement electrode 801. Fourth measurement terminal 804
Are provided on the surface of the dielectric layer 72, and the lead conductors 805
Through the fourth measurement electrode 81.

According to the circuit element assembly board described above, the third
The probes 91 and 92 of the capacitance measuring device 9 are applied to the measurement terminal 803 and the fourth measurement terminal 804, and the capacitance generated between the third measurement electrode 801 and the fourth measurement electrode 81 is measured. Based on the measured value, the ground electrode GND
A characteristic adjustment method for determining the amount of trimming can be adopted.

That is, the third and fourth measurement electrodes 801 and 8
Since 1 is provided on the front surface and the back surface of the dielectric layer 72, by measuring the capacitance generated between the third measurement electrode 801 and the fourth measurement electrode 81, the third and fourth values that are known in advance are measured. 4, the area of the measurement electrodes 801 and 81,
From the dielectric constant of the dielectric layer 72, the thickness of the dielectric layer 72 can be calculated.

Then, the calculated thickness of the dielectric layer 72 and the capacitor electrode C1 adjusted by the process of FIG.
The capacitance obtained at the current electrode area (design value) is calculated from the area of the ground electrode GND1 and C1, C31, C41, and C51, and the dielectric constant of the dielectric layer 72. The ground electrode GND1 provided on the surface of the dielectric layer 72 is trimmed by a trimming means such as a laser so as to be equal.

As a specific trimming means, the configuration shown in FIG. 19 can be employed. Returning to FIG. 19, the ground electrode GND1 is imaged using the imaging device 12 such as a CCD camera, processed by the computer 13, projected on the monitor screen 14, and the amount of change in the area ratio viewed on the monitor screen 14 is calculated. The capacitance value is adjusted to a predetermined value by driving the trimming means 10 according to a command from the computer 13 so as to have a predetermined predetermined area.

According to this characteristic adjusting method, the characteristics of the individual circuit elements included in the circuit element assembly board can be easily and accurately adjusted.

After the adjustment is completed, the dielectric layer 71 is laminated on the dielectric layer 72, and the sixth dielectric layer is placed on the fifth dielectric layer 76.
Are laminated. As a result, a completed product of the circuit element assembly board shown in FIG. 25 is obtained.

Next, after necessary electronic components are mounted on the surface of the dielectric layer 71 constituting the uppermost layer of the circuit element assembly board shown in FIG. 25 or a conductor pattern is formed, the circuit element assembly board is removed. By performing the dividing step at the boundary between the circuit elements Q11 to Q58, individual power amplification modules can be obtained.

[0107]

As described above, according to the present invention, the following effects can be obtained. (A) A small power amplification module can be provided. (B) A circuit element assembly board suitable for manufacturing a power amplification module can be provided. (C) It is possible to provide a property adjusting method suitable for adjusting the characteristics of the individual circuit paths included in the circuit element assembly board.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-frequency circuit unit in a digital mobile communication device (W-CDMA compatible) using a power amplification module according to the present invention.

FIG. 2 is a block diagram showing details of a power amplification circuit section PWA in which the power amplification module according to the present invention is used.

FIG. 3 is a circuit diagram showing a specific circuit configuration of the power amplification module according to the present invention.

FIG. 4 is a partial cross-sectional view showing a configuration of the power amplification module shown in FIGS.

FIG. 5 is a cross-sectional view of a multilayer substrate used in the power amplification module shown in FIG.

FIG. 6 is a plan view of a first (uppermost) dielectric layer from the top in the power amplification module shown in FIG. 4;

FIG. 7 is a circuit diagram of the power amplification module shown in FIG.
FIG. 9 is a plan view showing a surface of a third dielectric layer.

FIG. 8 shows the power amplification module shown in FIG.
FIG. 9 is a plan view showing a surface of a third dielectric layer.

FIG. 9 shows the power amplification module shown in FIG.
FIG. 9 is a plan view showing the surface of a third core layer.

FIG. 10 shows a power amplification module shown in FIG.
It is a top view showing the surface of the 5th dielectric layer.

FIG. 11 shows the power amplification module shown in FIG.
It is a top view showing the surface of the 6th dielectric layer.

FIG. 12 is a diagram illustrating the power amplifying module shown in FIG.
It is a top view showing the surface of the 7th dielectric layer.

FIG. 13 shows the power amplification module shown in FIG.
It is a top view showing the back of the 7th dielectric layer.

FIG. 14 is a perspective view of a circuit element assembly board suitable for manufacturing a power amplification module.

15 is a plan view of the circuit element assembly board shown in FIG.

FIG. 16 is a partial sectional view taken along the line 16-16 in FIG. 15;

FIG. 17 is an enlarged plan view showing one of measurement electrodes included in the circuit element assembly substrate shown in FIGS. 14 to 16;

FIG. 18 is a partial sectional view taken along line 18-18 in FIG. 17;

FIG. 19 is a diagram showing a specific example of a characteristic adjustment method according to the present invention.

FIG. 20 is a perspective view showing another embodiment of the circuit element assembly board according to the present invention.

21 is a plan view of the circuit element assembly board shown in FIG.

FIG. 22 is a partial sectional view taken along the line 22-22 in FIG. 21;

FIG. 23 is an enlarged plan view showing one of the measurement electrodes.

FIG. 24 is a partial sectional view taken along the line 24-24 in FIG. 23;

FIG. 25 is a perspective view of a circuit element assembly obtained by the characteristic adjustment method shown in FIGS. 14 to 24;

[Explanation of symbols]

 2 Power amplification module 71-73 Dielectric layer 74 Core layer 75-77 Dielectric layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J091 AA01 AA41 CA92 CA98 FA16 HA06 HA09 HA25 HA29 HA33 KA12 KA29 KA44 KA66 QA04 SA14 TA01

Claims (7)

[Claims] 1. A power amplification module including an MMIC, an impedance matching circuit, and a multilayer substrate, wherein the MMIC constitutes an amplification circuit, the impedance matching circuit includes a capacitor, and includes a capacitor. Connected to at least one of an input side or an output side, wherein the multilayer substrate includes a dielectric layer, supports the MMIC and the impedance matching circuit, and includes a capacitor included in the impedance matching circuit. At least one is a power amplification module configured by a pair of capacitor electrodes arranged on both surfaces of the dielectric layer. 2. The power amplification module according to claim 1, wherein one of said pair of electrodes is a ground electrode. 3. The power amplification module according to claim 2, wherein at least one of one or the other of the pair of capacitor electrodes is trimmed. 4. The power amplifying module according to claim 1, wherein the multilayer substrate includes at least one core layer and a plurality of dielectric layers. Is an organic layer containing glass fiber, the dielectric layer is made of a mixed material obtained by mixing an organic resin material and a dielectric powder, and constitutes a part of a circuit element included in the power amplification unit. The power amplification module, wherein the dielectric layer is adjacent to both surfaces of the core layer. 5. A circuit element assembly substrate used for manufacturing a power amplification module, comprising: a dielectric layer, a number of capacitor electrodes, and a measurement electrode, wherein the capacitor electrode is formed of the dielectric layer. The measurement electrodes are provided at opposing positions on both surfaces and are arranged at an interval on the both surfaces, wherein the measurement electrodes include a first measurement electrode and a second measurement electrode, and the first measurement An electrode is provided on one surface of the dielectric layer, and the second measurement electrode is provided on the other surface of the dielectric layer, faces the first measurement electrode, and penetrates the dielectric layer. A circuit element assembly led to the one surface of the dielectric layer by a lead conductor to be formed. 6. The circuit element assembly board according to claim 5, further comprising a first measurement terminal and a second measurement terminal, wherein the first measurement terminal is a dielectric material. The second measurement terminal is provided on the one surface of the body layer and is electrically connected to the first measurement electrode. The second measurement terminal is provided on the one surface of the dielectric layer and the second measurement terminal is provided through the lead conductor. Circuit element assembly that is in conduction with the measurement electrode of FIG. 7. A method for adjusting characteristics of each of circuit elements on a circuit element assembly board, wherein the circuit element assembly board is any one of claims 5 and 6, A characteristic adjusting method for measuring a capacitance generated between a first measurement electrode and the second measurement electrode, and determining a trimming amount of the capacitor electrode based on the measured value.