JP2002304161A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the power source voltage of a driver by performing polarity inversion, in a cycle which is one hour or longer in a liquid crystal display. SOLUTION: In the liquid crystal display, polarity inversion having a long cycle is realized, without making a user incongruity feel on the image, by performing the polarity inversion only during the non-use time which is specified by the user, such as the time of turning on of power source or the time of turning off of the power source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor display device (hereinafter, referred to as a display device), and more particularly to an active matrix type display device having a thin film transistor (hereinafter, referred to as a TFT) formed on an insulator. About.

[0002]

2. Description of the Related Art In recent years, a display device formed by using a semiconductor thin film on an insulator, particularly a glass substrate, particularly an active matrix display device using a TFT has been widely used. The active matrix display device arranges pixels in a matrix, arranges TFTs in each of the pixels, controls the luminance of each pixel using these TFTs, and displays an image.

In recent years, a technique has been developed in which, in addition to pixel TFTs forming pixels, TFTs for forming a driving circuit are simultaneously formed in a peripheral portion of a pixel portion using a polycrystalline semiconductor. This greatly contributes to miniaturization and low power consumption of the device. Accordingly, in recent years, an active matrix display device has become an indispensable device for a display section of a portable information device whose application field is remarkably expanding. Further, examples of the active matrix display device include an active matrix liquid crystal display device using a liquid crystal element, an active matrix OLED display device using an OLED (organic light emitting diode) element, and the like. Attention is focused mainly on an active matrix type liquid crystal display device.

Here, in this specification, a liquid crystal element is 2
An element having a structure in which a liquid crystal material is sandwiched between an electrode and an alignment film is illustrated. As the liquid crystal material, a material having a known structure can be used freely.

FIG. 6 shows a schematic diagram of a conventional active matrix type liquid crystal display device of a system for performing display using a digital video signal (hereinafter, referred to as a digital system). A pixel portion 1308 is provided at the center. A source signal line driver circuit 1301 for controlling a signal input to a source signal line included in each pixel is provided above the pixel portion 1308. The source signal line driver circuit 1301 includes a shift register 1303, a first latch circuit 1304,
Latch circuit 1305, D / A (digital / analog)
The circuit includes a conversion circuit (indicated as DAC in the figure) 1306, an analog switch 1307, and the like. On the left and right of the pixel portion 1308, a gate signal line driver circuit 1302 for controlling a signal input to a gate signal line included in each pixel is provided. In FIG. 6, the gate signal line driving circuit 1302 is provided on both the left and right sides of the pixel portion 1308, but may be provided on one side. However, it is desirable to dispose them on both sides of the pixel portion 1308 from the viewpoint of driving efficiency and driving reliability.

The source signal line driving circuit 1301 has a configuration as shown in FIG. The source signal line driving circuit shown as an example in FIG. 7 has x pixels in the horizontal direction and has 3 pixels.
A source signal line driving circuit corresponding to a display device that receives a digital video signal of 1 bit and performs grayscale display (hereinafter, referred to as 3-bit digital grayscale), and includes a shift register (S
R) 1401, the first latch circuit (LAT1) 140
2, a second latch circuit (LAT2) 1403, a D / A conversion circuit (DAC) 1404, and the like. In FIG. 7, the analog switch 1307 shown in FIG. 6 is not shown. Although not shown in FIG. 7, a buffer circuit, a level shifter circuit, and the like may be provided as necessary.

The operation will be briefly described with reference to FIGS. 6 and 7. First, a shift register 1303 (in FIG. 7,
A clock signal (clock pulse, inverted clock pulse) and a start pulse are input to SR. Then, a pulse is sequentially output from the shift register 1303 to the first pulse.
The digital video signal (digital data) input to the latch circuit 1304 of FIG. 7 (denoted as LAT1 in FIG. 7) and also input to the first latch circuit 1304 is held.

Here, D3 is the most significant bit (MSB: Most Significant Bit) of the digital video signal, and D1 is the least significant bit (LSB: Least Significant) of the digital video signal.
antBit). In the first latch circuit 1304,
When the holding of the digital data for one horizontal cycle is completed, the digital video signal held by the first latch circuit 1304 is simultaneously supplied to the second latch circuit 1304 during the retrace period by the input of the latch signal (latch pulse). Latch circuit 1305 (FIG. 7)
LAT2).

After that, the shift register 1303 operates again, and the holding of digital data for the next horizontal cycle is started. At the same time, the digital data held in the second latch circuit 1305 is output to the D / A conversion circuit 1306 (FIG. 7).
, And DAC). This analog signal is supplied to a source signal line (S1 in FIG. 7).
To Sx) and written to each pixel.

FIG. 8 shows a configuration of a pixel portion of a general active matrix type liquid crystal display device.

It is assumed that the pixel section has pixels in x columns and y rows.

A capacitor 1001, a switching TFT 1002, and a liquid crystal element 1003 are arranged for each pixel. Switching TFT 10 for each pixel
02 is connected to any one of the gate signal lines G1 to Gy, and the switching T
One of a source region and a drain region of the FT 1002 is connected to one of the source signal lines S1 to Sx, and the other is connected to one electrode of the capacitor 1001 and the liquid crystal element 1003.

The analog signals input to the source signal lines S1 to Sx are turned on by the switching TFT 100 which is turned on by the signals input to the gate signal lines G1 to Gy.
2 through the drain-source of the capacitor 1001
And input to the liquid crystal element 1003. The transmittance of the liquid crystal element 1003 changes according to the voltage of this signal, and the luminance of each pixel is expressed.

Here, if an electric field in a fixed direction is continuously applied between the two electrodes of the liquid crystal element, ions in the liquid crystal material are biased, causing a problem that the deterioration of the liquid crystal element is promoted. Therefore, in a display device or the like using a general liquid crystal element, the polarity of a voltage applied to the liquid crystal element is changed at regular intervals to change the direction of an electric field applied between two electrodes of the liquid crystal element. A driving method is used.

FIG. 2 schematically shows the polarity of the voltage applied to each pixel of the liquid crystal display device. 2 (1), 2 (2), and 2 (3) show the state of the pixel unit in the n-th frame and the state of the pixel unit in the (n + 1) -th frame. Note that in FIG. 2, pixels of 4 rows and 4 columns are representatively shown as a pixel portion. In the figure, the polarity of the voltage applied to the liquid crystal element is different between the pixel indicated by + and the pixel indicated by-.

For example, FIG. 2A shows a driving method called gate line inversion in which the polarity of a signal voltage applied to a liquid crystal element is made different between adjacent gate signal lines. FIG. 2B shows a driving method called source line inversion in which the polarity of a signal applied to a liquid crystal element is made different between adjacent source signal lines. Finally, 1
FIG. 2C shows a driving method called frame inversion in which the polarity of a signal applied to a liquid crystal element is inverted every time an image is displayed (hereinafter, referred to as one frame period). Note that the driving method is not limited to the driving method shown in FIG. 2, and the driving method is various.

The operation of the conventional active matrix type liquid crystal display device will be described with reference to timing charts shown in FIGS.

In the timing chart of FIG. 9, every frame period as shown in FIG.
The operation in frame inversion drive, which inverts the polarity of a signal applied to a liquid crystal element, is used.

That is, a signal having a polarity opposite to that of the signals input to the source signal lines S1 to Sx in the first frame period (F1) is generated in the source signal lines S1 to Sx in the second frame period (F2). Input from In the third frame period (F3), signals having polarities different from those of the signals input in the second frame period (F2) are input from the source signal lines S1 to Sx.

In the first frame period (F1), the gate signal line G1 is selected first. Then, the switching TFT having the gate electrode connected to the gate signal line G1.
1002 becomes conductive. Thereafter, the source signal line S1
To Sx. In the timing chart of FIG. 9, one source signal line Sm (m
(Where is a natural number), and shows only signals input to the source signal line Sm.

It is assumed that a signal having a potential of -V to V is input to the source signal line.

Here, a period in which one gate signal line is selected is referred to as one horizontal period (one line period: L). In particular, a period during which the gate signal line G1 is selected will be referred to as a first line period L1. Here, the switching TFT 10 connected to the gate signal line G1
02, the signal is input to the gate signal line G2, and all the switching TFTs 1 whose gate electrodes are connected to the gate signal line G2.
002 becomes conductive. Thus, the second line period L
Input of the signal in 2 starts.

The above operation is repeated for all the gate signal lines G1 to G
One frame period (F1) ends when y is repeated until the y-th line period Ly ends.

Next, a second frame period (F2) starts. In the second frame period (F2), the polarity of the signal input to the source signal lines S1 to Sx is the same as the polarity of the signal voltage input to the source signal lines S1 to Sx in the first frame period (F1). different. Thus, the image is displayed.

When the second frame period (F2) ends, a third frame period (F3) starts. Here, in the third frame period (F3), a signal voltage having a different polarity from that in the second frame period (F2) is input to the source signal line. That is, a signal voltage having the same polarity as that of the first frame period (F1) is input to the source signal line.

The above operation is repeated to display an image.

FIG. 3 shows the potential of the pixel electrode (pixel potential) and
The relationship between the potential of the counter electrode (counter potential) and the power supply voltage of the gate driver (gate signal line driving circuit) is shown.

In FIG. 3, the vertical axis indicates the potential (V).
In FIG. 3, the potential difference between 0 V and 16 V corresponds to the power supply voltage of the gate driver (gate signal line driving circuit). FIG. 3 shows a case where the liquid crystal is normally white. In the case of performing black display, a voltage of about 5 V is normally applied between the counter electrode and the pixel electrode.

In FIG. 3A, the counter potential has a constant value. Since only the potential of the pixel electrode is inverted, the signal potential input to the source signal line fluctuates by about 10 V in total. That is, the potential difference between the highest potential and the lowest potential of the signal potential input to the source signal line is about 10V. Therefore, the power supply voltage of the source signal line driving circuit is about 10 V.

FIG. 3B shows an example in which the counter voltage is fluctuated at an amplitude of 5V. Here, it is assumed that the pixel shown in the figure is a pixel located at the center of the screen and writing is performed in the middle of the opposite polarity inversion. The potential of the pixel electrode is driven in accordance with the movement of the counter electrode.

Even if the signal potential input from the source signal line is the same, the potential of the pixel electrode changes as the potential of the counter electrode changes. Therefore, the signal potential input to the source signal line only needs to swing about 5V. Therefore, the power supply voltage of the source signal line driver circuit can be about 5 V.

Thus, in the driving method shown in FIG. 3B, the power supply voltage of the source signal line driving circuit can be reduced as compared with the driving method shown in FIG.

In the example of FIG. 3B, since the power supply voltage of the gate driver (gate signal line driving circuit) is the same as that of FIG. However, when the power supply voltage of the gate driver (gate signal line driving circuit) is reduced to 10 V, a problem may occur.

FIG. 4 is a diagram showing a driving method when the power supply voltage of the gate driver (gate signal line driving circuit) is reduced to 10V. In FIG. 4, in the region indicated by the arrow, the pixel TFT (the switching TFT shown in FIG.
FT1002) is turned on, and the voltage applied to the liquid crystal element of the pixel cannot be held (because the source potential is lower than the gate potential of the pixel TFT). For this reason, the state in which the voltage applied to the liquid crystal element of the pixel cannot be held becomes 2
Since this occurs once during the reversal of the polarity, the image quality is greatly reduced.

That is, in a liquid crystal display that requires a voltage of about 5 V to drive the liquid crystal and frequently inverts the polarity, in either case of FIGS. 3 (1) and 3 (2),
The power supply voltage of the gate driver (gate signal line drive circuit) needs to be about 15V.

[0036]

As described above, when the signal voltage applied to the liquid crystal is AC-inverted every frame period, the power supply voltage of the gate driver (gate signal line driving circuit) needs to be about 15V. Therefore, the TFT constituting the gate driver (gate signal line drive circuit) must have reliability enough to withstand a voltage of 15V.

In general, in order to enhance the reliability of a TFT, an LDD, particularly, an LDD that overlaps with a gate electrode by 1 to 1.5 μm is formed. In order to make such an LDD, a method of forming an LDD only on a TFT to which a high voltage is applied using a photomask,
There is a method in which LDDs are formed in all TFTs by self-alignment. In the former case, there is a problem that the number of steps increases because a photomask is added. In the latter case, since an LDD of 1 to 1.5 μm is formed in all TFTs,
LDDs are also formed in TFTs requiring high-speed operation, which is disadvantageous in operation.

Accordingly, an object of the present invention is to provide a liquid crystal display device which simultaneously satisfies the reliability of TFT, high-speed operation, and simplification of the process.

[0039]

SUMMARY OF THE INVENTION The present invention proposes a liquid crystal display device that performs display by inverting a signal voltage applied to a liquid crystal element with an extremely long cycle, or a liquid crystal display device that does not reverse polarity.

As a result, the power supply voltage of the driver (source signal line drive circuit or gate signal line drive circuit) can be reduced,
A liquid crystal display device which satisfies high-speed operation by suppressing the length of an LDD of a TFT constituting a driver or the like is provided.

Hereinafter, the configuration of the liquid crystal display device of the present invention will be described.

According to the present invention, a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. In a liquid crystal display device, there is provided a liquid crystal display device characterized in that a polarity of a signal for driving a liquid crystal is inverted in synchronization with power-on or power-off.

According to the present invention, a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. In a liquid crystal display device, there is provided a liquid crystal display device in which the polarity of a signal for driving liquid crystal is inverted at a timing at which the entire liquid crystal screen is rewritten.

According to the present invention, a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. There is provided a liquid crystal display device wherein the polarity of a signal for driving liquid crystal is inverted at a specific time determined by a user.

According to the present invention, there is provided a liquid crystal display device having a backlight, wherein the polarity of a signal for driving liquid crystal is inverted during a period in which the backlight is turned off.

According to the present invention, the first electrode provided on the same substrate, the second electrode provided substantially in parallel with the first electrode, and the voltage between the first and second electrodes are driven. In a liquid crystal display device having a liquid crystal, a polarity of a signal for driving the liquid crystal is inverted in synchronization with power-on or power-off.

According to the present invention, a first electrode provided on the same substrate, a second electrode provided substantially parallel to the first electrode, and a voltage between the first and second electrodes are driven. In a liquid crystal display device having liquid crystal, a polarity of a signal for driving the liquid crystal is inverted at a timing when the entire liquid crystal screen is rewritten.

According to the present invention, the first electrode provided on the same substrate, the second electrode provided substantially in parallel with the first electrode, and the voltage between the first and second electrodes are driven. In a liquid crystal display device having a liquid crystal, a polarity of a signal for driving the liquid crystal is inverted at a specific time determined by a user.

The liquid crystal is IPS (In-Plane Swi)
(tching) mode liquid crystal display device.

The liquid crystal display device may be characterized in that the polarity inversion cycle is one hour or more.

According to the present invention, a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. In the liquid crystal display device, there is provided a liquid crystal display device wherein the polarity of the voltage between the pixel electrode and the counter electrode is not inverted.

According to the present invention, the first electrode provided on the same substrate, the second electrode provided substantially in parallel with the first electrode, and the voltage between the first and second electrodes are driven. In a liquid crystal display device having a liquid crystal, a voltage between the first electrode and the second electrode is not inverted.

A liquid crystal display device having a function of performing display by correcting the deterioration of the liquid crystal may be used.

The liquid crystal display device may be characterized in that the liquid crystal deterioration is corrected by storing the accumulated time of voltage application for each pixel.

A television, a personal computer, a portable terminal, a video camera, or a head-mounted display characterized by using the liquid crystal display device may be used.

[0056]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a liquid crystal display device according to the present invention will be described below.

First, as the first embodiment, a case in which an AC inversion (inversion of the polarity of the voltage applied to the liquid crystal element) is performed for a very long period (for example, once an hour) will be described.

In the conventional liquid crystal display device, the AC inversion is 60
It is performed at a frequency of １００100 Hz, that is, at a period of 10１０〜16.6 ms. A longer cycle is perceived as flicker by human eyes.

In the liquid crystal material of the 1980's, there is a problem that the liquid crystal deteriorates in a relatively short time, for example, 10 hours, unless the alternating current is inverted frequently. However, the degree of deterioration of liquid crystal materials in recent years has been reduced.

The present inventor pays attention to this point, and solves the above-mentioned problem of the prior art by performing polarity inversion at a very long cycle.

If the polarity is inverted at a very long period, flicker is not considered. This is because flicker is perceived by moving images having different luminances in a cycle that can be visually perceived.

FIG. 1 shows the relationship between the potential of the pixel electrode (pixel potential), the potential of the counter electrode (counter potential), and the power supply voltage of the gate signal line driving circuit when driving the liquid crystal display device to which the present invention is applied. Shown in Compared with FIG. 4 of the conventional example, the period in which the polarity inversion occurs is much longer. Therefore, there is a time (indicated by an arrow in FIG. 1) during which the pixel TFT is turned on and the liquid crystal element of the pixel cannot hold the signal voltage.
The ratio of the time is very small as compared with the conventional example.

The problem with the driving method as shown in FIG. 1 is that when polarity inversion occurs once in a long cycle,
The effect is that an image is disturbed for a moment.

As a countermeasure for this, there are the following.

1) The polarity is inverted while the user is not using the liquid crystal display. For example, the polarity is inverted when the power of the liquid crystal display device is turned on or off, or the polarity is inverted at a specific time specified by the user (for example, at a time when the device is not normally used, such as midnight). 2) Polarity inversion is performed when the entire screen of the liquid crystal display device changes to another screen.

By taking such measures, it is possible to solve the problem that the image is instantly disturbed when the polarity is reversed.

Thus, in the present invention, the driver (the source signal line driving circuit and the gate signal line driving circuit) can be driven at a voltage of about 10 V.

The details of the above driving method will be described in embodiments.

Next, as a second embodiment, an example in which the polarity is not inverted will be considered.

Although the liquid crystal element has been hardly deteriorated in recent years, when a DC voltage is applied for a long time, the V
The T curve (transmittance-applied voltage curve) changes, and the display characteristics change. FIG. 5 is a schematic diagram of a VT curve of a liquid crystal element. With respect to the initial value (indicated as initial in FIG. 5),
As time passes, the curve shifts to the left (Fig. 5
Medium, after aging). Therefore, when the liquid crystal element is deteriorated in this way, some correction is required. Various images are displayed on the screen of the liquid crystal display device. In other words, since various video signal voltages are applied to individual pixels, the manner in which signal voltages are applied and the history differ for each pixel. Therefore, when the liquid crystal display device is driven without reversing the polarity, the degree of the deterioration is different for each pixel.

Therefore, when the liquid crystal element performs the correction in response to the deterioration, it is necessary to configure a circuit for performing the correction in accordance with the history for each pixel. FIG. 13 is a block diagram illustrating a configuration of a display system that performs correction. In this system, there are blocks with the following functions. First, the data of the memory circuit is initially 0. In this case, when the digital video signal is input to the cumulative luminance adding circuit, an output corresponding to 0 is input to the video correction circuit. In this case, no correction is performed, and the digital video signal is input as is to an LCD (liquid crystal display).

The output of the cumulative luminance adding circuit is also input to the memory circuit and stored.

Next, when a digital video signal is input, new digital video signal data is added to the contents stored in the memory circuit. Using this data, the video correction circuit corrects the digital video signal. The addition data is input to the memory circuit and rewrites the data stored in the memory circuit. By repeating this, the accumulated luminance of each pixel is obtained. Using these data, the deterioration of the liquid crystal is predicted and corrected for each pixel.

When the power supply of the liquid crystal display device is turned off, the data of the memory circuit is transferred to the non-volatile memory so that the stored contents are not erased. When the power of the liquid crystal display device is turned on, data is transferred from the nonvolatile memory to the memory circuit and used. The non-use of the non-volatile memory is due to the slow response of the non-volatile memory and the small number of possible rewrites.

In this manner, the voltage applied to each pixel is stored, and it is possible to know which pixel has been cumulatively applied and how much load has been applied. Deterioration of a liquid crystal element can be corrected by determining a correction amount according to the applied load and performing correction. That is, the liquid crystal element can be driven without inverting the polarity, and the power supply voltage of the display device can be reduced. Specifically, driving at a voltage of about 10 V becomes possible.

[0076]

Embodiments of the present invention will be described below.

[Embodiment 1] FIG. 10 shows an example in which the polarity is inverted in synchronization with the power-off of the liquid crystal display device. First, at t1, the backlight is turned off. Thus, if the displayed image is disturbed thereafter, the user does not see it. Next, at t2, the polarity is inverted and a signal is written. It is desirable to write several times. Next, at t3, the power supply of the liquid crystal display device is turned off.

By forming such a sequential structure, the user does not need to see a decrease in image quality due to polarity inversion. When the power supply of the liquid crystal display device is turned on, the polarity inversion has already been completed. Therefore, image display may be started as it is.

Although not shown, the same technique can be used to invert the polarity when the power of the liquid crystal display device is turned on. After the power supply of the display device is turned on, polarity inversion is performed. After that, writing is performed several times, and then the backlight is turned on. Also in this method, as in the method shown in FIG. 10, the user does not need to see the image quality degradation at the time of polarity inversion.

[Embodiment 2] FIG. 11 is a block diagram showing a system for setting a polarity inversion time according to a user's request.

The user sets a desired time in the polarity inversion time setting timer circuit via the user interface. For example, the time is set at 3:00 am When the set time comes, the polarity inversion time setting timer circuit gives a signal to the CPU to switch the polarity. CPU
Receives the signal and outputs a signal to the LCD controller,
The drive circuit of the liquid crystal display (LCD) is operated to invert the polarity. When the polarity inversion ends, the CPU stops the operation of the liquid crystal display (LCD).

By having the function as shown in FIG. 11, during the time when the user does not normally use the display device,
The polarity inversion is performed, and the user does not see the image quality deterioration at the time of polarity switching. Of course, at this time, the backlight does not need to be turned on.

[Embodiment 3] This embodiment is an example in which the polarity of the image on the screen is inverted by detecting the case where the entire screen is switched instead of the part.

For example, when the display device is a television,
At the time of channel switching, the image content changes significantly. In such a case, even if there is a discontinuity between the previous video and the subsequent video, the user does not feel uncomfortable because the original video signal is also discontinuous.

It is also possible to perform polarity reversal at the time of switching over the entire screen so as to avoid visual recognition of image quality degradation at the time of polarity switching.

[Embodiment 4] FIG. 12 shows a liquid crystal display device having an IPS
4 is a pixel diagram when an (In-Plane-Switching) mode is used.

The IPS mode is different from the TN mode in that the liquid crystal layer between the counter electrode on the counter substrate and the pixel electrode on the pixel substrate is not driven, but the two parallel electrodes on the same substrate are not driven.
Drive the liquid crystal layer between the two electrodes. Therefore, a liquid crystal display device driven in the IPS mode has a feature of having a wider viewing angle than a liquid crystal display device driven in the TN mode. The present invention is effective when the IPS mode is used, as in the case where the TN mode is used.

The first, second, and third embodiments described above.
Can be combined with this embodiment.

[Embodiment 5] In the present embodiment, the pixel portion of the liquid crystal display device of the present invention and the T
A method for simultaneously manufacturing FTs will be described. However, for the sake of simplicity, a CMOS circuit, which is a basic unit for the drive circuit unit, is illustrated.

The pixel portion has a write TF
Only T (switching TFT), source signal line, and storage capacitor are shown.

First, as shown in FIG. 14A, oxidation is performed on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass. A base film 5002 made of an insulating film such as a silicon film, a silicon nitride film, or a silicon oxynitride film is formed.
For example, a plasma CVD method SiH _4, NH _3, N ₂ silicon oxynitride film 5002a made from O 10 to 2
00 [nm] (preferably 50 to 100 [nm]) is formed, similarly SiH _4, N ₂ O hydrogenated silicon oxynitride film 5002b made from 50 to 200 [nm] (preferably 100
１５０150 [nm]). Although the base film 5002 has a two-layer structure in this embodiment, the base film 5002 may have a single-layer structure or a structure in which two or more insulating films are stacked.

Each of the island-shaped semiconductor layers 5003 to 5006 is formed of a crystalline semiconductor film formed by using a semiconductor film having an amorphous structure by a laser crystallization method or a known thermal crystallization method.
The thickness of the island-shaped semiconductor layers 5003 to 5006 is 25 to 8
It is formed with a thickness of 0 [nm] (preferably 30 to 60 [nm]). The material of the crystalline semiconductor film is not limited, but is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to form a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser is used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 [Hz], and the laser energy density is 100 to 400 [mJ / cm ² ] (typically, 2
00 to 300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used, the pulse oscillation frequency is set to 1 to 10 [kHz], and the laser energy density is set to 30.
0 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ / c]
m ² ]). And a width of 100 to 1000 [μm],
For example, a laser beam condensed linearly at 400 [μm] is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser beam at this time is set to 80 to 98 [%].

Next, island-shaped semiconductor layers 5003 to 5006
Is formed to cover the gate insulating film 5007. The gate insulating film 5007 is formed by a plasma CVD method or a sputtering method.
It is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm]. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicat
e) and O ₂ were mixed, the reaction pressure was 40 [Pa], and the substrate temperature was 30.
It can be formed by discharging at a high frequency (13.56 [MHz]) and a power density of 0.5 to 0.8 [W / cm ² ] at 0 to 400 [° C.]. The silicon oxide film thus manufactured can obtain favorable characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed of Ta to a thickness of 50 to 100 [nm],
A second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

The Ta film is formed by a sputtering method by sputtering a Ta target with Ar. in this case,
When an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. Also, α
The phase Ta film has a resistivity of about 20 [μΩcm] and can be used as a gate electrode, but the β phase Ta film has a resistivity of about 180 [μΩcm] and is not suitable for a gate electrode. . In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to the Ta α-phase is formed on a Ta base with a thickness of about 10 to 50 [nm]. Can be easily obtained.

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
[μΩcm] or less is desirable. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, in the case of using the sputtering method, a W target having a purity of 99.9999 [%] is used, and a W film is formed by giving sufficient consideration so as not to mix impurities from the gas phase during film formation. Resistivity 9-20
[μΩcm] can be realized.

In this embodiment, the first conductive film 500 is used.
8 was Ta, and the second conductive film 5009 was W. However, there is no particular limitation, and any of Ta, W, Ti, Mo, Al, and Cu was used.
Alternatively, it may be formed of an element selected from the above, or an alloy material or a compound material containing the element as a main component. Also,
A semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As a desirable example of a combination other than this embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN) and the second conductive film 5009 is W,
008 is formed of tantalum nitride (TaN), and the second conductive film 5009 is made of Al.
08 is made of tantalum nitride (TaN), and the second conductive film 5009 is made of Cu.

If the LDD can be reduced in size, the structure may be a single W layer. Even if the structure is the same, the length of the LDD can be reduced by increasing the taper angle. .

Next, a mask 5010 made of a resist is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, ICP (Inductively Coupled)
d Plasma: Inductively coupled plasma) etching method,
CF ₄ and Cl ₂ are mixed as an etching gas, and RF (13.56 [MH]) of 500 [W] is applied to the coil type electrode at a pressure of 1 [Pa].
z]) Power is supplied to generate plasma. 100 [W] RF (13.56 [MH] also on the substrate side (sample stage)
z]) Apply power and apply a substantially negative self-bias voltage. When CF ₄ and Cl ₂ are mixed, the W film and Ta
The film is etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the edges of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 [nm] by over-etching. become. Thus, by the first etching process, the first conductive layer and the second conductive layer
Conductive layers 5011 to 5016 (first conductive layer 50
11a to 5016a and second conductive layers 5011b to 501
6b) is formed. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched to a thickness of about 20 to 50 [nm] to form a thinned region. (FIG. 24A)

Then, a first doping process is performed to add an impurity element imparting N-type. The doping may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~5 × 10
¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [keV]. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, the conductive layers 5011 to 5016 serve as a mask for the impurity element imparting n-type, and the first impurity region 50 is self-aligned.
17 to 5020 are formed. First impurity region 501
For 7 to 5020, 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ]
Is added within the concentration range of n.
(FIG. 14 (B))

Next, as shown in FIG. 14C, a second etching process is performed without removing the resist mask. Using CF ₄ , Cl ₂ and O _{2 as an} etching gas,
The film is selectively etched. At this time, the second shape conductive layers 5021 to 5026 are formed by the second etching process.
(First conductive layers 5021a to 5026a and second conductive layers 5021b to 5026b) are formed. At this time, in the gate insulating film 5007, the second shape conductive layer 50 is formed.
The area not covered by 21 to 5026 is further 20 to 50 [n
m] to form a thinned region.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ionic species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, the dose is lower than that of the first doping process, and n is set as a condition of a high acceleration voltage.
Doping with an impurity element for giving a mold. For example, the acceleration voltage of 70~120 [keV], 1 × 10 13 [atoms / cm
² ], a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. The doping is performed in the second shape conductive layer 5021.
To 5026 are used as masks for the impurity elements, and the semiconductor layers in regions below the first conductive layers 5021a to 5026a are also doped so that the impurity elements are added. Thus, second impurity regions 5027 to 5031 are formed. The second impurity regions 5027 to 5031
The concentration of phosphorus (P) added to the first conductive layer 502
It has a gradual concentration gradient according to the thickness of the tapered portion of 1a to 5026a. Note that the first conductive layer 5021a
In the semiconductor layer overlapping the tapered portion of 5026a to 5026a,
Although the impurity concentration slightly decreases from the end of the tapered portion of the first conductive layers 5021a to 5026a toward the inside, the impurity concentration is substantially the same.

Subsequently, a third etching process is performed as shown in FIG. This is performed using a reactive ion etching method (RIE method) using CHF ₆ as an etching gas. By the third etching treatment, the first conductive layer 502
By partially etching the tapered portions 1a to 5026a, a region where the first conductive layer overlaps with the semiconductor layer is reduced. By the third etching process, the third shape conductive layers 5032 to 5037 (first conductive layers 5032a to 5032) are formed.
37a and second conductive layers 5032b to 5037b). At this time, in the gate insulating film 5007, a region which is not covered with the third shape conductive layers 5032 to 5037 is further etched by about 20 to 50 [nm] to form a thinned region.

By the third etching process, in the second impurity regions 5027 to 5031, the second impurity region 50 overlapping with the first conductive layers 5032a to 5037a is formed.
27a to 5031a and third impurity regions 5027b to 5031 between the first impurity region and the second impurity region.
b is formed.

Then, as shown in FIG.
The island-shaped semiconductor layer 5004 forming the channel type TFT has
Fourth impurity region 5039 having a conductivity type opposite to that of the first conductivity type
To 5044 are formed. Third shape conductive layer 5033b
Is used as a mask for impurity elements,
An impurity region is formed. At this time, the N-channel TFT
Island-shaped semiconductor layers 5003 and 5005 forming a storage capacitor
The part 5006 and the wiring part 5034 are
The whole surface is covered with 38. Impurity regions 5039-50
44 has different concentrations of phosphorus
But diborane (B _TwoH₆) Formed by ion doping method
The impurity concentration is 2 × 10
²⁰~ 2 × 10^{twenty one}[atoms / cm^Three].

Through the above steps, impurity regions are formed in the respective island-shaped semiconductor layers. Third overlapping with the island-shaped semiconductor layer
Shape conductive layers 5032, 5033, 5035, 503
6 functions as a gate electrode. 5034 functions as an island-shaped source signal line. 5037 functions as a capacitance wiring.

After removing the resist mask 5038, a step of activating the impurity element added to each island-shaped semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace.
In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 400 to 700 in a nitrogen atmosphere of 1 [ppm] or less, preferably 0.1 [ppm] or less.
In this embodiment, the heat treatment is performed at 500 ° C. for 4 hours.
However, in the case where the wiring material used for the third shape conductive layers 5037 to 5042 is weak to heat, activation is performed after forming an interlayer insulating film (mainly containing silicon) to protect the wiring and the like. It is preferred to do so.

Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-like semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, the first interlayer insulating film 5045 is formed from a silicon oxynitride film to a thickness of 100 to 200 [nm]. A second interlayer insulating film 5046 made of an organic insulating material is formed thereon. Next, an etching step for forming a contact hole is performed.

Then, a source wiring 504 for forming a contact with the source region of the island-shaped semiconductor layer in the drive circuit portion.
7, 5048, a drain wiring 5049 for forming a contact with the drain region is formed. In the pixel portion, a connection electrode 5050 and pixel electrodes 5051 and 5052 are formed (FIG. 16A). With the connection electrode 5050, the source signal line 5034 is electrically connected to the writing TFT. Note that the pixel electrode 5052 and the storage capacitor are of an adjacent pixel.

In this embodiment, the writing TFT is used.
Has a double gate structure, but may have a single gate structure, a triple gate structure, or a multi-gate structure.

As described above, the N-channel TFT,
A driver circuit portion having a P-channel TFT and a pixel portion having a writing TFT and a storage capacitor can be formed over the same substrate. In this specification, such a substrate is called an active matrix substrate.

In this embodiment, the ends of the pixel electrodes are arranged so as to overlap with the source signal lines and the write gate signal lines so that the gap between the pixel electrodes can be shielded from light without using a black matrix. ing.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the island-like semiconductor layer pattern, the first wiring pattern (source signal line, capacitor wiring), The mask pattern, the contact hole pattern, and the second wiring pattern (including the pixel electrode and the connection electrode) of the p-channel region can be used. As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

Subsequently, after obtaining the active matrix substrate in the state of FIG. 16B, an alignment film 5053 is formed on the active matrix substrate, and a rubbing process is performed.

On the other hand, a counter substrate 5054 is prepared. The color filter layers 5055 to 505 are provided on the opposite substrate 5054.
7. An overcoat layer 5058 is formed. The color filter layer is a red color filter layer 5 above the TFT.
055 and a blue color filter layer 5056 are formed so as to overlap each other and also serve as a light-shielding film. At least TFT
In addition, since it is necessary to shield light between the connection electrode and the pixel electrode, it is preferable that a red color filter and a blue color filter are arranged so as to overlap each other so as to shield those positions.

Further, a spacer is formed by overlapping a red color filter layer 5055, a blue color filter layer 5056, and a green color filter layer 5057 in accordance with the connection electrode 5050. The color filter of each color is a mixture of acrylic resin and pigment, and is 1-3 [μm]
Formed with a thickness of This can be formed in a predetermined pattern using a photosensitive material and a mask. The height of the spacer is 1 to 4 μm, which is the thickness of the overcoat layer 5058.
m], 2 to 7 μm, preferably 4 to
The height can form a gap when the active matrix substrate and the opposing substrate are bonded to each other. The overcoat layer 5058 is formed using a photocurable or thermosetting organic resin material, and for example, polyimide or an acrylic resin is used.

The arrangement of the spacers may be determined arbitrarily. For example, as shown in FIG. 16B, the spacers may be arranged on the counter substrate 5054 so as to be aligned with the connection electrodes. Alternatively, the spacer may be arranged on the counter substrate 5054 so as to be aligned with the TFT of the driving circuit portion. The spacer may be disposed over the entire surface of the drive circuit portion, or may be disposed so as to cover the source wiring and the drain wiring.

After forming the overcoat layer 5058,
A counter electrode 5059 is formed by patterning, and an alignment film 506 is formed.
After forming 0, a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the drive circuit portion are formed and the opposing substrate are sealed with a sealant 50.
Attach at 62. A filler is mixed in the sealant 5062, and the two substrates are bonded to each other at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 5061 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Liquid crystal material 506
For 1, a known liquid crystal material may be used. Thus, the active matrix liquid crystal display device shown in FIG. 16B is completed.

Although the TFT in the active matrix type liquid crystal display device manufactured by the above-described process has a top gate structure, a TFT having a bottom gate structure.
This embodiment can be easily applied to TFTs having other structures.

In this embodiment, a glass substrate is used. However, the present invention is not limited to a glass substrate but may be implemented by using a substrate other than a glass substrate, such as a plastic substrate, a stainless steel substrate, or a single crystal wafer. Is possible.

This embodiment can be implemented by freely combining with Embodiments 1 to 4.

[Embodiment 6] In this embodiment, an example of a manufacturing process in a case where the present invention is applied to a reflection type liquid crystal display device will be described.

According to the fifth embodiment, an active matrix substrate shown in FIG. 17A (similar to FIG. 16A) is formed. Subsequently, after forming a resin film as the third interlayer insulating film 5201, a contact hole is opened in the pixel electrode portion, and a reflective electrode 5202 is formed. As the reflective electrode 5202, it is preferable to use a material having excellent reflectivity, such as a film mainly containing Al or Ag, or a stacked film thereof.

On the other hand, a counter substrate 5054 is prepared. In this embodiment, a counter electrode 520 is provided on the counter substrate 5054.
5 is formed by patterning. Counter electrode 5205
Is formed as a transparent conductive film. As a transparent conductive film,
A material formed of a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used.

Although not shown, a color filter layer is formed when a color liquid crystal display device is manufactured. At this time, it is preferable that adjacent color filter layers of different colors are formed so as to be overlapped with each other so as to also serve as a light shielding film in the TFT portion.

Thereafter, alignment films 5203 and 5204 are formed on the active matrix substrate and the counter substrate, and
A rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the drive circuit portion are formed and the opposing substrate are sealed with a sealant 52.
Attach at 06. A filler is mixed in the sealant 5206, and the two substrates are bonded at a uniform interval by the filler and the spacer. Thereafter, a liquid crystal material 5207 is injected between the two substrates, and completely sealed with a sealant (not shown). Liquid crystal material 520
For 7, a known liquid crystal material may be used. Thus, the reflective liquid crystal display device shown in FIG. 17B is completed.

In this embodiment, the present invention is not limited to a glass substrate, and it is also possible to use a substrate other than a glass substrate, such as a plastic substrate, a stainless steel substrate, or a single crystal wafer.

Further, the present invention can be easily applied to a case of producing a transflective display device in which half of the pixel is a reflective electrode and the other half is a transparent electrode.

The present invention can be implemented by freely combining with Embodiments 1 to 5.

[Embodiment 6] The liquid crystal display device of the present invention has various uses. Example 1 In this example, a semiconductor device incorporating the liquid crystal display device of the present invention will be described.

Semiconductor devices incorporating a liquid crystal display device include portable information terminals (electronic organizers, mobile computers,
Mobile phones, etc.), video cameras, digital cameras, personal computers, televisions and the like. Examples of these are shown in FIGS.

FIG. 19 (A) shows a mobile phone,
01, audio output unit 2602, audio input unit 2603, display unit 2604, operation switch 2605, antenna 2606
It is composed of The present invention can be applied to the display portion 2604.

FIG. 19B shows a video camera, which includes a main body 2611, a display portion 2612, an audio input portion 2613, operation switches 2614, a battery 2615, and an image receiving portion 261.
Consists of six. The present invention can be applied to the display portion 2612.

FIG. 19C shows a mobile computer or a portable information terminal.
22, an image receiving unit 2623, operation switches 2624, and a display unit 2625. The present invention can be applied to the display portion 2625.

FIG. 19D shows a head-mounted display, which includes a main body 2631, a display section 2632, and an arm section 2.
633. The present invention can be applied to the display portion 2632.

FIG. 19E shows a television, which is a main body 264.
1, speaker 2642, display portion 2643, receiving device 2
644, an amplification device 2645, and the like. The present invention can be applied to the display portion 2643.

FIG. 19F shows a portable book, and the main body 26 is shown.
51, a display unit 2652, a storage medium 2653, an operation switch 2654, and an antenna 2655, and a mini disk (MD) or a DVD (Digital Ver.).
It displays the data stored in the satellite disc) and the data received by the antenna. The present invention can be applied to the display portion 2652.

FIG. 18A shows a personal computer, which includes a main body 2701, an image input section 2702, and a display section 27.
03, and a keyboard 2704. The present invention can be applied to the display portion 2703.

FIG. 18B shows a player that uses a recording medium on which a program is recorded, and includes a main body 2711, a display section 2712, a speaker section 2713, a recording medium 2714,
It is composed of an operation switch 2715. This apparatus uses a DVD (Digital Versat) as a recording medium.
ile Disc), a CD, and the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2612.

FIG. 18C shows a digital camera, which comprises a main body 2721, a display portion 2722, an eyepiece 2723, operation switches 2724, and an image receiving portion (not shown).
The present invention can be applied to the display portion 2722.

FIG. 18D shows a head mounted display of one eye, which comprises a display portion 2731 and a band portion 2732. The present invention can be applied to the display portion 2731.

[0148]

In the conventional liquid crystal display device, it is necessary to invert the polarity once in one frame period, and in order to perform the inversion once in one frame period and to ensure a good display, a driver is required. The power supply voltage of the (source signal line drive circuit, gate signal line drive circuit) had to be set to 15 V or more. Therefore, a large LDD is unavoidable for the TFT constituting the driver, and the manufacturing process is complicated.

In the liquid crystal display device of the present invention, the driving voltage of the driver can be reduced without impairing the image quality by performing the polarity inversion at a long period as described above.

As described above, a liquid crystal display device which can be manufactured with low power consumption and simplified steps can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a waveform of a pixel potential of a liquid crystal display device of the present invention.

FIG. 2 is a diagram showing a pixel inversion method.

FIG. 3 is a diagram showing a waveform of a pixel potential of a conventional liquid crystal display device.

FIG. 4 is a diagram showing a waveform of a pixel potential when a power supply voltage is reduced.

FIG. 5 is a diagram showing a VT curve of a liquid crystal element.

FIG. 6 illustrates a structure of a liquid crystal display device.

FIG. 7 illustrates a structure of a source signal line driver circuit of a liquid crystal display device.

FIG. 8 illustrates a structure of a pixel of a liquid crystal display device.

FIG. 9 is a timing chart showing a driving method of a conventional liquid crystal display device.

FIG. 10 is a diagram showing a first embodiment of the present invention.

FIG. 11 is a diagram showing a second embodiment of the present invention.

FIG. 12 is a plan view of a pixel using IPS.

FIG. 13 is a system block diagram of the present invention.

FIG. 14 illustrates a method for manufacturing a liquid crystal display device of the present invention.

FIG. 15 illustrates a method for manufacturing a liquid crystal display device of the present invention.

FIG. 16 illustrates a method for manufacturing a liquid crystal display device of the present invention.

FIG. 17 illustrates a method for manufacturing a liquid crystal display device of the present invention.

FIG. 18 is a view showing applied equipment of the liquid crystal display device of the present invention.

FIG. 19 is a diagram showing an applied device of the liquid crystal display device of the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680A 680T 680V

Claims (18)

[Claims] 1. A liquid crystal display in which a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. A liquid crystal display device, wherein a polarity of a signal for driving a liquid crystal is inverted in synchronization with a rise or fall of a power supply. 2. A liquid crystal display in which a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. A liquid crystal display device, wherein the polarity of a signal for driving the liquid crystal is inverted at a timing when the entire liquid crystal screen is rewritten. 3. A liquid crystal display in which a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. A liquid crystal display device, wherein a polarity of a signal for driving liquid crystal is inverted at a specific time determined by a user. 4. A liquid crystal display device having a backlight, wherein the polarity of a signal for driving liquid crystal is inverted during a period in which the backlight is turned off. 5. A liquid crystal driven by a voltage between a first electrode provided on the same substrate, a second electrode provided substantially parallel to the first electrode, and the first and second electrodes. 2. A liquid crystal display device according to claim 1, wherein the polarity of the signal for driving the liquid crystal is inverted in synchronization with the rise or fall of the power supply. 6. A liquid crystal driven by a voltage between a first electrode provided on the same substrate, a second electrode provided substantially in parallel with the first electrode, and the first and second electrodes. Wherein the polarity of a signal for driving the liquid crystal is inverted at a timing at which the entire surface of the liquid crystal screen is rewritten. 7. A liquid crystal driven by a voltage between a first electrode provided on the same substrate, a second electrode provided substantially in parallel with the first electrode, and the first and second electrodes. Wherein the polarity of the signal for driving the liquid crystal is inverted at a specific time determined by the user. 8. The liquid crystal display device according to claim 5, wherein the liquid crystal is an IPS (In-Plane Switch).
ing) mode liquid crystal display device. 9. A liquid crystal display device according to claim 1, wherein the polarity inversion cycle is one hour or more. 10. A liquid crystal display in which a plurality of pixel electrodes are arranged in a matrix on a first substrate, a counter electrode is arranged on a second substrate, and a liquid crystal is sandwiched between the first and second substrates. 2. A liquid crystal display device according to claim 1, wherein the polarity of the voltage between said pixel electrode and said counter electrode is not inverted. 11. A liquid crystal driven by a voltage between a first electrode provided on the same substrate, a second electrode provided substantially parallel to the first electrode, and the first and second electrodes. The liquid crystal display device according to claim 1, wherein the polarity of the voltage between the first electrode and the second electrode is not inverted. 12. The liquid crystal display device according to claim 10, wherein the liquid crystal display device has a function of correcting deterioration of the liquid crystal and performing display. 13. A liquid crystal display device according to claim 12, wherein the correction of the deterioration of the liquid crystal is performed by storing the accumulated time of voltage application for each pixel. 14. A television using the liquid crystal display device according to claim 1. Description: 15. A personal computer using the liquid crystal display device according to any one of claims 1 to 13. 16. A portable terminal using the liquid crystal display device according to any one of claims 1 to 13. 17. A video camera using the liquid crystal display device according to any one of claims 1 to 13. 18. A head mounted display using the liquid crystal display device according to claim 1. Description: