JP2002314579A - Communication unit and configuration method for fpga - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication unit in which a circuit scale can be reduced without deteriorating its performance, reliability and extendability. SOLUTION: The communication unit has a common section with a processor and an extension section provided depending on an extended function, the common section is provided with an extended-NP(Network Processor) interface section comprising FPGA(field programmable gate array) that converts a format of data sent/received between the extension section and the processor into a format depending on respective processing forms, and the extension section is provided with a configuration use EEPROM storing configuration data to activate the extended-NP interface section as a prescribed logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device such as a router, and more particularly to a common unit having a processor and the like and an extension unit provided according to an extension function.
(Field Programmable Gate Arrays).

[0002]

2. Description of the Related Art In a printed circuit board incorporated in various devices such as a communication device, for example, an ASIC (Application Specific I / O) is required in order to realize many functions required for the device.
Integrated circuit devices such as integrated circuits) are used. However, the development of ASIC requires a long period of 3 to 6 months, and it is a high-performance and large-scale programmable logic solution in recent years that requires a shortened development period in response to rapidly changing market needs. FP
The use of GA is increasing.

[0003] An FPGA is an EEPROM (Electrically).
A predetermined logic circuit is configured according to a program (configuration data) recorded in an Erasable Programmable Read Only Memory (Erasable Programmable Read Only Memory), and various functions can be realized by changing the program.

On the other hand, in the recent Internet, POS (Packet Over Sone) has been used as its infrastructure (WAN PHY).
t), ATM (Asynchronous Transfer Mode), Eth
Various transmission schemes such as ernet are known. Further, in each transmission system, 100 MHz, 155 MHz,
Since transmission bands such as 622 MHz, 1 GHz, and 2.4 GHz are standardized, a large number of line interfaces (line aggregation) are required for communication devices such as routers in order to support these transmission methods and transmission bands. .

Therefore, recent communication apparatuses generally have a configuration in which a common unit that performs forwarding (routing) processing and the like and an extension unit that is provided according to an extension function are separated, and only the extension unit is replaced. Supports various line aggregations. More specifically, the common unit is a printed circuit board such as a motherboard on which a CPU and a memory are mounted, and the extension unit is a communication board for transmitting and receiving data to and from the outside by POS, ATM, Ethernet, or the like.

FIG. 3 is a block diagram showing the configuration of a conventional communication device.

As shown in FIG. 3, the conventional communication apparatus has a common unit 4 and a plurality of extension units 5 for terminating transmission / reception data, and the common unit 4 and the extension unit 5 are connected to a data transmission line. Are connected via the extension unit-common unit interface 6. In FIG. 3, OC-3 (155 MHz) of POS and Fast Ether
2 shows a configuration in which two extension units 5 are provided corresponding to the network (100 MHz). There are a plurality of types of extension unit-common unit interface 6, and there are more types of line interfaces than the extension unit-common unit interface 6.

[0008] The common unit 4 includes a network processor (hereinafter referred to as NP) 41 for performing forwarding processing of data transmitted and received with the extension unit 5 and data transmitted and received between the extension unit 5 and the NP 41 in respective processing modes. Multiple extensions -N consisting of FPGA to convert to the appropriate format
A P interface unit 42, a plurality of configuration EEPROMs 44 storing configuration data for operating the extension-NP interface unit 42 as a predetermined logic circuit, a transmission buffer function and a reception buffer function, respectively. A plurality of driver / receiver units (Drv / Rc) which are devices for preventing data corruption when data is transmitted and received between the extension unit and the common unit
v) 43. The extension-NP interface unit 42, the driver / receiver unit 43, and the configuration EEPROM 44 are provided corresponding to the plurality of extension units 5, respectively.

The extension unit 5 includes a line interface unit 51 for terminating data transmitted / received according to the line interface, and data transmitted / received between the common unit 4 and the line interface in a format corresponding to each processing mode. A line / common interface unit 54 composed of an FPGA to be converted, and a driver / driver which is provided with a transmission buffer function and a reception buffer function, respectively, and is a device for preventing data corruption when transmitting / receiving data between the extension unit 5 and the common unit 4. Receiver (Drv / Rcv) 53
And a configuration EEPROM 5 storing configuration data for operating the line-common interface unit 54 as a predetermined logic circuit.
2 is provided.

In such a configuration, when the power is turned on, the common unit 4 sets a plurality of configuration EEPROMs.
The configuration data is downloaded from the M44 to the corresponding extension-NP interface unit 42, and each extension-NP interface unit 42 transmits the configuration data when transferring the data from the extension unit 5 to the NP41 or from the NP41 to the extension unit 5. It operates as a conversion circuit for converting data into a transfer destination format.

On the other hand, in the extension unit 5, the configuration data is downloaded from the configuration EEPROM 52 to the line-common interface unit 54, and each extension-NP interface unit 54 is connected from the common unit 4 to the line interface or the line interface. When data is transferred to the unit 4, it operates as a conversion circuit for converting the data into a transfer destination format.

[0012]

As described above, in a conventional communication apparatus, data from various types of line interfaces is terminated, and an FPGA or ASIC is provided at both ends of the interface in order to perform conversion to a common interface. I'm using Since there are a plurality of types of line interfaces, it is difficult to unify the data format between the extension part and the common part.

To convert the data format,
In addition to the configuration shown in FIG. 3, a configuration in which a conversion circuit for converting a data format is mounted only on one of the common unit and the extension unit is also conceivable.

However, when the conversion circuit is mounted only on one of the common part and the extension part, there is a problem that the circuit scale of the conversion circuit becomes large. In particular, when the conversion circuit is mounted only on the common part, every time the extension part is added, the common part configuration EEPROM is added.
Since the contents of the OM must be rewritten, there is a problem that extension cannot be performed easily.

Therefore, in the conventional communication apparatus, as shown in FIG. 3, a conversion circuit (with a medium circuit scale) is mounted on each of the common unit and the extension unit.

In the field of communications, where competition is intensifying in recent years, cost reduction and low power consumption of communication devices are indispensable.
An increase in circuit size and power consumption or deterioration of expandability are issues that must be avoided as much as possible.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and can reduce the circuit scale without deteriorating performance, reliability, or expandability. It is an object to provide a communication device.

[0018]

According to another aspect of the present invention, there is provided a communication apparatus having a common unit having a processor and an extension unit provided in accordance with an extension function. An extension-NP interface unit comprising an FPGA for converting data transmitted and received between the extension unit and the processor into a format corresponding to each processing mode, wherein the extension unit comprises the FPGA
Is provided with a configuration memory in which configuration data for operating the device as a predetermined logic circuit is stored.

At this time, the extension-NP interface unit may be provided corresponding to each of the plurality of extension units. The extension-NP interface unit may be an extension-common interface that is a transmission line for transmitting the configuration data. It may be provided for each of the plurality of extension parts.

On the other hand, an FPGA configuration method according to the present invention provides a configuration for configuring an FPGA provided inside a communication device having a common unit having a processor and an extension unit provided in accordance with an extension function. A method, wherein the common unit is provided in advance with an extension-NP interface unit configured of the FPGA for converting data transmitted and received between the extension unit and the processor into a format according to each processing mode. In this method, when the extension unit is activated, the configuration data corresponding to the type of the line interface of the extension unit is downloaded to the extension-NP interface unit.

At this time, the extension-NP interface section may be provided corresponding to each of the plurality of extension sections, and the common section and the extension section are connected by a transmission line for transmitting the configuration data. Certain extensions-
They may be connected by a common unit interface.

According to the communication device and the FPGA configuration method as described above, the FPGA is mounted only on the common unit, and the configuration data is transferred from the configuration EEPROM of the extension unit to the FPGA of the common unit. The number of components can be reduced without deteriorating the performance, reliability, or expandability of the device.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

As described above, in the conventional communication device, the FPGA and the configuration memory (EEPROM) are respectively mounted on the common unit and the extension unit. The communication device of the present invention has a configuration in which an FPGA is mounted on a common unit, a configuration memory is mounted on an expansion unit, and configuration data is transferred (downloaded) from the configuration memory of the expansion unit to the FPGA of the common unit. is there.

FIG. 1 is a block diagram showing a configuration example of a communication device according to the present invention.

As shown in FIG. 1, the communication device of the present invention comprises:
It has a common unit 1 and a plurality of extension units 2 for terminating transmission / reception data. The common unit 1 and the extension unit 2 are connected via an extension unit-common unit interface 3 which is a data transmission line. Configuration. In FIG. 1, the POS
OC-3 (155 MHz) and Fast Ethe
The configuration in which two extension units 2 are provided corresponding to rnet (100 MHz) is shown. The number of extension units 2 is not limited to two, and is provided according to a plurality of types of line interfaces connected to the communication device as described above.

The common unit 1 includes an NP 11 for performing a forwarding process of data transmitted / received to / from the extension unit 2, and an extension unit 2.
And a plurality of extension-NP interface units 12 composed of FPGAs for converting data transmitted and received between the NP 11 and the NP 11 into a format corresponding to each processing mode, and a transmission buffer function and a reception buffer function. A plurality of driver / receiver units (Drv) which are devices for preventing data corruption when data is transmitted and received between units (Drv
/ Rcv) 13. Note that the extension -N
The P interface unit 12 is provided corresponding to each of the plurality of extension units 2. Further, two driver / receiver units 13 are provided for each of the plurality of extension units 2.

The extension unit 2 has a line interface unit 21 for terminating data transmitted and received in accordance with the line interface, and a transmission buffer function and a reception buffer function. Configuration data for operating the driver / receiver unit (Drv / Rcv) 23, which is a device for preventing data corruption during transmission and reception, and the extended-NP interface unit 12 of the common unit 1 as a predetermined logic circuit are stored. EEPR for multiple configurations
OM22.

It should be noted that two driver / receiver units 23 are provided for each of the plurality of extension units 2, one of which is used for transmitting / receiving data to be forwarded to / from the common unit 1, and the other of which is used for transmitting configuration data. Used to transmit to the common unit 1.

In such a configuration, the extension-NP interface unit 12 mounted on the common unit 1
EEPROM 22 for configuration mounted on
Of the data transmitted and received between the line interface and the NP in accordance with the configuration data stored in the.

There are a plurality of types of extension units 2 for each line interface, and the extension-N of the common unit 1 is provided from the dedicated configuration EEPROM 22 provided for each type.
The contents of the P interface unit 12 are rewritten.

The extension unit 2 has a plurality of types depending on the type of line interface connected to the communication device. The type of line interface is, for example, POS (15
5MHz, 622MHz, 2.4GHz, ...), ATM
(155 MHz, 622 MHz), Ethernet
(10 MHz, 100 MHz, 1 GHz, 10 GHz,
…) Etc.

As described above, the FPGA is mounted only on the common unit 1 and the configuration EEPROM is mounted on the extension unit 2.
EEPR for configuration of extension 1
By transferring the configuration data from the OM to the FPGA of the common unit 1, the number of components can be reduced and the circuit can be simplified without deteriorating the performance, reliability, or expandability of the communication device. Price reduction and low power consumption can be realized.

Next, the operation of the communication device of the present invention will be described with reference to FIG.

FIG. 2 is a flowchart showing a processing procedure of the communication apparatus shown in FIG.

As shown in FIG. 2, first, the power is turned on to the common unit 1 (the turning-on means is arbitrary: step S1), and the common unit 1 is activated (step S2). However, at this stage, the configuration data is not downloaded to the extension-NP interface unit 12 (FPGA).

Next, when the extension unit 2 is mounted on the common unit 1 (step S3), power is supplied from the common unit 1 to the extension unit 2 by connecting the extension unit 2 to the common unit 1 (step S4). ). The extension unit 2 is activated when power is supplied (step S5).

When the extension unit 2 is started, the configuration data for each line interface type is transmitted from the configuration EEPROM 22 mounted on the extension unit 2 via the extension unit-common unit interface 3 to extend the common unit 1. Downloaded to the NP interface unit 12 (step S6), the extension-N
The P interface is configured according to the data (step S7).

Here, if the configuration is successful, the common unit 1 and the extension unit 2 start operating normally (step S8).

On the other hand, when the configuration fails, the common unit 1 and the extension unit 2 turn on the LED for notifying the occurrence of the abnormality to the outside (step S9), and stop the operation while the abnormality is displayed. (Step S10).

[0041]

Since the present invention is configured as described above, the following effects can be obtained.

An FPGA is mounted only on the common section, and the configuration section EEPROM is replaced with the common section FP.
By transferring the configuration data to GA,
The number of components can be reduced without deteriorating the performance, reliability, or expandability of the communication device. Therefore, cost reduction and low power consumption of the communication device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a communication device according to the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of the communication device illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a conventional communication device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Common part 2 Extension part 3 Extension part-common part interface 11 Network processor 12 Extension-NP interface part 13, 23 Driver / receiver part 21 Line interface part 22 Configuration EEPROM

Claims (6)

[Claims] 1. A communication device comprising: a common unit having a processor; and an extension unit provided in accordance with an extension function, wherein the common unit transmits data transmitted and received between the extension unit and the processor. To convert to a format according to the processing form of F
A communication device comprising: an extension-NP interface unit made of PGA; and the extension unit has a configuration memory in which configuration data for operating the FPGA as a predetermined logic circuit is stored. 2. The communication device according to claim 1, wherein the extension-NP interface unit is provided corresponding to each of the plurality of extension units. 3. The communication device according to claim 1, wherein an extension unit-common unit interface, which is a transmission line for transmitting the configuration data, is provided for each of the plurality of extension units. 4. A configuration method for configuring an FPGA provided inside a communication device having a common unit having a processor and an extension unit provided in accordance with an extension function, wherein the common unit is provided in advance. In addition, an extension-NP interface unit for converting data transmitted and received between the extension unit and the processor into a format corresponding to each processing mode, comprising the FPGA, is provided. FP for downloading configuration data corresponding to the type of the line interface of the extension unit to the extension-NP interface unit
GA configuration method. 5. The FPGA configuration method according to claim 4, wherein said extension-NP interface section is provided for each of said plurality of extension sections. 6. The FPGA configuration method according to claim 4, wherein the common unit and the extension unit are connected by an extension unit-common unit interface, which is a transmission line for transmitting the configuration data.