JP2002325255A - Decoding apparatus, decoding method and program for causing computer to perform the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cause respective processing unit of a decoder to operate efficiently and thereby to increase the speed of decoding processing. SOLUTION: One or a plurality of processing units (variable-length decoding units(VLD) 21, inverse quantization units(IQ) 22, inverse scanning units(IS) 23, inverse DCT units(IDCT) 24, and motion compensating units(CM) 25) for performing processing at each processing stage are provided for each stage, and each processing unit determines whether processing by the processing unit for performing processing of subsequent processing stages is possible or not, and outputs processed data to the processing unit which is determined to be able to perform processing based on the determination.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus, a decoding method, and a program for causing a computer to execute the method. More particularly, the present invention aims to efficiently operate each processing unit of a decoder to speed up decoding processing. Decoding device,
The present invention relates to a decoding method and a program.

[0002]

2. Description of the Related Art Conventionally, MPEG (MPEG: moving)
There is a decoding device that decodes an encoded stream obtained by encoding a moving image by a compression encoding method called a picture experts group. As such a decoding device,
In general, variable-length coded data arranged sequentially from the beginning of the coded stream is sequentially decoded one by one, but recently, the coded stream is transmitted to a plurality of processing systems for each predetermined unit. It is also known to perform the decoding process in parallel by sorting.

FIG. 11 is a diagram showing a configuration of a decoding apparatus that performs decoding processing in parallel. As shown in FIG. 1, the decoding device according to the related art includes a stream buffer 101.
, A stream buffer control unit 102, a decoder control unit 103, a plurality of decoders 110, an image memory 12
0, and each decoder 110 includes a variable length decoding unit (VLD) 111 and an inverse quantization unit (IQ) 112
, An inverse scan unit (IS) 113, and an inverse DCT unit (ID
CT) 114 and a motion compensation unit (MC) 115.

[0004] The decoding process performed by the decoding apparatus will be described. First, the stream buffer control unit 102 writes an externally input coded stream into the stream buffer 101. This stream buffer 1
When writing to 01, the position where the start code of each slice forming the encoded stream is written is also written as start code information.

[0005] Subsequently, the decoder control unit 103 refers to the start code information written in the stream buffer 101 and converts the encoded stream written in the stream buffer 101 into slice units for each decoder.
0 is sequentially input. Then, each decoder 110 sequentially decodes the input slice, and sequentially writes the decoded pixel data to the image memory 120.

More specifically, the decoding process by the decoder 110 is a process in which the variable-length decoding unit 111 decodes the variable-length coded data and restores the quantized DCT coefficients. A process of dequantizing the quantized DCT coefficient restored by the variable-length decoding unit 111 to restore the DCT coefficient; a process of the inverse scanning unit 113 scanning the DCT coefficient restored by the inverse quantization unit 112 in reverse; DC
A T unit (inverse discrete cosine transform unit) 114 for inverse DCT transforming the DCT coefficient inversely scanned by the inverse scan unit 113 to restore pixel data; a motion compensation unit 115
Is performed through each processing step of performing motion compensation on the pixel data restored by the inverse DCT unit 114, and writing the motion-compensated pixel data into the image memory 120.

As described above, the decoding apparatus according to the prior art shown in FIG. 11 includes a plurality of decoders 110, and each decoder 110 decodes the coded stream in a slice unit in parallel, thereby providing one processing system. The decoding process is performed at a higher speed than a decoding device having only this.

[0008]

However, in the above-mentioned prior art, a plurality of decoders 110 are provided in parallel, so that each decoder 110 simply performs processing in parallel. There was a problem that there was a limit to achieving this.

That is, the processing time of each processing unit (variable length decoding unit 111, inverse quantization unit 112, inverse scan unit 113, inverse DCT unit 114, and motion compensation unit 115) of the decoder 110 is not always constant. Instead, it depends on the configuration (size) of the data to be processed.

For example, if the data to be processed is empty data such as a macroblock skip or a block skip, the variable length decoding unit 111, the inverse quantization unit 112, the inverse scan unit 113, and the inverse DCT Part 114
Although the processing time of each processing unit is short, the processing time of the motion compensation unit 115 is long. On the other hand, when the data to be processed is data that does not have a space like an intra macro block, the processing time of the motion compensation unit 115 is short, but the variable length decoding unit 111, the inverse quantization unit 112, and the inverse scan Part 113
In addition, the processing time of each processing unit of the inverse DCT unit 114 becomes longer.

As described above, the processing time of each processing unit of the decoder 110 varies depending on the configuration of data to be processed. Therefore, a plurality of decoders 110 are simply connected in parallel as in the above-described decoding apparatus according to the prior art. , It is not possible to operate each processing unit of each decoder 110 efficiently.

More specifically, for example, when one decoder 110 processes a block skip and another decoder 110 processes an intra block, the former decoder 110 performs variable length decoding. The processing of each processing unit of the transforming unit 111, the inverse quantization unit 112, the inverse scanning unit 113, and the inverse DCT unit 114 ends immediately, but the processing of the motion compensation unit 115 does not end immediately.
On the other hand, in the latter decoder 110, the processing of each processing unit of the variable length decoding unit 111, the inverse quantization unit 112, the inverse scan unit 113, and the inverse DCT unit 114 does not end immediately, but the processing of the motion compensation unit 115 The process ends immediately. In other words, the processing unit in which the processing is not being executed immediately in one decoder 110 and the processing is being executed, and the processing in the other decoder 110 is ended immediately and is in a halt state.

For this reason, in the decoding apparatus according to the prior art, each decoder 110 is provided with the same processing unit so that the same processing can be performed in parallel. Each processing unit of the decoder 110 cannot be operated efficiently without a break, and there has been a limit to speeding up the decoding process.

Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, and it is possible to efficiently operate each processing unit of the decoder and to speed up the decoding process. An object is to provide an apparatus, a decoding method, and a program for causing a computer to execute the method.

[0015]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, a decoding apparatus according to the first aspect of the present invention includes a processing step of performing variable length decoding processing on an encoded stream, a processing step of performing inverse quantization processing, a processing step of performing inverse discrete cosine transform processing, and a motion. A decoding device that decodes the encoded stream through a processing step of performing a compensation process, wherein one or a plurality of processing units that perform processing in each processing step are provided for each processing step, and each processing unit is Determining means for determining whether or not processing by a processing unit that performs processing at the processing stage is possible; and output means for outputting processed data to the processing unit determined to be processable by the determining means. It is characterized by having.

Further, the decoding device according to the second aspect of the present invention,
The invention according to claim 1, wherein each of the processing units further includes a notifying unit that notifies that the process is being executed from the start of the process to the end of the process, and the determination unit includes: When the notification unit notifies that the processing is being executed, it is determined that the processing by the processing unit is impossible.

Further, the decoding device according to the third aspect of the present invention
3. The invention according to claim 1, further comprising processing disable control means for controlling a predetermined processing unit selected from among the processing units so that processing is disabled, and wherein the output means performs processing by the processing disable control means. The processed data is output to a processing unit other than the processing unit controlled to be disabled.

Further, the decoding device according to the invention of claim 4 is:
4. The processing unit according to claim 1, 2 or 3, wherein each of the processing units performing the variable-length decoding process omits a processing step of the inverse quantization process and the inverse discrete cosine transform process on the processed data. Determination skipping means for determining whether or not the data is possible, and a skip for skipping and outputting the processed data determined to be omissible by the omission determination means to the processing unit performing the motion compensation processing And output means.

Further, a decoding device according to a fifth aspect of the present invention,
In the invention according to any one of claims 1 to 4, each of the processing units includes a timer unit that counts time from the start of processing, and a time period counted by the timer unit exceeds a predetermined time. In this case, a forced ending means for forcibly terminating the process being executed is further provided.

Further, the decoding device according to the invention of claim 6 provides:
The invention according to any one of claims 1 to 5, further comprising a distribution output unit that distributes and outputs the encoded stream in slice units to each processing unit that performs the variable length decoding process. It is characterized by having.

The decoding device according to the invention of claim 7 is
The invention according to any one of claims 1 to 5, further comprising a distribution output unit that distributes and outputs the coded stream in units of rows to each processing unit that performs the variable length decoding process. It is characterized by having.

Further, the decoding device according to the invention of claim 8 provides:
The invention according to any one of claims 1 to 5, further comprising a distribution output unit that distributes and outputs the encoded stream in macroblock units to each processing unit that performs the variable length decoding process. It is characterized by having.

Further, the decoding method according to the ninth aspect of the present invention,
Each processing step includes a processing step of performing a variable-length decoding process on an encoded stream, a processing stage of performing an inverse quantization process, a processing stage of performing an inverse discrete cosine transform process, and a processing stage of performing a motion compensation process. A decoding method for a decoding device having one or a plurality of processing units for performing processing and decoding the encoded stream through each processing step, wherein each processing unit performs processing in a subsequent processing step. It is characterized by including a determining step of determining whether or not processing is possible and an output step of outputting processed data to a processing unit determined to be capable of processing by the determining unit.

According to a tenth aspect of the present invention, there is provided a program for performing a variable length decoding process on an encoded stream, a process stage for performing an inverse quantization process, a process stage for performing an inverse discrete cosine transform process, and a motion compensation process. One or a plurality of processing units for performing the processing in each processing step for each processing step of performing the processing, and causing a computer to execute a decoding method in a decoding device that decodes the encoded stream through each processing step A program, wherein each processing unit determines whether or not processing by a processing unit that performs processing in a subsequent processing stage is possible; and processing is performed on the processing unit determined to be processable by the determination unit. And outputting an already-processed data to a computer.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a decoding device, a decoding method, and a program for causing a computer to execute the method according to the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is referred to as M
A case where the present invention is applied to a decoding device that decodes an encoded stream called an MPEG2 bit stream encoded according to the PEG2 method will be described. However, an encoded stream encoded according to any image encoding method such as MPEG1 or MPEG4 is described. Can be similarly applied to the decoding of

(Data Structure of MPEG2 Bit Stream) First, the data structure of an MPEG2 bit stream to be decoded by the decoding apparatus according to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram for explaining the data structure of the MPEG2 bit stream, FIG. 2 is a diagram for explaining the correspondence between the MPEG2 bit stream and the screen, and FIG. FIG. 4 is a diagram for explaining codes.

The data of the MPEG2 bit stream is
The data structure is determined in detail so that the decoding device can correctly receive the data.
As shown in the sequence, GOP (Group of Pictur
e) has a hierarchical structure of pictures, slices, macroblocks, and blocks.

The sequence includes one or more GOs.
P and generally corresponds to an encoded signal of one entire video program. The sequence starts with a sequence header and ends with a sequence end. The sequence header includes information related to the entire sequence, such as information indicating the size of an image, the number of frames to be encoded in one second, and the communication speed. included. After the sequence header, function extension information indicating that the signal is an MPEG2 coded signal is inserted, and the input image signal format and the like are specified.

A GOP is an I picture that can be intra-coded, a P picture that performs forward motion compensation using only past frames, and a bidirectional motion compensation using both past and future frames. It consists of one or more pictures among the B pictures to be performed. Note that each G
An I picture is always inserted as the first picture of the OP, and the GOP header includes time stamp information and the like for enabling time alignment with audio or the like at the time of image restoration.

A picture is composed of one or more slices and, as shown in FIG. 2, corresponds to one screen (m pixels × n lines) constituting a moving image signal. The picture header of this picture includes information for identifying I, P, and B pictures, information for specifying the display order of each picture, and the like. In addition, the function extension information following the picture header includes MP frame information such as frame / field structure settings.
Information that specifies a function introduced in EG2 is included.

A slice is composed of one or more macroblocks from left to right, and the slice information includes coded information used in this slice, such as information indicating a quantization characteristic. It should be noted that the arrangement of the macroblocks extends only from left to right, and is not allowed to extend further from top to bottom so that the influence of an error in the communication line does not extend in the vertical direction on the screen.

As shown in FIG.
In the 4: 2: 0 format, four 8 × 8 Y signal blocks, one 8 × 8 Cr signal block, and 8 × 8
, And one Cb signal block. Note that the macroblock information includes information for performing coding control in macroblock units.

As shown in FIG. 2, the blocks are 4: 2:
0 format, 8 × 8 Y signal, Cr signal,
It is composed of DCT coefficient data of one of the Cb signals.
Although this DCT coefficient data is configured as continuous variable-length encoded data (see FIG. 5), each block ends with an EOB (End of Block) code.

As described above, the data of the MPEG2 bit stream has a hierarchical structure consisting of six layers, but is arranged in byte units in each layer of sequence, GOP, picture, and slice (in a bit position which is a multiple of 8 from the head). ) Is inserted. That is, start codes as shown in FIG. 3 are sequentially inserted.

The bit pattern of this start code is
In the MPEG2 bit stream, it never occurs at a position other than the start code position. For this reason, the decoding device that has received the MPEG2 bit stream can perform decoding processing in parallel by a plurality of processing systems for each slice, for example, by detecting the start code.

Although FIG. 2 shows the data structure in the 4: 2: 0 format, the present invention is not limited to this, and the same applies to the 4: 2: 2 format. Can be applied.

(Embodiment 1) In Embodiment 1, each processing step of decoding an encoded stream (variable length decoding processing, inverse quantization processing, inverse DCT processing, and motion compensation processing)
A decoding device having one or a plurality of processing units for performing processing in each processing stage for each case will be described.

FIG. 4 is a block diagram showing a configuration of the decoding apparatus according to the first embodiment. As shown in the figure, the decoding device according to the first embodiment includes a stream input unit 11
, A start code detection unit 12 and a clock generation unit 13
, A stream buffer control unit 14 and a buffer 15
(Stream buffer 15a and start code buffer 15b), picture decoder 16, decoder control unit 17, decoder 20, and image memory 30.

As shown in the figure, the decoder 20 includes a variable length decoding unit (VLD) 21 and an inverse quantization unit (I
Q) 22, an inverse scan unit (IS) 23, an inverse DCT unit (IDCT) 24, and a plurality of motion compensation units (MC) 25 (two in this case). The wiring is connected to each of the plurality of processing units that perform the processing of the subsequent processing stage. Further, each processing unit of the decoder 20 includes a flag F.

Generally, the decoding device according to the first embodiment stores an MPEG2 bit stream input from outside the device via the stream input unit 11 in the stream buffer 15a, and stores the stored MPEG2 bit stream in the stream buffer 15a. Under the control of the decoder control unit 17, the data is distributed to each variable length decoding unit 21 of the decoder 20 for each slice and output, and the image data decoded through the processing of each processing unit of the decoder 20 is stored in the image memory 30. .

Here, the decoding apparatus according to the first embodiment is characterized by processing performed in cooperation with each processing unit of the decoder 20. Specifically, each processing unit performs processing in a subsequent processing stage. By determining whether or not processing by the processing unit that performs the processing is possible, and by outputting processed data to the processing unit determined to be processable by this determination,
Operate each processing unit of the decoder 20 efficiently without a break,
The configuration is such that the speed of the decoding process can be increased.

Next, the processing of each section in the decoding device shown in FIG. 4 will be described. The stream input unit 11 receives an encoded stream (MP) input from outside the apparatus via a recording medium such as a DVD or a network such as the Internet.
EG2 bit stream) to the start code detector 12
Is a processing unit that supplies the data to

The start code detection unit 12 converts the encoded stream input from the stream input unit 11 and predetermined start code information into a stream buffer control unit 14.
Is a processing unit that supplies the data to Specifically, after detecting each start code of the encoded stream shown in FIG. 3, a start including a type of the detected start code and a write pointer indicating a position where the start code is written to the stream buffer 15a. Code information is generated, and the start code information and the coded stream are supplied to the stream buffer control unit 14.

The clock generation unit 13 is a processing unit that generates a predetermined basic clock and supplies this basic clock to the stream buffer control unit 14. The stream buffer control unit 14 converts the encoded stream and the start code information input from the start code detection unit 12 into a stream buffer 15a and a start code buffer 15b of the buffer 15 according to the basic clock supplied from the clock generation unit 13. And a processing unit for writing to each of these.

The stream buffer 15a is a memory such as a DRAM (Dynamic Random Access Memory) for storing the encoded stream input from the stream buffer control unit 14, and stores, for example, an encoded stream of 4: 2: 2P @ HL. When decoding, the VBV buffer size required for such decoding is 47,185,9.
It has a capacity of 20 bits. Start code buffer 1
Reference numeral 5b denotes a memory such as a DRAM for storing start code information input from the stream buffer control unit 14.

The picture decoder 16 controls the start code buffer 15 via the stream buffer controller 14.
b is a processing unit that reads out start code information from b and performs a predetermined decoding process. Specifically, at the start of decoding, the “Sequence heade”
Since the decoding starts from “r”, a write pointer corresponding to “Sequence header code” which is the start code of the sequence is read out from the start code buffer 15b, and based on the write pointer, the “Sequence header code” is read from the stream buffer 15a. And starts decoding.

Then, as in the reading of the “Sequence header”, the picture decoder 16
extention, GOP header, Picture coding exten
“sion” and the like are read from the stream buffer 15a and sequentially decoded. Thus, the picture decoder 1
6 is the first “Slic” from the start code buffer 15b.
When "e start code" is read, all the parameters necessary for decoding the picture are completed.
Then, the picture decoder 16 outputs the decoded picture layer parameters to the decoder control unit 17.

The decoder control unit 17 is a processing unit that distributes the coded stream from the stream buffer 15a to the decoder 20 for each slice unit via the stream buffer control unit 14, and outputs the coded stream. Specifically, based on the picture layer parameters input from the picture decoder 16, the start code information of the corresponding slice is read from the start code buffer 15b. The slice to be decoded by any one of the plurality of variable length decoding units 21 in the decoder 20 has a register indicating the number of the slice included in the encoded stream, and while referring to the register, The picture layer parameters and the slice write pointer included in the start code information are supplied to one of the plurality of variable length decoding units 21.

The decoder 20 reads out the corresponding slice from the stream buffer 15a via the stream buffer control unit 14 based on the slice write pointer input from the decoder control unit 17, and
The processing unit decodes the read slice and outputs the decoded slice to the image memory 30 according to the picture layer parameters input from the decoder control unit 17. This decryption process
Variable length decoding unit 21, inverse quantization unit 22, inverse scan unit 2
3. The processing is performed through processing by each processing unit of the inverse DCT unit 24 and the motion compensation unit 25. The processing of each processing unit of the decoder 20 will be described below.

The variable length decoding unit 21 decodes the variable length coded data included in the coded stream and performs quantization DCT.
This is a processing unit for restoring coefficients. Specifically, based on the slice write pointer input from the decoder control unit 17, the corresponding slice is read from the stream buffer 15a via the stream buffer control unit 14. Then, the macro block is separated from the read slice, the quantized DCT coefficient of each macro block is decoded, and the decoded quantized DCT coefficient is output to the inverse quantization unit 22. When decoding the variable-length encoded data, FIG.
Is referred to.

The variable length decoding unit 21 also decodes parameters such as a prediction mode and a prediction vector, and converts the decoded prediction mode and prediction vector into a motion compensation unit 25.
Output to

The inverse quantization unit 22 is a processing unit that inversely quantizes the quantized DCT coefficient input from the variable length decoding unit 21 to decode the DCT coefficient, and outputs the decoded DCT coefficient to the inverse scan unit 23. is there. At the time of the inverse quantization, a predetermined inverse quantization table is referred to, similarly to the decoding of the variable-length coded data.

The inverse scanning unit 23 is a processing unit that performs inverse scanning of the DCT coefficient input from the inverse quantization unit 22 and outputs the inversely scanned DCT coefficient to the inverse DCT unit 24.
FIG. 4 illustrates a configuration in which the inverse scan process is performed after the inverse quantization process is performed.
It is not always necessary to follow this order, and a configuration in which the inverse quantization process is performed after the inverse scan process is performed may be employed.

The inverse DCT unit 24 performs an inverse DCT transform on the DCT coefficients input from the inverse scan unit 23 to decode pixel data before encoding, and decodes the decoded pixel data into the motion compensation unit 2.
5 is a processing unit that outputs the data to the processing unit 5.

The motion compensation unit 25 performs motion compensation based on the pixel data input from the inverse DCT unit 24 and the prediction mode and the prediction vector input from the variable length decoding unit 21 to perform motion compensation. The processing unit writes the pixel data into the image memory 30.

The pixel data written in the image memory 30 is used for display output and as reference data for another image. That is, the inverse DCT unit 24
In the case where the macroblock input from the image data uses motion compensation, the motion compensator 25 determines whether the pixel data is luminance data according to the prediction vector input from the variable-length decoder 21. The reference pixel is read from the luminance buffer of the memory 30, and if the pixel data is the color difference data, the reference pixel data is read from the color difference buffer of the image memory 30. Then, motion compensation is performed by adding the read reference pixel data to the pixel data input from the inverse DCT unit 24, and the pixel data on which the motion compensation has been performed is written to the image memory 30.

In the decoding device according to the first embodiment, the decoder 20 includes the variable length decoding unit 21, the inverse quantization unit 22, the inverse scan unit 23, the inverse DCT unit 24, and the motion compensation unit 25. A plurality of processing units are provided. Each processing unit is provided with a flag F for notifying that the processing is being executed from the start of the processing to the end of the processing, and processing by the processing unit that performs processing in the subsequent processing stage is possible. Whether or not the data is processed is determined by the flag F, and the processed data is output to the processing unit determined to be processable.

That is, each processing unit notifies the fact that the processing is being executed by setting a flag F from the start of the processing to the end of the processing for each unit of data to be processed, When each of the other processing units is notified that the processing is being executed, it determines that the processing by the processing unit is impossible. For example, the variable length decoding unit 21
Receives data to be processed in units of slices from the stream buffer 15a and outputs data processed in units of macroblocks to the inverse quantization unit 22.
The flag F is set from the start of the variable length decoding process for the first macroblock of the slice to the end of the variable length decoding process for all macroblocks in the slice.

For this reason, the decoder control unit 17, which controls the variable-length decoding unit 21 to output the slice to be processed, terminates the processing, and the variable-length decoding unit 21 in which the flag F is not set is set. , The slices to be processed are sequentially output.

On the other hand, the inverse quantization unit 22 and the inverse scan unit 2
3. The respective processing units of the inverse DCT unit 24 and the motion compensation unit 25 receive the data to be processed in macroblock units and output the data processed in macroblock units to the subsequent processing units. The processing units of the conversion unit 22, the inverse scanning unit 23, the inverse DCT unit 24, and the motion compensation unit 25 start processing for the first block of the macroblock, and end processing for all blocks in the macroblock. During this time, the flag F is set.

For this reason, each processing unit (variable length decoding unit 21, inverse quantization unit 22, inverse scanning unit 23, and inverse DC unit) that outputs data to be processed to these processing units
The T unit 24) outputs the data to be processed in units of macroblocks to a subsequent processing unit in which the flag F has not been set after the process is completed.

As described above, according to the first embodiment, each processing unit of the decoder 20 determines whether or not processing by a processing unit that performs processing in a subsequent processing stage is possible by using the flag F. Since the processed data is output to the processing unit determined to be processable by this determination, each processing unit of the decoder 20 can be operated efficiently, and the decoding process can be speeded up.

That is, in the case of the decoder 110 of the decoding device according to the prior art shown in FIG. 11, while one of the decoders 110 is in the process of executing the processing without terminating immediately, the other decoder 110 is performing the processing. May be terminated quickly and some processing units may be in a halt state. However, in the decoder 20 of the decoding device according to the first embodiment, a subsequent processing unit whose processing is terminated immediately is selected. And outputs the data to be processed, thereby avoiding the occurrence of a processing unit in which the processing is in a halt state, and
Can be efficiently operated, and the speed of the decoding process can be increased.

Further, by increasing the speed of the decoding process, it is possible to improve the processing performance, and it is also possible to smoothly perform variable speed reproduction such as fast forward. Further, by improving the processing performance, it is possible to operate with a clock having a lower frequency, thereby achieving low power consumption.

In the first embodiment, the decoder 20
Although the case where all of the respective processing units are operable has been described, the present invention is not limited to this, and even when a predetermined processing unit selected from the respective processing units is controlled to be unprocessable. The same applies.

In other words, a clock supply unit for supplying a clock to each processing unit in the decoder 20 is provided with control means for controlling a predetermined processing unit selected from each processing unit to be unprocessable. As shown in FIG. 6, the clock supply to one motion compensating unit 25 is stopped to control the motion compensating unit 25 so that processing cannot be performed. In this case, the inverse DCT unit 24
Outputs the data to be processed to the motion compensating unit 25 other than the motion compensating unit 25 that is controlled to be unprocessable. As described above, by stopping the clock supply to the processing unit having the surplus processing capacity, it is possible to reduce the power consumption while maintaining the high speed of the decoding process.

In the first embodiment, the decoder 20
In the above description, the case where two processing units for performing the processing of each processing stage of the decoding processing are provided respectively, but the present invention is not limited to this, and the case where a predetermined processing unit is added The same can be applied to.

That is, for example, as shown in FIG. 7, a variable length decoding unit 21 is added. This makes it possible to perform the processing at a predetermined processing stage in the decoding processing at a high speed, and thus to perform the decoding processing at a higher speed. In particular, the variable-length decoding process requires continuous variable-length decoding of continuous variable-length coded data, but requires more processing time than other processing stages. Adding the decoding unit 21 is extremely effective for speeding up the decoding process.

(Embodiment 2) In the present embodiment 2, the inverse quantization is performed among the decoding processes including the variable-length decoding process, the inverse quantization process, the inverse DCT process, and the motion compensation process. A decoding device that omits the processing and the inverse DCT processing will be described.

FIG. 8 is a block diagram showing a configuration of the decoding apparatus according to the second embodiment. As shown in the figure, this decoding apparatus is different from the decoding apparatus according to Embodiment 1 (see FIG. 4) in that
And a skip line 26 in which the motion compensator 25 and the motion compensator 25 are connected by wiring.

The variable length decoding unit 21 shown in FIG.
Determines whether the processed data is data that can omit the processing steps of the inverse quantization process and the inverse discrete cosine transform process, and the processed data determined to be omissible by this determination. Is output to the motion compensation unit 25 via the skip line 26.

More specifically, in the second embodiment, when the data to be subjected to variable length decoding is empty data due to macroblock skipping, block skipping, or the like, Since the inverse quantization process and the inverse discrete cosine transform process are unnecessary, the processed data is output to the motion compensation unit 25 in order to skip these processes. On the other hand, the processed data determined to be not omissible is output to the inverse quantization unit 22 in which the flag F is not set, as in the first embodiment.

As described above, according to the second embodiment, the variable length decoding unit 21 can omit the processing steps of the inverse quantization process and the inverse discrete cosine transform process on the processed data. It is determined whether the data is appropriate data, and the processed data determined to be omissible by this determination is output to the motion compensator 25 via the skip line 26. The quantization process and the inverse discrete cosine transform process can be omitted, so that the decoding process can be performed at higher speed.

In the second embodiment, the skip line 26 connected from the variable length decoding unit 21 to the motion compensation unit 25
Has been described for each variable-length decoding unit 21, but the present invention is not limited to this, and a plurality of motion compensation units 25 are provided from each of the plurality of variable-length decoding units 21. The same applies to the case where a plurality of skip lines 26 are provided so as to be connected to each other.

In this case, the variable length decoding unit 21 outputs the processed data determined to be omissible to the motion compensation unit 25 in which the flag F is not set via the skip line 26. Thus, similarly to the above-described first embodiment, the motion compensation unit 25 of the decoder 40 can be operated efficiently, and thus the decoding process can be performed at a higher speed.

(Embodiment 3) In Embodiment 3, each processing unit (variable length decoding unit, inverse quantization unit, inverse scan unit, inverse DCT unit, and motion compensation unit) of the decoder is set to a predetermined condition. The following describes a decoding device that forcibly terminates a process being executed on the assumption that data to be processed has an error.

FIG. 9 is a block diagram showing a configuration of a decoding apparatus according to the third embodiment. As shown in the figure, this decoding device is the decoding device according to the second embodiment (FIG. 8).
), Each processing unit (variable length decoding unit 21, inverse quantization unit 22, inverse scan unit 23, inverse DC
The T unit 24 and the motion compensation unit 25) include a timer T that measures time from the start of processing.

Each processing unit of the decoder 50 shown in FIG. 9 stores in advance the maximum processing time required for processing in each processing stage, and the time measured by the timer T exceeds the maximum processing time. In this case, the process being executed is forcibly terminated.

Specifically, in the third embodiment, each processing unit of the decoder 50 determines the maximum processing time calculated based on the maximum size of data to be processed, such as a slice unit or a macro block unit. Remember. And
The timer T of each processing unit starts timing at the same time as the processing is started for the first macroblock or block of the data to be processed, and the time counted by the timer T exceeds the maximum processing time. In this case, the processing being executed is forcibly terminated assuming that there is an error in the data to be processed.

When the process being executed is forcibly terminated, the time measured by the timer T is reset.
The flag F set at the start of the process is also lowered,
Data to be newly processed is input to the processing unit. If the processing is terminated before the time counted by the timer T exceeds the maximum processing time, the processing is started again for the first macroblock or block of the data to be processed, and again. Start timing.

As described above, according to the third embodiment, each processing unit of the decoder 50 includes the timer T for measuring the time from the start of the processing, and the maximum time required for the processing in each processing stage. The processing time is stored in advance, and if the time measured by the timer T exceeds the maximum processing time, the processing being executed is forcibly terminated. It is possible to prevent the processing unit from being hung up, so that the decoding process can be performed quickly and smoothly.

(Embodiment 4) The above-described Embodiments 1 to
3 describes a decoding device that distributes and outputs data to be processed in slice units to each of a plurality of variable length decoding units in a decoder, but the present invention is not limited to this. The present invention can be similarly applied to a decoding device that distributes and outputs a macroblock. Therefore, in a fourth embodiment, a description will be given of a decoding apparatus that distributes data to be processed in macroblock units and outputs the data to each of a plurality of variable length decoding units in a decoder.

FIG. 10 is a block diagram showing a configuration of the decoding apparatus according to the fourth embodiment. As shown in the figure, this decoding apparatus is different from the decoding apparatus according to the third embodiment (see FIG. 9) in that a predecode section 18 is provided instead of the start code detection section 12, and a start code A macroblock boundary buffer 19b is provided in place of the buffer 15a.

The predecoding unit 18 converts the coded stream input from the stream input unit 11 and predetermined macroblock boundary information into a stream buffer control unit 1.
4 is a processing unit to supply. Specifically, it has a decoding table similar to the decoding table of the variable-length decoding unit 21, and refers to this decoding table to determine the macroblock boundary of each macroblock from the encoded stream, that is, E
OB (End Of Block) is detected.

The predecoding unit 18 generates macroblock boundary information including a write pointer indicating the position where the macroblock boundary is written to the stream buffer 19a, and outputs the macroblock boundary information and the coded stream as a stream. Buffer control unit 14
To supply. Note that the stream buffer control unit 14
According to the basic clock supplied from the clock generator 13, the encoded stream and the start code information input from the predecoder 18 are respectively stored in the buffer 1
9 to the stream buffer 19a and the macroblock boundary buffer 19b.

Further, the decoder control unit 17 according to the fourth embodiment transmits the coded stream from the stream buffer 15a to the variable length decoding unit 21 of the decoder 20 for each macroblock via the stream buffer control unit 14.
Output to each distribution. Then, each variable length decoding unit 21 sequentially performs the variable length decoding process on a macroblock basis.

As described above, in the fourth embodiment, since the plurality of variable length decoding sections 21 perform processing by accepting data to be processed in macroblock units, the variable length decoding processing is performed. Can be performed in parallel on a macroblock basis. As a result, the variable length decoding process requiring a long processing time can be performed at a high speed among the respective processing stages of the decoding process, so that the entire decoding process can be performed at a higher speed.

In the fourth embodiment, the code table is referred to when the macroblock boundary is detected by the pre-decoding unit 18, so that it is possible to simultaneously determine whether or not there is an error in the coded stream. When an error is detected, the decoding process for the data in the error portion is stopped in advance, so that the decoding process can be performed quickly and smoothly.

In the fourth embodiment, the case where a macroblock boundary is detected by one predecoding section 17 has been described. However, the present invention is not limited to this. With this arrangement, the present invention can be similarly applied to the case where the macroblock boundaries are detected in parallel.

In the fourth embodiment, the case where the variable-length coded stream is distributed and output in units of macro blocks by referring to the macro block boundary information written in the macro block boundary buffer 19b has been described. However, the present invention is not limited to this. By embedding the boundary information at the position where the macroblock boundary of the coded stream is detected, the coded stream can be converted to the macroblock without providing the macroblock boundary buffer 19b. The same can be applied to the case where the output is distributed in units.

Further, in the fourth embodiment, the case has been described where the coded stream is distributed to each of the plurality of variable length decoding units 21 in macroblock units and output, but the present invention is not limited to this. However, the present invention can be similarly applied to a case where the coded stream is distributed and output for each row, that is, for each set of slices having the same row (row) number.

The decoding methods described in the first to fourth embodiments can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This program can be distributed via a network such as the Internet. Further, this program is recorded on a computer-readable recording medium such as a hard disk, a floppy (registered trademark) disk, a CD-ROM, an MO, and a DVD, and can be executed by being read from the recording medium by the computer.

[0093]

As described above, according to the first aspect of the present invention, one or a plurality of processing units for performing the processing in each processing stage are provided for each processing stage, and each processing unit performs the following processing. It is determined whether or not the processing by the processing unit that performs the stage processing is possible, and the processed data is output to the processing unit that is determined to be processable by this determination. And a decoding device capable of speeding up the decoding process can be obtained.

According to the second aspect of the present invention, each processing unit reports that the processing is being executed from the start of the processing to the end of the processing, and the other processing units perform the processing. When it is notified that the processing is being performed, it is determined that the processing by the processing unit is not possible.
It is possible to obtain a decoding device that can easily and surely determine whether or not processing by a processing unit that performs processing in a subsequent processing stage is possible, and that can speed up decoding processing.

According to the third aspect of the present invention, a predetermined processing unit selected from the respective processing units is controlled so as not to be processed.
Since each processing unit outputs the processed data to the processing units other than the processing unit controlled to be unprocessable,
By stopping the supply of the clock to the processing unit having a surplus processing capacity, there is an effect that a decoding device capable of reducing the power consumption while maintaining the high speed of the decoding process is obtained.

According to the fourth aspect of the present invention, each processing unit that performs the variable length decoding process can omit the processing steps of the inverse quantization process and the inverse discrete cosine transform process on the processed data. It is determined whether or not the data is appropriate data, and the processed data determined to be omissible by this determination is skipped and output to the processing unit that performs the motion compensation processing. In addition, it is possible to omit the inverse quantization process and the inverse discrete cosine transform process, thereby providing a decoding device capable of performing the decoding process at higher speed.

According to the fifth aspect of the invention, each processing unit measures the time from the start of the processing, and forcibly cancels the processing being executed when the measured time exceeds a predetermined time. Therefore, it is possible to prevent each processing unit from being hung up due to an error existing in the encoded stream, and to obtain a decoding device capable of performing decoding processing at high speed and smoothly. The effect is that it can be done.

According to the sixth aspect of the present invention, the coded stream is distributed and output in units of slices to the respective processing units that perform the variable length decoding process.
An effect is obtained in that a decoding apparatus capable of performing variable-length decoding processing requiring a long processing time in each of the decoding processing steps in parallel on a slice basis is obtained.

According to the seventh aspect of the present invention, the coded stream is distributed and output in units of rows to the respective processing units that perform the variable length decoding processing. Among the stages, there is an effect that a decoding device capable of performing the variable-length decoding process requiring a long processing time in parallel on a row basis is obtained.

According to the eighth aspect of the present invention, the coded stream is distributed and output in units of macroblocks to each processing unit that performs the variable length decoding process. An advantage is obtained in that a decoding device capable of performing variable-length decoding requiring a large amount of processing time in parallel in macroblock units in a processing stage is obtained.

According to the ninth aspect of the present invention, each of the one or more processing units provided for each processing stage and performing the processing in each processing stage performs processing in the subsequent processing stage. It is determined whether or not processing is possible, and the processed data is output to the processing unit determined to be processable by this determination, so that each processing unit operates efficiently and the high-speed decoding process is performed. There is an effect that a decoding method capable of achieving the encryption can be obtained.

According to the tenth aspect of the present invention, one or a plurality of processing units provided for each processing stage and performing processing in each processing stage are each provided by a processing unit performing processing in a subsequent processing stage. Determine whether processing is possible,
Since the processed data is output to the processing unit determined to be processable by this determination, a program capable of efficiently operating each processing unit and increasing the speed of the decoding process is obtained. The effect is that it can be done.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a data structure of an MPEG2 bit stream.

FIG. 2 is a diagram for explaining the correspondence between an MPEG2 bit stream and a screen.

FIG. 3 is a diagram for explaining a start code of an MPEG2 bit stream.

FIG. 4 is a block diagram showing a configuration of a decoding device according to the first embodiment.

FIG. 5 is a diagram illustrating a configuration example of a table used for variable-length decoding.

FIG. 6 is a block diagram illustrating a configuration of a decoding device when a predetermined processing unit is controlled to be unprocessable.

FIG. 7 is a block diagram illustrating a configuration of a decoding device when a predetermined processing unit is added.

FIG. 8 is a block diagram showing a configuration of a decoding device according to the second embodiment.

FIG. 9 is a block diagram illustrating a configuration of a decoding device according to Embodiment 3.

FIG. 10 is a block diagram showing a configuration of a decoding device according to Embodiment 4.

FIG. 11 is a block diagram illustrating a configuration of a decoding device according to the related art.

[Explanation of symbols]

 Reference Signs List 11 stream input unit 12 start code detection unit 13 clock generation unit 14 stream buffer control unit 15, 19 buffer 15a, 19a stream buffer 15b start code buffer 19b macroblock boundary buffer 16 picture decoder 17 decoder control unit 18 predecoder unit 20, 40 , 50 decoder 21 variable length decoding unit (VLD) 22 inverse quantization unit (IQ) 23 inverse scan unit (IS) 24 inverse DCT unit (IDCT) 25 motion compensation unit (MC) 26 skip line 30 image memory F flag ( flag) T timer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK13 KK49 MA00 MA23 MC11 MC38 ME01 PP04 PP16 SS08 SS13 UA05 UA33 5J064 AA02 AA03 BA09 BA16 BC14 BD04

Claims (10)

[Claims] 1. A processing step of performing a variable length decoding process on an encoded stream, a processing stage of performing an inverse quantization process, a processing stage of performing an inverse discrete cosine transform process, and a processing stage of performing a motion compensation process. A decoding device that performs one or more processing units for performing processing in each processing stage, and each processing unit is capable of performing processing by a processing unit that performs processing in a subsequent processing stage. A decoding device comprising: a determination unit that determines whether or not the data is processed; and an output unit that outputs processed data to a processing unit determined to be processable by the determination unit. 2. The method according to claim 1, wherein each of the processing units further includes a notifying unit that notifies that the process is being performed from a time when the process is started to a time when the process is completed. 2. The decoding device according to claim 1, wherein when it is notified that the process is being executed, it is determined that the process by the processing unit is impossible. 3. A processing control unit for controlling a predetermined processing unit selected from among the processing units to be incapable of processing, wherein the output unit includes a processing unit that is controlled to be incapable of processing by the processing disable control unit. The decoding device according to claim 1, wherein the processed data is output to a processing unit other than the processing unit. 4. A processing unit for performing the variable-length decoding processing, the processing unit determines whether the processed data is data that can omit processing steps of the inverse quantization processing and the inverse discrete cosine transform processing. And a skip output unit that skips and outputs the processed data determined to be omissible by the omission determination unit to a processing unit that performs the motion compensation process. The decoding device according to claim 1, 2 or 3, wherein: 5. Each of the processing units includes a timer for counting time from the start of the process, and forcibly executes a process being executed when the time counted by the timer exceeds a predetermined time. 5. The decoding apparatus according to claim 1, further comprising: a forced termination unit for terminating the decryption. 6. A distribution output means for distributing and outputting the coded stream in slice units to each processing unit for performing the variable-length decoding process. The decoding device according to any one of the above. 7. The apparatus according to claim 1, further comprising distribution output means for distributing and outputting said coded stream on a row-by-row basis to each processing unit for performing said variable-length decoding processing. The decoding device according to any one of the above. 8. The apparatus according to claim 1, further comprising a distribution output unit that distributes and outputs the coded stream in macroblock units to each processing unit that performs the variable length decoding process. 5. The decoding device according to any one of 5. 9. A processing step for performing a variable-length decoding process on an encoded stream, a processing stage for performing an inverse quantization process, a processing stage for performing an inverse discrete cosine transform process, and a processing stage for performing a motion compensation process. A decoding method in a decoding device that has one or more processing units that perform processing in each processing stage and decodes the encoded stream through each processing stage, wherein each processing unit performs processing in a subsequent processing stage. And a outputting step of outputting processed data to a processing unit determined to be processable by the determination unit. Decoding method. 10. A processing step for performing a variable length decoding process on an encoded stream, a processing stage for performing an inverse quantization process, a processing stage for performing an inverse discrete cosine transform process, and a processing stage for performing a motion compensation process. A program for causing a computer to execute a decoding method in a decoding device that decodes the encoded stream through each processing step, the program including one or more processing units that perform processing in each processing step, A determining step of determining whether or not processing by a processing unit that performs processing of a subsequent processing stage is possible; and an output step of outputting processed data to the processing unit determined to be processable by the determination unit, Which causes a computer to execute the program.