JP2002335275A - Packet processing device - Google Patents

Abstract

(57) Abstract: The present invention relates to a packet processing device, and an object of the present invention is to provide a packet processing device capable of speeding up packet processing. SOLUTION: A packet is discriminated from an input packet using a pattern matching logic 10 in advance,
The packet processor 20 switches the internal state of the packet processor 20 without driving an instruction in accordance with the packet identification information, thereby operating a desired program according to the packet identification information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a packet processing device. With the expansion of the use of systems that interconnect computers and various information processing devices via networks, network expansion or interconnection
There arises a need for interconnecting networks, for example, interconnecting LANs (local area networks) with LANs, and LANs with dedicated lines. Currently, the mainstream of networks constructed in this way is a network based on IP (Internet Protocol).

[0002] IP stands for ISO (Internationa
l Organization for Standa
OSI (Open System)
This is a connectionless protocol corresponding to a network layer in an (mInterconnection) model. Unlike a connection-type protocol that secures a communication path between terminals in advance, in connectionless-type IP communication, a packet relay device that interconnects LANs requires:
By performing relay processing on a packet storing communication data based on information stored in the IP header of the packet, communication between terminals is realized.

Therefore, packet relay processing in an IP network requires packet processing such as destination table search and header rewriting processing. The present invention relates to a packet processing system that performs packet processing such as destination table search and header rewriting processing in a packet relay device in a communication network in which terminals and relay devices are interconnected as described above.

[0004]

2. Description of the Related Art In packet processing by an IP network, a packet relay apparatus determines a packet format of a received packet from header information of the packet, calculates a checksum of a packet header according to each packet format, and checks a destination table. The processing required for relaying a packet, such as a search and rewriting of a packet header, is realized by performing processing on the packet.

Further, in general, a packet relay apparatus is required to implement packet filtering for restricting a specific communication in a network in addition to the processing required for relaying the above-described packet. In order to identify a packet that satisfies packet filtering conditions such as limiting the relay of a packet having a specific destination address, packet discrimination processing according to the packet format is required.

[0006] Regarding the packet processing including the above-described packet discrimination processing, when constructing a packet processing system that can withstand a change in the processing procedure accompanying the revision of the protocol itself after the completion of the apparatus, conventionally, the packet processing is performed by software using a processor. Is common.

By the way, as a tendency of packet processing, the first packet discriminating process at the time of packet reception is as follows.
Despite the large number of comparison patterns for a particular field in a packet for packet discrimination, the dependence of each individual comparison process is weak. On the other hand, in the packet processing after the above-described comparison processing with a large number of comparison patterns is once performed, the dependency between the respective packet discrimination processings is complicated. There is a tendency to perform arithmetic processing and rewriting processing.

In contrast to the above-described tendency of packet processing, the packet processing by the processor is a program control which is a sequential processing, so that the number of comparison patterns is large, and the comparison processing itself is called a dependency between the comparison processings. In a simple case, the number of instruction steps, that is, the processing time is particularly large as compared with the comparison processing circuit using dedicated hardware.

The packet processing by the processor is as follows:
Compared to packet processing by dedicated hardware, it has the advantage of high flexibility that can withstand revisions of the protocol itself and addition of communication services provided by the packet relay device, but the above-described packet discrimination processing at the time of packet reception is fixed. There are many specific processing contents, and it is unlikely that the above-mentioned advantage of high flexibility is exhibited.

Therefore, conventionally, packet processing is performed by software using a processor based on the above-described tendency of packet processing in the packet relay apparatus, the tendency of the number of instruction steps required for packet processing by the processor, and the tendency of comparison processing circuits using dedicated hardware. At this time, in order to reduce the number of instruction steps executed by the processor, as shown in FIG.
Before the packet processing by the processor 20 in FIG. 2 is performed, the received packet is determined to some extent by the comparison processing circuit (hereinafter, referred to as pattern matching logic) 10 using dedicated hardware, and the received packet 1 and the determination accompanying the received packet 1 are determined. The information 1a is transmitted from the pattern matching logic 10 to the processor 20, and the
By performing 0, packet processing that requires high flexibility thereafter is executed, thereby efficiently executing packet processing while reducing the number of instruction steps executed by the processor.

FIG. 8 is a diagram showing a configuration of packet processing using a conventional processor. In the figure, reference numeral 10 denotes a pattern matching logic for receiving a packet 1 and performing a comparison process. In the processor 20, reference numeral 11 denotes a general-purpose interface connected to the bus 2, and reference numeral 12 denotes a control unit, which comprises an instruction decoder 12a and a program counter 12b. 13 is a general-purpose register, 14 is a computing unit, 15
Is an external bus buffer connected to the arithmetic unit 14, and 16 is a flag register connected to the arithmetic unit 14.

The configuration of the processor 20 is the same as that of a normal processor. The external bus buffer 15 is a bidirectional buffer, and the flag register 16
Is put into a register, and a status is issued for the result. The packet 1 is input to the general-purpose register 13 via the general-purpose interface 11, is operated by the arithmetic unit 14, and a result reflecting the result is returned to the bus 2 again and exits as the packet 1.

[0013]

However, in the conventional configuration shown in FIG. 8, in the packet relay device, the processor 20 registers the packet discrimination information 1a output from the pattern matching logic 10 through the general-purpose interface 11 in the register. By issuing an instruction conforming to the architecture of the processor 20, such as an access instruction or a memory access instruction, the processor accesses the packet identification information and executes subsequent packet processing according to the packet identification information. Therefore, there is a problem that the processor 20 consumes the number of instruction steps to access the packet identification information.

Unlike the processing directly related to the packet processing, such as the calculation of the header checksum, it is the packet relay apparatus that the processor 20 executes the processing not directly related to the packet processing by the instruction. When the processing time that the processor 20 can execute on one packet is limited by the throughput of the packet processing,
Lowering of packet processing contents executable by the processor 20;
That is, the flexibility of the packet relay device is reduced. From another point of view, if the processor 20 executes a process that is not directly related to the packet processing by an instruction, the processor 20 needs more processing time to execute the same packet processing content, It is a cause that cannot be speeded up.

The present invention has been made in view of the above problems, and has as its object to provide a packet processing device capable of speeding up packet processing.

[0016]

(1) FIG. 1 is a block diagram showing the principle of the present invention. 8 are denoted by the same reference numerals. 8 differs from the conventional configuration shown in FIG.
, And the program bank value is directly input to the control unit 12 in the processor 20 via the program bank value signal line 4. Other configurations are the same as those in FIG. In the figure, a solid line is a data line in the processor, and a broken line is a control line in the processor.

In the present invention, in order to solve the problem of consuming the number of instruction steps, as shown in FIG. 1, an output relating to packet discrimination information of the pattern matching logic 10 is directly input to the control unit 12 in the processor 20. ing. Then, the processor 20 changes the internal state of the processor 20 according to the packet discrimination information without executing the instruction by the arithmetic unit 14. This realizes packet processing according to the packet discrimination information without consuming the number of instruction steps.

Here, the internal state of the processor 20 is as follows.
For example, it is a program bank value indicating a bank value of a memory that stores a program executed by the processor 20 when a packet arrives at the processor as a trigger. The apparatus designer stores in advance in the respective program banks each program for performing packet processing executed by the packet relay apparatus according to the packet identification information, and the pattern matching logic 10 determines in advance the apparatus designer according to the packet identification result. And outputs the corresponding program bank value determined by.

The processor 20 receives a program bank value from the program bank value signal line 4 instead of a general-purpose interface in which access processing by an instruction occurs, and the control unit 12 in the processor 20 executes the received packet. Switches the program bank value.

As a method of setting the corresponding program bank value in advance by the device designer in accordance with the above-mentioned packet discrimination result, for example, a received packet is transmitted by TCP (Transmission) which is a kind of IP transport layer protocol.
pattern control logic), the pattern matching logic 10 determines from the header information of the received packet, the program bank value output by the pattern matching logic 10 in response to the determination result. There is a method that the device designer sets at the time of device startup.

With this configuration, the processor receives the packet data and switches its internal state without driving the instruction, so that the desired program according to the packet discrimination information without consuming the number of instruction steps can be obtained. Can be operated. This makes it possible to perform packet processing with the same flexibility at higher speed.

(2) The invention according to claim 2 is characterized in that the pattern matching logic is configured using a CAM and a RAM. According to this configuration, the pattern matching logic can have flexibility such that the matching logic can be changed after the device is completed, as compared with the case of dedicated fixed hardware.

(3) The invention according to claim 3 is characterized in that the packet discrimination information is stored in an operation data of the packet processor.
It is characterized by not operating. With this configuration, the program operation memory can be used efficiently by using the operation / non-operation control signal as a part of the packet discrimination information.

(4) The invention according to claim 4 is characterized in that the packet discrimination information is a program bank of the packet processor. With this configuration, a desired program is driven from among the program banks according to the packet identification information, so that the program can be flexibly executed on the received packet data without consuming the number of instruction steps. It becomes possible.

(5) The invention according to claim 5 is characterized in that the pattern matching logic is composed of fixed hardware which cannot change the processing procedure of the packet discriminating process after completion of the device and comparison logic of the packet discriminating process after the device is completed. Changeable CA
M and RAM, and the CAM and RAM correct the output packet discrimination information of the fixed hardware.

With this configuration, a circuit with higher flexibility can be realized by configuring the pattern matching logic using the fixed hardware, the CAM, and the RAM determination circuit.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows a block diagram of a packet relay device as an example equipped with the packet processing device of the present invention. Packets received from the physical link
The data is converted into a data stream by the driver / receiver 25 of the physical layer, and is extracted as a packet through the framer 26. The packet received in this manner is subjected to packet classification processing such as relay destination determination in the packet classification unit 22 to determine a destination and necessary quality control, and is switched via the switch interface 24 to the switch unit 3.
Deliver the packet to 0. Here, the packet classifying unit 22 is a part according to the present invention, and the CAM and the RAM
And a packet engine 22a.

The switch unit 30 relays the packet to an output destination specified by the classifying process. The line card 21 that has received the packet relay from the switch unit 30 via the switch interface 24 enqueues in the output queue determined based on the result of the packet classification, and is determined based on the packet scheduling result when the physical link becomes free. The packet in the queue is converted into a format corresponding to the physical link by a framing process and a physical layer process and transmitted to the physical link.

The packet processing system according to the present invention uses a packet classifying unit 2 in this switching router.
2, the protocol type of the packet is determined, the destination is determined based on the packet header, and information on where to relay to the switch interface 24 / switch unit 30 is sent together with the packet. Applicable quality control is determined accordingly.

FIG. 3 is a block diagram showing a first embodiment of the present invention.
It is constituted by a RAM. 1 are denoted by the same reference numerals. A feature of the present invention is that the pattern matching logic 10 includes a CAM (Content Add).
resable Memory) and RAM (Rand)
am Access Memory).

In the figure, 41 is a CAM, 43 is a RAM
It is. Reference numeral 42 denotes a CAM control unit connected to the CAM 41, and includes a packet data extraction unit 42a therein. Data is sent from the CAM controller 42 to the CAM 41 via the data line 42b, and the CAM 41 sends the address via the match address line 41a and the hit / miss hit information via the hit / miss hit line 41b. This is provided to the CAM control unit 42.

Reference numeral 44 denotes a RAM control unit connected to the RAM 43. An address is sent to the RAM 43 via an address line 44a, and data is supplied from the RAM 43 to the RAM control unit 44 via a data line 43a. Also,
A hit / miss hit signal is supplied from the CAM control unit 42 to the RAM control unit 44 via a hit / miss hit line 46, and an address signal is supplied to the RAM control unit 44 via a match address line 47.
It is provided to the AM control unit 44.

The packet 1 is a packet data extraction unit 42a
Is output from the CAM control unit 42 via the CAM control unit 42 and supplied to a FIFO (first-in first-out) 45.
The packet arrival signal is transmitted from the packet data extraction unit 42a via the packet arrival signal line 48 to the FIFO 45.
Given to.

The packet arrival signal output from the FIFO 45 is supplied to the control unit 12 of the processor 20, and the packet enters the general-purpose interface 11 of the processor 20 via the bus 2 and is input into the processor 20. Also, a program bank value signal is sent from the RAM control unit 44 via the program bank value signal line 49 to the processor 20.
And a processor operation control signal is supplied to the processor 2 via a processor operation control signal line 50.
0 is provided to the control unit 12.

FIG. 4 shows a CA according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating the contents of an M / RAM. Unlike a RAM that outputs data stored at an address by specifying an address, the CAM searches the stored content by specifying data (search key data) and finds a matching entry data. If there is a hit (hit), the memory device outputs an address value storing the entry data.

Since the comparison processing between each entry data and the search key data is processed in parallel by dedicated hardware,
The CAM can search for the corresponding search key data at high speed. Further, as the CAM entry data, in addition to the “0” and “1” bits, “X” (Dont
Care) bits also have a generally definable function.

In the embodiment shown in FIG. 3, the pattern matching logic 10 is constituted by the CAM 41 and the RAM 43. The packet processing system shown in the figure transmits a packet received by the network interface 5 to the CAM control unit 42 of the pattern matching logic 10. At this time, the network interface 5 transmits a packet arrival signal to the CAM controller 42 via the packet arrival signal line 48 in synchronization with the packet data, and the CAM controller 42 detects the arrival of the packet based on the packet arrival signal. can do. Thereafter, the FIFO 45 and the processor 20 also detect the arrival of the packet based on the packet arrival signal, and execute packet processing on the received packet 1 using this as a trigger.

Upon receiving the packet, the CAM control unit 42
A part to be the search key data of the CAM is extracted from the packet data, and the data is extracted through the data line (search key) 42b.
A search is instructed to AM41. The packet data extraction unit 42a in the CAM control unit 42 extracts search key data from the above-described packet data to the CAM 41. As an extraction method, the packet data extraction unit 42a
For example, the data in the fixed area may be extracted from the beginning of the packet data as search key data, or the offset from the beginning of the packet data may be extracted based on a value in a register specified in advance by a device designer. , Can also be extracted.

When the CAM 41 receives the search key data,
The entry data corresponding to the search key data is searched, and if there is the corresponding entry data, its address value (match address) and the value indicating the hit are matched address line 41a and hit / miss hit line 41, respectively.
b to the CAM control unit 42. Here, the correspondence between the extracted packet data and the entry data in the CAM 41, and the match address and the RAM
The correspondence with the data will be described later.

Next, if the hit / miss hit line 46 indicates a hit, the RAM control unit 44 that has received the match address uses the received match address as it is in the RA.
The data is provided as an address to the M43, and data corresponding to the address is received from the RAM 43. At this time, since a certain processing time is required for the above-described series of read access processing to the RAM 43, the FIFO 45 stores the packet data and the packet arrival signal during the processing time, and the processing time and the RAM control unit 44 described above. Synchronize with the output data from.

Next, the RAM control unit 44 that has received the data from the RAM 43 determines the program bank value and the processor operation control signal based on the value in the data, and transmits them to the processor 20. The program bank value is equivalent to the contents described above, and the processor operation control signal is a control signal for controlling the instruction driving operation itself of the processor.
When the processor operation control signal indicates non-operation, the processor 20 does not execute the instruction driving operation even when receiving the packet arrival signal. This means that for a particular packet,
When execution of the program processing is not desired, “NOP” (No Operation) is executed in a specific program bank.
n) It is possible to avoid inefficient use of a program bank such as filling with an instruction. According to this, by making the operation / non-operation control signal a part of the packet discrimination information, the program operation memory can be used efficiently.

As described above, according to the present invention,
By making the pattern matching logic using CAM and RAM, the pattern matching logic has the flexibility that the matching logic can be changed after the device is completed, as compared to the case of dedicated fixed hardware. Can be.

The processor 20 that has received the packet arrival signal from the packet arrival signal line 48 switches the program bank 17 according to the processor operation control signal and the value of the program bank signal from the program bank value signal line 49, and receives the received packet data. By driving a desired program corresponding to the received packet data, the program can be flexibly executed according to the received packet data without consuming the number of instruction steps.

The correspondence between the extracted packet data and the entry data in the CAM 41 and the correspondence between the match address and the data in the RAM will now be described with reference to FIG.

The content of the CAM and the content of the RAM in FIG. 4 indicate that the received IP packet is a UDP (User Datagram).
m Protocol), the program bank whose program bank value is “5” is assigned to the processor 20.
Is the entry content to instruct to execute.
Here, UDP is a protocol of a transport layer which is an upper layer as a protocol stack of an IP packet.

Whether the received packet is a UDP packet can be determined by referring to a protocol field present at a fixed position (offset) from the head of the header in the IP header, and its value is 17. In the figure, the protocol field in the IP header of the search key data extracted from the packet data is 17. this is,
In the search key data extracted from the packet data, FIG.
Indicates that it corresponds to the position indicated by.

When the CAM 41 performs a search using the search key data shown in the figure, the address value = 0x0000 is hit from the entry data content. Here, “0x” is 16
Represents hexadecimal. Next, the RAM data of the address value is stored in RA
Referring to the M control unit 44, the values are the operation / non-operation flag = 1 and the program bank value = 5. By notifying the data to the processor 20 via a signal line, the processor 20 The program with the program bank value = 5 is executed. It should be noted that “High” in FIG.
"est Priority" indicates the priority between hit entries when a plurality of entry data hits the search key data. In the case of the figure, when multiple hits occur, the CAM 41 uses a smaller address value as a match address. Means to output.

The device designer can set the CAM and RAM entry data and code the program to be stored in the program bank in advance based on the correspondence between the CAM / RAM function and the packet data. . As described above, instead of configuring the pattern matching logic 10 with dedicated fixed hardware,
By using a CAM / RAM, there is an effect that the pattern matching logic 10 can have the flexibility of changing the matching logic after the device is completed.

Although the program bank is stored in the processor 20 in the embodiment of FIG. 3, the program bank is stored in a storage device such as a memory outside the processor, and the processor 20 stores the program therefrom. It may be configured to read.

In the embodiment of FIG. 3, the processor 20 transmits packet data to the general-purpose interface 1.
1, the packet data may be read not through the general-purpose interface but through some dedicated packet data receiving interface.

In the embodiment of FIG. 3, all packet discrimination information (the processor operation control signal and the program bank value in the embodiment of FIG. 3) is used to issue an instruction (consumption of each step number). The processor receives the packet identification information via the interface which is not accompanied by the processor. For example, the processor receives some packet identification information via the interface accompanied by instruction issuance (consumption of the number of steps) and issues some packet identification information by the instruction. A configuration is also possible in which reception is performed via an interface that does not involve (consumption of each step number). The fact that the processor receives the packet discrimination information in a general-purpose data format has a disadvantage in terms of speeding up packet processing, but has an advantage in terms of the degree of freedom of transmitted information, and the two have a complementary relationship. is there.

FIGS. 5 and 6 are block diagrams showing a second embodiment of the present invention, and FIG. 7 is a diagram showing the contents of a RAM entry in the pattern matching logic in FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals. In the embodiment shown in FIGS. 5 and 6, the pattern matching logic is the same as that of the first embodiment shown in FIG.
An embodiment in which an M / RAM is configured and combined with a fixed hardware packet determination circuit, and a correction function of the output value of the packet determination information of the fixed hardware packet determination circuit is added to the CAM / RAM configuration circuit. It is. 5 to 6 indicate the same connection points.

As a packet processing processor for receiving the output value of the pattern matching logic, a packet processing processor having a pipeline configuration as shown in FIG. 6 is configured to constitute the entire packet processing system.

In FIG. 5, reference numeral 60 denotes a fixed hardware packet judgment circuit provided in the pattern matching logic 10. The fixed hardware packet determination circuit 60 receives a packet and a packet arrival signal from the network interface 5 and outputs packet determination information. Here, #a, #b, #
An example of outputting three pieces of packet identification information up to c is shown.
The packet determination information #a, #b, #c is input to the multiplexing unit (MUX) 51.

On the other hand, in addition to the program bank value signal and the processor operation control signal, the RAM control section 44 outputs packet discrimination information correction signals #a, #b, #c. These packet discrimination information correction signals #a, #b, and #c are input to the multiplexing unit 51. The multiplexing unit 51 is configured to correct the packet discrimination information #a, #b, #c output from the fixed hardware packet discrimination circuit 60 with the packet discrimination information correction signals #a, #b, #c. .

In FIG. 6, reference numeral 70 denotes a packet processing unit, which comprises a plurality of packet processing processors 80. Here, the packet processor is Prc # 1
ＰPrc # 3. Processor 80 is a CAM
81, RAM 82, access control unit 83, internal register 84, arithmetic unit 85, program 86, control unit 8
7, an internal state 88, a timing control section 89, a data input section 90, a packet access register 91, and a data output section 92. This configuration is different from other Prc #
2, Prc # 3.

The packet identification information #a, #b, #c (output of the multiplexing unit 51) and the packet data from the pattern matching logic 10 enter the data input unit 90, and the packet arrival signal enters the timing control unit 89. , The program bank value signal and the processor operation control signal are Prc
It is in the control unit 87 of # 1. The processors 80 are connected in series to form a pipeline. This pipelined packet processor is proposed by the applicant in Japanese Patent Application No. 11-158514.

The feature is that a packet data access mechanism for accessing packet data at high speed is constructed by providing a packet access register 91 which is a register for directly taking in packet data in the processor 80, and a read / write process for packet data is performed. By eliminating the overhead of (1), the flexibility that a processing procedure can be described by a program and the high-speed packet processing are realized.

The above-described packet processor 80
When one packet is focused on by connecting a plurality of serially connected and using the packet processing result output of the previous packet processing processor as the data input of the next packet processing processor, the whole packet processing is performed by the serially arranged processors. It is easy to adopt a configuration of executing by pipeline processing.

By configuring such a pipeline processing system, even if the desired packet processing is complicated and the number of instruction steps increases when a program is described, the processing steps are performed for each processor constituting the pipeline. By dividing the processing so that the processing amount per processor is equal to or less than a certain value, it is possible to increase the packet processing throughput. Further, in the above configuration, the internal state 88 of the processor is taken over between the packet processing processors to the next processor.

In the packet processing system shown in FIG. 6, a program bank signal, which is an output value of the pattern matching logic, and a processor operation control signal are directly input to the control unit 87 of the first packet processing processor having a pipeline configuration. And while switching its internal state,
By taking over the internal state of the first packet processor 80 to the internal state of the next packet processor, a plurality of packet processors 80 can execute a series of packet processing programs.

On the other hand, the packet discrimination information #a, #b, #c, which is the output value of the pattern matching logic 10, is received by the packet processor 80 as a general-purpose packet accompanying parameter via the bus shown in FIG. , The packet processor 80 can also execute a program process based on the information. In order for the packet processor 80 to refer to the general-purpose packet accompanying parameters, an instruction is issued, but there is an advantage that the packet processor 80 has a high degree of freedom in interpreting the received data.

The operation of the pattern matching logic will be described below. In the pattern matching logic 10 shown in FIGS. 5 and 6, at the same time that the CAM / RAM executes the comparison processing of the packet data, the newly provided fixed hardware packet determination circuit 60 also executes the comparison processing of the packet data. Fixed hardware packet judgment circuit 60
Since the circuit is created by optimizing the circuit only for the packet data and the packet format for the logical comparison processing itself, there is an advantage that the circuit scale is smaller than that of the CAM and an advantage that the multi-stage comparison processing can be performed. On the other hand, the comparison process cannot be changed after the device is designed.

Therefore, the pattern matching logic 10
As shown in FIG. 7, the correction information for the packet determination information #a, #b, and #c output from the fixed hardware packet determination circuit 60 is stored as an entry in the RAM of FIG. The value can be changed flexibly to some extent after the device is designed. In the configuration of the RAM shown in FIG. 7, packet identification information correction enable data and packet identification information correction data are stored in pairs for each of a to c with respect to an address value. The packet discrimination information correction signal shown in FIG. 5 includes packet discrimination information correction enable data and packet discrimination information correction data. The operation / non-operation and program bank values are also stored.

By configuring the pattern matching logic using the fixed hardware packet determination circuit 60 and the CAM / RAM determination circuit as in the above-described combination, the advantages of the above-described two circuits can be exhibited more flexibly. Becomes possible.

The contents of the RAM entry of the pattern matching logic 10 of FIGS. 5 and 6 and the method of correcting the output of the fixed hardware packet determination circuit 60 will be specifically described below.

In FIG. 5, for example, the fixed hardware packet determination circuit 60
#B and #c are output. For example, packet identification information #
When it is desired to correct the results of a and #b, the device designer sets entry data such as an address value 0x0000 in the RAM. The meaning of the address value 0x0000 of the RAM in FIG. 7 means that the entry of the address value hit by the CAM 41 is, for example, the packet discrimination information correction enable (Ena).
ble) If # a = 1 (enable), it means that the packet discrimination information #a, which is the output value of the fixed hardware packet discrimination circuit 60, is changed to the value of the packet discrimination information correction data #a.

In the case of the entry data having the address value 0x0000 in the RAM of FIG. 7, the multiplexing unit 51 receives the packet discrimination information #a, #b, #c and the packet discrimination information correction signals #a, #b, #c. Then, the packet identification information #a is changed to “5” and the packet identification information #b is changed to “10”,
The output value of the fixed hardware packet determination circuit 60 is transmitted to the packet processor 80 as it is without changing the packet determination information #c.

By configuring the pattern matching logic 10 and the packet processing processor 80 as described above, a plurality of packet processors have high flexibility in interpreting the packet determination information according to the packet determination information of the pattern matching logic. A series of packet processing can be executed at high speed.

[0070]

As described above, according to the present invention,
The following effects can be obtained. (1) According to the first aspect of the present invention, the processor receives the packet data and switches its internal state without driving the instruction, thereby following the packet discrimination information without consuming the number of instruction steps. A desired program can be operated. This makes it possible to perform packet processing with the same flexibility at higher speed.

(2) According to the second aspect of the present invention, the pattern matching logic is provided with the flexibility that the matching logic can be changed after the device is completed, as compared with the case of dedicated fixed hardware. Can be.

(3) According to the third aspect of the invention, by using the operation / non-operation control signal as a part of the packet discrimination information, the program operation memory can be used efficiently.

(4) According to the fourth aspect of the present invention, by driving a desired one of the program banks in accordance with the packet discrimination information, the received packet data can be processed without consuming the number of instruction steps. And the program can be executed flexibly.

(5) According to the fifth aspect of the present invention, by configuring the pattern matching logic using the fixed hardware, the CAM, and the RAM determination circuit, a circuit with higher flexibility can be realized.

As described above, according to the present invention, it is possible to provide a packet processing apparatus capable of speeding up packet processing.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of a packet relay device according to the present invention.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a CAM / RAM according to the first embodiment of the present invention;
It is a figure which shows the content of.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing the contents of a RAM according to the second embodiment.

FIG. 8 is a diagram showing a configuration of a packet processing using a conventional processor.

[Explanation of symbols]

 1 packet 2 bus 3 packet arrival signal line 4 program bank value signal line 10 pattern matching logic 11 general-purpose interface 12 control unit 12a instruction decoder 12b program counter 13 general-purpose register 14 arithmetic unit 15 external bus buffer 16 flag register 17 program bank 20 Processor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Yasuyuki Umezaki Inventor 3-2-2-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Mitsuharu Wakayoshi Hakata, Fukuoka City, Fukuoka Prefecture 3-22-8, Hakata Ekimae, F-term F-term in Fujitsu Kyushu Digital Technology Co., Ltd. (reference) 5K030 HA08 HB19 KA01 KA02 KA05 5K033 AA02 CC01 DB12 DB14 5K034 AA02 EE11 FF01 HH25 HH63

Claims (5)

[Claims] An input packet is discriminated in advance using a pattern matching logic, and a packet processor switches the internal state of the packet processor without driving an instruction according to the packet discrimination information. A packet processing device for operating a desired program according to packet discrimination information. 2. The method according to claim 1, wherein the pattern matching logic is a CA.
2. The apparatus according to claim 1, wherein the memory is configured using M and a RAM.
The packet processing device according to claim 1. 3. The packet processing device according to claim 1, wherein the packet discrimination information is set to an operation / non-operation of the packet processor. 4. The packet processing apparatus according to claim 1, wherein the packet discrimination information is a program bank of the packet processing processor. 5. The pattern matching logic is composed of fixed hardware that cannot change the processing procedure of packet discrimination processing after device completion, and CAM and RAM that can change comparison logic of packet discrimination processing after device completion. 3. The packet processing apparatus according to claim 2, wherein the CAM and the RAM correct the output packet discrimination information of the fixed hardware.