JP2002518825A - An etching process for producing substantially undercut-free silicon on an insulator structure - Google Patents

Abstract

Abstract: A reactive ion etching process in which the ion density is reduced to limit ion charging in recesses of various sizes so as to perform a uniform etching in a vertical direction is used as a finishing etching step. A method is disclosed for performing anisotropic plasma etching on a silicon-on-insulator substrate, which substantially eliminates undercut.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] Field of the Invention The present invention relates, silicon-on-insulator (silicon on insulator; SOI)
An improved method of anisotropically etching a semiconductor material that substantially eliminates undercuts in the structure.

2. Description of the Related Art An important step in manufacturing silicon-containing devices, including semiconductor chips, is to etch various layers, such as polysilicon and silicon, that make up the completed semiconductor chip or thin film circuit.

It has been found that SOI structures such as trenches cause undercuts when etched down to the silicon-insulator interface.

[0004] The individual structures to be etched into the substrate are usually so-called masking layers, for example,
Defined by an etching mask applied to the silicon substrate via a photoresist layer, the masking layer remains on the substrate after being exposed to UV light and subsequently developed, thereby protecting the silicon layer from the etchant.

[0005] Anisotropic etching techniques require the formation of a well defined laterally defined recess (trench through a contact) in silicon. Such deep recesses must have sidewalls that need to be as vertical as possible.

[0006] The edges of the masking layer covering the silicon substrate regions that are not to be etched are not undercut to maximize the lateral accuracy of the mask-to-silicon structural transition. Thus, it is necessary to ensure that the etching can only proceed at the bottom of the structure and not laterally on the already made sidewalls of the structure.

To this end, it has been proposed to etch features on a silicon substrate using a plasma etching method. In this method, in a reactive gas mixture in a reactor, with the aid of discharge, chemically reactive species and charged particles (ions and electrons) are formed. The positively charged cations thus generated are accelerated toward the substrate by the induced electric bias by applying an RF electric field to the silicon substrate, and fall on the substrate surface in a substantially vertical manner, and react. Drives the chemical reaction between the reactive plasma species and the silicon on the etching base.

[0008] Because the cations fall almost vertically, the etching should proceed progressively toward the sidewalls of the structure, and optimally not at all.

It is known to use fluorine-based, non-hazardous and stable reactive gases in the process. However, such reactive gases allow for very high etch rates and very high selectivity between the substrate to be etched and the mask,
It shows a remarkably isotropic etching behavior.

The fluorine radicals generated in the plasma exhibit a high spontaneous reaction rate where the structural edges (transverse surfaces) are rapidly etched, and therefore the mask edges, undercuts of the trench sidewalls, and insulator interfaces Undercutting of the upper trench becomes undesirable.

Various proposals have been made to solve the problem of undercut. One such method involves providing a protective layer, e.g., in U.S. Pat. A reactive etching technique is disclosed. The gate sidewalls are protected from etching by applying a layer of polytetrafluoroethylene.

In US Pat. No. 5,501,893, hereinafter referred to as the Bosch process, a silicon substrate is first subjected to a plasma etching step, after which the exposed areas are covered with a polymer layer forming a temporary etching stop. An etching process is disclosed in which a second polymerization stage is performed. These two steps constitute a process by alternately repeating the etching step and the polymerization step.

In an alternative method described in detail herein, the sidewalls are covered with one or more polymer-forming compounds that are simultaneously present in the plasma during etching, whereby
A polymer film protects the walls. Since the polymer film is also formed on the etching base, a stable drop of ions should separate the film from the polymer and allow etching there. However, it is formed partially from the fluorine carrier itself, or by splitting the fluorine groups, or by intentionally added unsaturated compounds or corroded organic photoresist mask material. The resulting polymer-forming compound added to the plasma is
The disadvantage of occurring as a recombination partner for fluorine groups exists in connection with the above technique. This reverse reaction, whose goal is chemical equilibrium, consumes a significant portion of the fluorine required for etching, while at the same time losing the corresponding components of the polymer-forming material required for sidewall passivation. Therefore, the etching rate that can be achieved by this method is significantly reduced.

Since the etching fluorine group thus depends on the unsaturated polymer forming compound in the plasma, the etching rate and the etching shape depend on the free silicon substrate surface to be etched. This is because the fluorine groups react with the polymer forming compounds present in the plasma, thereby reducing the fluorine groups available for etching the silicon substrate.

Another disadvantage that may arise is that unsaturated species present in the plasma, which give rise to polymer-forming compounds, preferably etch certain masking materials, and thus selectivity, ie silicon It occurs when the ratio between the etching rate and the mask etching rate is reduced. In addition, if non-uniform sidewall protection is provided, the polymer is directly and thicker coated at the mask edges of the sidewalls, so that the sidewalls are adequate in this area rather than at increasingly larger etch depths of the structure Protected.

In this case, as the depth increases, the polymer coating on the side walls decreases rapidly, and undercuts occur on the side walls, resulting in a bottle-shaped etched shape.

Instead of using a fluorine-based reactive gas, it has been proposed to use another halogen-based reactive gas, such as chlorine or bromine, or a reactive gas that releases chlorine or bromine in a plasma. ing. These gases are less reactive on the silicon surface.

Groups derived from reactive gases, usually formed in plasma, for example SF₆, C _Four F₈, NF_ThreeRadicals produced from
First, etching is caused, and ions are supported at the same time. Capacitively coupled low RF power
At the pole, a negative self-induced DC bias potential can be created on the electrode with respect to ground.
Generally known. Thus, the ions hit the silicon substrate virtually vertically
Therefore, these reactive gases mainly etch only the bottom of the structure,
This provides the advantage of not etching the side walls. However, the reaction of these reactive gases
The disadvantage is that it is very susceptible to moisture.

In this case, not only is an expensive transfer device required for the silicon substrate in the reactor, but also the leak rate of the entire etching system must be kept at a very low value. Even in the event of negligible moisture generation in the reactor, local silicon oxidation will cause micro-roughness at the bottom of the silicon etch, thus completely destroying the etch.

[0020] One An object of the present invention is to overcome the known shortcomings of the prior art. Specifically, one objective is to develop an anisotropic reactive ion etching method with reduced ion density that provides the advantage of substantially suppressing undercuts at the silicon-on-insulator interface.

In one aspect of the invention, this object is achieved by providing a method for etching a silicon substrate surface, wherein substantial etching of the underlying insulating oxide layer is avoided. The method involves an anisotropic plasma reactive ion etch that serves as a clearing phase where a "finish" etch is performed.

[0022] The objects of the invention are also realized by another aspect of the invention in which the polymerization deposition step is combined with reactive ion etching. It is possible to combine the etching species with a polymer forming compound in the plasma. Alternatively, it is contemplated that etching and polymerization are performed sequentially in the method of the present invention. The result is a deep structure (e.g., trench) with vertical edges with little or no undercut on the silicon-on-insulator substrate.

[0023] Other objects, features and advantages of the present invention will become more apparent from a consideration of the following preferred embodiments.

A preferred embodiment of the description the present inventors, in reducing the undercut of a silicon-oxide interface of the SOI structure, and found that the ion density is an important factor. N for silicon substrate
It should be understood that mold and p-type substrates and other silicon-blended substrates can be included. A method developed by the inventors to achieve reduced ion density is to use a plasma etching technique during the clearing phase of the etch. That is, most of the etching is performed by any etching technique known to those skilled in the art, followed by a clearing etch using the low ion plasma etching technique of the present invention. The present inventors have discovered that by reducing the ion density below about 10 ⁹ ions / cm ^3, undercut is substantially eliminated. The speed should decrease, but the undercut should decrease. The intent is to reduce the number of ions entering the trench, thereby eliminating or reducing the accumulation of charge found at the bottom of the trench insulator. The present inventors have determined that the RIE step can reduce the ion density.

After removing the bulk of the silicon from the higher aspect ratio features, the remainder of the etch is performed using process conditions that favor passivation and reduce etch corrosivity. This technique does not change the charging structure at the oxide / silicon interface described above, but instead relies on the ability to tightly control the degree of overcut.

The clearing phase of the present invention includes a plasma etching step, preferably a reactive ion etch (RIE), the process conditions of which favors passivation and reduces etch corrosivity. Using a clearing phase or "finish" etch is necessary to etch down to the insulator interface. When using plasma etching, lag can occur.
A lag is a diffusion limiting condition in various sized trenches / holes that reduces the etch rate as the trench aspect ratio increases. Most of the etching performed prior to performing the plasma etching step of the present invention is isotropic at high ion densities, and therefore has straight sidewalls that are perpendicular to the insulator layer and limit charge accumulation. Manufacturing requires plasma etching (RIE) to etch the recesses vertically (anisotropically) with low ion density.

One method of performing an initial etch involves a cyclic etch and a polymerization deposition step, as described by Bosch. In performing the process of the present invention after the Bosch process, the polymer is removed from the base using plasma etching (RIE). This is because the rate of polymer removal from the base is greater than the rate of polymer removal from the sidewalls.

During the polymerization deposition step, the polymer layer applied to the etching base is rapidly destroyed during the subsequent clearing phase of reactive ion etching. This is because the polymer is stripped off very quickly, the ions are supported,
This is because a chemical reaction between the reactive plasma species and silicon can proceed on the etching base.

During the reactive ion etching of the clearing step, the sidewalls of the structure are etched and the rest is protected by the polymer applied during the polymerization step.

Although we do not want to be bound by one theory, we believe that charge storage occurs by the following mechanism.

In a plasma etching system having a low RF electrode that is capacitively coupled, a negative self-induced DC bias potential is generated on the electrode with respect to ground. Poisson
son) 's equation creates a bias due to charge separation. In the case of a negatively biased electrode, electrons must accumulate on this electrode / wafer for this bias to occur. Under time-averaged conditions, the amount of stored electrons increases as the number of ions accelerated to the surface becomes equal to the number of electrons reaching the surface, until the attractive force on the ions increases. In other words, the net DC current to the wafer or electrode is zero. This factor is one of the limitations on capacitively coupled electrodes. There is a transient current, but no steady state DC current. We have:
It is considered that such a transient current during a steady state causes undercut.

For a flat conductive silicon wafer surface, the charge distribution across the wafer surface is fairly uniform, ie, the DC potential across the surface is uniform under steady state conditions. Since the charge distribution across the wafer is uniform, the ion acceleration towards the wafer is uniform. It is known that some surfaces are conductive, while others are insulators. The charge distribution varies across the surface depending on the characteristics of the surface. Therefore, the electric field fluctuates. Under quasi-neutral conditions, the net zero DC to the wafer
The current maintains a steady state for the silicon topography. However, during the transient local charge storage phase, a local DC potential occurs. Such local potential fluctuations are
This is a variation that causes an undercut at the on-insulator interface.

FIG. 1 shows one possible charge distribution configuration featuring surface topography. This represents a cross section of the trench. There is a negative charge along the silicon and photoresist sidewalls. This negative charge forms a potential barrier for electrons entering the trench in the future. The narrower the trench, the stronger the electric field coupling and thus the barrier.

The stronger the barrier, the less likely it is that electrons can penetrate the trench. On the other hand, this charge dispersion forms a potential well for ions. Ions easily enter the trench. However, in this case, an imbalance exists, where more ions than electrons enter the trench, especially smaller trenches where the electron barrier is larger. Such ions "pull" the attraction toward each wall, but some ions create an attraction to the bottom of the trench. If the bottom of the trench is an insulator, for example SiO ₂ , there is no possibility of escaping or releasing ionic charges, thus accumulating positive charges. This is a situation where silicon undercut is likely to occur at the oxide interface. There is an attractive force due to negative charges on the side walls and a repulsive force due to accumulation of positive charges at the bottom of the trench. Both the attractive force and the repulsive force curve the path of future ions to the bottom of the silicon wall, as shown in FIG. Thus, such ions strike the bottom of the silicon wall and form an undercut between the silicon and the insulator layer.

The rate and amount of charge accumulation are important factors affecting the degree of undercut. Accumulation, the ion current density J _i, oxide thickness t _ox, oxide dielectric constant E _ox, and including an aspect ratio (t _h / t _w) depends on a number of factors are not limited thereto . J _i can be adjusted by the process of the present invention. There is a factor, J _i , used to represent the current per unit area, the ion current density term. The current density is represented by the following equation.

## EQU1 _{J i = en i v i (} 1) where "e" is the charge, v _i is the ion velocity, n _i is the ion density. Thus, changing the charge, ion velocity, and ion density affects the ion current density.

The average ion velocity is the average DC bias across the sheath above the electrode as follows:
It can be calculated from _Vb and plasma potential φp.

(Equation 2)

Solving v _i and substituting it into equation (1) yields an equation relating to the average current density of ions reaching the wafer surface, as shown in equation (3).

(Equation 3)

Equation 3 shows that three major factors affect current density. Greatest effect giving and most easily changing factors is an ion density n _i. this is,
The ion density is directly proportional to the ion current and is a function of the high density source, ie,
This is because it is a function of the main product of the ionic species in the process of the present invention. Low RF
Power also contributes to ion density, but to a lesser extent than high density sources. Adjustability 2
The second important factor is the DC bias _Vb . This bias is a function of a number of parameters, including low RF power, process pressure, gas type, and frequency. However, the ion current varied only as the square root of this bias, but was a linear function of ion density. Therefore, the degree of regulation by changing this factor is low. The third factor to consider is the mass m _i of the species to be charged. Many groups are present during plasma processing, but the mass value subdivides the etchant gas and gas
May vary depending on the capabilities of the ICP. Increasing the mass of ions decreases the current density, and decreasing the mass of ions increases the current density. The mass value is
It is not easy to adjust because it is a square root function similar to bias.

Although the above discussion is primarily about steady state situations, charge builds up,
Therefore, there is also a transient situation in which an undercut at the silicon-on-insulator interface occurs.

The electrical circuit of FIG. 3 illustrates the effect of the lower oxide as a capacitor and its relationship to charging. FIG. 3 shows the electrical characteristics when the trench is etched down to the oxide layer. The resistance R _t represents the number of collisions that occur before the ionic species crosses the trench and reaches the oxide interface. R _t is a function of the width, length, and depth of the trench. The greater the number several collisions, the value of R _t is increased, greater the fewer collisions, the value of R _t is lower. R _si represents the resistance of the silicon beam from the bottom of the wall to the silicon surface. _Row represents the resistance between the oxide surface and the bottom of the wall. _Cox is the associated capacitance of the oxide at the bottom of the trench. This capacitance depends on the oxide thickness, area, and dielectric constant. R _b is the associated resistance under the oxide in the bulk of the wafer. The DC bias voltage _Vb is negative and represents a measured bias on the wafer surface. In practice, the bias is measured at the electrodes, and therefore depends on the measurement and clamping scheme, ie
Depending on whether it is a mechanical clamp, an ESC (electrostatic chuck), or just a thermal contact, there will be some difference between the bias at the wafer surface and the bias at the electrodes. It should be understood that the electrodes are at the same potential as the silicon wafer surface.
However, all voltages are referenced to ground. The last voltage on the circuit is V _ox
It is. This voltage is positive and is the last or steady state voltage measured at the bottom of the trench on the oxide surface.

The ions traversing the sheath and reaching the wafer surface have an average total energy φp−V _b
Having. This is the average onset energy of the ions at the wafer surface, ie, the energy lost by collisions with the walls, other species in the trench, and the oxide surface. The average ion can strike the photoresist at the start or enter the trench, as can be seen in FIGS. When ions enter the trench, they can recombine with the silicon wall surface if they are close enough. Ions can reach the oxide surface if they cross the center and have enough energy to survive collisions in a downward path.
When the amount of positive charge present on the oxide surface is small, little deflection or repulsion of new ions occurs. Over time, the ions remaining in this path to the bottom are continually added to the charge storage. When charge storage reaches the point where more ions are repelled from the oxide surface, the _ow increases the ionic current component to the silicon wall. This occurs because of the large potential difference between the positive oxide and the negatively charged silicon wall. The return path is _{simply a} recombination at the silicon wall surface embodied as an increase in electron flow through the beam to the wall surface due to the resistance _Rsi . Since there are two walls in every trench, there are actually two return paths. R _si represents the coupling resistance of these pathways.

In short, charge storage depends on three factors. The first is charging current, the second is ion bombardment in the trench, and the third is recombination with the wall surface.

It can be shown that the voltage at the bottom of the trench at the oxide surface increases exponentially with time for the V _ox values shown in FIG. The rate of increase is R _eff and
Depends on the value of _Cox . The product of the two gives the time constant of the system. The voltage V (t) as a function of time is given in equation (4).

(Equation 4) Where:

(Equation 5) and

(Equation 6) It is.

In theory, at time zero (t = 0), equation (4) shows that the starting voltage becomes zero and V (t
) Indicates that it approaches the value of V _ox over time. V _ox is a function of plasma potential Φ _p and bias V _b as shown in equation 4b. As described above, it is difficult to adjust Φ _p , but V _b can be adjusted. Therefore, one means of limiting the storage voltage _Vox is to lower the bias. Zero _Vb is ideal, but as shown in equation (3), zero _Vb means that there is no ion current to the wafer surface. Ion current is required for etching, but the inventor
It has been found that the ionic current can be adjusted so that the accumulation of _Vox is avoided. The time required to accumulate V _ox is adjusted by the product of _Reff and _Cox . Equation (5) is
The relationship between the shape of the oxide and _Cox is shown.

(Equation 7)

The exposed area of the oxide is represented by “A” in equation (5) and is the product of the width and length of the trench. The dielectric constant of the oxide is given by ε _ox and the thickness of the oxide is given by t _ox . Thus, one method of increasing the time constant, is to increase the C _{o x} value. Equation (5) shows the relationship for increasing the _Cox value by reducing the oxide thickness, increasing the dielectric constant, and increasing the area. If the trenches have the same depth but different widths, the smaller the width of the trench, the lower the capacitance and therefore the faster the charging. In theory, for the same process conditions, smaller trenches will show faster undercuts than larger trenches. Since the time constant also depends on R _eff ,
Increasing the resistance increases the charging time and slows the undercut. Formula (
4a) suggests that the bulk silicon resistance _Rb should be increased. In other words, silicon with higher resistivity reduces undercut. Also, R _t ,
When R _si and R _ow are increased, the undercut is reduced. R _b and R _si can be calculated, but R _t and R _ow are unknown. These magnitudes are important in determining whether R _si and R _b have a significant effect on the time it takes to charge the oxide and on the value of _Vox . While the above description has described a trench, it will be readily apparent to those skilled in the art that the description is equally applicable to other structures.

The amount of RF power applied during the clearing stage is between about 5W and 500W, preferably between about 50W and 200W, and most preferably between about 80W and 150W. The flow rate of the etchant gas is about 100 sccm to 200 sccm, and the flow rate of the polymer gas is about 0 sccm to 100 sccm.
sccm, and the maximum etchant-polymer forming compound ratio is 2: 1. The pressure during the etching step is between about 1 mT and 500 mT, preferably between about 20 mT and 50 mT. The temperature during the etching step is about 15 ° C. to 25 ° C., but can be as low as the liquid N ₂ temperature (−177 ° C.). The following example is merely illustrative, but it should be understood that RF power is applied only to the substrate during the RIE phase.

Comparative Example FIG. 4 is an SEM photograph showing an undercut occurring at the silicon / oxide interface of a trench having a width of 4 μm or more after a standard etching for 8.5 minutes. In this example, including a three-stage circulation process, there are alternating stages of an etching process and a polymerization deposition process,
The standard Bosch process disclosed in US Pat. No. 5,501,893 was used. The etching process is performed for about 2 to 6 seconds at a pressure of about 23 mT, at a temperature of about 15 ° C., and by applying an electric power of about 825 W, wherein the gas flow rate of the reactive gas is about 50 to 100 sccm
And the gas flow rate of the inert gas is 40 sccm. The polymerization deposition step is performed for about 5 seconds at a pressure of about 22 mT, a temperature of about 15 ° C., and by applying a power of about 825 W, in which case the gas flow rate of the reactive gas is about 70 sccm, and the inert gas flow rate is about 70 sccm. Gas flow is about 40
sccm. The thickness of the oxide (20000 °) is represented by _tox . Undercut 2
Occurred while trying to form a μm trench. 3 μm trench, ie
The third trench from the right has not reached the oxide interface, but shows no signs of undercut in the silicon. The 4 μm trench, ie the trench to the left of the 3 μm trench, already shows signs of undercut. This undercut is
It shows how much faster a smaller trench is charged compared to a larger trench. Since the exposed oxide area is smaller, the associated capacitance is lower. Using the same charging current, the lower capacitance is charged faster and reaches a steady state. The charging causes off axis ion bombardment and recombination on the wall surface.

When etching a silicon substrate, one factor to consider is the inherent lag exhibited when etching smaller features. To understand the amount of lag, FIG. 5 shows a graph illustrating the relationship between lag% and trench width for two different low RIE powers. For comparison, all lugs are based on a 100 μm trench width. Looking at the 9W RIE curve (black diamond), a 20 μm hole with 12% lag has a 12% lower etch rate than a 100 μm hole. Measurements were taken up to a 2 μm hole where the lugs were slightly over 40%. Using a lower RIE wattage reduces lag. Although lag can be adjusted to some extent by RIE, it is not sufficient, and therefore a careful choice is made to properly end the etching process that achieves a significant amount of etching. RIE etch rate is about 2 times faster than high density sources
It has an order of magnitude lower ion density and therefore lower etch rates. Formula (4b)
As shown, the bias _Vb contributes to the voltage accumulation _Vox in the trench. Therefore, the bias must be high enough to allow ions to reach the wafer surface. Thus, when the ion density becomes lower, a higher bias can be used than would otherwise be obtained with a high density source. Therefore,
Reduced lag is one of the unexpected advantages provided by the present invention.

Another important factor is the selectivity of the mask / resist layer. Increasing the bias generally causes the resist to degrade rapidly due to physical collisions, and therefore adjusting the bias affects selectivity.

EXAMPLE The following example is an example using a standard Bosch for the initial etch in which three circulation steps are performed. The etching process lasts about 2 to 6 seconds, with a pressure of about 23 mT and a temperature of about
It is carried out at 15 ° C. by applying a power of about 825 W, in which case the gas flow of the reactive gas is about 50 sccm to 100 sccm and the gas flow of the inert gas is 40 sccm. The polymerization deposition step is performed for about 5 seconds at a pressure of about 22 mT, a temperature of about 15 ° C., and by applying a power of about 825 W, in which case the gas flow rate of the reactive gas is about 70 sccm, and the inert gas flow rate is about 70 sccm. The gas flow is about 40 sccm. After this initial etching step, the etching step of the present invention is performed. The RIE process is performed for about 4 minutes,
A bias of about 80 W is applied to the substrate at 25 mT to 35 mT at a temperature of about 20 ° C.
The gas flow rate of the reactive gas is about 200 sccm. The process of the present invention can include a cyclic etching and a polymerization deposition process. This polymerization deposition step is performed for about 5 seconds at a pressure of about 25 mT, a temperature of about 15 ° C., and applying an electric power of about 825 W, in which case the gas flow rate of the reactive gas is about 70 sccm, Is 30 sccm.

EXAMPLE 1 FIG. 6 shows the results of a standard Bosch process followed by an acyclic RIE process that includes a clearing phase of the etching process. The two trenches on the right side of FIG. 6 have been etched down to the oxide layer, with no indication of undercut. This indicates that the preferred RIE-only etch technique has the ability to eliminate undercuts at the oxide / silicon interface. Therefore, the RIE technique is suitable for substrates having a wide range of aspect ratios.

The ability to continuously etch an oxide interface using a process such as the Bosch process requires a suitable endpoint detector because the timing of the process to prevent undercut is important. Such endpoint detectors are known to those skilled in the art.

In another embodiment of the present invention, the inventors consider that RIE, which serves to reduce undercut by lowering ion density, is combined with a polymer deposition step, thereby increasing polymer deposition on the wall. An etching process that prevents undercuts has been developed. Using this technique makes it possible to eliminate the RIE lag. However, when using this step, the time required to sufficiently etch the desired fine features increases. The smaller the trench width, the longer the time required to form the trench. However, if the ratio between the maximum trench and the minimum trench is small, the over-etching time is short.

Example 2 Using the techniques described above, experiments were performed to demonstrate this aspect of the process of the present invention. Trench widths ranged from 2 μm to 100 μm. One of these runs
The results are shown in FIG. Most of the etching is performed according to the Bosch process, followed by the etching process of the present invention, including cyclic deposition and etching steps.
FIG. 7 shows trench widths in the range of 2 μm to 10 μm. The side wall shown in FIG.
It is more linear than. Even if the over-etching time is long, there is almost no undercut. The success of this technique depends on the ability to form larger trenches by standard etching processes known to those skilled in the art before switching to the etching process of the present invention and etching the remaining silicon as a "finish" etch. I do.

In one aspect of the present invention, an initial plasma etching step is performed according to the Bosch process, where a specific ratio of saturated to unsaturated species, ie, a specific ratio of fluorine groups to polymer-forming compounds, is considered. And thus the actual etching step can be optimized for etch rate and selectivity without adversely affecting the overall process anisotropy. After the initial plasma etching and polymerization steps, the RIE process of the present invention with reduced ion current density is performed.

In an alternative embodiment of the present invention, during the initial plasma etching step and
During the step-wise polymerization step, ion energy bombards the silicon substrate.
Due to this simultaneous collision with ion energy, no or substantially no polymer is formed on the etch base, and therefore,
Higher etch rates can be achieved during the initial etch stage because the conventionally required decomposition of the polymer layer on the etch base is not required. Significant mask selectivity and anisotropy can be achieved by this collision of low ion energy.

Due to a strong exothermic reaction between fluorine groups and silicon, which occurs due to a high etching rate at the time of an initial etching step, the temperature of the silicon substrate becomes considerably high. Therefore, the silicon substrate is preferably cooled during the etching process, preferably by a helium gas flow. Preferably, the substrate is cooled as the high temperature drives the etching of the polymer adhesion layer and the mask layer.

To complete a “finish” etch to create deep structures, such as trenches, with sharp vertical edges, without substantial undercut, reduce the ion density during the clearing step as described above. Need to be maintained. Higher ion energies generally disperse or exfoliate and then interfere with the reaction of uncontrolled redeposited material. However, the energy of the ions acting on the silicon substrate must be sufficient to prevent accumulation of deposits on the structural base so that a smooth etching base is obtained.

If the silicon substrate is already bombarded with low ion energy during polymerization, little or no polymer will form on the etch base. Thus, it is preferred that the polymerizable monomer accumulates on the sidewalls and provides a particularly effective protection against the clearing phase on the sidewalls, whereas the etching base is uncoated or substantially uncoated.

Both alternatives exhibit a very high anisotropy with ionic effects only during the plasma etching stage or between both the plasma etching stage and the polymerization stage, ie, substantially A structure with virtually strictly vertical edge shapes without undercutting is realized.

In a preferred embodiment, the anisotropic etching can be performed with low ion energy. If no polymer is deposited on the etch base during the polymerization step, ion energies of only about 5 eV can be used. During the initial etching phase, 5e is used, so that the structure base is completely free of deposits from the plasma, so that initially the roughness of the etching base cannot be established.
Ion collisions with energies from V to 30 eV are recommended. If the ions are only accelerated towards the silicon substrate during the clearing phase, they will also penetrate well within a few seconds through the etching base polymer which will adhere during the polymerization phase. In this mode of operation, the microloading effect on the etch rate is further reduced.

[0062] Since the natural rate of reaction between the fluorine groups and silicon is high, silicon etching basically does not require ionic support.

A preferred embodiment of the present invention for performing anisotropic etching on a silicon substrate is implemented as follows.

The silicon substrate was patterned and coated with an etching mask, for example, a photoresist. This etching mask is a mask for leaving a region of the silicon substrate to be subjected to anisotropic etching, and the etching mask is subjected to a first etching step. It should be understood that etching masks other than photoresists known to those skilled in the art are within the scope of the invention.

An initial etch of a mixture of a fluorinated gas such as SF ₆ , NF ₃ and CF ₄ and an inert gas such as argon Ar at a gas flow rate of 0 sccm to 500 sccm and a processing pressure of 5 mT to 100 mT Can be used for Plasma generation for bulk or initial etch is preferably 300 W to 1200 W (up to about 2.45 GHz)
A) done by RF excitation or other high density sources.

At the same time, a substrate RF (radio frequency) bias for accelerating ions is applied to the substrate electrode. The substrate bias is preferably 5V to 100V and can be obtained with a high frequency power supply (13.56MHz) with an output of 2W to 20W.

During the initial etch, reactive species and charged particles (ions) are created in the reactor with the aid of discharge in a mixture of fluorinated and inert gases.

The positively charged cations thus generated are accelerated toward the silicon substrate by the RF bias applied to the substrate electrode, and fall almost vertically onto the substrate surface vacated by the etching mask. And promote the chemical reaction between the reactive plasma species and silicon.

This etching can be performed over a period to obtain an etching depth of about 5 μm to about 500 μm. The absolute depth of the recess depends on the thickness of the substrate to be etched and the amount of etching desired.

In the polymerization deposition step, for example, a mixture of a fluorinated gas such as CHF ₃ and argon (Ar) can be used, and other perfluorinated aromatic substances having appropriate peripheral groups, for example, perfluorinated Styrene-like monomers and ether-like fluorine compounds can also be used.

The surfaces exposed during the previous etching, ie the etching base and the side walls, are covered with the polymer during the polymerization. This polymer layer forms an etch stop on the etched edge or surface.

The polymer applied to the etching edge during the polymerization step is stripped off during a subsequent clearing phase that includes a reactive ion etching step. The edges exposed during the initial etching step are protected from further etching attack by the polymer layer during the reactive ion etching step. The reactive ion etching _{process, F 2, SiF 4, C} 2 F 6, MoF 5, WF 6, XeF 2, SF 6, C 3 F 8, NF 3, CHF 3, and fluorinated gases such as CF ₄ A mixture of and an inert gas such as argon Ar can be used. The clearing etch can be repeated cyclically, ie, the clearing etch can be followed by a polymer deposition, including further etching. Cyclically polymerized adhering repeated with clearing etch, the fluorinated gases, for _{example, CHF 3, CH 3 F,} C 2 H 2 F 2, C 2 H 2 F 4, C 3 F 8, and C ₄ F _{Use 8} . The gas mixture has a flow rate between about 0 sccm and 250 sccm, preferably about 0 sccm.
m to 100 sccm. When the output is preferably 300W to 1200W, microwave, I
CP, TCP, helicon, ECR, or other high-density excitation source.

It is known that the released monomers tend to settle back to be directly continuous with one another, the positive consequence of which is that additional local sidewall protection occurs during the clearing phase. That is, the polymer exfoliated during the etching phase can be redeposited on the side wall. As a result of the release of the monomers, this effect greatly enhances the anisotropy of the etching and clearing steps performed separately from the polymerization step in the plasma.

The polymerization stage is selected such that during polymerization, the Teflon-like polymer layer is long enough to settle on the sidewalls or the etching base. The thickness of the polymer layer is approximately
1 nm to 100 nm, preferably 10 nm to 75 nm, most preferably about 40 nm to 50 nm. It takes about 2 to 60 seconds for the polymer of the above thickness to adhere to the substrate.

In all media used, it is important to achieve a high density of reactive species and ions with low but tightly tunable energy at which the generated ions reach the substrate.

Other embodiments of the present invention will be apparent to one of skill in the art upon reviewing the specification and examples of the invention disclosed herein. It is intended that the specification be considered exemplary only, with a true scope and spirit of the invention being indicated by the following claims. Also, all documents cited herein are specifically incorporated herein by reference.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a trench, showing one possible charge distribution configuration due to the nature of the surface topography.

FIG. 2 shows a trench showing charge accumulation along the silicon-oxide interface.

FIG. 3 is an electric circuit diagram showing the relationship between the lower oxide and the effect as a capacitor and charging.

FIG. 4 is an SEM photograph showing the undercut occurring at the silicon / oxide interface in trenches having a width of 4 μm or more after 8.5 minutes of etching.

FIG. 5 is a graph showing the relationship between lag% and trench width for two different low RIE powers.

FIG. 6 is an SEM photograph in which two trenches on the right have been etched down to the oxide, and no signs of undercut are seen. The lag is evident from the varying etching depth. Narrower trenches indicate larger lugs.

FIG. 7 is an SEM photograph showing a range of a trench width of 2 μm to 10 μm in which a side wall is more linear than that of FIG. 6 and almost no undercut exists.

──────────────────────────────────────────────────の Continuation of front page (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE ), JP, KR (72) Inventor Debre Michael W. K. United States Florida Safety Harbor Hillside Lane 3130 F-term (reference) 5F004 AA05 BA09 BB21 BB22 BB25 CA02 CA04 CA06 CA09 DA00 DA01 DA17 DA18 DA23 DB01 DB23 EA13 EA28 EB04 5F032 AA03 AC02 BA01 CA07 DA25

Claims (19)

[Claims] 1. A method for preventing undercuts at a silicon-insulator interface during etching of a silicon substrate, comprising the step of etching the silicon substrate by reactive ion etching, wherein the ion density is reduced. Thereby,
A method in which vertical etching of sidewalls formed during etching is performed. 2. The method further comprising polymerizing by introducing at least one polymer-forming compound into the plasma, wherein the compound deposits on the exposed surface of the silicon;
The method of claim 1, wherein a temporary coating layer is thereby formed. 3. The method of claim 2, wherein the reactive ion etching and polymerization are cyclic and repeated. 4. A method for preventing undercuts at a silicon-insulator interface during the etching of a silicon substrate, comprising the steps of: a) contacting a reactive etching gas with the silicon to remove material from the surface of the silicon; Anisotropic plasma etching by removing and producing an etched surface; b) polymerizing at least one polymer-forming compound and depositing it on the exposed surface of the silicon, whereby the compound is exposed to the plasma. Forming a temporary coating layer by introducing; and c) a reactive ion having a reduced ion density of less than about 10 ⁹ ions / cm ³ , wherein reactive ions impacting the surface of the silicon are generated in the plasma. Ion etching. 5. The method of claim 4, wherein the etching (a) is performed substantially without a polymer forming compound in the plasma. 6. The polymer applied at the time of deposition (b) on the laterally defined recess structure formed by the etching (a) is subjected to reactive ion etching (c).
5. The method of claim 4, wherein the etching is partially performed. 7. The method of claim 4, wherein the reactive etching gas is a mixture of sulfur hexafluoride and argon. 8. The method of claim 1, wherein the first etching step removes material from a surface of the silicon to a preselected depth, and wherein the first etching step is performed over a period of time to provide the preselected etching depth. 5. The method of claim 4, wherein the method is performed. 9. The reactive ion used in the reactive ion etching (c) is F ₂ , SiF ₄ , C ₂ F ₆ , MoF ₅ , WF ₆ , XeF ₂ , SF ₆ , C ₃ F ₈ , NF _3, CHF _3, and CF ₄ is selected from the group consisting of the method of claim 4, wherein. 10. The method of claim 4, wherein the silicon surface is patterned before plasma etching. 11. The method of claim 4, wherein the etching (a) and the deposition (b) are alternately repeated before performing the reactive ion etching (c). 12. The method of claim 4, further comprising an additional polymerization step after the reactive ion etching. 13. The method of claim 12, wherein the additional polymerization step and reactive ion etching are cyclic and repeated. 14. A method of reactive ion etching at an ion velocity, ion density, ion mass, bias, power, and pressure sufficient to achieve an ion current density of less than about 10 ⁹ ions / cm ³ . 15. The power provided is in the range of about 5 watts to 500 watts.
2. The method of claim 1, further comprising applying a low density power to the silicon substrate. 16. The power supplied is in a range from about 5 watts to 500 watts.
The method of claim 4, further comprising applying a low density power source to the silicon substrate during the reactive ion etching (c). 17. The method according to claim 1, wherein the flow rate of the gas used during the etching is between about 100 sccm and
The method of claim 1 or 4, wherein the flow rate of the gas used during the polymerization is 00 sccm and the flow rate is about 0 sccm to 100 sccm. 18. The method of claim 1, wherein the pressure of the etching, polymerization, and reactive ion etching steps is about 1 mT to 500 mT. 19. The method of claim 1, wherein the temperature of the step is about 15 ° C. to 25 ° C.