JP2002528893A - Low dielectric constant film of CVD nanoporous silica - Google Patents

Abstract

(57) [Abstract] Reaction of a nanoporous low-k film with a peroxide compound with a silicon hydride-containing compound or mixture with an optionally thermally unstable organic group and a peroxide compound A method and apparatus for depositing the same. The deposited silicon oxide-based film is annealed to form dispersed microscopic voids that remain within the nanoporous silicon oxide-based film having a cellular structure. Nanoporous silicon oxide-based films are useful for filling gaps between metal interconnects with or without a liner or cap layer. Nanoporous silicon oxide based films can also be used as intermetal dielectric layers to fabricate dual damascene structures. Preferred nanoporous silicon oxide based membranes are the reaction of 1,3,5-trisilanocyclohexane, bis (formyloxysilano) methane, or bis (glyoxylylsilano) methane with hydrogen peroxide, followed by hydrogen peroxide Cure / anneal including a gradual increase in temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The invention relates to the manufacture of integrated circuits. More particularly, the present invention relates to a process and apparatus for depositing a dielectric layer on a substrate.

[0002]

BACKGROUND OF THE INVENTION

One of the major steps in the manufacture of modern semiconductor devices is the formation of metal and dielectric films on substrates by chemical reactions of gases. Such a deposition process is called chemical vapor deposition or CVD. Conventional thermal CVD processes supply a reactive gas to the substrate surface where a thermally induced chemical reaction occurs to create the desired film. The high temperatures at which some thermal CVD processes operate can damage device structures that have layers already formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma enhanced CVD (PEC).
VD) technology, for example, described in US Pat. No. 5,362,526, entitled "Plasma Enhanced CVD Process Using TEOS to Deposit Silicon Oxide," which is incorporated herein by reference. Be incorporated. Plasma enhanced CVD technology
Application of radio frequency (RF) energy to the reaction zone near the substrate surface facilitates the excitation and / or dissociation of the reactive gas, thereby creating a highly reactive nuclide plasma. The high reactivity of the dissociated nuclides reduces the energy required for the chemical reaction to take place, thus lowering the temperature required for such a PECVD process.

[0003] The dimensions of semiconductor devices have dramatically decreased in size since the decades when such devices were first introduced. Since then, integrated circuits generally follow the law of two years / half size (often called Moore's law), which means that the number of devices mounted on a chip doubles every two years I do. Current manufacturing facilities are constantly producing devices with feature sizes of 0.35 μm and even 0.25 μm, and future facilities will soon produce devices with even smaller geometries.

In order to further reduce the size of devices on integrated circuits, conductive materials with low resistivity and low k (dielectric constant <4.0) to reduce capacitive coupling between adjacent metal lines ) Has to be used. A backing / barrier layer was used between the conductive material and the insulator to prevent diffusion of by-products, such as moisture, over the conductive material as described in WO 94/01885. For example, moisture that can be generated during the formation of a low-k dielectric readily diffuses to the surface of the conductive metal, increasing the resistivity of the conductive metal surface. Barrier / liner layers formed from conventional silicon oxide or silicon nitride materials can prevent the diffusion of by-products. However, the barrier / liner layer usually has a dielectric constant significantly greater than 4.0, which results in a composite insulator that cannot significantly reduce the dielectric constant.

FIG. 1A shows a PECVD process for depositing a barrier / liner layer as described in WO 94/01885. The PECVD process is
Depositing a multi-component dielectric layer, wherein a silicon dioxide (SiO ₂ ) liner layer 2 is first deposited on a patterned metal layer having metal lines 3 formed on a substrate 4. You. The liner layer 2 is deposited at 300 ° C. by a plasma enhanced reaction of silane (SiH ₄ ) and nitrous oxide (N ₂ O). A self-planarizing low-k dielectric layer 5 is then deposited on the liner layer 2 by a thermal reaction of a silane compound and a peroxide compound at a temperature below 200 ° C. The self-planarizing layer 5 retains moisture, which is removed by annealing. The liner layer 2 is an oxidized silane film and has effective barrier properties when deposited in a manner that provides a dielectric constant of at least 4.5. The dielectric constant of the oxidized silane film can be reduced to about 4.1 by modifying the process conditions in a manner that reduces the moisture barrier properties of the film. Conventional liner layers, such as SiN, have even higher dielectric constants, and the combination of a high-k dielectric liner layer and a low-k dielectric layer provides little or no overall stacked dielectric constant and capacitive coupling. Does not provide improvement.

As shown in FIG. 1B, WO 94/01885 further describes an optional SiO ₂ capping layer 6, which is deposited on the low-k dielectric layer 5 by the reaction of silane with N ₂ O. The cap layer 6 is also an oxidized silane film and has good barrier properties when deposited in a manner that provides a dielectric constant of about 4.5. Both the liner layer 2 and the cap layer 6 have a dielectric constant greater than 4.5, and a high dielectric constant layer substantially reduces the benefits of the low k dielectric layer 5.

[0007] As devices become smaller, liner and cap layers having higher dielectric constants contribute more to the overall dielectric constant of the multi-component dielectric layer. Moreover, known low-k dielectric materials generally have low oxide content, which makes this material unsuitable as an etch stop layer during etching of vias and / or interconnects. Silicon nitride has been the etch stop material of choice for making interconnect wiring in low-k dielectric materials. However, silicon nitride has a relatively high dielectric constant (a dielectric constant of about 7) compared to the surrounding low-k dielectric layer. It has also been discovered that silicon nitride can significantly increase the capacitive coupling between interconnect wires, even when otherwise low-k dielectric materials are used as the primary insulator. This can cause crosstalk and / or resistance-capacitance (RC) delays that degrade the overall performance of the device. Thus, the silicon nitride etch stop layer is typically removed after etching the underlying dielectric layer.

[0008] Ideally, low-k dielectric layers having both good barrier properties for use as a liner layer and sufficient oxide content for use as an etch stop have been identified and Could be deposited in the same chamber as the low-k dielectric material. Such a barrier layer would not increase the overall dielectric constant of the dielectric layer, and such an etch stop layer would not have to be removed after etching the underlying layer.

US Pat. No. 5,554,570 describes a barrier layer for use with thermal CVD silicon oxide in which an organosilane having a C—H group or group is a silane. Instead of being oxidized, it increases the density of the deposited film and improves interlayer adhesion. For example, a thermal CVD layer made from tetraethoxysilane (TEOS) and ozone can be deposited between a PECVD silicon oxide film made from organosilane and N ₂ O or O ₂ .

[0010] The barrier layer described in the '570 patent is preferably a high density silicon oxide layer having a low carbon content. The dense layer is deposited using 400 W of high frequency RF power, although low frequency RF power is claimed to improve film stress. Barrier layer is preferably an alkoxysilane or chlorinated alkylsilanes and N ₂ O
Made from and reduce the carbon content of the layer and increase the density.

The '570 patent does not identify process conditions for creating a barrier layer with a low dielectric constant or for creating an oxide-rich etch stop layer.
The '570 patent also discloses the use of the above layers as barrier layers adjacent to low k dielectric layers.
Or suggest use as an etch stop.

[0012] There remains a need for dielectric layers with low dielectric constant, good barrier properties, and high oxide content for use as barrier or etch stop layers in submicron devices.

[0013]

[Means for Solving the Problems]

The present invention provides a method and apparatus for depositing a nanoporous silicon oxide layer having a low dielectric constant. The nanoporous silicon oxide layer may contain organic groups or groups that are more thermally unstable in the silicon / oxygen containing material. Created by depositing the material and by controlled annealing of the deposited silicon / oxygen-containing material to form microscopic gas pockets that are uniformly dispersed in the silicon oxide layer. The relative volume of the microscopic gas pocket relative to the silicon oxide layer is controlled to maintain a closed cell structure that results in a low dielectric constant. The silicon / oxygen material is chemically reacted by condensing the peroxide compound onto the surface of the substrate and by contacting the deposited peroxide compound with a reactive compound or mixture containing hydrogenated silicon. Vapor phase deposition. If the labile organic group is in a reactive compound or mixture, the labile organic group will have enough oxygen to convert to a gaseous product when the deposited silicon oxide layer is annealed. It contains.

The hydrogenated silicon-containing reactive compound or mixture that forms the layer of the nanoporous silicon oxide substrate under controlled annealing includes silane, methylsilane, dimethylsilane, disilanomethane, bis (methylsilano) methane, 1,3,5-trisilanocyclohexane, cyclo-1,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene, 1,3-bis (silanomethylene) siloxane, and 1,2 -Disilanotetrafluoroethane, and combinations thereof. 1,
Void formation using 3,5-trisilanocyclohexane and cyclo-1,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene is enhanced due to its non-planar cyclic structure. You.

The reactive compound or mixture containing silicon and the thermally labile organic group is bis (formyloxysilano) methane, bis (glyoxylylsilano) methane, bis (formylcarbonyldioxysilano) methane 2,2-bis (formyloxysilano) propane, 1,2-bis (formyloxysilano) ethane, 1,2
2-bis (glyoxylylsilano) ethane and mixtures thereof. Such compounds react with hydrogen peroxide to form a gel-like silicon / oxygen-containing material that carries many of the labile organic moieties. The amounts of labile organic moieties include methyl maleate anhydride, 3-formyloxy-2,5-furandione, glycidaldehyde, oxiranyl glyoxalate, dioxiranyl carbonate, dioxiranyl mesoxalate, and anhydrous glycidic acid. It can be increased by mixing the reactive compound with a non-silicon-containing component that contains one or more labile organic moieties, such as an acid. Alternatively, the silicon-free component can be silane, methylsilane, dimethylsilane, disilanomethane, bis (methylsilano) methane, 1,3,5-trisilanocyclohexane, cyclo-1,3,5,7-tetrasilano-2,6- It is mixed with a reactive silicon-containing material that does not contain an unstable organic group, such as dioxy-4,8-dimethylene, 1,3-bis (silanomethylene) siloxane, and 1,2-disilanotetrafluoroethane. obtain.

The deposited silicon / oxygen-containing material is preferably annealed with an increasing temperature profile to provide a nanoporous material having a low dielectric constant due to a bubble structure closing the unstable organic groups. Transform into gas pockets dispersed within the silicon oxide layer. Annealing preferably increases the temperature of the deposited material to about 400 ° C. or higher.

In a preferred gap-filling embodiment, the nanoporous silicon oxide layer of the present invention is prepared using one or more reactive silicon-containing compounds and suboxides, preferably using low levels of constant or pulsed RF power. Deposited on a silicon oxide barrier layer deposited on a patterned metal layer by a plasma assisted reaction with nitrogen. Next, a nanoporous silicon oxide layer is deposited without RF power in the same chamber. After the anneal described above, the nanoporous silicon oxide layer is optionally coated with an organosilane and / or organosiloxane compound and nitrous oxide using low levels of constant or pulsed RF power in the same chamber. Capped by the reaction. The liner and cap layers act as barriers protecting the nanoporous silicon oxide layer.

The present invention further provides an intermetal dielectric material (IMD) comprising a nanoporous silicon oxide layer deposited on a conventional etch stop, such as silicon oxide or silicon nitride. Silicon oxide can also be deposited as a thin adhesive layer.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

A more detailed description of the invention, briefly summarized above, will be set forth in the accompanying drawings, so that the manner in which the features, advantages, and objects of the invention set forth above may be attained in detail. It is obtained with reference to the embodiment.

However, as the present invention may allow other equally effective embodiments, the accompanying drawings illustrate only exemplary embodiments of the invention, and therefore are not intended to limit its scope. Note that it is not considered limiting. For a further understanding of the invention,
See detailed description.

The present invention provides a method and apparatus for depositing a nanoporous silicon oxide layer having a low dielectric constant. The nanoporous silicon oxide layer is optionally deposited by depositing a silicon / oxygen containing material containing thermally labile organic groups; and
Created by controlled annealing of silicon / oxygen containing material deposited to form microscopic gas pockets that are uniformly dispersed within the silicon oxide layer. The relative volume of the microscopic gas pocket to silicon oxide is controlled to maintain a closed cell structure that provides low dielectric constant and low permeability after annealing. The nanoporous silicon oxide layer will have a dielectric constant less than about 3.0.

[0022] Organosilane and organosiloxane compounds generally include the following structures:

[0023]

(Equation 1)

Wherein each Si is bonded to at least two hydrogen atoms, may be bonded to one or two carbon atoms, and C is an organic group, preferably —CH ₃ ,
It is included in an alkyl group or an alkenyl group such as —CH ₂ —CH ₃ , —CH ₂ —, or —CH ₂ —CH ₂ —, or a fluorinated carbon derivative thereof. The organosilane or organosiloxane compound contains two or more Si atoms, each Si being a different Si atom.
And -O -, - if the C-, or -C-C-by are isolated, C for each crosslinking organic atomic group, _{preferably, -CH 2 -, - CH 2} -CH 2 -, - CH ( CH ₃₎ -
, —C (CH ₃ ) ₂ — or a fluorinated carbon derivative thereof. Preferred organosilane and organosiloxane compounds are gases or liquids near room temperature and can be vaporized above about 10 Torr. Preferred organosilanes and organosiloxanes include:

[0025]

(Equation 2)

And fluorinated carbon derivatives thereof, such as 1,2-disilanotetrafluoroethane. Hydrocarbon groups in organosilanes and siloxanes can be partially or completely fluorinated to convert CH bonds to CF bonds. Many of the preferred organosilane and organosiloxane compounds are commercially available. A combination of two or more organosilanes or organosiloxanes can be employed to provide the desired blend of properties, such as dielectric constant, oxide content, hydrophobicity, film stress, and plasma etching properties.

The silicon / oxygen material condenses a peroxide compound, such as hydrogen peroxide, onto the surface of the substrate and converts the deposited peroxide compound to silicon hydride groups and optionally thermally. Chemical vapor deposition by contact with reactive compounds or mixtures containing labile organic groups. 1,3,5-trisilanocyclohexane and cyclo-1,3,5,7-tetrasilano-2,6-dioxy-4,8
-Void formation using some compounds such as dimethylene is achieved during annealing without adding unstable groups due to its non-planar ring structure. Thermally labile organic moieties contain enough oxygen to form gaseous products when the silicon oxide layer is annealed. Preferred labile groups are formyloxy (CH (O) -O-), glyoxylyl (CH (O) -CO-O-), and formylcarbonyldioxy (CH (O) -O-CO-O). -).

Reactive compounds containing silicon hydride and thermally labile organic moieties include:

[0029]

(Equation 3)

Such compounds react with hydrogen peroxide to form gelled silicon / oxygen containing materials that carry many of the unstable organic groups at temperatures below about 40 ° C. The amount of labile organic groups retained in the deposited silicon / oxygen-containing material can be increased by mixing the reactive compound with a non-silicon-containing component that includes one or more labile organic groups. . Unstable organic groups include formyloxy (CH (O) —O—), glyoxylyl (CH (O
) -CO-O-) and formylcarbonyldioxy (CH (O) -O-CO
-O-) group and other oxygen-containing organic groups. Preferred silicon-free compounds include:

[0031]

(Equation 4)

Alternatively, a non-silicon-containing component can be mixed with a reactive silicon-containing material that does not contain labile organic groups, such as:

[0033]

(Equation 5)

And fluorinated carbon derivatives thereof.

The deposited silicon / oxygen-containing material is preferably annealed at increasing temperatures to provide a nanoporous silicon oxide having a low dielectric constant due to a closed cell structure closing the unstable organic groups Transform into gas pockets dispersed in the layer.

In a preferred gap-filling embodiment, the nanoporous silicon oxide layer of the present invention is prepared using one or more reactive silicon-containing compounds and suboxides, preferably using low levels of constant or pulsed RF power. Deposited on the silicon oxide barrier layer deposited on the patterned metal layer by a plasma assisted reaction with nitrogen. Reactive silicon compounds are preferably silanes and other compounds listed above with silanes. Next, the nanoporous silicon oxide layer is deposited without RF power in the same multi-chamber clustered CVD system and optionally heated to about 400 ° C. using an increasing temperature profile. The nanoporous silicon oxide layer is optionally used to further react the reactive silicon compound with nitrous oxide using low levels of constant or pulsed RF power in the same chamber used to deposit the barrier layer. Capped by reaction. The liner and cap layers act as barriers protecting the nanoporous silicon oxide layer.

[0037] The liner layer and the cap layer may be deposited by plasma-assisted oxidation of a reactive silicon-containing compound. A preferred reactive silicon-containing compound is dimethylsilane, which is a constant RF power of about 10 to about 200 W, or about 20 to about 2
Deposited using pulsed RF power up to 00W. Pulsed RF power can operate at higher peak power levels and provide the same total power input as non-pulsed RF power at lower power levels. Carbon remaining in the liner and cap layers contributes to low dielectric constant and barrier properties. The remaining carbon preferably contains enough CH or CF bonds to provide a hydrophobic layer that is a good moisture barrier.

The reactive silicon-containing compound is oxidized during the deposition of the liner and cap layers by a plasma-assisted reaction with oxygen formed during the deposition process by the decomposition of an oxygen-containing compound such as nitrous oxide (N ₂ O). Is done. Nitrous oxide does not react without the aid of plasma, and oxygen-nitrogen bonds are more easily broken at lower energies than bonds in reactive silicon-containing compounds. The oxidized compound forms a film that is deposited in intimate contact with a contact surface, such as a patterned layer of a semiconductor substrate. The deposited film is reduced in pressure and about 2
Cured and annealed at a temperature from 00 to about 450 ° C., preferably above about 400 ° C., to stabilize the barrier properties of the film. The deposited film has a carbon content sufficient to provide barrier properties. The carbon content is preferably C-H or C-
Including an F bond provides a hydrophobic membrane that is an excellent moisture barrier.

The present invention further provides a substrate processing system, which has a plasma reactor including a reaction zone, a substrate holder for positioning a substrate in the reaction zone, and a vacuum system. The processing system further includes a gas / liquid distribution system connecting the reaction area of the vacuum chamber to a source of reactant gas and inert gas, and an RF coupled to the gas distribution system to generate a plasma in the reaction area. A generator is provided. The processing system further comprises a controller comprising a computer for controlling the plasma reactor, the gas distribution system, and the RF generator, and a memory coupled to the controller, wherein the memory comprises an organosilane or organosiloxane compound and an oxidizer. A computer usable medium including computer readable program code for selecting a process step for depositing a low dielectric constant film with a plasma of a gas.

The processing system further includes, in one embodiment, depositing a liner layer of the oxidized organosilane compound, depositing a different dielectric layer, and optionally, depositing the oxidized organosilane compound. It may include computer readable program code for selecting a process for depositing the cap layer.

A further description of the invention is directed to a specific apparatus for depositing a nanoporous silicon oxide layer of the invention and to a preferred gap-filling film.

Exemplary CVD Plasma Reactor One suitable CVD plasma reactor capable of performing the method of the present invention is shown in FIG. 2, which is a parallel plate chemical vapor deposition reactor 10 having a high vacuum section 15.
FIG. The reactor 10 contains a gas distribution manifold 11, which is a substrate support plate or susceptor 1 that is raised or lowered by a lift motor 14.
This is for dispersing the process gas through a through-hole in the manifold to a substrate, ie, a wafer (not shown) mounted on 2. Liquid injection systems (not shown), such as those commonly used for liquid injection of TEOS, may also be provided for injecting liquid reagents. The preferred liquid injection system is AMAT Gas Precision Liq
uid Injection System (GPLIS) and AMAT Extended Precision Liquid
Injection System (EPLIS), both available from Applied Materials, Inc.

The reactor 10 may include a resistance heating coil (not shown) or an external lamp (not shown)
As with, including heating of the process gas and the substrate. Referring to FIG.
The susceptor 12 is mounted on a support stem 13, such that the susceptor 12 (and the wafer supported on the upper surface of the susceptor 12) is adjacent to the lower loading / unloading position and the manifold 11. It can be controllably moved to and from an upper processing position.

When the susceptor 12 and the wafer are in the processing position 14, they are
7 and process gas exhaust holes 24 to the manifold. During the process,
The gas injected into the manifold 11 is evenly distributed in the radial direction over the surface of the wafer. A vacuum pump 32 with a throttle valve controls the rate of gas exhaust from the chamber.

Before reaching the manifold 11, the deposition and carrier gases are mixed in the mixing system 1.
The gas is input into the pipe 9 through a gas pipe 18, mixed therein, and then sent to the manifold 11. Generally, the process gas supply pipe 18 for each of the process gases
(I) a safety shut-off valve (not shown) that can be used to automatically or manually shut off the flow of process gas into the chamber, and (ii) a mass flow rate that measures the flow rate of gas through the gas supply line. Includes a controller (also not shown). When toxic gases are used in the process, several safety shut-off valves are placed in each gas supply line in a conventional configuration.

The deposition process performed in reactor 10 can be either a non-plasma process on a cooled substrate pedestal or a plasma-enhanced process. In a plasma process, a controlled plasma is typically formed adjacent to the wafer by RF energy applied from RF power supply 25 to distribution manifold 11 (with susceptor 12 grounded). Alternatively, RF power can be provided to susceptor 12, or RF power can be provided to different components at different frequencies. The RF power supply 25 can provide single frequency or mixed frequency RF power and enhance the decomposition of reactive nuclides introduced into the high vacuum zone 15. Mixed-frequency RF power sources typically have 13
. 56 MHz high RF frequency (RF1) to distribution manifold 11 and 3
Power is supplied to the susceptor 12 at a low RF frequency (RF2) of 60 kHz. The silicon oxide layers of the present invention are most preferably created using low or pulsed levels of high frequency RF power. The pulsed RF power provides 13.56 MHz RF power at about 20 to about 200 W with a duty cycle period of about 10 to about 30%. The unpulsed RF power is preferably 1 unit as described in more detail below.
Provide 3.56 MHz RF power at about 10 to about 150W. Low power deposition preferably occurs at a temperature in the range of about -20 to about 40C. In the preferred temperature range,
The deposited film is partially polymerized during deposition, and the polymerization is completed during the later film cure.

Typically, any or all of the chamber lining, gas inlet manifold faceplate, support stem 13 and various other reactor metal parts are made of a material such as aluminum or anodized aluminum. Such CVD
A suitable example of a reactor is issued to Wang et al. And assigned to the assignee of the present invention, Applied Materials, I
U.S. Pat. No. 5,000,113 to U.S. Pat. No. 5,000,113, entitled "Thermal CVD / PECVD Reactor and Use for Thermochemical Vapor Deposition of Silicon Dioxide and In-Situ Multi-Stage Planarization Process."".

The elevating motor 14 raises and lowers the susceptor 12 between the processing position and the lower wafer loading position. The motor, the gas mixing system 19, and the RF power supply 25 are controlled by a system controller 34 via control wiring 36. The reactor consists of mass flow controllers (MFCs) and standard or pulsed R
It includes analog assemblies such as an F generator, which are controlled by a system controller 34 executing system control software stored in a memory 38, which in the preferred embodiment is a hard disk drive. Motors and optical sensors are used to move and determine the position of a movable mechanical assembly, such as a motor for positioning the throttle valve and susceptor 12 of the vacuum pump 32.

The system controller 34 controls all operations of the CVD reactor, and preferred embodiments of the controller 34 include a hard disk drive, a floppy disk drive, and a card rack. The card rack contains a single board computer (SBC), analog and digital input / output boards, interface boards, and stepper motor controller boards. The system controller complies with the Versa Modular Europeans (VME) standard, which
Defines the dimensions and model of the card cage and connectors. VME standard is 1
A bus structure having a 6-bit data bus and a 24-bit address bus is also defined.

The system controller 34 operates under the control of a computer program stored on the hard disk drive 38. The computer program dictates the timing of certain processes, gas mixing, RF power levels, susceptor position, and other parameters. The interface between the user and the system controller is via the CRT monitor 40 and light pen 44 shown in FIG. In a preferred embodiment, a second monitor 42 is used, the first monitor 40 being mounted on the wall of the clean room for the operator and the other monitor 42 being mounted behind the wall for the service technician. Both monitors 40, 42 display the same information at the same time, but only one light pen 44 is enabled. The light pen 44 detects light emitted by the CRT display with a light sensor at the tip of the pen. To select a particular screen or function, the operator touches a designated area of the display screen and presses a button on pen 44. The touched area changes its highlight color, or a new menu or screen is displayed, confirming communication between the light pen and the display screen.

Referring to FIG. 4, the process may be implemented, for example, using a computer program product 410 running on the system controller 34. The computer program code may be written in any conventional computer readable programming language, such as, for example, 68000 assembly language, C, C ++, or Pascal. The appropriate program code is entered into a single file or multiple files using a conventional text editor and stored or embodied in a computer usable medium, such as a computer memory system. If the input code text is in a high-level language, the code is compiled and the resulting compiler code is then linked with the object code of the uncompiled window library routine. To execute the linked and compiled object code, the system user invokes the object code, causes the computer system to load the code into memory, from which the CPU reads and executes the code, and performs the tasks identified by the program. Perform

FIG. 4 shows an exemplary block diagram of the hierarchical control structure of the computer program 410. The user enters the process set number and process chamber number into the process selector subroutine 420 by using the light pen 44 interface in response to a menu or screen displayed on the CRT monitor 40. The process set is a predetermined set of process parameters required to execute a specific process, and is identified by a predetermined set number. The process selector subroutine 420 is based on (i) the Centura® platform (Applied M
selecting a desired process chamber on a cluster tool (available from aterials, Inc.), and (ii) a desired set of processes required to operate the process chamber to perform the desired process. Select a parameter. Process parameters for performing a particular process include, for example, process gas composition and flow rate, temperature, pressure, plasma conditions such as RF bias power level and magnetic field power level, cooling gas pressure, and chamber wall temperature, etc. It relates to the process conditions and is provided to the user in the form of a recipe. The parameters specified in the recipe are entered using the light pen / CRT monitor interface.

The signals for monitoring the process are provided on the analog input and digital input boards of the system controller, and the signals for controlling the process are output on the analog output and digital output boards of the system controller 34.

The process sequencer subroutine 430 includes the process selector subroutine 4
Includes program code for receiving certified process chambers and sets of process parameters from 20 and for controlling operation of various process chambers. Multiple users can enter the process set number and process chamber number, or one user can enter multiple process chamber numbers, so that the sequencer subroutine 430 operates to plan the selected processes in the desired order. I do. Preferably, sequencer subroutine 430 includes (
i) monitoring the operation of the process chamber to determine if the chamber is being used; (ii) determining what process is being performed in the chamber being used; and (iii) utilizing the process chamber. It includes computer readable program code for performing the steps of performing a desired process based on the likelihood and type of process being performed. Conventional methods of monitoring the process chamber, such as polling, may be used. When planning which process is to be performed, the sequencer subroutine 430 determines the current condition of the process chamber being used, or each particular input that has entered a request, as compared to the desired process conditions for the selected process. It may be designed to take into account the "age" of the user, or any other relevant factor that the system programmer would like to include to determine the plan priority.

After the sequencer subroutine 430 has determined which combination of process chamber and process set will be executed next, the sequencer subroutine 430 proceeds with the process set in the process chamber 10 according to the process set determined by the sequencer subroutine 430. The process set is executed by routing specific process set parameters to a chamber manager subroutine 440 that controls a number of process tasks. For example, chamber manager subroutine 440 includes program code for controlling CVD process operation in process chamber 10. The chamber manager subroutine 440 also controls the execution of various chamber component subroutines that control the operation of the chamber components required to execute the selected set of processes. Examples of chamber component subroutines are a susceptor control subroutine 450, a process gas control subroutine 460, a pressure control subroutine 470, a heater control subroutine 480, and a plasma control subroutine 490. Those of ordinary skill in the art will readily recognize that other chamber control subroutines may be included depending on the desired process to be performed in reactor 10.

In operation, the chamber manager subroutine 440 selectively schedules or calls process component subroutines according to the particular set of processes to be performed. The chamber manager subroutine 440 plans the process component subroutines in a manner similar to the way the sequencer subroutine 430 plans the process chamber 10 and process set to be executed next. Typically, the chamber manager subroutine 440 monitors the various chamber components, determines the components that need to be operated based on the process parameters for the process set to be performed, and monitors and determines. Executing a chamber component subroutine in response to the step.

The operation of a particular chamber component subroutine will now be described with reference to FIG. The susceptor control positioning subroutine 450 loads the substrate onto the susceptor 12 and optionally raises the substrate to a desired height within the reactor 10 to control the spacing between the substrate and the gas distribution manifold 11. Program code for controlling the chamber components used in the system. As the substrate is loaded into the reactor 10, the susceptor 12 is lowered to receive the substrate,
Thereafter, the susceptor 12 is raised to a desired height within the chamber, maintaining the substrate at a first distance or distance from the gas distribution manifold 11 during the CVD process. In operation, the susceptor control subroutine 450 executes the chamber manager subroutine 44
0 controls the movement of the susceptor 12 in response to the process set parameter transferred from 0.

The process gas control subroutine 460 has program code for controlling process gas composition and flow rates. The process gas control subroutine 460 also controls the open / close position of the safety shut-off valve and the start / stop of the mass flow controller to achieve the desired gas flow rate. Process gas control subroutine 460 is invoked by chamber manager subroutine 440 to receive process parameters for the desired gas flow rate from chamber manager subroutine, as are all chamber component subroutines. Normally, the process gas control subroutine 460 opens a gas supply line, and
Repeating (i) reading the required mass flow controller, (ii) comparing the reading to the desired flow rate received from the chamber manager subroutine 440, and (iii) adjusting the flow rate of the gas supply line as needed. To work by. In addition, the process gas control subroutine 460 includes monitoring gas flow rates for dangerous rates and activating a safety shut-off valve if a dangerous condition is detected.

In some processes, an inert gas, such as helium or argon, is flowed into the reactor 10 to stabilize the pressure in the chamber before the reactive process gas is introduced into the chamber. For this process, the process gas control subroutine 460 is programmed to include the step of flowing an inert gas into the chamber 10 for the time required to stabilize the pressure in the chamber, and then The described steps will be performed. In addition, if the process gas is vaporized from a liquid precursor, for example, 1,3,5-trisilanocyclohexane, the process gas control subroutine 460 will pass a delivery gas, such as helium, through the liquid precursor in the bubbler assembly. It will be written to include a whipping step. For this type of process, the process gas control subroutine 460 adjusts the delivery gas flow rate, the pressure in the bubbler, and the bubbler temperature to achieve the desired process gas flow rate. As discussed above, the desired process gas flow rate is transferred to process gas control subroutine 460 as a process parameter. In addition, the process gas control subroutine 460 accesses the stored table containing the required values for a given process gas flow rate to provide the required delivery gas flow rate, bubbler pressure, And obtaining a bubbler temperature. After the required values have been obtained, the delivery gas flow rate, bubbler pressure, and bubbler temperature are monitored, compared to the required values, and adjusted accordingly.

The pressure control subroutine 470 includes program code for controlling the pressure in the reactor 10 by adjusting the size of the opening of the throttle valve in the exhaust pump 32. The size of the throttle valve opening is set to control the chamber pressure to a desired level with respect to the total process gas flow, the size of the process chamber, and the pump set point pressure for the exhaust pump 32. When the pressure control subroutine 470 is invoked, the desired or target pressure level is received from the chamber manager subroutine 440 as a parameter. The pressure control subroutine 470 measures the pressure in the reactor 10 by reading one or more conventional manometers connected to the chamber, compares the measured value to a target pressure, and a PID (proportional, Integral and derivative) values are obtained from the stored pressure table, and the throttle valve is operated in accordance with the PID values obtained from the pressure table. Alternatively, the pressure control subroutine 470 may be written to open or close the throttle valve to a particular opening size to adjust the reactor 10 to a desired pressure.

The heater control subroutine 480 includes program code for controlling the temperature of the heating module or radiant heating used to heat the susceptor 12. The heater control subroutine 480 is also invoked by the chamber manager subroutine 440 and receives a target, or set point temperature parameter. The heater control subroutine 480 measures the temperature by measuring the voltage output of a thermocouple located within the susceptor 12, compares the measured temperature to the set point temperature, and applies the measured temperature to the heating module to achieve the set point temperature. Increase or decrease the applied current. The temperature is obtained from the measured voltage by looking up the corresponding temperature in a stored conversion table and by calculating the temperature using a fourth order polynomial.
The heater control subroutine 480 includes a ramp up / up of the current applied to the heating module.
Control the fall slowly. Slow start / stop increases the life and reliability of the heating module. In addition, a built-in fail-safe mode can be included to detect process safety compliance, and if the reactor 10 is not properly configured, operation of the heating module can be stopped.

The plasma control subroutine 490 sets the power level of the RF bias voltage applied to the process electrode in the reactor 10 and optionally sets the level of the magnetic field generated in the reactor. Including program code.
Similar to the chamber component subroutine described above, the plasma control subroutine 490 is invoked by the chamber manager subroutine 440.

The above description of the CVD system is provided primarily for illustrative purposes, and other plasma CVD devices, such as electron cyclotron resonance (ECR) plasma CVD devices, inductively coupled RF high density plasma CVD devices, etc., may be employed. Can be done. In addition, variations on the systems described above are possible, for example, susceptor designs, heater designs, placement of RF power connections, and other variations. For example, a wafer could be supported and heated by a resistively heated susceptor. The pretreatment and method for forming the pretreatment layer of the present invention are not limited to any particular apparatus or any particular plasma excitation method.

Deposition of Nanoporous Silicon Oxide Layer in Three-Layer Gap Filling Process The nanoporous silicon oxide layer of the present invention is used in a three-layer gap-filling process as shown in FIG. 5 using the PECVD chamber of FIG. Can be done. Referring to FIG. 5, a wafer is positioned (200) in a reactor 10 and a layer of silicon oxide substrate is
Deposited from a plasma containing a reactive silicon-containing compound such as dimethylsilane by a CVD process (205). The deposition step 205 may include a capacitively coupled plasma or a combination of both inductive and capacitive plasma in the process chamber 15 according to methods known in the art. An inert gas such as helium is commonly used for PECVD deposition to assist in plasma generation. The nanoporous gap-filling layer of the present invention is then uniformly dispersed in the gap-filling layer by depositing a silicon / oxygen-containing material containing a more unstable organic group on the liner layer. (210) by controlled annealing of the silicon / oxygen containing material deposited to form a microscopic gas pocket. The gap filling layer is preferably
Self-planarize by condensing hydrogen peroxide onto the surface and reacting hydrogen peroxide with a silicon-containing compound or mixture containing labile organic groups.
A cap layer is then deposited over the gap-fill layer, preferably using the same process that deposited the liner layer (215). The wafer is then placed in the reactor 1
It is removed from 0 (220).

Referring to FIGS. 6A-6E, the three-layer gap-fill process provides a PECVD liner layer 300 of an oxidized reactive silicon-containing compound. The liner layer 300
It acts as an isolation layer between the subsequent nanoporous gap filling layer 302 and the underlying substrate surface 304 and metal interconnects 306, 308, 310 formed on the substrate surface. The nanoporous gap-filling layer 302 is made of PECVD of an oxidized reactive silicon-containing compound.
It is capped by the cap layer 312. This process is performed in the CVD reactor 1
0 is implemented and controlled using a computer program stored in the memory 38 of the computer controller 34 for the C.O.

Referring to FIG. 6A, a PECVD liner layer 300 is formed in a reactor 10 by a reactive silicon-containing compound such as dimethylsilane ((CH ₃ ) ₂ SiH ₂ ), an oxidizing gas such as N ₂ O, and helium. Is deposited by introducing a carrier gas. The substrate is maintained at a temperature of about -20 to about 400C, and preferably at a temperature of about 15 to 20C, during the deposition of the PECVD liner layer. PECVD liner layer 30
Zero is deposited with a process gas that includes a mixture of a reactive silicon-containing compound at a flow rate of about 5 sccm to about 500 sccm and an oxidizing gas at a flow rate of about 5 sccm to about 2000 sccm. The process gas is provided by an inert gas such as He, Ar, Ne or a relatively inert gas such as nitrogen at a flow rate of about 0.2 to about 20 lpm, which is not normally incorporated into the membrane. Conveyed. The process gas reacts at a pressure of about 0.2 to about 20 Torr, preferably less than 10 Torr, to form a conformal silicon oxide layer on the substrate surface 304 and the metal lines 306, 308, 310. The reaction is conducted at a power density ranging from 0.05 W / cm ² to 1000 W / cm ² , preferably less than about 1 W / cm ² , most preferably about 0.1 to about 0.3 W / cm ² . Plasma enhanced at power densities that span a range.

High frequency RF of approximately 13.56 MHz for a single 8 ″ wafer chamber
A source is preferably connected to the gas distribution system and driven at about 10 to about 200 W, while a 350 kHz to MHz low frequency RF source is optionally connected to the susceptor and driven at about 0 to about 100 W. In a preferred embodiment, the high frequency RF source is driven with about 20-200 W of pulsed RF power and the low frequency RF source is driven with about 0-50 W of pulsed RF power. High frequency RF
If the power is not pulsed, the power level is preferably from about 10 W to about 150 W
W range.

The oxidized liner layer is then annealed at a pressure below the deposition pressure and at a temperature from about 200 to about 450 ° C. Optionally, the anneal could be performed after the deposition of an additional dielectric layer.

The above process conditions result in the deposition of a PECVD liner layer 300 (at about 2000 ° per minute) for the subsequent deposition of the gap fill layer 302 shown in FIG. 6B.
The liner layer obtained from dimethylsilane has sufficient C—H to be hydrophobic.
It has bonding and is an excellent moisture barrier.

The process gas for the nanoporous gap-filling layer 302 is one of a silicon-containing compound having an unstable organic group, a non-silicon-containing component having an unstable organic group, and a reactive silicon-containing component. As described above, it includes hydrogen peroxide (H ₂ O ₂ ) which is vaporized and mixed with an inert carrier gas such as helium.

The process gas flow rate is 20-1000 sccm, 5
0.1 to 3 g / min for 0% H ₂ O ₂ and 0-2000 sc for He
cm. Preferred gas flow rate, 2g 50-500sccm, from 0.3 relative to 50% H ₂ O ₂ with respect to the silicon-containing compound having a labile organic atomic group
/ Min, and 100-500 seem for He. These flow rates are provided for a chamber having a volume of approximately 5.5 to 6.5 liters. Preferably, reactor 10 is configured to provide about 0.2 to about 5 t during deposition of gap-fill layer 302.
orr pressure. The gap filling layer 302 may be partially cured as shown in FIG. 6C to remove volatile constituents such as water prior to the deposition of the cap layer 312 as shown in FIG. 6D. Cure is accomplished by pumping the wafer to 10 Torr or less under an inert gas atmosphere in the reactor 10 while progressively heating the wafer to a higher temperature.

The gap-filling layer is preferably annealed at increasing temperatures to retain the gaseous products as dispersed microscopic bubbles and / or to provide optional labile organic moieties. Into dispersed microscopic gas bubbles that are retained as voids in a closed cell structure within the cured silicon oxide film. A preferred anneal process includes a heating time period of about 10 minutes and includes ramping the temperature at about 50 ° C./min to a final temperature of about 400 ° C. or more. The dispersion of gas bubbles is
It can be controlled by altering the temperature / time profile and by controlling the concentration of labile organic groups in the deposited film.

Referring to FIG. 6D, after the deposition of the gap filling layer 302, the reactor 10 resumes the deposition of the reactive silicon-containing component, optionally for the deposition of the cap layer 312. Referring to FIG. 6E, after deposition of the cap layer, the deposited layer is further annealed in a furnace or another chamber at a temperature of about 200 to 450 ° C. to drive out residual volatile products such as water. Of course, the process conditions will vary according to the desired properties of the deposited film.

Deposition of Dual Damascene Structure A dual damascene structure including a nanoporous intermetal dielectric layer is shown in FIG. Preferably, the first dielectric layer 510 comprising the nanoporous silicon oxide layer of the present invention is
12, and then a conventional silicon oxide, silicon nitride, or silicon hydride silicon carbide etch stop 514 is deposited on the first dielectric layer. The etch stop is then patterned to define the contact / via 516 openings. Second
A nanoporous dielectric layer 518 is then deposited over the patterned etch stop,
It is then patterned to define interconnect wiring 520. Next, a single etch process is performed to define the interconnect wiring until the etch stop is reached, and to etch the unprotected dielectric exposed by the patterned etch stop to form the contacts / vias. To define.

A preferred dual damascene structure manufactured in accordance with the present invention includes a liner layer as shown in FIG. 8H, and the method of making that structure is schematically illustrated sequentially in FIGS. FIG. 3 is a cross-sectional view of a substrate having the steps of the present invention formed.

As shown in FIG. 8A, an initial first nanoporous dielectric layer 510 is deposited on a substrate 512 with a thickness of about 5,000 to about 10,000 °, depending on the size of the structure to be fabricated. Deposited and then annealed. As shown in FIG. 8B, a low-k etch stop 514, which is an dimethylsilane layer oxidized as described above for three-layer gap fill, but then on the first nanoporous dielectric layer Using a low level of RF power to a thickness of about 200 to about 1000 °. The low-k etch stop 514 is then patterned and etched to define a contact / via opening 516, as shown in FIG. 8C, and a first nanoporous region in the region where the contact / via is formed. The dielectric layer 510 is exposed. Preferably, low-k etch stop 514 is patterned etched using conventional photolithography and an etching process using fluorine, carbon, and oxygen ions. Low k
Etch stop 514 is etched to pattern contacts / vias,
After the photoresist has been removed, a second nanoporous dielectric layer 518 is deposited over etch stop 514 to a thickness of about 5,000 to about 10,000, as shown in FIG. Is done. The second nanoporous dielectric layer 518 then comprises
As shown in FIG. 8E, the interconnections 520 are preferably patterned with a photoresist layer 522 using a conventional photolithography process. The interconnect lines and contacts / vias are then etched using reactive ion etching or other anisotropic etching techniques to form metallized structures (ie, interconnect lines and contacts / vias, as shown in FIG. 8F). Vias). Any photoresist or other material used to pattern the etch stop 514 or the second dielectric layer 518 is removed using oxygen stripping or other suitable process.

A metallized structure is then formed of a conductive material such as aluminum, copper, tungsten, or a combination thereof. At present, the low resistivity of copper (1.7 μΩ-cm,
There is a tendency to use copper in forming smaller features because of the 3.1 μΩ-cm of aluminum). Preferably, as shown in FIG. 8G, a suitable barrier layer 524, such as tantalum nitride, is first conformed to the metallization pattern.
mal) to prevent migration of copper into the surrounding silicon and / or dielectric material. Thereafter, copper 526 is deposited using chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form a conductive structure. After the structure is filled with copper or other metal, the surface is planarized using chemical mechanical polishing, as shown in FIG. 8H.

Deposition of Adhesion Layer A dual damascene structure is shown in FIG. 9, which includes an oxidized dimethylsilane layer as the adhesion layer between the premetal dielectric layer and the intermetallic nanoporous dielectric layer. An oxidized dimethylsilane layer 612 is deposited on a pre-metal dielectric layer 610, such as a conventional PSG or BPSG layer, and then annealed. A nanoporous intermetal dielectric layer 614 as described herein is then deposited over the adhesive layer 612. A conventional silicon oxide or silicon nitride etch stop 616 is deposited,
Next, the vias 620 are patterned in a conventional manner. A second nanoporous intermetal dielectric layer 622 is then deposited over the patterned etch stop,
It is then patterned to define interconnect wiring. Next, a single etch process is performed to define the interconnect wiring until the etch stop is reached and to etch the unprotected dielectric exposed by the patterned etch stop before metallization. To define contacts / vias.

A preferred dual damascene structure with a nanoporous dielectric layer according to the present invention is shown in FIG. 10H, and the method of making that structure is schematically illustrated in FIGS. 10A-10H in sequence, which is formed on a substrate. 1 is a cross-sectional view of a substrate having the steps of the present invention.

As shown in FIG. 10A, a first nanoporous intermetal dielectric layer 710 is
Above, about 5,000 to about 10,000 $ depending on the size of the structure to be manufactured
Deposited to a thickness of As shown in FIG. 10B, a low-k adhesion layer 714, which is preferably an oxidized dimethylsilane layer, is then deposited on the first nanoporous intermetal dielectric layer 710 by a thickness of about 50 to about 200 °. Deposited. A conventional silicon oxide or silicon nitride etch stop 716 may have about 50 to about 20
Deposited to a thickness of 0 °. A second low k adhesive layer 718, which is preferably an oxidized dimethylsilane layer, is then deposited on etch stop 716 from about 50 to about 2
Deposited to a thickness of 00 °. Etch stop 716 and adhesive layers 714, 718
Next, as shown in FIG. 10C, is patterned and etched to define a contact / via opening 720 and a first nanoporous intermetal dielectric layer in the region where the contact / via is formed. Expose 710. Preferably, the etch stop 716 is patterned etched using conventional photolithography and an etching process using fluorine, carbon, and oxygen ions. After the etch stop 716 and the adhesive layers 714, 718 have been etched to pattern the contacts / vias and the photoresist has been removed, as shown in FIG.
A second nanoporous intermetal dielectric layer 722 overlies second adhesive layer 718 by about 5,000.
To a thickness of about 10,000 °. Second nanoporous intermetal dielectric layer 72
2 are then patterned with a photoresist layer 726, preferably using a conventional photolithographic process, as shown in FIG.
Define 24. The interconnect lines and contacts / vias are then etched using reactive ion etching or other anisotropic etching techniques to form metallized structures (ie, interconnect lines and contacts / vias, as shown in FIG. 10F). Vias). The etch stop 716 or any photoresist or other material used to pattern the second nanoporous intermetal dielectric layer 722 is removed using oxygen stripping or another suitable process.

A metallized structure is then formed of a conductive material, such as aluminum, copper, tungsten, or a combination thereof. At present, the low resistivity of copper (1.7 μΩ-cm,
There is a tendency to use copper in forming smaller features because of the 3.1 μΩ-cm of aluminum). Preferably, as shown in FIG. 10G,
A suitable barrier layer 728, such as tantalum nitride, is first deposited following the metallization pattern to prevent migration of copper into the surrounding silicon and / or dielectric material. Thereafter, copper is deposited using chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form a conductive structure. After the structure has been filled with copper or other metal, the surface is planarized using chemical mechanical polishing, as shown in FIG. 10H.

The present invention is further illustrated by the following examples of deposited nanoporous silicon oxide based films.

[0083] The following examples demonstrate deposition of a nano-porous silicon oxide substrate film having dispersed microscopic Gasuboido. This example is performed using a chemical vapor deposition chamber, specifically a CENTURA "DLK" system manufactured and sold by Applied Materials, Inc. of Santa Clara, California.

Reactive silicon compounds with silicon hydride groups (hypothetical) nanoporous silicon oxide based films were prepared using a 1.0 Torr chamber pressure and 0?
At a temperature of ° C., it was vaporized and deposited from a reactive gas flowing into the reactor as follows: 1,3,5-trisilanocyclohexane 125 sccm hydrogen peroxide (50%) 1000 sccm helium, He 200 sccm substrate Positioned at 600 mils from the gas distribution showerhead, the reactive gas was introduced for 2 minutes. The substrate is then heated at 50 ° C./min for 400 minutes at 400 ° C.
By heating to a temperature of ° C. and heating, the nanoporous silicon oxide substrate film was cured and annealed.

Reactive silicon compounds with thermally labile organic moieties (hypothetical) Nanoporous silicon oxide based membranes were prepared at 1.0 Torr chamber pressure and 0 ° C.
Deposited from the reactive gas vaporized at a temperature of and flowing into the reactor as follows: bis (formyloxysilano) methane 150 sccm hydrogen peroxide (50%) 1000 sccm helium, He 200 sccm substrate gas distribution shower Positioned 600 mils from the head, reactive gas was introduced for 2 minutes. The substrate is then heated at 50 ° C./min for 400 minutes at 400 ° C.
By heating to a temperature of ° C. and heating, the nanoporous silicon oxide substrate film was cured and annealed.

Reactive silicon compounds with thermally labile organic moieties (hypothetical) Nanoporous silicon oxide based membranes were prepared at 1.0 Torr chamber pressure and 0 ° C.
At a temperature of, it was vaporized and deposited from the reactive gas flowing into the reactor as follows: bis (glyoxylylsilano) methane 150 sccm hydrogen peroxide (50%) helium at 1000 sccm helium at 200 sccm He substrate gas distribution Positioned at 600 mils from the showerhead, the reactive gas was introduced for 2 minutes. The substrate is then heated at 50 ° C./min for 400 minutes at 400 ° C.
By heating to a temperature of ° C. and heating, the nanoporous silicon oxide substrate film was cured and annealed.

The reactive silicon-containing component and added thermally labile organic moieties (hypothetical) nanoporous silicon oxide-based membranes were treated at a chamber pressure of 1.0 Torr and 0 ° C.
At a temperature of, it was vaporized and deposited from the reactive gas flowing into the reactor as follows: bis (methylsilano) methane 100 sccm glycidaldehyde 50 sccm hydrogen peroxide (50%) 1000 sccm helium, He 200 sccm the substrate Positioned at 600 mils from the gas distribution showerhead, the reactive gas was introduced for 2 minutes. The substrate is then heated at 50 ° C./min for 400 minutes at 400 ° C.
By heating to a temperature of ° C. and heating, the nanoporous silicon oxide substrate film was cured and annealed.

The reactive silicon-containing component and the added thermally labile organic group (hypothetical) nanoporous silicon oxide-based film were treated at a chamber pressure of 1.0 Torr and 0 ° C.
At a temperature of, vaporized from the reactive gas entering the reactor as follows: 1,3,5-trisilanocyclohexane 100 sccm methyl maleate anhydrous 50 sccm hydrogen peroxide (50%) helium at 1000 sccm, The substrate was positioned at 600 mils from a gas distribution showerhead at 200 sccm He and a reactive gas was introduced for 2 minutes. The substrate is then heated at 50 ° C./min for 400 minutes at 400 ° C.
By heating to a temperature of ° C. and heating, the nanoporous silicon oxide substrate film was cured and annealed.

While the above is directed to preferred embodiments of the invention, other and further embodiments of the invention may be devised without departing from its basic scope,
Its scope is determined by the appended claims.

[Brief description of the drawings]

FIG. 1A is a schematic diagram of a dielectric layer deposited on a substrate by processes known in the art.

FIG. 1B is a schematic diagram of a dielectric layer deposited on a substrate by processes known in the art.

FIG. 2 is a cross-sectional view of a typical CVD reactor configured for use in accordance with the present invention.

FIG. 3 is a view showing a system monitor in the CVD reactor of FIG. 2;

FIG. 4 is a flow chart of a process control computer program product used in connection with the exemplary CVD reactor of FIG.

FIG. 5 is a flowchart illustrating steps performed to deposit a liner layer and a cap layer in a gap filling process according to one embodiment of the present invention.

6A is a schematic diagram of a layer deposited on a substrate by the process of FIG.

FIG. 6B is a schematic diagram of a layer deposited on a substrate by the process of FIG.

FIG. 6C is a schematic diagram of a layer deposited on a substrate by the process of FIG.

FIG. 6D is a schematic diagram of a layer deposited on a substrate by the process of FIG. 5;

FIG. 6E is a schematic diagram of a layer deposited on a substrate by the process of FIG. 5;

FIG. 7 is a cross-sectional view showing a dual damascene structure including the silicon oxide layer of the present invention.

FIG. 8A is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8B is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8C is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8D is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8E is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8F is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8G is a cross-sectional view illustrating one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 8H is a cross-sectional view showing one embodiment of a dual damascene deposition sequence of the present invention.

FIG. 9 is a cross-sectional view showing an adhesive layer including a silicon oxide layer of the present invention between a premetal dielectric layer and an intermetal dielectric layer.

FIG. 10A is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10B is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10C is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10D is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10E is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10F is a cross-sectional view illustrating a dual damascene deposition sequence in which the silicon oxide of the present invention is used to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10G is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

FIG. 10H is a cross-sectional view illustrating a dual damascene deposition sequence used by the silicon oxide of the present invention to bond an intermetal dielectric film to a conventional etch stop.

[Explanation of symbols]

2 ... silicon dioxide (SiO ₂₎ liner layer, 3 ... metal wiring, 4,512,71
2 ... substrate, 5 ... self-planarizing layer, 5 ... self-planarizing low k dielectric layer, 6 ... SiO ₂ cap layer, 10 ... CVD reactor (process chamber), 11 ... gas distribution manifold, 12 ... susceptor 13 ... Support stem, 14 ... Processing position, 15 ... High vacuum area, 17 ... Insulator, 18 ... Process gas supply pipe, 19 ... Gas mixing system, 24 ...
Process gas exhaust hole, 25 RF power supply, 32 vacuum pump, 34 controller, 36 control wiring, 38 memory, 40 first monitor, 42 second monitor, 44
... light pen, 300 ... liner layer, 302: gap filling layer, 304 ... substrate surface, 30
6, 308, 310 metal wiring, 312 cap layer, 312 PECVD cap layer of reactive silicon-containing compound, 410 computer program, 420
Process selector subroutine, 430 ... Process sequencer subroutine, 4
40: chamber manager subroutine, 450: susceptor control subroutine,
460: process gas control subroutine, 470: pressure control subroutine, 48
0 ... heater control subroutine, 490 ... plasma control subroutine, 510 ... first dielectric layer, 514 ... etch stop, 516, 720 ... contact / via opening, 518 ... second dielectric layer, 520, 724 ... interconnection Wiring, 522, 726
.., Photoresist layer, 524, 728, barrier layer, 526, copper, 610, premetal dielectric layer, 612, 714, 718, adhesive layer, 614, 622, 710, 72
2 ... intermetal dielectric layer, 616 ... etch stop, 620 ... via, 714 ... adhesive layer, 716 ... etch stop, 716 ... etch stop, 718 ... second adhesive layer,
718: Second low-k adhesive layer.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Cheung, David United States of America, California, Foster City, Billingsgate Rain, 235 (72) Inventor Yau, Wy-Fan United States of America, California, Mountain View, Gretel Rein 1568F Terms (Reference) 4K030 AA06 AA14 AA16 BA29 BA44 CA04 DA09 FA01 FA10 LA15 5F033 HH08 HH11 HH19 HH32 JJ01 JJ08 JJ11 JJ19 JJ32 KK00 MM02 MM12 MM13 NN06 NN07 QQ09 QQ10 QQ11 QQ25 Q04 RR QS06 BD04 BF07 BF08 BF09 BF27 BF29 BG02 BG03 BG04 BH01 BH10 BJ02 BJ05

Claims (23)

[Claims] 1. A method for depositing a low dielectric constant film, comprising: depositing a peroxide compound on a surface of a substrate; and contacting the deposited peroxide compound with a silicon hydride-containing compound or mixture. Reacting, and annealing the substrate to form a silicon oxide substrate film, whereby dispersed voids are formed in the silicon oxide substrate film. 2. The method according to claim 1, wherein the silicon hydride-containing compound or mixture is formyloxy (CH (O) —O—), glyoxylyl (CH (O) —CO—O—), or formylcarbonyldioxy (CH (O 2.) The method of claim 1, wherein the method comprises a) -O-CO-O-) group. 3. The silicon hydride-containing compound or mixture comprises bis (formyloxysilano) methane, bis (glyoxylylsilano) methane, bis (formylcarbonyldioxysilano) methane, 2,2-bis (formyloxy) Cyrano)
Claims comprising a compound selected from the group consisting of propane, 1,2-bis (formyloxysilano) ethane, 1,2-bis (glyoxylylsilano) ethane, fluorinated carbon-bridged derivatives thereof, and combinations thereof. Item 3. The method according to Item 2. 4. The method of claim 1, wherein the silicon-containing compound or mixture further comprises anhydrous maleic anhydride, 3-formyloxy-2,5-furandione, glycidaldehyde,
4. The method of claim 3, comprising a non-silicon component selected from the group consisting of oxiranyl glyoxalate, dioxiranyl carbonate, dioxiranyl mesoxalate, and glycidic anhydride. 5. The silicon-containing compound or mixture comprises silane, methylsilane, dimethylsilane, disilanomethane, bis (methylsilano) methane, 1,2-disilanoethane, 1,2-bis (methylsilano) ethane,
2,2-disilanopropane, 1,3,5-trisilanocyclohexane, cyclo-
1,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene,
3-dimethyl-disiloxane, 1,3-bis (silanomethylene) disiloxane,
A silicon compound selected from the group consisting of bis (1-methyldisiloxanyl) methane and 2,2-bis (1-methyldisiloxanyl) propane and a fluorinated carbon derivative thereof; and maleic anhydride. Non-silicon component selected from the group consisting of methyl acrylate, 3-formyloxy-2,5-furandione, glycidaldehyde, oxiranyl glyoxalate, dioxiranyl carbonate, dioxiranyl mesoxalate, and glycidic anhydride The method of claim 1, comprising: and. 6. The silicon-containing compound or mixture comprises 1,3,5-trisilanocyclohexane, cyclo-1,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene, bis (formyl) Oxysilano) methane or bis (
Glyoxylylsilano) methane, or a fluorinated carbon cross-linked derivative thereof,
The method of claim 1. 7. The method of claim 1, wherein the dispersed voids are formed by annealing the substrate with a temperature profile that includes a gradual rise to a final temperature of at least 400 ° C. 8. The method of claim 1, wherein the dispersed voids are formed by reacting the deposited peroxide compound with a silicon hydride-containing compound or mixture having a non-planar cyclic structure. Method. 9. A method of depositing a low dielectric constant film on a patterned metal layer on a substrate, comprising forming a conformal liner layer on the patterned metal layer with one or more reactive silicon-containing compounds. Depositing from a process gas comprising: and a oxidizing gas; depositing a peroxide compound on the conformal liner layer; reacting the deposited peroxide compound with a silicon hydride-containing compound or mixture. Annealing the substrate to form a silicon oxide substrate film, whereby dispersed voids are formed in the silicon oxide substrate film. 10. The silicon hydride-containing compound or mixture is bis (formyloxysilano) methane, bis (glyoxylylsilano) methane, bis (formylcarbonyldioxysilano) methane, 2,2-bis (formyloxy) Including a compound selected from the group consisting of silano) propane, 1,2-bis (formyloxysilano) ethane, 1,2-bis (glyoxylylsilano) ethane, fluorinated carbon-bridged derivatives thereof, and combinations thereof. The method of claim 9. 11. The silicon hydride-containing compound or mixture may further comprise methyl maleate anhydride, 3-formyloxy-2,5-furandione, glycidaldehyde, oxiranyl glyoxalate, dioxiranyl carbonate, dioxiranyl. 10. The method of claim 9, comprising a non-silicon component selected from the group consisting of mesoxalate and glycidic anhydride. 12. The silicon hydride-containing compound or mixture includes silane, methylsilane, dimethylsilane, disilanomethane, bis (methylsilano) methane, 1,2-disilanoethane, 1,2-bis (methylsilano) ethane,
2,2-disilanopropane, 1,3,5-trisilanocyclohexane, cyclo-
1,3,5,7-tetrasilano-2,6-dioxy-4,8-dimethylene,
3-dimethyldisiloxane, 1,3-bis (silanomethylene) disiloxane, bis (1-methyldisiloxanyl) methane, and 2,2-bis (1-methyldisiloxanyl) propane, and A compound selected from the group consisting of fluorinated carbon derivatives, methyl maleate anhydride, 3-formyloxy-2,5-furandione, glycidaldehyde, oxiranyl glyoxalate, dioxiranyl carbonate, dioxiranyl methoxa And a non-silicon component selected from the group consisting of glycidic anhydride. 13. The method of claim 9, further comprising the step of depositing a cap layer on said silicon oxide substrate film from a process gas comprising said one or more reactive silicon-containing compounds and said oxidizing gas. 14. The method of claim 1, wherein the silicon hydride-containing compound or mixture is 1,3,5.
-Trisilanocyclohexane, cyclo-1,3,5,7-tetrasilano-2,6
10. The method of claim 9, comprising -dioxy-4,8-dimethylene, bis (formyloxysilano) methane, bis (glyoxylylsilano) methane, or a fluorinated carbon cross-linked derivative thereof. 15. The method of claim 9, wherein the dispersed voids are formed by annealing the substrate using a temperature profile that gradually increases to a final temperature of at least 400 ° C. 16. The method of claim 9, wherein the dispersed voids are formed by reacting the deposited peroxide compound with a silicon hydride-containing compound or mixture having a non-planar cyclic structure. Method. 17. A substrate processing system, comprising: a reactor having a vacuum system and a reaction zone adjacent to a substrate holder; and a gas distribution system connecting the reaction zone to one or more sources of gaseous or liquid reactants. And a controller comprising a computer for controlling the reactor and the gas distribution system; and a memory coupled to the controller, wherein the memory deposits a peroxide compound on a surface of a substrate. Reacting the deposited peroxide compound with a silicon hydride-containing compound or mixture, and annealing the substrate to form a silicon oxide-based film, whereby the dispersed voids are Computer readable for selecting a process formed in a silicon oxide substrate film Comprising a medium usable in a computer comprising program code, a substrate processing system. 18. The substrate processing system according to claim 17, further comprising computer readable program code for depositing a dual damascene structure. 19. A substrate processing system, comprising: a reactor comprising a vacuum system and a reaction zone adjacent to a substrate holder; and a gas distribution system connecting the reaction zone to one or more sources of gaseous or liquid reactants. And a controller comprising a computer for controlling the reactor and the gas distribution system; and a memory coupled to the controller, the memory comprising a conformal liner layer and a patterned metal on a substrate. Depositing from a process gas comprising one or more reactive silicon hydride-containing compounds and an oxidizing gas on a layer; depositing a peroxide compound on the conformal liner layer; Reacting the compound with a silicon hydride-containing compound or mixture; Annealing the substrate to form an iodine-based film, whereby dispersed voids are formed in the silicon oxide-based film.
A substrate processing system comprising a computer usable medium containing computer readable program code for selecting a process comprising: 20. The computer readable program code for depositing a cap layer on the silicon oxide substrate film from a process gas comprising the reactive silicon hydride-containing compound and an oxidizing gas. 20. The system according to 19. 21. A method for forming a dual damascene structure, comprising: depositing a film of a first nanoporous silicon oxide substrate on a substrate; and providing a low k etch stop on the first silicon oxide substrate film. Depositing; etching the low-k etch stop to define a vertical interconnect opening exposing the first silicon oxide substrate film; and depositing the low-k etch stop and the exposed first. Depositing a second nanoporous silicon oxide-based film over the silicon oxide-based film; and defining horizontal interconnects exposing the vertical interconnect openings in the low-k etch stop. Etching said second nanoporous silicon oxide substrate film; and said first nanomultiple through said vertical interconnect opening to define a vertical interconnect. Etching a film of a porous silicon oxide substrate. 22. The first and second silicon oxide based films are dispersed microscopically formed by annealing the substrate using a temperature profile that gradually increases to a final temperature of at least 400 ° C. With a special void
A method according to claim 21. 23. The dispersion of claim 1 wherein said first and second silicon oxide based films are formed by reacting a deposited peroxide compound with a silicon hydride containing compound or mixture having a non-planar cyclic structure. 22. The method according to claim 21, comprising provided microscopic voids.