JP2003051582A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of a memory cell and its characteristics by improving the oxygen barrier property of a lower electrode of a FeRAM memory cell. SOLUTION: An FeRAM is formed on a barrier layer B1a made of an alloy of Al (aluminum) and Ir (iridium).
Pt to be the lower electrode 10a of the capacitor C of the memory cell
After depositing the (platinum) film, the atmosphere is
Annealing (heat treatment) is performed at 0 to 700 ° C. as a result,
A Pt crystal grain boundary in a Pt film composed of a plurality of crystal grains has A
Since l ₂ O ₃ (aluminum oxide) is formed, even if annealing is then performed in an oxygen atmosphere for crystallization of the PZT film serving as the capacitance insulating film 11a, for example,
Oxygen can be prevented from penetrating into the lower electrode 10a, the barrier layer B1a thereunder, and the lower plug P1 via the grain boundaries of the Pt crystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to FeRAM (ferroelectric random access memory).

[0002]

2. Description of the Related Art Ferroelectric memory (FeRAM) is a lead zirconate titanate (PZT: (Pb (Z
It is a non-volatile memory that utilizes the binary property of the polarization state such as r _y Ti _Z ) O ₃ ), y + z = 1). The memory cell of this FeRAM includes a memory cell selection MISFET and this MI
It is composed of an SFET and an information capacitor connected in series, and a ferroelectric material such as PZT is used for the capacitive insulating film of the capacitor.

As will be described in detail later, the lower electrode of the capacitor and the source and drain regions of the memory cell selecting MISFET are connected by a plug made of a conductive film.

On the other hand, heat treatment for crystallization and heat treatment for recovering characteristics after etching are indispensable for forming a capacitance insulating film made of a ferroelectric substance.

However, since this heat treatment is carried out in an oxygen atmosphere, for example, oxygen diffuses into the lower electrode and the plug, and an oxide is generated at these portions, which is a cause of conduction failure. .

[0006] For example, in Japanese Unexamined Patent Publication No. 2000-174224, an oxygen barrier alloy layer is provided on the interface between the diffusion prevention layer TiN and the lower electrode, and during the heat treatment for crystallization of the dielectric thin film,
A technique for preventing oxygen from passing through a lower electrode to diffusion-preventing TiN or a polycrystalline silicon plug is described.

[0007]

DISCLOSURE OF THE INVENTION The present inventors have found that FeR
We are conducting research and development on AM, and are considering measures for the above-mentioned conduction failure problem.

As a countermeasure against the problem of conduction failure, various techniques for providing a barrier film for preventing oxidation between the lower electrode of the capacitor and the plug have been studied. Further, as the barrier film, TiAlN (titanium aluminum nitride), TaSiN (tantalum silicon nitride) are used.
Alternatively, a laminated film of Ir (iridium) and Ti (titanium) has been studied, but its antioxidant effect was not sufficient.

Therefore, in order to complement the antioxidation effect, the processing conditions are weakened such as the heat treatment for crystallization and the heat treatment temperature for recovering the characteristics after etching to weaken the treatment conditions so that the lower electrode of the capacitor and the plug are The continuity between them was secured.

However, heat treatment for crystallization,
If the heat treatment conditions for recovering the characteristics after etching are weakened, there is a problem that the crystallization and the recovery of the characteristics become insufficient, and the polarization characteristics of the ferroelectric material forming the capacitor insulating film cannot be secured.

Particularly, with the high integration of memory cells, the diameter of the plug and the area of the capacitor insulating film tend to be miniaturized.
It is becoming more and more important to take measures against poor conduction and to secure the characteristics of the ferroelectric material forming the capacitor insulating film.

An object of the present invention is to provide a technique for improving the oxygen barrier property of the lower electrode of a memory cell and reducing the poor connection between the lower electrode and the plug (conductive portion connected to the lower electrode). is there.

Another object of the present invention is to improve the yield of memory cells by improving the connection between the lower electrodes of the memory cells and the plugs, and to improve the characteristics thereof.

Another object of the present invention is to improve the characteristics of the memory cell by improving the film quality of the ferroelectric material forming the capacitive insulating film of the memory cell.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) The method of manufacturing a semiconductor device according to the present invention comprises:
A second conductor formed by forming a first conductor made of an alloy containing Al and a first metal as a main component on a semiconductor substrate and electrically connecting to the first conductor on the first conductor. After the body is formed or simultaneously with the formation of the second conductor, a high temperature is maintained in an oxidizing atmosphere. By this high temperature holding, Al oxide is formed in the crystal grain boundary of the second conductor, and it is possible to prevent oxygen from diffusing through the lower electrode.

(2) A semiconductor device of the present invention comprises a first conductor formed on a semiconductor substrate and containing an Al oxide therein, and a first insulating film formed on the first conductor. , With.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

The stack type F according to the first embodiment of the present invention
A method of manufacturing an eRAM will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, for example, 10Ω
A p-type well 3 is formed in a semiconductor substrate 1 made of p-type single crystal silicon having a specific resistance of about cm. The p-type well 3 is formed by ion-implanting p-type impurities such as boron (B) into the semiconductor substrate 1 and then annealing the semiconductor substrate 1 to thermally diffuse the impurities.

Next, a field oxide film 2 for element isolation is formed on the main surface of the semiconductor substrate 1. This field oxide film 2 is formed by the well-known LOCOS (Local Oxidation of S
ilicon) method. This field oxide film 2
The region surrounded by becomes the active region, and the n-channel type MISFET Qn for memory cell selection is formed in this region. Although the LOCOS method is used here as the element isolation method, the well-known STI (Shallow Trench Isolation) is used.
The method may be used.

Next, the surface of the semiconductor substrate 1 (p-type well 3) is wet-cleaned using a hydrofluoric acid-based cleaning liquid, and then a clean gate oxide film 5 is formed on the surface of the p-type well 3 by wet oxidation. .

Next, a conductive film such as a polycrystalline silicon film is deposited on the semiconductor substrate 1 and patterned to form a gate electrode G on the main surface of the p-type well 3.

Next, n-type impurities such as phosphorus (P) are ion-implanted on both sides of the gate electrode G on the p-type well 3 to form n-type semiconductor regions 7a and 7b (source and drain regions).

Through the above steps, the n-channel type MISFET Qn (memory cell selecting MISFET) forming the FeRAM memory cell is formed.

Then, on the upper portion of the semiconductor substrate 1, for example,
After depositing a silicon oxide film 9 of about 450 nm by a CVD (Chemical Vapor Deposition) method, C
The surface is flattened by polishing by the MP (Chemical Mechanical Polishing) method.

Through the above steps, the n-channel type MISFETQn (memory cell selecting MISFET) forming the FeRAM memory cell is formed.

Next, as shown in FIG. 2, using the resist film (not shown) on the silicon oxide film 9 as a mask, the source / drain regions 7a and 7b of the n-channel type MISFET Qn are formed.
The contact hole C1 is formed by removing the upper silicon oxide film 9. Next, contact hole C1
A conductive film such as Si (silicon) is deposited on the silicon oxide film 9 including the inside. Then, the conductive film outside the contact hole C1 is removed by the CMP method or etch back to form the plug P1. A refractory metal film such as W (tungsten) may be used instead of silicon.

Next, the capacitor C is formed on the plug P1 on the source / drain region 7b. The process will be described in detail below with reference to FIGS. 4 to 7 are enlarged views of the vicinity of the plug P1 on the source / drain region 7b.

First, as shown in FIG. 3, Al (aluminum) is formed on the silicon oxide film 9 including the plug P1.
And a barrier layer B1 made of an alloy of Ir (iridium) is deposited to a thickness of 50 nm. This barrier layer B1 is made of, for example, Al
However, it can be formed by a sputtering method using an alloy target having an atomic percentage (at%) of 30%. The barrier layer B1 formed by this method is amorphous (amorphous).

Next, the Pt (platinum) film 10 to be the lower electrode is formed by sputtering using a pure Pt target.
Deposit 0 to 200 nm. The Pt film 10 is formed by a sputtering method, so that the (111) plane of the Pt crystal grows parallel to the substrate surface. Thus, the Pt film 10 has the orientation of the (111) plane. If the PZT film, which is a ferroelectric film, is formed on the Pt film 10 having the (111) plane orientation as described above, the PZT film also has (11)
1) It has a plane orientation. The PZT film having the orientation of the (111) plane has a larger residual polarization amount than the non-oriented PZT film. The remanent polarization amount means a polarization amount retained when a positive or negative electric field higher than the coercive electric field is once applied and then the electric field is returned to zero again. The larger the remanent polarization amount, the information retention characteristics and the writing / writing
Readout characteristics can be improved, and the number of times the electric field is applied can be increased. Further, the Pt film has, for example, an oxygen solid solution limit in crystals and a small volume change compared to Ru (ruthenium) film and Ir (iridium) film, and an alignment film suitable for the alignment of the ferroelectric film. Since it is easily obtained, it is suitable for use as an electrode. An adhesion layer made of Ti (titanium), TiN (titanium nitride), or a laminated film of these may be formed between the silicon oxide film 9 and the barrier layer B1.

After that, RTA (Rapi) for 30 seconds at 500 to 700 ° C. in an atmosphere containing oxygen (in an oxidizing atmosphere).
d Thermal Anneal). This anneal is
At the grain boundary of the Pt crystal of the Pt film forming the lower electrode, Al ₂
Performed to form O ₃ (aluminum oxide). The oxygen partial pressure, temperature, and processing time are appropriately adjusted so as to control the diffusion of oxygen into the Pt film 10 and to promote the diffusion of Al in the barrier layer B1 into the Pt film 10. To do.

That is, as shown in FIG. 4, the Pt film 10 on the barrier layer B1 is composed of a plurality of crystal grains. As shown in FIG. 5, Al diffuses from the barrier layer B1 to the grain boundary of the Pt crystal in the Pt film 10 and is processed in an atmosphere containing oxygen. Therefore, the Pt crystal in the Pt film 10 is processed. At the grain boundaries of
Oxygen is supplied. As a result, Al reacts with oxygen and P
Al ₂ O ₃ (aluminum oxide) is formed at the grain boundaries of the Pt crystal in the t film 10. In addition to the grain boundaries of the Pt crystal, Al ₂ O ₃ is also formed on the surface of the Pt film 10. This is because the oxygen supply amount is the largest on the surface of the Pt film 10 and the oxidation reaction is promoted.

Here, the film thickness of the Pt film 10 is 100 to 2
Since it is about 00 nm and the Pt crystal grain size is also about the same, the conduction of the lower electrode to the barrier layer B1 and the plug P1 is not prevented by Al ₂ O ₃ .

Here, a Pt film is formed by a sputtering method,
The method of annealing after that was explained, but the Pt film was MOC.
It can also be formed by a VD (metal organic chemical vapor deposition) method. In that case, since the film formation process itself is carried out at a high temperature in an atmosphere containing oxygen, A is not formed at the grain boundary of the Pt crystal during the Pt film formation.
l ₂ O ₃ can be formed. Therefore, the annealing process for forming Al ₂ O ₃ described above can be omitted.

Next, as shown in FIG. 6, in order to remove Al ₂ O ₃ on the surface of the Pt film 10, the surface of the Pt film 10 is etched by about 10 nm by sputter etching. Since Al ₂ O _{3 on the} surface of the Pt film 10 is a low dielectric constant film, if a film that exists between the lower electrode and the PZT film formed thereon exists, the voltage applied to the PZT film is increased. Otherwise, the desired operation (polarization characteristic) cannot be obtained. Therefore, by removing Al ₂ O ₃ on the surface of the Pt film 10, it is possible to suppress an effective drop in the applied voltage to the PZT film. In addition, it is possible to reduce deterioration of polarization characteristics.

The annealing conditions are as follows: the thickness of Al ₂ O _{3 on} the surface of the Pt film 10 is thin, or Al on the surface of the Pt film 10 is Al.
If it can be adjusted that ₂ O ₃ is not formed, the above-mentioned etching process of the surface of the Pt film 10 can be omitted. Further, even when the operating voltage can be increased, the above-described etching process of the surface of the Pt film 10 can be omitted.

Next, as shown in FIG. 7, a PZT film 11 which is a ferroelectric film is deposited on the Pt film 10 for 100 to 150 n.
Deposit about m. As described above, the PZT film 11 is
Since it is formed on the Pt film 10 having the orientation of the (111) plane, it has the orientation of the (111) plane in which the polarizability is large.

The composition of the PZT film will be described below.
It PZT is Pb (Zr_yTi_z) O ₃(Y + z = 1)
It is represented by. Composition ratio of these atoms forming the PZT film
Is derived from the crystal structure of PZT (herovskite structure)
Be done. There is one Pb atom in PZT at each of the eight corners of the cube.
Zr or Ti atoms are arranged in a cubic shape.
It is located in the center. In addition, the oxygen atom is a cubic
It is located at the center of each surface. Therefore, in the cube,
1 (1/8 x 8) Pb and 1 Zr or T
i and 3 (1/2 × 6) oxygen atoms exist.

Further, since the Pb atom in the PZT film has a property of being easily volatilized, when the PZT film 11 is formed, Pb
An amorphous film having a composition ratio of b of 1 + α is deposited. This amorphous film is crystallized by annealing (heat treatment) performed after film formation.

After that, in order to crystallize the PZT film 11,
RTA (heat treatment) for 30 seconds at 700 ° C in an oxygen atmosphere
I do. The annealing process for forming Al ₂ O ₃ described above is omitted, and in the RTA (heat treatment) process for this crystallization, the grain boundary of the Pt crystal in the Pt film 10 is A.
l ₂ O ₃ may be formed.

As described above, according to this embodiment, the barrier layer B1 made of an alloy of Al (aluminum) and Ir (iridium) is formed under the lower electrode, and annealing is performed in an atmosphere containing oxygen. Since Al ₂ O ₃ is formed at the grain boundary of the Pt crystal in the Pt film 10, even if annealing is subsequently performed in an oxygen atmosphere for crystallization of the PZT film 11, the Pt crystal of Oxygen can be prevented from entering (diffusing) into the lower electrode, the barrier layer B1 thereunder, and the plug P1 in the lower layer via the grain boundaries.

The Pt crystal itself is chemically stable and hardly dissolves and diffuses other elements including oxygen, but on the other hand, mass transfer easily occurs at the crystal grain boundaries of the Pt film. Pt
By forming Al ₂ O ₃ at the grain boundary of the Pt crystal in the film 10, this grain boundary diffusion can be prevented and the substance permeability in the Pt film 10 can be largely prevented.

As a result, it is possible to prevent the barrier layer B1 and the plug P1 from being oxidized, and it is possible to reduce the conduction failure due to the oxide.

The barrier layer B1 serving as a supply source of Al is made of an alloy of Ir and Al. The alloy is formed by allowing the Al element to exist in a solid state with a high melting point, and by annealing as described above, This is to prevent Al in the barrier layer from melting. Therefore, an alloy of Al and another metal may be used. In addition to Ir, other metals include Ru and Re (rhenium). Especially, Ir, Ru and Re are
It is suitable for use as an alloy material with Al because it has conductivity even if it has a low oxidation rate or is oxidized into an oxide. Further, as a material replacing Al, the oxide is stable, and the diffusion rate of oxygen in the oxide is low.
Alternatively, Cr (chrome) or the like may be used.

Further, in the present embodiment, Al and I
A barrier layer was formed by a sputtering method using an alloy target of r, and a laminated film of Al and Ir, for example, Ir-
An Al layer, an Al-Ir layer, an Ir-Al-Ir layer, or the like can be used as the barrier layer. The stacking order and number of stacks are
It can be set arbitrarily. Further, such a laminated film may be annealed in an oxygen-free atmosphere to form an alloy layer. Regarding the method of forming this barrier layer, in addition to an alloy of Ir and Al,
It can also be applied to the alloy of Ru or Re described above and Si or Cr.

Further, as described above, the Pb atoms in the PZT film have a property of being easily separated from the crystal, and the separation of the Pb atoms deteriorates the polarization characteristics of the PZT film. In the crystallization annealing of the PZT film, Pb easily separates from PZT and diffuses into the Pt film because of the high temperature. The Pt crystal itself is chemically stable and does not easily dissolve and diffuse other elements, but P
The crystal grain boundaries of the t film are dominated by diffusion due to mass transfer.
According to the present embodiment, since Al ₂ O ₃ is formed at the grain boundary of the Pt crystal in the Pt film 10, Pb passes through the grain boundary of the Pt crystal and the lower electrode and the barrier layer below it. B1 or
Furthermore, it is possible to prevent the diffusion to the lower layer plug P1. Further, it is possible to prevent the diffusion of other elements forming the PZT film. As a result, the deterioration of the polarization characteristics of the PZT film can be reduced and the retention characteristics can be improved. This retention characteristic indicates the information retention time of the memory cell (the time during which the information stored in the information capacitor can be read).

In the silicon oxide film 9 etc., H ₂
(Hydrogen) and H ₂ O (water) are contained, and this H ₂ and H ₂
The penetration of O into the PZT film on the Pt film deteriorates the polarization characteristics of the ferroelectric film.

However, according to the present embodiment, P
Al in the grain boundary of the Pt crystal in the t film 10 ₂O₃Is formed
Therefore, H in the silicon oxide film 9 etc.₂And H₂O is this P
It may enter the PZT film on the Pt film through the grain boundary of the t crystal.
And can be prevented. As a result, the polarization of the PZT film
It is possible to reduce deterioration of characteristics. In particular, the Pt film 10
Has a catalytic action, and H₂Radicalize. This radio
When cal hydrogen reaches the PZT film, the reducing action
Will destroy its crystallinity. However, the book
According to the embodiment, the grain boundary of the Pt crystal in the Pt film 10 is
Al₂O₃On the Pt crystal surface,
The catalytic action can be suppressed.

Then, as shown in FIG. 8, a PZT film 11 is formed.
IrO ₂ (iridium oxide) film 1 serving as the upper electrode
2 is deposited to a thickness of about 150 nm. The IrO ₂ film 12 is
For example, it can be formed by a reactive sputtering method using an Ir target in an Ar (argon) and O ₂ (oxygen) atmosphere.

Next, Al ₂ O ₃ is deposited to a thickness of about 100 nm on the IrO ₂ film 12, and etching is performed by using a resist film (not shown) as a mask to etch the hard mask HM.
To form.

Then, as shown in FIG. 9, the IrO ₂ film 12, the PZT film 11, the Pt film 1 are used with the hard mask as a mask.
0 and the barrier layer B1 are plasma-etched to form barrier layers B1a and Pt made of an alloy of Al and Ir on the plug P1 on the source / drain region 7b.
A lower electrode 10a made of a film, a capacitive insulating film 11a made of a PZT film 11, and an upper electrode 12a made of an IrO ₂ film 12 are formed. The lower electrode 10a and the capacitive insulating film 1
A capacitor C is composed of 1a and the upper electrode 12a.

Then, in order to recover the defects on the side wall of the capacitor C (PZT film 11a) caused by the plasma etching, annealing is performed at 650 ° C. for 1 hour in an oxygen atmosphere.

At this time, according to the present embodiment, the plug P
1, a barrier layer B1a made of an alloy of Al and Ir is formed, and the side wall of the barrier layer B1a is exposed to an oxygen atmosphere. Therefore, at the initial stage of annealing, the side wall of the barrier layer B1a is A.
An l ₂ O ₃ B1b film is formed (FIG. 10). Therefore, this Al ₂ O ₃ B1b can prevent the diffusion of oxygen due to this annealing. In particular, oxidation of the plug P1 on the source / drain region 7b can be prevented. Since the surface of the plug P1 on the source / drain region 7a is exposed to the oxygen atmosphere, the surface can be oxidized. The oxide film on the surface of the plug is removed by etching in a subsequent step, for example, when forming the contact hole C2.

Then, as shown in FIG. 11, on the hard mask HM (capacitor C) and the silicon oxide film 9,
The Al ₂ O ₃ film S1 is deposited by the sputtering method. This A
The l ₂ O ₃ film S1 plays a role of a reduction resistant barrier film. That is, as described above, the silicon oxide film used as an interlayer insulating film, which contains the H ₂ and H ₂ O, the H ₂
Intrusion of H ₂ O and H ₂ O into the PZT film on the Pt film deteriorates the polarization characteristics of the ferroelectric film.

Therefore, by covering the capacitor C with the Al ₂ O ₃ film S1, H ₂ and H ₂ O are formed in the PZT film from the silicon oxide films (13, 20) formed on the capacitor C.
To prevent intrusion. The H ₂ and H ₂ O are not only present in the film, but can also be generated during film formation. Further, it may occur not only in the step of forming an interlayer insulating film made of a silicon oxide film or the like but also in the step of forming a plug (P2 etc.).

However, according to the present embodiment, it is possible to reduce the influence of H ₂ and H ₂ O in these steps and in the film. As a result, the deterioration of the polarization characteristics of the ferroelectric film can be reduced.

Since the hard mask HM is made of Al ₂ O ₃ , this mask can also be left as a reduction resistant barrier film, and the reduction resistant barrier film S1 can be used.
However, since the Al ₂ O ₃ film having the same quality as the hard mask is used, etching at the time of forming the contact hole C2 described later becomes easy.

Further, the Al ₂ O ₃ film S1 and the hard mask HM
Can prevent not only the invasion of H ₂ and H ₂ O but also the invasion of oxygen during the subsequent treatment in an oxygen atmosphere.

Through the above steps, the capacitor C forming the FeRAM is formed. Since the capacitor C has a so-called stack structure formed on the source / drain region 7b of the n-channel type MISFET Qn, it is Fe.
The area of the RAM memory cell can be reduced. In addition, a single capacitor C and a MISFET Qn connected in series to the single capacitor C
By configuring one cell with (1T1C cell), the area of the FeRAM memory cell can be further reduced.

Then, as shown in FIG.
Then, the silicon oxide film 13 is deposited. Then, the upper power
Silicon oxide film 13 on the pole 12a, hard mask HM
Al ₂O₃And etching the reduction resistant barrier film S1
Thus, the contact hole C2 is formed. Also,
On the plug P1 on the drain and drain regions 7a.
The toe hole C2 is formed. At this time, the above-mentioned plug P1
Perform over etching to remove the oxide film above
(Not shown).

Then, a conductive film of tungsten (W) or the like is deposited on the silicon oxide film 13 including the inside of the contact hole C2. Subsequently, the conductive film outside the contact hole C2 is removed by the CMP method or the etch back to form the plug P2.

Then, an Al film is deposited on the silicon oxide film 13 including the plug P2, and the Al film is etched into a desired shape to form a first layer wiring M1.

Next, two more layers of wiring are formed on the first layer wiring M1 by repeating the formation of the silicon oxide film (20 etc.), the plug and the Al film, but illustration and detailed description thereof are omitted. To do.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0067] Particularly, in the above embodiment, Al although the substances formed by oxidizing expressed as Al ₂ O _3, Al and the ratio of O is completely 2: of Al ₂ O _3-X is not a 3 Al like
Similar effects can be obtained even if oxides are generated.

Ir is used as the upper electrode of the capacitor C.
Although an O ₂ film was used and a Pt film was used as the lower electrode, the present invention is not limited to this, and Pt,
A single layer film mainly composed of a platinum group metal such as Ir, IrO ₂ , Ru, RuO ₂ or an oxide or complex oxide thereof, or a laminated film composed of two or more kinds of conductive films selected therefrom. May be used.

Further, in the above-mentioned embodiment, the PZT film is used as the ferroelectric film for the capacitance insulating film, but the present invention is not limited to this and, for example, PLZT (Pb
_1-x La _x (Zr _y Ti _z ) O ₃ ) or the like may be used. In addition, a bismuth layer compound represented by SBT (SrBi ₂ Ta ₂ O ₉ ) and included in a perovskite structure in a broad sense may be used. In this case, the diffusion of Bi in the SBT film can be prevented by Al ₂ O _{3 at the} grain boundary of Pt forming the lower electrode.

In the above embodiment, FeR
Although the AM has been described as an example, a semiconductor device such as a DRAM (Dyna
Widely applicable to micRandom Access Memory).
Examples of such a dielectric film include BST (barium strontium titanate, (Ba, Ti) TiO ₃ ) and S.
TO (strontium titanate, SrTiO ₃ ) and the like can be mentioned. The above-mentioned substances used for the ferroelectric and high-dielectric-constant films may contain an additive element in order to improve their characteristics.

[0071]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

After the second conductor forming the lower electrode of the capacitor of the memory cell is formed on the first conductor made of an alloy containing Al and the first metal as a main component, heat treatment is performed in an oxidizing atmosphere. Since Al ₂ O ₃ is formed at the crystal grain boundaries of the second conductor, it is possible to prevent oxygen and the like from diffusing through the lower electrode.

As a result, it is possible to improve the oxygen barrier property of the lower electrode of the memory cell and reduce the connection failure between the lower electrode and the plug (conductive portion connected to the lower electrode) therebelow.
Further, the yield of the memory cells is improved by reducing the connection failure between the lower electrode of the memory cell and the plug,
In addition, the characteristics of the memory cell can be improved.

Further, it is possible to improve the film quality of the ferroelectric material forming the capacitive insulating film of the memory cell and improve the characteristics of the memory cell.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate showing a method for manufacturing a FeRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a substrate showing a method for manufacturing an FeRAM memory cell according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view of an essential part of a substrate showing a method for manufacturing an FeRAM memory cell according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the FeRAM memory cell according to the embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 field oxide film 3 p-type well 5 gate oxide film G gate electrode 7a n-type semiconductor region (source / drain region) 7b n-type semiconductor region (source / drain region) 9 silicon oxide film C1 contact hole P1 plug B1 Barrier layer 10 Pt film 11 PZT film 12 IrO ₂ film HM Hard mask B1a Barrier layer 10a Lower electrode 11a Capacitance insulating film 12a Upper electrode B1b Al ₂ O ₃ S1 Reduction-resistant barrier film (Al ₂ O ₃ film) 13 Silicon oxide film C2 contact hole P2 plug M1 first layer wiring 20 silicon oxide film C capacitor Qn n channel type MISFET

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiromichi Waki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 5F083 FR02 GA25 JA14 JA15 JA17                       JA36 JA38 JA39 JA40 JA43                       MA06 MA17 MA19 NA01 NA08                       PR33 PR34 PR39 PR40

Claims (53)

[Claims] 1. A step of: (a) forming a first conductor made of an alloy containing Al and a first metal as a main component on a semiconductor substrate; and (b) forming the first conductor on the first conductor. Forming a second conductor electrically connected to the conductor, and (c) holding at a high temperature in an oxidizing atmosphere at the same time as the step (b) or after the step (b). A method of manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (c), an Al oxide is formed inside the second conductor. Production method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (c), A is present in a crystal grain boundary of the second conductor.
1. A method for manufacturing a semiconductor device, characterized in that an oxide is formed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (c), the second conductor suppresses oxygen diffusion. 5. The semiconductor device manufacturing method according to claim 2, wherein the second conductor has a greater effect of suppressing oxygen diffusion as compared with the case where no Al oxide is formed inside. Device manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal has conductivity when it becomes an oxide. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the first metal is made of Ir. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductor has orientation. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductor is made of Pt. 10. The method for manufacturing a semiconductor device according to claim 1, further comprising: (d) removing the Al oxide formed on the surface of the second conductor after the step (c). A method of manufacturing a semiconductor device, comprising: 11. (a) a step of forming a plug on a semiconductor substrate; and (b) an alloy mainly composed of Al and a first metal, which is electrically connected to the plug on the plug. A step of forming a first conductor, and (c) a step of forming a second conductor electrically connected to the first conductor on the first conductor. Of manufacturing a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising: (d) forming an interlayer insulating film on the semiconductor substrate before the step (a).
A method of manufacturing a semiconductor device, comprising: 13. The method of manufacturing a semiconductor device according to claim 11, further comprising: (e) holding a high temperature in an oxidizing atmosphere, simultaneously with the step (c) or after the step (c). A method of manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 11, further comprising: (f) a step of forming a first insulating film on the second conductor after the step (c), and (g) And a step of performing heat treatment in an oxidizing atmosphere after the step (f). 15. The method of manufacturing a semiconductor device according to claim 13, wherein after the step (e), an Al oxide is formed inside the second conductor. Production method. 16. The method of manufacturing a semiconductor device according to claim 14, wherein in the step (g), the second conductor suppresses passage of a substance. 17. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film is made of PZT, and Pb in the PZT is diffused in the second conductor during the step (g). A method of manufacturing a semiconductor device, comprising: 18. The method of manufacturing a semiconductor device according to claim 11, wherein the plug is made of Si or W. 19. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film has orientation. 20. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film is made of a ferroelectric material. 21. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film is made of PZT. 22. (a) a step of forming a plug on a semiconductor substrate; (b) a first conductor made of an alloy of Al and a first metal, which is electrically connected to the plug on the plug. And (c) forming a second conductor on the first conductor that is electrically connected to the first conductor, and (d) after the step (c). In the oxidizing atmosphere, (e) forming the first insulating film on the second conductor, and (f) in the oxidizing atmosphere after the step (e). A method of manufacturing a semiconductor device, comprising: a step of performing heat treatment; and (g) a step of forming a third conductor on the first insulating film. 23. The method of manufacturing a semiconductor device according to claim 22, further comprising (h) a step of forming a second insulating film on the third conductor after the step (g), and (i) The first to the third exposed from the second insulating film
A method of manufacturing a semiconductor device, comprising: a step of removing a conductor and a first insulating film; and (j) a step of performing heat treatment in an oxidizing atmosphere after the step (i). 24. The method of manufacturing a semiconductor device according to claim 23, further comprising (k) on the second insulating film, and the first to third conductors and the first insulating layer after the step (j). A method of manufacturing a semiconductor device, comprising: a step of forming a third insulating film on a side wall of the film; and (l) a step of forming an interlayer insulating film on the third insulating film. 25. The method of manufacturing a semiconductor device according to claim 22, wherein after the step (d), an Al oxide is formed inside the second conductor. Production method. 26. The method of manufacturing a semiconductor device according to claim 22, wherein after the step (d), the second conductor suppresses passage of a substance. 27. The method of manufacturing a semiconductor device according to claim 23, wherein Al is formed on a sidewall of the first conductor by the step (j).
A method of manufacturing a semiconductor device, wherein an oxide is formed. 28. The method of manufacturing a semiconductor device according to claim 24, wherein the second insulating film and the third insulating film are made of Al oxide. 29. (a) a first conductor formed on a semiconductor substrate and containing an Al oxide therein, and (b) a first insulating film formed on the first conductor. A semiconductor device having. 30. The semiconductor device according to claim 29, further comprising (c) an interlayer insulating film formed between the semiconductor substrate and the first conductor. 31. The semiconductor device according to claim 29, wherein the first conductor contains Al oxide. 32. The semiconductor device according to claim 29, wherein an Al oxide is contained in a crystal grain boundary of the first conductor. 33. The semiconductor device according to claim 30, wherein the interlayer insulating film contains H ₂ or H ₂ O. 34. The semiconductor device according to claim 33, wherein the first conductor prevents the first insulating film from being reduced by the H ₂ or H ₂ O. 35. The semiconductor device according to claim 29, wherein the first conductor has an orientation. 36. The semiconductor device according to claim 29, wherein the first conductor is made of Pt. 37. The semiconductor device according to claim 29, wherein the first insulating film is made of a perovskite type ferroelectric material or a high dielectric material. 38. The semiconductor device according to claim 29, wherein the first insulating film has orientation. 39. The semiconductor device according to claim 29, wherein the first insulating film is made of PZT. 40. The semiconductor device according to claim 39, wherein the first conductor prevents a constituent element in the PZT from diffusing via the first conductor. 41. (a) A formed on a semiconductor substrate
a first conductor made of an alloy containing l and a first metal as a main component, and (b) an Al oxide on the first conductor and electrically connected to the first conductor. A semiconductor device comprising: a second conductor including: (c) a first insulating film formed on the second conductor. 42. The semiconductor device according to claim 41, wherein the first metal has conductivity when it becomes an oxide. 43. The semiconductor device according to claim 41, wherein the first metal is made of Ir. 44. (a) a plug formed on a semiconductor substrate; and (b) a first plug made of an alloy containing Al and a first metal as a main component, which is electrically connected to the plug on the plug. 1 conductor, and (c) a second conductor which is on the first conductor and is electrically connected to the first conductor and which contains an Al oxide therein. Semiconductor device. 45. The semiconductor device according to claim 44, further comprising: (d) a first insulating film formed on the second conductor. 46. The semiconductor device according to claim 44, wherein the plug is made of Si or W. 47. The semiconductor device according to claim 44, wherein the second conductor prevents oxygen diffusion into the plug. 48. (a) a plug formed on a semiconductor substrate, and (b) a first plug made of an alloy containing Al and a first metal as a main component and electrically connected to the plug on the plug. 1 conductor, (c) a second conductor that is electrically connected to the first conductor and contains an Al oxide therein, and (d) the second conductor A semiconductor device comprising: a first insulating film formed on the first insulating film; and (e) a third conductor formed on the first insulating film. 49. The semiconductor device according to claim 48, further comprising: (f) a first interlayer insulating film formed between the semiconductor substrate and the first conductor. 50. The semiconductor device according to claim 48, further comprising: (g) a second insulating film formed on the third conductor, (h) on the second insulating film, and the first to third insulating films. A semiconductor device comprising: a third insulating film formed on a sidewall of a third conductor and a first insulating film; and (i) a second interlayer insulating film formed on the third insulating film. 51. The semiconductor device according to claim 48, wherein an Al oxide is formed on a sidewall of the first conductor. 52. The semiconductor device according to claim 50, wherein the second interlayer insulating film contains H ₂ or H ₂ O. 53. The semiconductor device according to claim 52, wherein the third insulating film prevents the H ₂ or H ₂ O from reducing the first insulating film.