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JP2003059946A - GaN-based semiconductor device - Google Patents

GaN-based semiconductor device

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Publication number
JP2003059946A
JP2003059946A JP2001246113A JP2001246113A JP2003059946A JP 2003059946 A JP2003059946 A JP 2003059946A JP 2001246113 A JP2001246113 A JP 2001246113A JP 2001246113 A JP2001246113 A JP 2001246113A JP 2003059946 A JP2003059946 A JP 2003059946A
Authority
JP
Japan
Prior art keywords
layer
gan
undoped
based semiconductor
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001246113A
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Japanese (ja)
Other versions
JP4906023B2 (en
Inventor
Kiyoteru Yoshida
清輝 吉田
Takahiro Wada
崇宏 和田
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Furukawa Electric Co Ltd
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Furukawa Electric Co Ltd
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Priority to JP2001246113A priority Critical patent/JP4906023B2/en
Publication of JP2003059946A publication Critical patent/JP2003059946A/en
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Abstract

(57)【要約】 【課題】 動作時のオン抵抗が低く、大電流動作が可能
なHEMT構造のGaN系半導体装置を提供する。 【解決手段】 全体がGaN系半導体材料で構成され、
第1のアンドープ材料から成る下層3と第1のアンドー
プ材料よりもバンドギャップエネルギーが大きい第2の
アンドープ材料から成る上層4との層構造が基板1の上
に形成され、上層4の表面には、ゲート電極G、ソース
電極S、およびドレイン電極Dが形成されているGaN
系半導体装置Aであって、ソース電極Sとドレイン電極
Dの形成領域4Aにおける上層4の厚みが、他の領域4
Bにおける厚みよりも薄くなっているGaN系半導体装
置。
[PROBLEMS] To provide a GaN-based semiconductor device having a HEMT structure, which has a low on-resistance during operation and can operate at a large current. SOLUTION: The whole is made of a GaN-based semiconductor material,
A layer structure of a lower layer 3 made of the first undoped material and an upper layer 4 made of the second undoped material having a band gap energy larger than that of the first undoped material is formed on the substrate 1. , On which a gate electrode G, a source electrode S, and a drain electrode D are formed
In the system semiconductor device A, the thickness of the upper layer 4 in the formation region 4A of the source electrode S and the drain electrode D is
A GaN-based semiconductor device thinner than the thickness in B.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はGaN系半導体装置
に関し、更に詳しくは、GaN系半導体材料から成るH
EMT構造であって、従来に比べて動作時のオン抵抗が
大幅に低下するので大電流動作が可能なGaN系半導体
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN-based semiconductor device, and more specifically, H made of a GaN-based semiconductor material.
The present invention relates to a GaN-based semiconductor device that has an EMT structure and has a significantly reduced on-resistance during operation as compared with the related art, and is capable of high-current operation.

【0002】[0002]

【従来の技術】GaN,InGaN,AlGaN,Al
InGaNなどのGaN系半導体材料は、例えばGaA
s系の材料に比べてそのバンドギャップエネルギーが大
きく、しかも耐熱度が高く高温動作が優れているので、
これらの材料、とくにGaNを用いて電界効果トランジ
スタ(Field Effect Transistor:FET)や高移動度
トランジスタ(High Electorn Mobility Transistor:
HEMT)などの電子デバイスの開発研究が進められて
いる。
2. Description of the Related Art GaN, InGaN, AlGaN, Al
GaN-based semiconductor materials such as InGaN are, for example, GaA.
Compared to s-based materials, its bandgap energy is large, its heat resistance is high, and its high-temperature operation is excellent.
Using these materials, especially GaN, field effect transistors (FETs) and high mobility transistors (High Electorn Mobility Transistors).
Research and development of electronic devices such as HEMTs is underway.

【0003】GaN系HEMT構造の1例を図5に示
す。このHEMT構造においては、例えばサファイア基
板のような半絶縁性基板1の上に、例えばGaNから成
るバッファ層2、アンドープGaN層3、および前記ア
ンドープGaN層3に比べれば超かに薄いアンドープA
lGaN層4が順次積層して成る層構造が形成されてい
る。
An example of a GaN type HEMT structure is shown in FIG. In this HEMT structure, on the semi-insulating substrate 1 such as a sapphire substrate, the buffer layer 2 made of, for example, GaN, the undoped GaN layer 3, and the undoped A that is extremely thin as compared with the undoped GaN layer 3 are used.
A layered structure is formed by sequentially stacking the lGaN layers 4.

【0004】そして、アンドープAlGaN層4の上に
は、ゲート電極G、ソース電極S、およびドレイン電極
Dが平面的に配置されている。その場合、ゲート電極G
は、直接、アンドープAlGaN層4の上に形成され
る。しかしながら、ソース電極Sとドレイン電極Dは、
一般に、アンドープAlGaN層4の表面のうち、これ
ら電極の形成領域に、一旦、例えばn型不純物であるS
iが高濃度でドーピングされて成るn−AlGaNのコ
ンタクト層5を形成し、このコンタクト層5の上に配置
される。その理由は、これら電極とアンドープAlGa
N層4の間を低抵抗化して動作時のオン抵抗を下げて大
電流動作を実現させるためである。
On the undoped AlGaN layer 4, a gate electrode G, a source electrode S and a drain electrode D are arranged in a plane. In that case, the gate electrode G
Are directly formed on the undoped AlGaN layer 4. However, the source electrode S and the drain electrode D are
In general, on the surface of the undoped AlGaN layer 4, once S, which is an n-type impurity, is temporarily formed in a region where these electrodes are formed.
A contact layer 5 of n-AlGaN is formed by doping i with a high concentration, and is placed on the contact layer 5. The reason is that these electrodes and undoped AlGa
This is because the resistance between the N layers 4 is reduced to reduce the on-resistance during operation to realize a large current operation.

【0005】なお、ソース電極Sとドレイン電極Dを、
直接、アンドープAlGaN層4の上に形成する場合も
あるが、この場合には、これら電極とアンドープAlG
aN層4の間が高抵抗となって大電流動作の実現が困難
となるため、上記したように、両者間にコンタクト層5
を介装した構造が通例である。図5で示したHEMT構
造の場合、アンドープGaNのバンドギャップエネルギ
ーはアンドープAlGaNのバンドギャップエネルギー
よりも小さい。そして、アンドープGaNは単結晶であ
るが、アンドープAlGaNはAlNとGaNの混晶に
なっている。そのため、両層のヘテロ接合界面において
は、結晶歪みに基づくピエゾ圧電効果でピエゾ電界が発
生し、両者の接合界面の直下に2次元電子ガス層6が形
成される。
The source electrode S and the drain electrode D are
It may be formed directly on the undoped AlGaN layer 4, but in this case, these electrodes and the undoped AlG layer 4 are formed.
Since there is a high resistance between the aN layers 4 and it is difficult to realize a large current operation, as described above, the contact layer 5 is formed between them.
The structure in which is interposed is common. In the HEMT structure shown in FIG. 5, the bandgap energy of undoped GaN is smaller than the bandgap energy of undoped AlGaN. And while undoped GaN is a single crystal, undoped AlGaN is a mixed crystal of AlN and GaN. Therefore, at the heterojunction interface between the two layers, a piezo electric field is generated by the piezo-piezoelectric effect due to crystal strain, and the two-dimensional electron gas layer 6 is formed immediately below the interface between the two.

【0006】GaN系材料の上記ヘテロ接合界面で形成
される2次元電子ガス層における電子ガス濃度は、5×
1018〜1×1020/cm3程度であり、この値は、例え
ばGaAs系材料で形成される2次元電子ガス層の電子
ガス濃度が5×1017〜1×1018/cm3程度であるこ
とに比べると、1桁以上高濃度になっている。このHE
MT構造いおいて、ソース電極Sとドレイン電極Dを作
動すると、アンドープAlGaN層4は電子の供給層と
して機能してアンドープGaN層3に電子を供給する。
供給された電子は2次元電子ガス層6の働きで高速移動
してドレイン電極Dへと走行していく。このとき、ゲー
ト電極Gを作動してその直下に所望厚みの空乏層を発生
させることにより、このHEMT構造に各種の変調動作
を実現させることができる。
The electron gas concentration in the two-dimensional electron gas layer formed at the heterojunction interface of the GaN-based material is 5 ×.
It is about 10 18 to 1 × 10 20 / cm 3 , and this value is about 5 × 10 17 to 1 × 10 18 / cm 3 when the electron gas concentration of the two-dimensional electron gas layer formed of a GaAs material is about 5 × 10 17 to 1 × 10 18 / cm 3 . Compared with some, the concentration is higher by one digit or more. This HE
In the MT structure, when the source electrode S and the drain electrode D are activated, the undoped AlGaN layer 4 functions as an electron supply layer and supplies electrons to the undoped GaN layer 3.
The supplied electrons move at high speed by the action of the two-dimensional electron gas layer 6 and travel to the drain electrode D. At this time, by operating the gate electrode G to generate a depletion layer having a desired thickness immediately below the gate electrode G, various modulation operations can be realized in this HEMT structure.

【0007】[0007]

【発明が解決しようとする課題】ところで、図5で示し
たHEMT構造の場合、アンドープAlGaN層4の上
に直接ソース電極Sとドレイン電極Dを形成したHEM
T構造の場合よりも動作時のオン抵抗は小さくなるとは
いえ、これら電極と2次元電子ガス層の間には高抵抗の
アンドープAlGaN層4が所定の厚みで介装された状
態になっているので、動作時のオン抵抗の低下実現に関
しては限界が生じてくる。
By the way, in the case of the HEMT structure shown in FIG. 5, a HEM in which the source electrode S and the drain electrode D are directly formed on the undoped AlGaN layer 4.
Although the on-resistance during operation is smaller than in the case of the T structure, a high resistance undoped AlGaN layer 4 is interposed between these electrodes and the two-dimensional electron gas layer with a predetermined thickness. Therefore, there is a limit to the reduction of the on-resistance during operation.

【0008】また、コンタクト層5は、通常、選択成長
によって形成されているが、仮にこの選択成長を行うこ
となく、動作時のオン抵抗が低下するHEMT構造を製
造することができれば、その工業的なメリットは大きく
なる。本発明は、図5で示した従来のHEMT構造にお
ける上記した問題を解決し、コンタクト層を形成するこ
となく、動作時のオン抵抗の低下を実現することができ
る新規なHEMT構造を有するGaN系半導体装置の提
供を目的とする。
Further, the contact layer 5 is usually formed by selective growth, but if it is possible to manufacture a HEMT structure in which the ON resistance during operation is lowered without performing this selective growth, it is industrially possible. The merit will be great. The present invention solves the above-mentioned problems in the conventional HEMT structure shown in FIG. 5 and has a novel HEMT structure having a novel HEMT structure capable of realizing a reduction in ON resistance during operation without forming a contact layer. An object is to provide a semiconductor device.

【0009】[0009]

【課題を解決するための手段】本発明者らは、GaN系
材料のヘテロ接合界面に形成される2次元電子ガス層の
電子ガス濃度は高く、また、例えばアンドープAlGa
NとアンドープGaNのヘテロ接合界面の場合、アンド
ープAlGaNが薄くなればなるほどアンドープGaN
内の2次元電子ガス層のしみ出し効果でアンドープ層の
キャリアが実効的に増加するため、抵抗が小さくなると
いう現象に着目した。
The inventors of the present invention have found that the two-dimensional electron gas layer formed at the heterojunction interface of a GaN-based material has a high electron gas concentration and, for example, undoped AlGa.
At the heterojunction interface between N and undoped GaN, the thinner undoped AlGaN becomes, the more undoped GaN
Attention was paid to the phenomenon that the resistance decreases because the carriers in the undoped layer effectively increase due to the seeping-out effect of the two-dimensional electron gas layer inside.

【0010】そして、ソース電極とドレイン電極を形成
する領域におけるアンドープAlGaN層を選択的に薄
層化すれば、その領域は従来のコンタクト層と同等の機
能を発揮することができるのではないかとの着想を抱
き、種々の実験を重ねてその着想の正しさを確認し、本
発明のGaN系半導体装置を開発するに至った。すなわ
ち、本発明のGaN系半導体装置は、全体がGaN系半
導体材料で構成され、第1のアンドープ材料から成る下
層と前記第1のアンドープ材料よりもバンドギャップエ
ネルギーが大きい第2のアンドープ材料から成る上層と
の層構造が基板の上に形成され、前記上層の表面には、
ゲート電極、ソース電極、およびドレイン電極が形成さ
れているGaN系半導体装置であって、前記ソース電極
と前記ドレイン電極の形成領域における前記上層の厚み
が、他の領域における厚みよりも薄くなっていることを
特徴とする。
Then, if the undoped AlGaN layer in the region where the source electrode and the drain electrode are formed is selectively thinned, that region may exhibit the same function as a conventional contact layer. Having an idea, various experiments were repeated and the correctness of the idea was confirmed, and the GaN-based semiconductor device of the present invention was developed. That is, the GaN-based semiconductor device of the present invention is entirely composed of a GaN-based semiconductor material, and is composed of a lower layer made of the first undoped material and a second undoped material having a bandgap energy larger than that of the first undoped material. A layer structure with an upper layer is formed on the substrate, and on the surface of the upper layer,
In a GaN-based semiconductor device in which a gate electrode, a source electrode, and a drain electrode are formed, a thickness of the upper layer in a region where the source electrode and the drain electrode are formed is smaller than a thickness in other regions. It is characterized by

【0011】[0011]

【発明の実施の形態】本発明のGaN系半導体装置の1
例Aを図1に示す。この装置Aは、半絶縁性基板1の上
に、例えばGaNから成るバッファ層2、後述する第1
のアンドープ材料から成る下層3、第2のアンドープ材
料から成る上層4が順次積層された層構造が形成されて
いる。そして全体の表面は例えばSiO2のような保護
膜7で被覆されている。
BEST MODE FOR CARRYING OUT THE INVENTION 1 of the GaN-based semiconductor device of the present invention
Example A is shown in FIG. This device A comprises a buffer layer 2 made of, for example, GaN on a semi-insulating substrate 1, a first layer described later.
Of the undoped material and the upper layer 4 of the second undoped material are sequentially stacked to form a layered structure. The entire surface is covered with a protective film 7 such as SiO 2 .

【0012】そして、上層4の一部領域4Aは他の領域
4Bに比べて薄くなっていて、その薄い領域4Aにソー
ス電極Sとドレイン電極Dのそれぞれが形成され、上記
した厚い他の領域4Bにはゲート電極Gが形成されてい
る。下層3の第1のアンドープ材料および上層4の第2
のアンドープ材料はいずれもGaN系半導体材料であ
る。その場合、第2のアンドープ材料と第1のアンドー
プ材料としては、前者のバンドギャップエネルギー(E
g)の方が後者のそれよりも大きい材料を選択し、両者
を組み合わせて用いられる。その結果、下層3と上層4
のヘテロ接合界面の直下、すなわち下層3の最上部には
2次元電子ガス層6が形成される。
The partial region 4A of the upper layer 4 is thinner than the other region 4B, and the source electrode S and the drain electrode D are formed in the thin region 4A, and the thicker region 4B is formed. A gate electrode G is formed on the. The first undoped material of the lower layer 3 and the second of the upper layer 4
All of the undoped materials are GaN-based semiconductor materials. In that case, as the second undoped material and the first undoped material, the former bandgap energy (E
The material of g) is selected larger than that of the latter, and both are used in combination. As a result, lower layer 3 and upper layer 4
The two-dimensional electron gas layer 6 is formed immediately below the heterojunction interface of, that is, at the uppermost part of the lower layer 3.

【0013】下層3の第1のアンドープ材料としては、
通常、GaN(Eg=3.40eV)が用いられる。その
とき、上層4の第2のアンドープ材料としては、例えば
AlGaN(Eg=4.16eV)、AlInGaN(E
g=3.8eV)、AlGaNAs(Eg=4.5eV)、A
lGaNP(Eg=4.2eV)、AlGaInNAsP
(Eg=4.0eV)、AlGaNAsPなどを用いるこ
とができる。
As the first undoped material of the lower layer 3,
Usually, GaN (Eg = 3.40 eV) is used. At that time, as the second undoped material of the upper layer 4, for example, AlGaN (Eg = 4.16 eV), AlInGaN (E
g = 3.8 eV), AlGaNAs (Eg = 4.5 eV), A
lGaNP (Eg = 4.2 eV), AlGaInNAsP
(Eg = 4.0 eV), AlGaNAsP, etc. can be used.

【0014】なお、第1のアンドープ材料はGaNに限
定されるものではなく、GaN系の各種混晶であっても
よいが、その場合、第2のアンドープ材料にはその混晶
よりもEgが大きいGaN系半導体材料を用いることが
必要である。ここで、下層3の厚みは格別限定されない
が、通常、1000〜4000nm程度に設定される。
The first undoped material is not limited to GaN and may be various GaN-based mixed crystals. In that case, the second undoped material has more Eg than the mixed crystal. It is necessary to use large GaN-based semiconductor materials. Here, the thickness of the lower layer 3 is not particularly limited, but is usually set to about 1000 to 4000 nm.

【0015】また、上層4における電極の形成領域4A
の厚みは、当該上層の構成材料とそれに組み合わされて
いる下層3の構成材料との関係や、2次元電子ガス層6
における電子ガス濃度の高低や、結晶欠陥などとの関係
で適宜決められる。形成領域4Aの厚みをあまり薄くす
ると、膜欠陥が生じて連続した2次元電子ガス層6の形
成が進まず、逆に厚くしすぎると、アンドープ層の抵抗
が高くなるなどの不都合が生ずるので、形成領域4Aの
厚みは1〜15nm程度に設定することが好ましい。
Further, the electrode forming region 4A in the upper layer 4 is formed.
The thickness of the two-dimensional electron gas layer 6 depends on the relationship between the constituent material of the upper layer and the constituent material of the lower layer 3 combined with the upper layer.
It is appropriately determined in relation to the level of electron gas concentration in (3) and crystal defects. If the thickness of the formation region 4A is too thin, a film defect occurs and the continuous two-dimensional electron gas layer 6 does not proceed. On the contrary, if the thickness is too thick, the undoped layer may have a high resistance. The thickness of the formation region 4A is preferably set to about 1 to 15 nm.

【0016】形成領域4Aの厚みが上記した範囲にある
と、その直下における2次元電子ガス層6の状態は良好
であり、またその電子ガス濃度も高く、電極と下層3と
の間で充分にコンタクト層としての機能を発揮する。こ
の装置Aは次のようにして製造することができる。ま
ず、半絶縁性基板1の上に、ガスソース分子線エピタキ
シャル成長法(GSMBE)や有機金属気相成長法(M
OCVD)などの結晶成長法で、例えばGaNから成る
バッファ層2、例えばアンドープGaNから成る下層
3,例えばアンドープAlGaNから成る上層4を順次
成膜して、図2で示した層構造A0を製造する。
When the thickness of the formation region 4A is within the above range, the condition of the two-dimensional electron gas layer 6 immediately below the formation region 4A is good, and the electron gas concentration thereof is also high, so that it is sufficient between the electrode and the lower layer 3. Functions as a contact layer. This device A can be manufactured as follows. First, on the semi-insulating substrate 1, a gas source molecular beam epitaxial growth method (GSMBE) or a metal organic chemical vapor deposition method (M
A layer structure A 0 shown in FIG. 2 is manufactured by sequentially forming a buffer layer 2 made of, for example, GaN, a lower layer 3 made of, for example, undoped GaN 3, and an upper layer 4 made of, for example, undoped AlGaN by a crystal growth method such as OCVD. To do.

【0017】ここで、基板1としては、通常、サファイ
ア基板が用いられるが、SiC,GaAs,Si,Ga
Nなどの基板であってもよい。ついで、層構造A0の表
面全体に例えばSiO2を堆積したのち、そこにレジス
トでパターニングし、更に、反応性イオンビームエッチ
ング法(RIBE)で、ゲート電極を形成すべき領域以
外の領域に所望する深さだけドライエッチングを行う。
Here, a sapphire substrate is usually used as the substrate 1, but SiC, GaAs, Si, Ga are used.
It may be a substrate such as N. Then, for example, SiO 2 is deposited on the entire surface of the layer structure A 0 , patterned with a resist there, and further subjected to a reactive ion beam etching method (RIBE) in a region other than the region where the gate electrode is to be formed. Dry etching is performed to the depth to be used.

【0018】その結果、図3で示したように、所望する
厚みの領域4Aとエッチングされない領域4Bが形成さ
れている上層4を有する層構造A1が製造される。つい
で、層構造A1のレジストとSiO2膜を除去したのち、
再び全面に例えばSiO2を成膜し、そのSiO2膜に対
してレジストでパターニングし、ソース電極とドレイン
電極を形成すべき箇所を開口し、そこに例えばスパッタ
法で電極材料を被着せしめる。
As a result, as shown in FIG. 3, the layer structure A 1 having the upper layer 4 in which the region 4A having a desired thickness and the region 4B which is not etched are formed is manufactured. Then, after removing the resist of the layer structure A 1 and the SiO 2 film,
Again, for example, a SiO 2 film is formed on the entire surface, the SiO 2 film is patterned with a resist, openings are formed at the locations where the source electrode and the drain electrode are to be formed, and an electrode material is deposited there by, for example, a sputtering method.

【0019】その結果、図4で示したように、上層4の
領域4Aにソース電極Sとドレイン電極Dが形成されて
いる層構造A2が製造される。なお、電極材料として
は、例えばTa−Si,Al/Ti,Ti/Auなどを
用いることができる。これらはいずれも上層4との間で
オーミック接触する。また、ソース電極とドレイン電極
の形成後、層構造A2を例えばN2ガス雰囲気炉で加熱処
理することが好ましい。これら電極の上層とのオーミッ
ク接触が一層良好になるからである。そのときの熱処理
温度は400〜800℃、処理時間は5〜30分間に設
定することが好ましい。
As a result, as shown in FIG. 4, the layer structure A 2 in which the source electrode S and the drain electrode D are formed in the region 4A of the upper layer 4 is manufactured. Note that Ta-Si, Al / Ti, Ti / Au, or the like can be used as the electrode material. All of them make ohmic contact with the upper layer 4. Further, it is preferable to heat-treat the layered structure A 2 in, for example, an N 2 gas atmosphere furnace after forming the source electrode and the drain electrode. This is because the ohmic contact with the upper layer of these electrodes becomes better. At that time, the heat treatment temperature is preferably set to 400 to 800 ° C. and the treatment time is preferably set to 5 to 30 minutes.

【0020】そして最後に、再び全面に例えばSiO2
を成膜したのち、前記と同様にして上層の領域4Bの上
にゲート電極を形成することにより、図1で示した装置
Aが製造される。なお、上記した一連の工程において、
層構造A1の領域4Aの表面に更にInGaNやGaN
などの薄層を成膜しておくと、図4で示した層構造A2
におけるソース電極Sおよびドレイン電極Dと領域4A
との間のオーミック接触は一層良好となる。
Finally, again, for example, SiO 2 is formed on the entire surface.
After forming a film, the device A shown in FIG. 1 is manufactured by forming a gate electrode on the upper region 4B in the same manner as described above. In the above series of steps,
InGaN or GaN is further formed on the surface of the region 4A of the layer structure A 1.
When a thin layer such as is formed, the layer structure A 2 shown in FIG.
Source electrode S and drain electrode D and region 4A in
The ohmic contact between and becomes even better.

【0021】[0021]

【実施例】図1で示した装置Aを次のようにして製造し
た。サファイア基板1の上に、ラジカル化窒素(3×1
-6Torr)、金属Ga(5×10-7Torr)、金属Si
(5×10-9Torr)を用い、GSMBE法により成長温
度640℃で厚み50nmのn−GaNから成るバッファ
層2を成膜し、更にその上に、金属Ga(1×10-6To
rr)とアンモニア(5×10-5Torr)を用い、成長温度
850℃で厚み1000nmのアンドープGaN層3を成
膜した。そして、更にその上に、金属Al(1×10-7
Torr)、金属Ga(1×10-7Torr)、アンモニア(5
×10-6Torr)を用い、成長温度850℃で厚み30nm
のアンドープAlGaN層4を成膜して図2の層構造A
0を形成した。
EXAMPLE The device A shown in FIG. 1 was manufactured as follows. On the sapphire substrate 1, radicalized nitrogen (3 × 1
0 -6 Torr), Ga metal (5 × 10 -7 Torr), Si metal
(5 × 10 −9 Torr) is used to form a buffer layer 2 of n-GaN having a thickness of 50 nm at a growth temperature of 640 ° C. by the GSMBE method, and further, a metal Ga (1 × 10 −6 Tor) is formed thereon.
rr) and ammonia (5 × 10 −5 Torr) were used to form an undoped GaN layer 3 having a thickness of 1000 nm at a growth temperature of 850 ° C. And on top of that, metal Al (1 × 10 −7
Torr), metallic Ga (1 × 10 −7 Torr), ammonia (5
X10 -6 Torr) at a growth temperature of 850 ° C and a thickness of 30 nm
Of the undoped AlGaN layer 4 of FIG.
Formed 0 .

【0022】この層構造A0の全面を、P−CVD法で
厚み100nmのSiO2膜で被覆したのち、レジストで
パターニングして、ゲート電極を形成すべき領域4B以
外に対してはバッファドフッ酸を用いた湿式エッチング
を行ってSiO2膜を除去した。そして表出したアンド
ープAlGaN層4に対してRIBEでドライエッチン
グを行って図3で示した層構造A1にした。
The entire surface of the layer structure A 0 is covered with a SiO 2 film having a thickness of 100 nm by the P-CVD method and then patterned with a resist, and buffered hydrofluoric acid is applied to regions other than the region 4B where the gate electrode is to be formed. The wet etching used was performed to remove the SiO 2 film. Then, the exposed undoped AlGaN layer 4 was dry-etched by RIBE to obtain the layer structure A 1 shown in FIG.

【0023】このとき、エッチングの深さを表1で示し
たように変化させて、領域4Aの厚みが異なる層構造A
1を製造した。ついで、領域4B上のレジストとSiO2
膜を除去したのち、再び全面にSiO2膜を成膜し、レ
ジストでパターニングしてソース電極とドレイン電極を
形成すべき箇所を開口し、そこにTa−Siをスパッタ
したのちリフトオフを行い、ソース電極Sとドレイン電
極Dを形成した(図4)。その後、全体を温度1050
℃のN2ガス雰囲気炉内で60分間の熱処理を行った。
At this time, by changing the etching depth as shown in Table 1, the layer structure A in which the thickness of the region 4A is different.
Manufactured 1 . Then, the resist on the region 4B and SiO 2
After removing the film, a SiO 2 film is formed again on the entire surface, and patterning is performed with a resist to open a portion where a source electrode and a drain electrode are to be formed, Ta-Si is sputtered there, and lift-off is performed to remove the source. The electrode S and the drain electrode D were formed (FIG. 4). After that, the whole temperature is 1050
The heat treatment was performed for 60 minutes in a N 2 gas atmosphere furnace at ℃.

【0024】最後に、領域4B上のSiO2膜を開口
し、ここにPt/Auを蒸着してゲート電極Gを形成
し、図1で示した装置Aにした。得られた装置につき、
電気的特性、すなわちFETのオン抵抗とソース・ドレ
イン間の電流を測定した。その結果を表1に示した。な
お、比較のために、図2の層構造の上に、Siドープn
−AlGaN(Siドーピング濃度1×1019/cm3
から成る厚み50nmのコンタクト層を形成したのちそこ
にソース電極Sとドレイン電極Dを形成したことを除い
ては実施例と同様の層構造を有するHEMTを製造し
た。その特性を従来例として表1に示した。
Finally, the SiO 2 film on the region 4B was opened, and Pt / Au was vapor-deposited thereon to form the gate electrode G, thereby completing the device A shown in FIG. About the obtained device,
The electrical characteristics, that is, the on-resistance of the FET and the current between the source and the drain were measured. The results are shown in Table 1. For comparison, on top of the layer structure of FIG.
-AlGaN (Si doping concentration 1 × 10 19 / cm 3 )
A HEMT having the same layer structure as that of the example was manufactured except that a source electrode S and a drain electrode D were formed on the contact layer having a thickness of 50 nm. The characteristics are shown in Table 1 as a conventional example.

【0025】[0025]

【表1】 [Table 1]

【0026】表1から次のことが明らかである。 (1)実施例装置は、オン抵抗がコンタクト層を積層し
た従来例に比べて低下しており、またソース・ドレイン
間の電流も大幅に大きくなっている。 (2)実施例装置において、領域4Aの厚みが15nmよ
り厚くなると、領域4Aの半導体層の抵抗は高くなり、
また1nmより薄くなると、歪みが小さくなって2次元電
子ガス層の効果が弱くなり、結果的に半導体層の抵抗が
高くなっている。このようなことから領域4Aの厚みは
1〜15nmに設定することが好ましい。
The following is clear from Table 1. (1) The on-resistance of the device of the embodiment is lower than that of the conventional example in which the contact layers are laminated, and the current between the source and the drain is significantly large. (2) In the device of the embodiment, when the thickness of the region 4A becomes thicker than 15 nm, the resistance of the semiconductor layer in the region 4A becomes high,
On the other hand, when the thickness is less than 1 nm, the strain becomes small and the effect of the two-dimensional electron gas layer becomes weak, and as a result, the resistance of the semiconductor layer becomes high. Therefore, the thickness of the region 4A is preferably set to 1 to 15 nm.

【0027】[0027]

【発明の効果】以上の説明で明らかなように、本発明の
GaN系半導体装置は、上層におけるソース電極とドレ
イン電極の形成領域の厚みを薄くすることにより動作時
のオン抵抗は小さくなり、大電流動作が可能になってい
る。また、この装置は、従来のように選択成長でコンタ
クト層を形成することが不要になるので、高い生産性の
下で製造することができる。
As is apparent from the above description, in the GaN-based semiconductor device of the present invention, the on-resistance during operation is reduced by reducing the thickness of the region where the source electrode and the drain electrode are formed in the upper layer. Current operation is possible. Further, this device does not need to form a contact layer by selective growth as in the conventional case, and can be manufactured with high productivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の装置の1例Aを示す断面図である。FIG. 1 is a cross-sectional view showing one example A of the device of the present invention.

【図2】装置Aの製造に用いる層構造A0を示す断面図
である。
2 is a cross-sectional view showing a layer structure A 0 used for manufacturing the device A. FIG.

【図3】層構造A0の上層に領域4Aと領域4Bが形成
されている層構造A1を示す断面図である。
FIG. 3 is a cross-sectional view showing a layer structure A 1 in which regions 4A and 4B are formed in an upper layer of the layer structure A 0 .

【図4】ソース電極とドレイン電極が形成された層構造
2を示す断面図である。
FIG. 4 is a cross-sectional view showing a layer structure A 2 in which a source electrode and a drain electrode are formed.

【図5】従来のGaN系HEMT構造例を示す断面図で
ある。
FIG. 5 is a cross-sectional view showing an example of a conventional GaN-based HEMT structure.

【符号の説明】[Explanation of symbols]

1 半絶縁性基板 2 バッファ層 3 第1のアンドープ材料から成る下層 4 第2のアンドープ材料から成る下層 4A 上層4におけるソース電極とドレイン電極の
形成領域 4B 上層4における領域4A以外の領域 5 コンタクト層 6 2次元電子ガス層 7 保護膜
1 Semi-Insulating Substrate 2 Buffer Layer 3 Lower Layer 4 Made of First Undoped Material Lower Layer 4A Made of Second Undoped Material Region 4B for Source and Drain Electrodes Formed in Upper Layer 4 Region 5 in Upper Layer 4 Other than Region 4A Contact Layer 6 Two-dimensional electron gas layer 7 Protective film

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F045 AA04 AA05 AB14 AB17 AB18 AB19 AB32 AC12 AD10 AD12 AF02 AF03 AF04 AF09 BB16 CA07 CB10 DA53 DA63 HA16 5F102 FA02 FA03 GB01 GC01 GJ02 GJ03 GJ04 GJ05 GJ10 GK04 GK08 GL04 GM04 GS01 GT01 GT03 GV07 HC01 HC19 HC21   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F045 AA04 AA05 AB14 AB17 AB18                       AB19 AB32 AC12 AD10 AD12                       AF02 AF03 AF04 AF09 BB16                       CA07 CB10 DA53 DA63 HA16                 5F102 FA02 FA03 GB01 GC01 GJ02                       GJ03 GJ04 GJ05 GJ10 GK04                       GK08 GL04 GM04 GS01 GT01                       GT03 GV07 HC01 HC19 HC21

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 全体がGaN系半導体材料で構成され、
第1のアンドープ材料から成る下層と前記第1のアンド
ープ材料よりもバンドギャップエネルギーが大きい第2
のアンドープ材料から成る上層との層構造が基板の上に
形成され、 前記上層の表面には、ゲート電極、ソース電極、および
ドレイン電極が形成されているGaN系半導体装置であ
って、 前記ソース電極と前記ドレイン電極の形成領域における
前記上層の厚みが、他の領域における厚みよりも薄くな
っていることを特徴とするGaN系半導体装置。
1. The whole is composed of a GaN-based semiconductor material,
A lower layer made of a first undoped material and a second layer having a bandgap energy larger than that of the first undoped material.
A GaN-based semiconductor device in which a layered structure with an upper layer made of an undoped material is formed on a substrate, and a gate electrode, a source electrode, and a drain electrode are formed on the surface of the upper layer. And a thickness of the upper layer in a region where the drain electrode is formed is smaller than a thickness in other regions.
【請求項2】 前記第1のアンドープ材料がGaNであ
り、前記第2のアンドープ材料がAlGaNである請求
項1のGaN系半導体装置。
2. The GaN-based semiconductor device according to claim 1, wherein the first undoped material is GaN and the second undoped material is AlGaN.
【請求項3】 前記ソース電極と前記ドレイン電極の形
成領域における上層の厚みは1〜15nmである請求項2
のGaN系半導体装置。
3. The upper layer in the formation region of the source electrode and the drain electrode has a thickness of 1 to 15 nm.
GaN-based semiconductor device.
JP2001246113A 2001-08-14 2001-08-14 GaN-based semiconductor device Expired - Lifetime JP4906023B2 (en)

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