JP2003092472A - Manufacturing method of laminated foil for forming multi-layer wiring board and multi-layer wiring board using the same - Google Patents
Manufacturing method of laminated foil for forming multi-layer wiring board and multi-layer wiring board using the sameInfo
- Publication number
- JP2003092472A JP2003092472A JP2001284903A JP2001284903A JP2003092472A JP 2003092472 A JP2003092472 A JP 2003092472A JP 2001284903 A JP2001284903 A JP 2001284903A JP 2001284903 A JP2001284903 A JP 2001284903A JP 2003092472 A JP2003092472 A JP 2003092472A
- Authority
- JP
- Japan
- Prior art keywords
- foil
- wiring board
- alloy
- forming
- surface layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011888 foil Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000010410 layer Substances 0.000 claims abstract description 51
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 42
- 239000002344 surface layer Substances 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 37
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 29
- 239000000956 alloy Substances 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 238000002844 melting Methods 0.000 claims abstract description 14
- 230000008018 melting Effects 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000010485 coping Effects 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 20
- 238000007747 plating Methods 0.000 description 20
- 230000004888 barrier function Effects 0.000 description 12
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 238000005553 drilling Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910017813 Cu—Cr Inorganic materials 0.000 description 1
- 229910017827 Cu—Fe Inorganic materials 0.000 description 1
- 229910017876 Cu—Ni—Si Inorganic materials 0.000 description 1
- 229910017985 Cu—Zr Inorganic materials 0.000 description 1
- 229910017061 Fe Co Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は多層配線板形成用積
層箔及びそれを用いた多層配線板の製造方法に関するも
のである。TECHNICAL FIELD The present invention relates to a laminated foil for forming a multilayer wiring board and a method for manufacturing a multilayer wiring board using the same.
【0002】[0002]
【従来の技術】近年携帯電話、ノート型パソコン等とい
った携帯情報機器の急速な普及に伴い、機器の軽量・小
型化ならびに高性能化は急激な進展を遂げており、これ
を構成する電子部品に対しても高密度化が要求されてい
る。これに対応してプリント配線板及び半導体パッケー
ジ配線板では、配線の微細パターン化、狭ピッチ化が推
進される一方で、多層配線板が主流となっている。2. Description of the Related Art In recent years, with the rapid spread of portable information devices such as mobile phones and notebook computers, the weight, size and performance of the devices have been rapidly increasing. On the other hand, high density is required. In response to this, in printed wiring boards and semiconductor package wiring boards, fine wiring patterns and narrower pitches are being promoted, while multilayer wiring boards are becoming the mainstream.
【0003】従来の多層配線板の層間接続に関しては、
例えば図6に模式的に示すように、(a)両面Cu張樹脂(2
1)を用いて、(b)Cu(23)と樹脂(22)を貫通する穴をあけ
た後、(c)穴の内部にCuめっき(24)を施し、層間の導通
を得て、(d)所望の配線パターンを形成する方法が使用
されている。この技術ではドリルまたはレーザを用いて
所謂スルーホール(25)を形成し、スルーホールめっきを
行う。また、例えば図7に模式的に示すように、(e)パ
ターニングしたコア基板(26)の両側に樹脂付き銅箔(27)
を配置し、(f)ビルドアップして、(g)内層の配線層で穴
が止まるようにレーザを用いて穴あけ後、(h)穴表面をC
uめっきし、(i)配線パターンを形成する、所謂IVH(28)
(Interstitial Via Hole)を形成するものが主流で
ある。Regarding inter-layer connection of a conventional multilayer wiring board,
For example, as shown schematically in FIG. 6, (a) double-sided Cu-clad resin (2
Using (1), (b) after forming a hole that penetrates the Cu (23) and the resin (22), (c) performs Cu plating (24) inside the hole to obtain conduction between layers, d) A method of forming a desired wiring pattern is used. In this technique, a so-called through hole (25) is formed using a drill or a laser, and through hole plating is performed. Further, for example, as schematically shown in FIG. 7, (e) resin-coated copper foil (27) is provided on both sides of the patterned core substrate (26).
Position, (f) build up, (g) use a laser to make holes stop in the inner wiring layer, and (h) hole surface C
u plating (i) forming a wiring pattern, so-called IVH (28)
(Interstitial Via Hole) is the mainstream.
【0004】[0004]
【発明が解決しようとする課題】スルーホールを有する
配線板において、高密度化に対応するにはレーザ穴あけ
が必要となるし、IVHを有する配線板においては、レー
ザ穴あけが必須である。しかしながら、レーザ穴あけは
位置精度が±数十μm程度と悪く、パッドを大きくとる
必要があり、配線設計の自由度が小さくなることや、穴
数の増加に伴いレーザ穴あけのコストが増大することな
ど、高密度化を阻害する要因も多い。また、レーザ穴あ
けし、めっきした後に配線やランド(引き回し配線も含
む)をエッチングで形成するため、配線厚さが増加し、
配線の微細化が困難であるといった問題も有する。本発
明の目的は、低融点の金属または合金からなる表面層を
有する積層箔を用いて、選択エッチング技術および拡散
接合技術を利用し配線板を形成することで、高密度化に
対応できる配線板をより安価に提供することができる多
層配線板形成用積層箔及びそれを用いた多層配線板の製
造方法を提供することである。In the wiring board having the through holes, laser drilling is necessary to cope with high density, and in the wiring board having the IVH, laser drilling is indispensable. However, laser drilling has poor positioning accuracy of ± several tens of μm and requires a large pad, which reduces the flexibility of wiring design and increases the cost of laser drilling as the number of holes increases. However, there are many factors that hinder high density. In addition, since the wiring and lands (including the leading wiring) are formed by etching after laser drilling and plating, the wiring thickness increases,
There is also a problem that it is difficult to miniaturize the wiring. An object of the present invention is to form a wiring board using a selective etching technology and a diffusion bonding technology using a laminated foil having a surface layer made of a metal or an alloy having a low melting point, and thus a wiring board that can cope with high density. It is an object of the present invention to provide a laminated foil for forming a multilayer wiring board which can be provided at a lower cost, and a method for manufacturing a multilayer wiring board using the same.
【0005】[0005]
【課題を解決するための手段】本発明者等は、低融点の
金属または合金からなる表面層を有する積層箔を用い
て、選択エッチング技術および拡散接合技術を利用し配
線板を形成することで、レーザ工程及びめっき工程が不
要となり、配線板の配線高密度化ならびにコスト削減が
実現できることを知見し、本発明に到達した。Means for Solving the Problems The present inventors have formed a wiring board using a selective etching technique and a diffusion bonding technique using a laminated foil having a surface layer made of a metal or alloy having a low melting point. The present invention has been accomplished by finding that the laser process and the plating process are unnecessary, and the wiring density of the wiring board can be increased and the cost can be reduced.
【0006】即ち本発明は、Cu箔またはCu合金箔とはエ
ッチング特性の異なる金属または合金でなる中間層を、
前記Cu箔またはCu合金箔で挟持するように配置した積層
箔の両方または何れか一方の表面に、融点が350℃以下
である金属または合金でなる表面層が形成されている多
層配線板形成用積層箔である。好ましくは、表面層がSn
またはSn合金でなる多層配線板形成用積層箔である。さ
らに好ましくは、中間層がSnまたはSn合金でなる多層配
線板形成用積層箔である。また、中間層がTiまたはTi合
金でなる多層配線板形成用積層箔であっても良い。That is, the present invention provides an intermediate layer made of a metal or alloy having a different etching characteristic from the Cu foil or Cu alloy foil,
For forming a multilayer wiring board in which a surface layer made of a metal or an alloy having a melting point of 350 ° C. or lower is formed on the surface of both or either of the laminated foils arranged so as to be sandwiched by the Cu foil or the Cu alloy foil. It is a laminated foil. Preferably, the surface layer is Sn
Alternatively, it is a laminated foil for forming a multilayer wiring board made of an Sn alloy. More preferably, it is a laminated foil for forming a multilayer wiring board in which the intermediate layer is Sn or a Sn alloy. Further, it may be a laminated foil for forming a multilayer wiring board in which the intermediate layer is made of Ti or a Ti alloy.
【0007】さらに、本発明の多層配線板の製造方法
は、上記に記載の何れかの多層配線板形成用積層箔を用
いて、中間層でエッチングが停止するように一方の表面
層および該表面層に連続するCu箔またはCu合金箔をエッ
チングして、表面層を有するバンプを形成し、該表面層
を有するバンプが絶縁体を貫通するような状態で、別の
Cu箔またはCu合金箔に前記表面層を有するバンプを突き
当て加熱圧接し、層間接続を得る多層配線板の製造方法
である。Furthermore, the method for producing a multilayer wiring board of the present invention uses one of the above-mentioned laminated foils for forming a multilayer wiring board, wherein one surface layer and the surface layer are formed so that etching stops at the intermediate layer. A Cu foil or Cu alloy foil continuous with the layer is etched to form a bump having a surface layer, and another bump is formed in such a state that the bump having the surface layer penetrates the insulator.
This is a method for manufacturing a multilayer wiring board in which bumps having the above-mentioned surface layer are butted against a Cu foil or Cu alloy foil and heated and pressed to obtain interlayer connection.
【0008】[0008]
【発明の実施の形態】以下に詳しく本発明について説明
する。本発明の重要な特徴は図1に示すように、Cu箔ま
たはCu合金箔とはエッチング特性の異なる金属または合
金からなる中間層(1)と、それを挟持するように配置さ
れたCu箔またはCu合金箔(2)からなる積層箔(3)の表面に
低融点の金属または合金からなる表面層(4)を形成させ
たことにある。本発明の積層箔を用いることの最大の利
点は、工程の熱履歴を利用し、表面層(4)とCu箔またはC
u合金箔(2)との拡散現象により強固な層間接続をとるこ
とが可能になり、接合信頼性の高いビア・オン・ビア構
造を安価で実現でき、高密度配線設計の自由度を大きく
とれる点にある。また、バンプ形成工程の前に表面層が
形成されているため、例えば、バンプ形成後に表面層を
形成する場合に比べて、ペースト塗布または、めっき工
程が必要なく、工程が短く、有効である。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below. As shown in FIG. 1, an important feature of the present invention is that an intermediate layer (1) made of a metal or an alloy having a different etching property from a Cu foil or a Cu alloy foil, and a Cu foil or a Cu foil arranged so as to sandwich the intermediate layer (1). This is because the surface layer (4) made of a metal or alloy having a low melting point was formed on the surface of the laminated foil (3) made of the Cu alloy foil (2). The greatest advantage of using the laminated foil of the present invention is that it takes advantage of the thermal history of the process, and the surface layer (4) and Cu foil or C
The diffusion phenomenon with the u-alloy foil (2) makes it possible to establish a strong interlayer connection, and a highly reliable via-on-via structure can be realized at low cost, allowing a high degree of freedom in high-density wiring design. In point. Further, since the surface layer is formed before the bump forming step, compared with the case where the surface layer is formed after the bump forming, for example, paste application or plating step is not required, and the step is short and effective.
【0009】以下に、本発明の多層配線板形成用積層箔
を用いた配線板の製造方法を示して具体的に説明する。
例えば、図2に示すように、先ず、
(a) Cu箔またはCu合金箔(2)とはエッチング特性の異な
る金属または合金でなる中間層(1)をCu箔またはCu合金
箔(2)で挟持した構造を有する積層箔の片側のCu箔また
はCu合金箔(2A)の表面に、融点が350℃以下の金属また
は合金でなる表面層を形成した多層配線板形成用積層箔
を準備する。表面層は図2に示すように片側でも良い
し、両側に形成されていても良い。以下の説明は図2に
従って行う。
(b) その両面に感光性レジスト(5)を付着させる。感光
性レジストはドライフィルムタイプをラミネートしても
良いし、液状タイプをディッピングやスピンコートなど
の方法で塗布しても良い。付着させた感光性レジストに
所望のパターンを描画したフィルムまたはガラス板をの
せ、露光し、現像して、エッチングマスクとする。The method for manufacturing a wiring board using the laminated foil for forming a multilayer wiring board of the present invention will be described below in detail.
For example, as shown in FIG. 2, first, (a) an intermediate layer (1) made of a metal or alloy having a different etching property from the Cu foil or Cu alloy foil (2) is formed by Cu foil or Cu alloy foil (2). A laminated foil for forming a multilayer wiring board is prepared in which a surface layer made of a metal or an alloy having a melting point of 350 ° C. or lower is formed on the surface of a Cu foil or Cu alloy foil (2A) on one side of the laminated foil having a sandwiched structure. The surface layer may be formed on one side as shown in FIG. 2 or may be formed on both sides. The following description will be given with reference to FIG. (b) A photosensitive resist (5) is attached to both sides of the photosensitive resist. As the photosensitive resist, a dry film type may be laminated, or a liquid type may be applied by a method such as dipping or spin coating. A film or glass plate on which a desired pattern is drawn is placed on the attached photosensitive resist, exposed and developed to form an etching mask.
【0010】次に、
(c) 表面層(4)およびその内側に連続するCu箔またはCu
合金箔(2A)について選択エッチングによりバンプ(6)を
形成する。この場合の選択エッチングは、まず表面層を
選択的にエッチングでき、Cu箔またはCu合金箔がエッチ
ングバリアとして機能するエッチング液を用いて、表面
層にパターニングし、次にCu箔またはCu合金箔を選択的
にエッチングでき、中間層がエッチングバリアとして機
能するエッチング液を用いてその内側に連続するCu箔ま
たはCu合金にパターニングするか、表面層およびCu箔ま
たはCu合金箔を選択的にエッチングでき、中間層がエッ
チングバリアとして機能するエッチング液を用いて同一
工程でエッチングすると良い。更に、
(d) 中間層(1)の露出部を選択エッチングする。この工
程は後述する配線パターニング(図3(h))の後に行っ
ても良い。この選択エッチング液は中間層をエッチング
でき、Cu箔またはCu合金箔がエッチングバリアとして機
能するエッチング液であれば良い。Next, (c) the surface layer (4) and a Cu foil or Cu continuous inside the surface layer (4).
Bumps (6) are formed on the alloy foil (2A) by selective etching. Selective etching in this case, first, the surface layer can be selectively etched, the Cu foil or Cu alloy foil using an etching solution that functions as an etching barrier, patterning the surface layer, then Cu foil or Cu alloy foil It can be selectively etched, and the inner layer can be patterned into a continuous Cu foil or Cu alloy with an etching solution that functions as an etching barrier, or the surface layer and Cu foil or Cu alloy foil can be selectively etched, Etching may be performed in the same step using an etching solution whose intermediate layer functions as an etching barrier. Further, (d) the exposed portion of the intermediate layer (1) is selectively etched. This step may be performed after the wiring patterning described later (FIG. 3H). The selective etching solution may be an etching solution capable of etching the intermediate layer and allowing the Cu foil or Cu alloy foil to function as an etching barrier.
【0011】次に、
(e) (b)で形成した感光性レジストを除去してバンプ付
きCu箔またはCu合金箔(7)を得る。そして、図3に示す
ように、
(f) 図2で得られたバンプ付きCu箔またはCu合金箔(7)
と、絶縁体(8)、Cu箔またはCu合金箔(2C)を準備する。
ここで、絶縁体はバンプ付きCu箔またはCu合金箔に付着
させてあっても良い。材料としては樹脂やセラミックス
が良い。好ましくは樹脂であって、熱可塑性であっても
熱硬化性であっても良い。そして、次に
(g) バンプ(6)で絶縁体(8)を突き刺すようにホットプ
レスし、表面層(2)を介してバンプとCu箔またはCu合金
箔(2C)との接合をとる。
(h) 外側にあるCu箔またはCu合金箔(2B、2C)について
エッチングにより、配線およびランド、パッドを形成し
て、二層配線板(11)を得る。Next, the photosensitive resist formed in (e) and (b) is removed to obtain a bumped Cu foil or Cu alloy foil (7). Then, as shown in FIG. 3, (f) the bumped Cu foil or Cu alloy foil obtained in FIG. 2 (7)
Then, an insulator (8) and Cu foil or Cu alloy foil (2C) are prepared.
Here, the insulator may be attached to the Cu foil with bumps or the Cu alloy foil. Resin and ceramics are good materials. It is preferably a resin and may be thermoplastic or thermosetting. Then, (g) hot pressing is performed so as to pierce the insulator (8) with the bump (6), and the bump and the Cu foil or the Cu alloy foil (2C) are joined via the surface layer (2). (h) The Cu foil or Cu alloy foil (2B, 2C) on the outside is etched to form wirings, lands, and pads to obtain a two-layer wiring board (11).
【0012】さらに、図4のように、積層させ、四層配
線板(12)を得ることもできるし、さらに積層させて、層
数を増やすことができる。また、図5に示すように二層
配線板(11)のパッド部にニッケルめっき(15)、金めっき
(16)を行い、他の配線部を半田レジスト(13)で被覆し、
チップ(17)をダイボンド(18)で配線板に固定し、チップ
と配線板を金ワイヤ(19)で接続して、封止樹脂(20)チッ
プと金ワイヤを封止し、もう一方側の面に半田ボール(1
4)を搭載して、パッケージとしても良い。配線板は二層
以上の多層構造であっても良い。チップと配線板の接続
はフリップチップ接続であっても良い。Further, as shown in FIG. 4, it is possible to obtain a four-layer wiring board (12) by laminating it, or further laminating it to increase the number of layers. Also, as shown in FIG. 5, nickel plating (15) and gold plating are applied to the pad portion of the double-layer wiring board (11).
(16), cover other wiring parts with solder resist (13),
The chip (17) is fixed to the wiring board with the die bond (18), the chip and the wiring board are connected with the gold wire (19), the sealing resin (20) is sealed with the chip and the gold wire, and the other side Solder ball (1
4) can be installed and packaged. The wiring board may have a multilayer structure of two or more layers. The connection between the chip and the wiring board may be flip chip connection.
【0013】以上のように、本発明の多層配線板用積層
箔ならびに、多層配線板の製造方法を用いると、高価な
レーザ穴あけ工程やCuめっき工程を削除でき、汎用性の
高いエッチング工程とホットプレス工程で高密度配線に
対応できる配線板を安価で得ることができる。しかも、
層間接続にはCuまたはCu合金箔と低融点金属との拡散現
象を利用しているため、信頼性の高い接合が得られる。As described above, by using the laminated foil for a multilayer wiring board and the method for manufacturing a multilayer wiring board according to the present invention, an expensive laser drilling step and Cu plating step can be eliminated, and a highly versatile etching step and hot etching step can be performed. A wiring board that can handle high-density wiring can be obtained at low cost in the pressing process. Moreover,
Since the diffusion phenomenon between Cu or Cu alloy foil and low melting point metal is used for interlayer connection, highly reliable bonding can be obtained.
【0014】ここで、本発明の多層配線板形成用積層箔
の構成について具体的に述べる。Cu箔またはCu合金箔は
配線形成に用いる場合、選択エッチングによりパターン
を形成するので、厚さは薄いほうがより微細な配線を狭
ピッチで形成できるため好ましい。また、バンプを形成
する場合も、狭ピッチを実現するためには、薄いほうが
良い。しかし、エッチングの制御をする上で薄すぎると
均一なパターンが得られないし、工程中の搬送や例えば
ホットプレスの工程にて、しわ等が発生する可能性があ
る。そのため、バンプ及び配線を形成するCu箔またはCu
合金箔の厚さはそれぞれ25μm〜150μmの範囲、3μm〜
50μmの範囲にあるものが良い。更にはそれぞれ35μm
〜115μmの範囲、9μm〜35μmの範囲の厚さのものが好
ましい。Here, the structure of the laminated foil for forming a multilayer wiring board of the present invention will be specifically described. When a Cu foil or a Cu alloy foil is used for wiring formation, a pattern is formed by selective etching. Therefore, a thinner thickness is preferable because finer wiring can be formed at a narrow pitch. Also, in the case of forming bumps, it is preferable to be thin in order to realize a narrow pitch. However, if the thickness is too thin to control etching, a uniform pattern cannot be obtained, and wrinkles or the like may occur during transportation during the process or during hot pressing, for example. Therefore, Cu foil or Cu that forms bumps and wiring
The thickness of alloy foil is in the range of 25μm-150μm, 3μm-
It should be in the range of 50 μm. Furthermore, each 35 μm
The thickness is preferably in the range of ˜115 μm and in the range of 9 μm to 35 μm.
【0015】一方、中間層の厚さはエッチングバリアと
して機能する程度の厚さが必要で、且つ選択エッチング
で迅速に除去できるようにできるかぎり薄いほうが良
い。バリア層の厚さは材質により異なるが、0.05μm〜5
μmの範囲にあることが好ましく、より好ましくは0.1μ
m〜1μmの範囲である。また、表面層の厚さは、エッチ
ングでパターニングするために、薄いほうが良いが、銅
箔または銅合金箔の表面粗さを吸収でき、拡散接合に十
分に寄与できる程度の厚さが必要である。したがって、
0.1μm〜5μmの範囲が好ましい。さらに好ましくは、
0.5μm〜2μmの範囲である。On the other hand, the thickness of the intermediate layer must be such that it functions as an etching barrier, and it is preferable that it be as thin as possible so that it can be quickly removed by selective etching. The thickness of the barrier layer varies depending on the material, but is 0.05 μm-5
It is preferably in the range of μm, more preferably 0.1 μm
It is in the range of m to 1 μm. In addition, the thickness of the surface layer is preferably thin because it is patterned by etching, but it is necessary that the surface layer can absorb the surface roughness of the copper foil or the copper alloy foil and sufficiently contribute to diffusion bonding. . Therefore,
The range of 0.1 μm to 5 μm is preferable. More preferably,
It is in the range of 0.5 μm to 2 μm.
【0016】次にCu箔またはCu合金箔は圧延製若しくは
電解製のどちらであっても良い。組成としては、純Cuの
他、リードフレームなどに用いられるCu-Fe系合金、Cu-
Fe-Co系合金、Cu-Ni-Si系合金、Cu-Cr-Ti系合金、Cu-Cr
-Zr系合金、Cu-Zr系合金などから選ぶと良い。ここで合
金とはその金属を主成分とするものを指す。中間層を挟
む両側のCuまたはCu合金箔は、異種材料であっても構わ
ない。電気抵抗や入手のし易さを考慮すると、Cuが望ま
しい。また、強度が必要な場合はCu合金が好ましい。Next, the Cu foil or Cu alloy foil may be either rolled or electrolytic. As for the composition, in addition to pure Cu, Cu-Fe alloys used for lead frames, Cu-
Fe-Co alloy, Cu-Ni-Si alloy, Cu-Cr-Ti alloy, Cu-Cr
-Select from Zr-based alloys, Cu-Zr-based alloys, etc. Here, the alloy means an alloy containing the metal as a main component. The Cu or Cu alloy foils on both sides of the intermediate layer may be different materials. Cu is preferable in consideration of electric resistance and availability. Further, when strength is required, Cu alloy is preferable.
【0017】導体層の選択エッチング液に関しては、銅
のエッチング液として一般に用いられている塩化第二鉄
溶液、塩化第二銅溶液、アルカリエッチャント、過酸化
水素水−硫酸系エッチャントなどが好ましい。特に塩化
第二鉄溶液は安価であり、一般に用いられており、好適
である。バリア層としては、Cu箔またはCu合金箔に対し
て選択エッチングが可能で、層間の導通を得る必要があ
るため、金属が好適であり、上述の導体層の選択エッチ
ング液に対してバリアとして機能するNi、Sn、Ti、Agの
金属または合金が好ましい。アルカリエッチャントに対
してはNi、Sn、Ti、Agはバリアとして機能する。塩化第
二鉄溶液及び塩化第二銅溶液に対してはTi、Agがバリア
として機能する。過酸化水素水−硫酸系エッチャントに
対してはAlがバリアとして機能する。Snは後述する工程
で、容易に形成可能であるため、有効である。また、Ti
は代表的なエッチャントに対してエッチングバリア性を
有するため、好ましい。As the selective etching solution for the conductor layer, a ferric chloride solution, a cupric chloride solution, an alkaline etchant, a hydrogen peroxide solution-sulfuric acid type etchant and the like which are generally used as an etching solution for copper are preferable. In particular, the ferric chloride solution is inexpensive, is generally used, and is suitable. As the barrier layer, a metal is suitable because it can be selectively etched with respect to Cu foil or Cu alloy foil, and it is necessary to obtain conduction between the layers, and it functions as a barrier against the selective etching liquid for the conductor layer described above. Preferred are Ni, Sn, Ti, Ag metals or alloys. Ni, Sn, Ti, and Ag function as a barrier against the alkaline etchant. Ti and Ag function as barriers to the ferric chloride solution and the cupric chloride solution. Al functions as a barrier against the hydrogen peroxide-sulfuric acid type etchant. Sn is effective because it can be easily formed in the process described below. Also, Ti
Is preferable because it has an etching barrier property with respect to a typical etchant.
【0018】表面層は融点が350℃以下の金属または合
金である必要がある。ここで、融点が350℃を超える金
属または合金では、Cu箔またはCu合金箔に対して配線板
を積層ホットプレスする程度の低温(300℃以下)では
拡散が十分に促進せず、十分な接合が得られない。融点
が350℃以下の金属では、Sn、Bi、Cd、In、Pbなどの金
属またはこれらを主成分とする合金が好ましい。なかで
もSnはCuとの拡散速度が低温でも速く、安定で強固な金
属間化合物を形成するため、好適である。具体的には、
表面層/Cu箔またはCu合金箔/中間層/Cu箔またはCu合金
箔の組み合わせとしては、Sn/Cu/Ti/Cu、Sn/Cu/Sn/Cuが
好ましい。The surface layer needs to be a metal or alloy having a melting point of 350 ° C. or lower. Here, for metals or alloys with a melting point above 350 ° C, diffusion is not sufficiently promoted at low temperatures (300 ° C or less) such that the wiring boards are laminated and hot pressed onto Cu foil or Cu alloy foil, and sufficient bonding is achieved. Can't get As the metal having a melting point of 350 ° C. or lower, metals such as Sn, Bi, Cd, In and Pb or alloys containing these as the main components are preferable. Among them, Sn is preferable because it has a high diffusion rate with Cu even at a low temperature and forms a stable and strong intermetallic compound. In particular,
The combination of surface layer / Cu foil or Cu alloy foil / intermediate layer / Cu foil or Cu alloy foil is preferably Sn / Cu / Ti / Cu or Sn / Cu / Sn / Cu.
【0019】本発明の積層箔の製造方法としては、めっ
きにより逐次積層する方法や、めっき法または乾式成膜
法と表面活性化接合法を組み合わせたものなどが好まし
い。なお、乾式成膜法は、物理蒸着法や化学蒸着法な
ど、気相やプラズマを利用した乾式の成膜方法全般のこ
とであり、この中には真空蒸着法は勿論、イオンプレー
ティングのように真空で加熱し蒸発させたものをイオン
化、加速して成膜する方法や、スパッタのように気体イ
オンをぶつけて所望の原子をたたき出し成膜する方法
や、特殊なるつぼを用い、ある特定の材料を分子線状に
引き出して蒸発させる分子線蒸着法も含まれるし(以
上、物理蒸着法)、化学蒸着法のようにある種の気体を
加熱反応させる成膜法も含まれる。As a method for producing the laminated foil of the present invention, a method of sequentially laminating by plating, a method of combining a plating method or a dry film forming method and a surface activated bonding method, and the like are preferable. The dry film forming method refers to all dry film forming methods using vapor phase or plasma, such as physical vapor deposition method and chemical vapor deposition method. A method of forming a film by ionizing and accelerating a material that has been heated in a vacuum and evaporating, a method of striking a desired atom by bombarding a gas ion like sputtering, or a special crucible is used. It also includes a molecular beam vapor deposition method in which a material is drawn out in a molecular beam shape and evaporated (above, physical vapor deposition method), and a film forming method in which a certain gas is heated and reacted like a chemical vapor deposition method.
【0020】中でも、近年の成膜技術の高速化が著し
い、真空蒸着法、スパッタリング法、イオンプレーティ
ング法などの物理蒸着法が好適である。真空蒸着法は蒸
着速度が速く、生産性が良い。スパッタリング法は、導
体層となる金属が高融点金属の場合も対応可能であり、
導体層となる金属の選択範囲が広く、何れの方法を用い
て形成される乾式成膜層でも均一で均質な成膜が可能で
ある。Among them, physical vapor deposition methods such as vacuum vapor deposition method, sputtering method and ion plating method, which have been remarkably accelerated in recent film forming technology, are suitable. The vacuum deposition method has high deposition rate and good productivity. The sputtering method can be applied even when the metal to be the conductor layer is a high melting point metal,
The metal used as the conductor layer has a wide selection range, and a dry film-forming layer formed by any method enables uniform and uniform film formation.
【0021】具体的には、例えばCu箔またはCu合金箔の
両面に表面層並びに中間層となる金属または合金をめっ
き法または乾式成膜法で形成し、その中間層の表面と別
に準備したCu箔またはCu合金箔の表面とを不活性雰囲気
内でイオンボンバードし、活性化された表面同士を突き
合わせるように接合させると良い。ここで、めっき法の
場合、特に表面層と中間層が同一材料であるときに有効
であり、表面層と中間層を同時に形成でき、効率的であ
る。そのため、Snを表面層とする場合、中間層もSnにす
ることが、有効である。一方、乾式成膜法はめっき法で
は得られない材料も表面層および中間層とすることがで
きるが、片面ずつしか成膜できない。Specifically, for example, a metal or an alloy to be a surface layer and an intermediate layer is formed on both surfaces of a Cu foil or a Cu alloy foil by a plating method or a dry film forming method, and Cu prepared separately from the surface of the intermediate layer. It is advisable to perform ion bombardment with the surface of the foil or Cu alloy foil in an inert atmosphere, and join so that the activated surfaces face each other. Here, the plating method is particularly effective when the surface layer and the intermediate layer are made of the same material, and is efficient because the surface layer and the intermediate layer can be simultaneously formed. Therefore, when Sn is used as the surface layer, it is effective to use Sn for the intermediate layer as well. On the other hand, in the dry film forming method, a material which cannot be obtained by the plating method can be used as the surface layer and the intermediate layer, but the film can be formed only on each side.
【0022】また、その他の方法として、2枚のCu箔ま
たはCu合金箔を準備し、各々の片側表面に真空漕内で中
間層となる材料を乾式成膜法により成膜し、成膜表面同
士を突き合わせて接合させて、三層積層箔を作製し、そ
の両側または片側の表面にめっき法または乾式成膜法に
より表面層を成膜すると良い。ここで、めっき法で成膜
する場合、両側の表面にも成膜したほうが、効率的であ
る場合があり、五層積層箔となることがあるが、五層積
層箔の場合でも本質的に本発明の効果が認められる。な
お、本発明の積層箔は上述の製造方法で作製したものに
限られるものではない。As another method, two Cu foils or Cu alloy foils are prepared, and a material to be an intermediate layer is formed on one surface of each by a dry film forming method in a vacuum tank. It is advisable to butt and bond each other to produce a three-layer laminated foil, and form a surface layer on the surfaces of both sides or one side thereof by a plating method or a dry film forming method. Here, when the film is formed by the plating method, it may be more efficient to form the film on both surfaces, and it may be a five-layer laminated foil, but even in the case of a five-layer laminated foil, it is essentially The effect of the present invention is recognized. The laminated foil of the present invention is not limited to the one produced by the above manufacturing method.
【0023】本発明の多層配線板形成用積層箔を用いる
ことで、レーザ穴あけ、Cuめっきを省略し、高密度化に
対応できる配線板をより安価に提供することができる。By using the laminated foil for forming a multilayer wiring board of the present invention, it is possible to provide a wiring board which can cope with high density without costing laser drilling and Cu plating at a lower cost.
【0024】[0024]
【発明の効果】本発明によれば、低融点の金属または合
金からなる表面層を有する積層箔を用いて、選択エッチ
ング技術および拡散接合技術を利用し配線板を形成する
ことで、高密度化に対応できる多層配線板をより安価に
提供することが可能となる。According to the present invention, by using a laminated foil having a surface layer made of a metal or an alloy having a low melting point, a wiring board is formed by utilizing a selective etching technique and a diffusion bonding technique, thereby increasing the density. It is possible to provide a multilayer wiring board that can meet the above requirements at a lower cost.
【図1】本発明の多層配線板形成用積層箔の一例を示す
断面模式図である。FIG. 1 is a schematic sectional view showing an example of a laminated foil for forming a multilayer wiring board of the present invention.
【図2】本発明の多層配線板形成用積層箔を用いたバン
プ付きCu箔またはCu合金箔の製造方法の一例を示す概略
図である。FIG. 2 is a schematic view showing an example of a method for manufacturing a Cu foil with bumps or a Cu alloy foil using the laminated foil for forming a multilayer wiring board of the present invention.
【図3】本発明の多層配線板の製造方法の一例を示す概
略図である。FIG. 3 is a schematic view showing an example of a method for manufacturing a multilayer wiring board according to the present invention.
【図4】本発明の多層配線板の製造方法の一例を示す概
略図である。FIG. 4 is a schematic view showing an example of a method for manufacturing a multilayer wiring board according to the present invention.
【図5】本発明の多層配線板形成用積層箔により作製し
た配線板を用いたパッケージの一例を示す断面模式図で
ある。FIG. 5 is a schematic cross-sectional view showing an example of a package using a wiring board manufactured from the laminated foil for forming a multilayer wiring board of the present invention.
【図6】従来の層間接続方法の一例を示す概略図であ
る。FIG. 6 is a schematic view showing an example of a conventional interlayer connection method.
【図7】従来の層間接続方法の一例を示す概略図であ
る。FIG. 7 is a schematic diagram showing an example of a conventional interlayer connection method.
1.中間層、2、2A、2B、2C.Cu箔またはCu合金
箔、3.積層箔、4.表面層、5.感光性レジスト、
6.バンプ、7.バンプ付きCu箔またはCu合金箔、8.
絶縁体、9.ランド、10.配線、11.二層配線板、
12.四層配線板、13.半田レジスト、14.半田ボ
ール、15.ニッケルめっき、16.金めっき、17.
チップ、18.ダイボンド、19.金ワイヤ、20.封
止樹脂、21.両面Cu張樹脂、22.樹脂、23.Cu、
24.Cuめっき、25.スルーホール、26.コア基
板、27.樹脂付きCu箔、28.IVH1. Intermediate layer, 2, 2A, 2B, 2C. Cu foil or Cu alloy foil, 3. Laminated foil, 4. Surface layer, 5. Photosensitive resist,
6. Bump, 7. Cu foil or Cu alloy foil with bumps, 8.
Insulator, 9. Land, 10. Wiring, 11. Two-layer wiring board,
12. Four-layer wiring board, 13. Solder resist, 14. Solder balls, 15. Nickel plating, 16. Gold plating, 17.
Chip, 18. Die bond, 19. Gold wire, 20. Sealing resin, 21. Double-sided Cu-clad resin, 22. Resin, 23. Cu,
24. Cu plating, 25. Through hole, 26. Core substrate, 27. Cu foil with resin, 28. IVH
Claims (5)
の異なる金属または合金でなる中間層を、前記Cu箔また
はCu合金箔で挟持するように配置した積層箔の両方また
は何れか一方の表面に、融点が350℃以下である金属ま
たは合金でなる表面層が形成されていることを特徴とす
る多層配線板形成用積層箔。1. A surface of both or one or both of a laminated foil in which an intermediate layer made of a metal or an alloy having a different etching characteristic from a Cu foil or a Cu alloy foil is arranged so as to be sandwiched between the Cu foil or the Cu alloy foil. A laminated foil for forming a multilayer wiring board, characterized in that a surface layer made of a metal or an alloy having a melting point of 350 ° C. or lower is formed on.
徴とする請求項1に記載の多層配線板形成用積層箔。2. The laminated foil for forming a multilayer wiring board according to claim 1, wherein the surface layer is made of Sn or Sn alloy.
徴とする請求項1または2に記載の多層配線板形成用積
層箔。3. The laminated foil for forming a multilayer wiring board according to claim 1, wherein the intermediate layer is made of Sn or Sn alloy.
徴とする請求項1または2に記載の多層配線板形成用積
層箔。4. The laminated foil for forming a multilayer wiring board according to claim 1, wherein the intermediate layer is made of Ti or a Ti alloy.
線板形成用積層箔を用いて、中間層でエッチングが停止
するように一方の表面層および該表面層に連続するCu箔
またはCu合金箔をエッチングして、表面層を有するバン
プを形成し、該表面層を有するバンプが絶縁体を貫通す
るような状態で、別のCu箔またはCu合金箔に前記表面層
を有するバンプを突き当て加熱圧接し、層間接続を得る
ことを特徴とする多層配線板の製造方法。5. The multilayer foil for forming a multilayer wiring board according to any one of claims 1 to 4, wherein one surface layer and a Cu foil continuous with the one surface layer so that etching is stopped at the intermediate layer, or The Cu alloy foil is etched to form bumps having a surface layer, and the bumps having the surface layer are formed on another Cu foil or Cu alloy foil while the bumps having the surface layer penetrate the insulator. A method for manufacturing a multilayer wiring board, which comprises butting, heating and pressing to obtain interlayer connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001284903A JP2003092472A (en) | 2001-09-19 | 2001-09-19 | Manufacturing method of laminated foil for forming multi-layer wiring board and multi-layer wiring board using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001284903A JP2003092472A (en) | 2001-09-19 | 2001-09-19 | Manufacturing method of laminated foil for forming multi-layer wiring board and multi-layer wiring board using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003092472A true JP2003092472A (en) | 2003-03-28 |
Family
ID=19108145
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001284903A Pending JP2003092472A (en) | 2001-09-19 | 2001-09-19 | Manufacturing method of laminated foil for forming multi-layer wiring board and multi-layer wiring board using the same |
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| JP2005136207A (en) * | 2003-10-30 | 2005-05-26 | North:Kk | Wiring circuit board, method for manufacturing same and method for manufacturing multilayer wiring board |
| JP2009158593A (en) * | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | Bump structure and method of manufacturing the same |
| US8558379B2 (en) | 2007-09-28 | 2013-10-15 | Tessera, Inc. | Flip chip interconnection with double post |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9496236B2 (en) | 2010-12-10 | 2016-11-15 | Tessera, Inc. | Interconnect structure |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10535626B2 (en) | 2015-07-10 | 2020-01-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US11973056B2 (en) | 2016-10-27 | 2024-04-30 | Adeia Semiconductor Technologies Llc | Methods for low temperature bonding using nanoparticles |
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2001
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| JP2005136207A (en) * | 2003-10-30 | 2005-05-26 | North:Kk | Wiring circuit board, method for manufacturing same and method for manufacturing multilayer wiring board |
| US8558379B2 (en) | 2007-09-28 | 2013-10-15 | Tessera, Inc. | Flip chip interconnection with double post |
| US8884448B2 (en) | 2007-09-28 | 2014-11-11 | Tessera, Inc. | Flip chip interconnection with double post |
| JP2009158593A (en) * | 2007-12-25 | 2009-07-16 | Tessera Interconnect Materials Inc | Bump structure and method of manufacturing the same |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9397063B2 (en) | 2010-07-27 | 2016-07-19 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9496236B2 (en) | 2010-12-10 | 2016-11-15 | Tessera, Inc. | Interconnect structure |
| US9818713B2 (en) | 2015-07-10 | 2017-11-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10535626B2 (en) | 2015-07-10 | 2020-01-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10892246B2 (en) | 2015-07-10 | 2021-01-12 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US11710718B2 (en) | 2015-07-10 | 2023-07-25 | Adeia Semiconductor Technologies Llc | Structures and methods for low temperature bonding using nanoparticles |
| US11973056B2 (en) | 2016-10-27 | 2024-04-30 | Adeia Semiconductor Technologies Llc | Methods for low temperature bonding using nanoparticles |
| US12027487B2 (en) | 2016-10-27 | 2024-07-02 | Adeia Semiconductor Technologies Llc | Structures for low temperature bonding using nanoparticles |
| US12211809B2 (en) | 2020-12-30 | 2025-01-28 | Adeia Semiconductor Bonding Technologies Inc. | Structure with conductive feature and method of forming same |
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