JP2003140964A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To heighten the efficiency of access to storage devices of the respective data processors in a system including a plurality of data processors sharing a plurality of storage devices. SOLUTION: Microprocessors X, Y read out an instruction from memories A, B through a control unit U. In a storage part formed of memories A, B, two consecutive addresses make one group, and the address group is periodically allocated to the memories A, B in an ascending order. When the microprocessors X, Y respectively jump to a leading address of a program PRGX and a leading address of a program PRGY at the same time, the microprocessor Y with a low priority is kept waiting for two processing cycles, and from that time on, an instruction can be read out from the different memory simultaneously with the microprocessor X.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system in which a plurality of data processing devices share a plurality of individually accessible storage devices.

[0002]

In a data processing system such as a microcomputer system, a plurality of microprocessors and a plurality of memories are provided in one system in order to speed up the processing and efficiently use hardware and software. The one with is proposed.

FIG. 7 shows a conventional configuration of a microcomputer system having two microprocessors and two memories (ROM). Between the two microprocessors X and Y and the two memories A and B, for connecting and controlling the data buses DX and DY of the microprocessors X and Y and the data buses DA and DB of the memories A and B. A control unit U is provided. The data buses DX, DY, DA, and DB all have the same bus width (16 bits), and the memory A has, for example, FD000.
Consecutive addresses from 0H to FDFFFFH are assigned, and the memory B has, for example, FE0000H.
To FEFFFFH are assigned consecutive addresses.

In the address area of the memory A, there are, for example, a program PRGX composed of instructions 0 to 4 and executed only by the microprocessor X, and a program PRGY composed of instructions 20 to 24 and executed only by the microprocessor Y. It has been written. Further, in the address area of the memory B, a subroutine program PRGZ composed of instructions 10 to 14 and executed by the microprocessors X and Y is written.

As can be seen, in a microprocessor system in which a plurality of microprocessors X and Y share a plurality of memories A and B, the microprocessors X and Y are
Can share a subroutine program, an interrupt processing routine program, table data, and the like, and moreover, the programs and data can be allocated to the entire storage capacities of the memories A and B without waste, so that the storage capacity can be reduced.

However, microprocessors X and Y
Cannot access the same memory A or B at the same time, therefore, when simultaneous reading is performed on the same memory, access by a microprocessor having a low priority is prohibited. FIG. 8 shows instruction read timings of the microprocessors X and Y.
When the microprocessors X and Y simultaneously jump to the start address of the program PRGX and the start address of the program PRGY written in the memory A, respectively, until the microprocessor X reads the instruction 0 to the instruction 4 written in the memory A. During this period, the microprocessor Y having a low priority is prohibited from accessing the memory A and enters a waiting state.

In this example, the waiting time of the microprocessor Y is 5 before the microprocessor X shifts to the subroutine program PRGZ written in the memory B.
It is an order. However, since the actual program has an extremely large number of instructions and it is very difficult to arrange the programs and data in such a way that they cannot be read simultaneously to the same memory, the efficiency of access decreases due to an increase in wait states. Was unavoidable.

The present invention has been made in view of the above circumstances, and an object thereof is to share a plurality of storage devices that can be individually accessed by a plurality of data processing devices, and to access the storage devices of each data processing device. It is to provide a highly efficient data processing system.

[0009]

According to the means described in claim 1, m (m ≧ 2) data processing devices and n (n ≧ n) data processing devices.
.Gtoreq.m) storage devices, and a group of consecutive p (p.gtoreq.1) addresses is formed, and the n address groups (each address when p = 1) have a predetermined order. Periodically assigned to the storage device in ascending or descending order. For example, when the data processing device accesses the storage device while incrementing the read address by 1 such as when reading a program, the storage device accessed by each data processing device periodically shifts in a predetermined order every p times of reading. I will do it. Therefore, for example, when two data processing devices request access to the same storage device at the same time, the low-priority data processing device can access the storage device by waiting for at most p instruction read periods. .

Further, in the present data processing system, since there are more storage devices than the number of data processing devices, a jump instruction or subroutine call is executed when all the data processing devices are executing the program read operation. As long as no interrupt processing occurs and internal processing (pipeline processing, etc.) of the data processing device does not stagnate, all data processing devices do not wait for access and are continuously stored in different storage devices. It becomes accessible. As described above, according to the present means, it is possible to improve the access efficiency of each data processing device to the storage device, as compared with the conventional configuration in which consecutive addresses are assigned to each storage device.

According to the means described in claim 2, since the address groups is composed of addresses of 2 ^q number of continuous (q ≧ 0), the access control device of a predetermined bit of the address output by the data processing device It is possible to allocate (decode) access to each storage device based on the value. This simplifies the configuration of the access control device.

According to the means described in claim 3, since the number of addresses forming the address group is 1 (p = 1), two data processing devices simultaneously request access to the same storage device. The waiting that occurs in some cases is only one reading period at the maximum, and the most efficient access is possible in the present invention.

According to the means described in claim 4, since the number m of data processing devices is equal to the number n of storage devices, the number of storage devices can be reduced as much as possible while maintaining the above-described effect of the present invention. .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment in which the present invention is applied to a microcomputer system will be described below with reference to FIGS.
FIG. 1 shows a schematic electrical configuration of a microcomputer system.
(Corresponding to a data processing system) is two memories A and B (corresponding to a storage device, n = 2) in which various programs and data are stored, and two microprocessors X and Y that share these memories A and B. (Equivalent to a data processing device, m
= 2) and a control unit U (corresponding to an access control device) that intervenes between the microprocessors X and Y and the memories A and B to control the connection therebetween.

Among them, the memories A and B are 16-bit data buses DA according to address signals and control signals (read signals, chip select signals, etc.) supplied from the control unit U via the control buses CA and CB, respectively. , And a ROM that can output data independently to the DB.

The storage unit consisting of these memories A and B is F
It has an address area from D0000H to FEFFFFH. Addresses are cyclically assigned such that two consecutive addresses form a group (p = 2, q = 1) and the address groups are arranged in the memories A and B in ascending order. That is, FD0000H and FD00 are stored in the memory A.
01H, FD0004H, FD0005H, ... Are allocated, and the memory B is FD0002H, FD0003.
H, FD0006H, FD0007H, ... Are assigned. Each address area is in units of words (16 bits).

The microprocessors X and Y have the same instruction system and operate in synchronization with the same clock. Like the memories A and B, these microprocessors X and Y are RISC type processors that have 16-bit data buses DX and DY and execute one instruction every clock. The inside has an internal data bus with a width of 32 bits, and is configured to be able to handle data in units of bytes (8 bits), words (16 bits), and longs (32 bits). . Here, when reading data in long units, upper data and lower data are continuously read in two times, and when reading data in bytes, data reading is performed in word units. After that, only the lower byte is valid.

The microprocessors X and Y supply address and control signals to the control unit via the control buses CX and CY, respectively, and when the stop signals HX and HY supplied from the control unit U are active. The operation is temporarily stopped (wait operation).

As shown in FIG. 2, the control unit U includes a data path unit 10 for connecting the data buses DX, DY and the data buses DA, DB, and a control bus CX,
A control path unit 20 for connecting the CY and the control buses CA and CB, various path control signals for driving the data path unit 10 and the control path unit 20 and a stop signal HX to the microprocessors X and Y, It is composed of a control unit 30 that generates HY.

Of these, the data path unit 10 includes an X-side read path circuit 11 and a Y-side read path circuit 12.
The X-side read path circuit 11 receives the data buses DA and DB according to the path control signal Sx (S11 to S14) from the control unit 30.
The data read from the memories A and B supplied via the data bus is supplied to the microprocessor X via the data bus DX. Similarly, the Y-side read path circuit 12 receives the path control signal Sy (S21 to S21) from the control unit 30.
According to 24), the data read from the memories A and B supplied via the data buses DA and DB are supplied to the microprocessor Y via the data bus DY.

The X-side read pass circuit 11 and the Y-side read pass circuit 12 have the same structure.
Is a selection signal S for selecting one of the pair of data buses DA and DB.
According to the selection signal Si3, a selection circuit M1 that selects according to i1, a work register M2 that stores the output of the selection circuit M1 at the timing of the latch signal Si2, and a pair of data buses DA and DB and the output of the work register M2 are selected. It is composed of a selection circuit M3 for selection and a tri-state gate circuit M4 which opens and closes between the output of the selection circuit M3 and the data bus DX according to a gate signal Si4. Here, the selection signals Si1, Si2, Si of the X-side read path circuit 11 are
3 and Si4 are S11, S12, S13 and S14 (= Sx) respectively
And the selection signals Si1, Si2 of the Y-side read path circuit 12,
Si3 and Si4 are S21, S22, S23 and S24 (= S
y).

The control path unit 20 comprises an A side control path circuit 21 and a B side control path circuit 22. The A-side control pass circuit 21 receives the pass control signal S from the control unit 30.
In accordance with ca, a control path for supplying the address and control signal supplied from the microprocessors X and Y via the control buses CX and CY to the memory A via the control bus CA is formed. Similarly,
The B-side control path circuit 22 stores the address and control signal supplied from the microprocessors X and Y via the control buses CX and CY in accordance with the path control signal Scb from the control unit 30 via the control bus CB. A control path for supplying to B is formed.

The A-side control path circuit 21 and the B-side control path circuit 22 have the same structure. For example, the A-side control path circuit 21 selects either the control buses CX or CY according to the path control signal Sca. A circuit M6 and a buffer circuit M connected between the output of the selection circuit M6 and the control bus CA.
It is composed of 5 and.

As shown in FIG. 3, the control unit 30 includes an X-side type identification unit 32, a Y-side type identification unit 33, an X-side arbitration / conversion unit 34, a Y-side arbitration / conversion unit 35, and a priority register 3.
6, data path control unit 37, control path control unit 3
8 and a stop control unit 39.

The X-side type identifying unit 32 identifies the access type requested by the microprocessor X based on the address signal, the control signal, and the LONG signal output from the microprocessor X, and the Y-side type identifying unit 33 also. It is the same. Here, the LONG signal is a signal output to indicate the state when the microprocessors X and Y are inputting / outputting data in long units.

The X-side arbitration / conversion unit 34 compares the access type identified by the X-side type identification unit 32 (hereinafter referred to as "identification access type") with the identification access type from the Y-side type identification unit 33. By doing so, the presence or absence of access conflict is checked, a stop request to the microprocessor X is output if necessary, and the identification access type on the microprocessor X side is converted into an execution access type used for actual control. ing. The same applies to the Y-side arbitration / conversion unit 35.

The priority register 36 is a register indicating which microprocessor has priority when access conflict occurs. This priority register 36
Allows the priority to be fixed to the microprocessor X side, fixed to the microprocessor Y side, or alternately switched whenever conflict occurs by an external switching signal (for example, setting by a dip switch). It is configured.

The data path control unit 37 includes an arbitration / conversion unit 3.
According to the enforcement access type generated in 4, 35,
A path control signal Sx for controlling the data path unit 10,
Sy is generated. The control path control unit 38 also controls the path control signal Sc for controlling the control path unit 20 according to the access type.
a and Scb are generated. Further, the stop control unit 39, in accordance with the stop request from the arbitration / conversion units 34 and 35, performs one processing cycle (one clock in this embodiment).
During this period, stop signals HX and HY for stopping the processing of the corresponding microprocessor are generated.

Next, regarding the operation when the microprocessors X and Y read and execute the program by accessing in word units, the microprocessors X and Y will be described.
The instruction read timing will be described with reference to FIG.

In the address area after FD0000H of the memories A and B, a program PR composed of instructions 0, 1, ..., A, B, ...
GX is stored, and in the address area after FE0000H, a program PRG including instructions 20, 21, ..., 2A, 2B ,.
Y is stored. Further, in other address areas, various subroutine programs, interrupt processing routine programs, table data and the like (not shown) are stored.

When the microprocessors X and Y simultaneously jump to the start address (FD0000H) of the program PRGX and the start address (FE0000H) of the program PRGY, the execution access types generated by the arbitration / conversion units 34 and 35 are both ". It becomes "A side word read", and access conflict occurs. At this time, the priority register 36 preferentially accesses the microprocessor X side according to the register value set in advance by a switching signal from the outside. That is, the data path control unit 37 outputs the path control signal Sx for reading “command 0” through the X-side read path circuit 11, and the stop control unit 3
The reference numeral 9 outputs a stop signal HY for temporarily stopping (waiting) the processing of the microprocessor Y. After the end of this read cycle, the program counter of the microprocessor X is incremented.

Also in the next cycle, since the microprocessors X and Y both access the memory A, contention occurs, and the microprocessor X gives priority to the memory A.
While reading the "instruction 1" from the microprocessor Y
The process of is stopped (waited).

However, in the subsequent cycle, the "instruction 2" of the microprocessor X is read from the memory B, so that the race condition is resolved. That is, the data path control unit 37 reads the “command 2” from the memory B through the X-side read path circuit 11, and the path control signal Sx.
And the path control signal Sy for reading the “command 20” from the memory A through the Y-side read path circuit 12. After that, as long as the instruction is not read from the same memory due to the occurrence of a jump instruction, a subroutine call, an interrupt process, etc., the microprocessors X and Y can read the instruction continuously and simultaneously from different memories.

As described above, according to the microcomputer system 1 of the present embodiment, when the instruction is read, the jump instruction or the subroutine call is executed, the interrupt is generated, and the access between the microprocessors X and Y is performed. When a conflict occurs, the microprocessor Y having a low priority may wait for a maximum of two processing cycles, but thereafter, instructions can be read simultaneously with the microprocessor X. Therefore, the access efficiency to the memories A and B of the microprocessors X and Y is improved, and the processing speed is increased.

Further, the addresses are periodically assigned to the memories A and B so that two consecutive addresses form a group and the addresses are arranged in ascending order. A1 bit (from the lower 2
The access to the memories A and B can be distributed (decoded) based only on the value of the (second bit). As a result, the structure of the decoding circuit in the data bus control unit 37 can be simplified.

Furthermore, two microprocessors X and Y
Share the two memories A and B, it is possible to arrange programs and data up to the total storage capacity of the memories A and B without waste, and to reduce the storage capacity.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6. The microcomputer system 2 shown in FIG.
For the microcomputer system 1 shown in FIG.
The address allocation methods for the memories A and B are different. That is, the memory A has an even address FD00.
00H, FD0002H, FD0004H, ... Are assigned, and the memory B has odd addresses FD0001H, F
D0003H, FD0005H, ... Are assigned (corresponding to the case of p = 1 and q = 0). F of memory A, B
Program PRG in the address area after D0000H
X is stored, and the program PRGY is stored in the address area after FE0000H. The other parts are the same as those shown in FIGS. 1 to 3.

FIG. 6 shows the instruction read timing of the microprocessors X and Y. When the microprocessors X and Y simultaneously jump to the start address (FD0000H) of the program PRGX and the start address (FE0000H) of the program PRGY, respectively, as shown in FIG.
Similarly, the access conflict occurs, and the processing of the microprocessor Y is temporarily stopped (waited). However, in the next cycle, the instruction read of the microprocessor X is from the memory B, so the race condition is resolved.

That is, according to the microcomputer system 2 of the present embodiment, when an access conflict occurs between the microprocessors X and Y at the time of reading an instruction, the microprocessor Y having a low priority has a maximum of 1. Although only the processing cycle may be kept waiting, the instruction can be read simultaneously with the microprocessor X after that. Therefore, the access efficiency to the memories A and B of the microprocessors X and Y is further improved, and the processing speed is further increased.

(Other Embodiments) The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
The memories A and B are not limited to ROM but may be RAM.
In this case, write data supplied from the microprocessors X and Y via the data buses DX and DY to the data path DA of the control unit U according to the path control signal from the controller 30. A side write path circuit for supplying to the memory A via the control unit 3,
According to the path control signal from 0, the data buses DX, DY
It is sufficient to add a B-side write path circuit for supplying write data supplied from the microprocessors X and Y via the data bus DB to the memory B.

The number of microprocessors may be three or more. Further, the number n of memories may be the number m or more of microprocessors. This prevents jump instructions, subroutine calls, interrupt processing, etc. from occurring and stalls in the microprocessor's internal processing (pipeline processing, etc.) when all microprocessors are executing instruction read operations. As far as possible, all microprocessors can successively access different memories without waiting for access.

The microprocessors X and Y are not limited to RISC type and may be CISC type processors. Further, as long as the instructions are continuously fetched by prefetching the instructions, the instruction system is not limited to the fixed length, and the variable length instruction system can be applied. As described in the above embodiment, the access efficiency can be expected to be improved especially in the case of instruction reading (fetch), but the access efficiency is also improved in the process of sequentially reading data from consecutive addresses. The number of addresses (p) forming the address group may be three or more, but since the access efficiency decreases as the number of addresses (p) increases, it is preferable to determine the processing speed in consideration.

[Brief description of drawings]

FIG. 1 is a schematic electrical configuration diagram of a microcomputer system showing a first embodiment of the present invention.

FIG. 2 is an electrical configuration diagram of a control unit.

FIG. 3 is an electrical configuration diagram of a control unit.

FIG. 4 is a diagram showing instruction read timings of microprocessors X and Y.

FIG. 5 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 6 is a view corresponding to FIG.

FIG. 7 is a diagram corresponding to FIG. 1 showing a conventional technique.

FIG. 8 is a view corresponding to FIG.

[Explanation of symbols]

Reference numerals 1 and 2 are a microcomputer system (data processing system), A and B are memories (storage devices), X and Y are microprocessors (data processing devices), and U is a control unit (access control device).

Claims (4)

[Claims] 1. m (m ≧ 2) data processing devices having the same instruction system and operating on the basis of clocks synchronized with each other, and m data processing devices shared by these m data processing devices, each of which is the same as the data processing device. N (n ≧ m) storage devices having a data bus width and individually accessible, and the addresses interposed between the data processing devices and the storage devices according to the addresses output by the data processing devices. And an access control device for controlling access to each of the storage devices specified by the above, wherein the consecutive p addresses (p ≧ 1) form one group, and the n address groups have a predetermined order. The data processing system is characterized in that the storage devices are periodically allocated to each storage device in ascending or descending order. 2. The address group includes 2 ^q consecutive (q
The data processing system according to claim 1, wherein the addresses of ≧ 0) are configured as a group. 3. The data processing system according to claim 1, wherein the number of addresses forming the address group is 1 (p = 1). 4. The number m of the data processing devices and the number n of the storage devices are equal to each other.
The data processing system according to any one of 1.