JP2003141885A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a highly integrated semiconductor device capable of applying a high voltage. A semiconductor substrate having a memory cell region and a level shift circuit region; a first gate insulating film formed in the memory cell region on the semiconductor substrate;
A first lower gate electrode formed on the gate insulating film, a first inter-gate insulating film formed on the first lower gate electrode, and a second upper gate formed on the first inter-gate insulating film Electrodes and a second electrode formed in the level shift circuit area.
A gate insulating film, formed on the second gate insulating film;
A second lower gate electrode to which the first potentials N5 and N6 are applied, a second inter-gate insulating film formed on the second lower gate electrode and accumulating charge as a capacitor insulating film, and a second inter-gate insulating film A second upper gate electrode formed over the film and supplied with second potentials N3 and WL different from the first potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a non-volatile memory area that uses a high voltage for rewriting data, and more particularly to a semiconductor device having a two-layer structure level shift circuit.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device, for example, EEP for electrically writing / erasing data
ROM (Electrically Erasable Programmable Read-On
ly Memory) is known. In this EEPROM,
Particularly in the case of the NAND type, memory cells are arranged at intersections of row lines and column lines intersecting with each other to form a memory cell array. A MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is usually used for the memory cell.

In the EEPROM, there is a flash memory that can be electrically erased collectively. As a flash memory, a NAND flash memory with high integration is widely used.

In the flash memory, a high voltage is used to rewrite the data, and therefore a level shift circuit is used. Next, the circuit configuration of a part of the conventional level shift circuit and the memory cell area will be described with reference to FIG. The address signal Address is input to a plurality of input terminals of the AND circuit AD1. The output of the AND circuit AD1 becomes the node N7. The node N7 is connected to the source of the depletion type NMOS transistor ND1. The gate of the NMOS transistor ND1 is the node N1. The gate of the NMOS transistor ND1 has a two-layer structure, and both gates have the node N1.
It is connected to the.

The drain of the NMOS transistor ND1 is an enhancement type NMOS transistor NE.
It is connected to the gate of 2. The gate of the NMOS transistor NE2 has a two-layer structure, and both gates are connected to the node N5. The source of the NMOS transistor NE2 is the node N3. A capacitor C1 is connected between the gate and the source of the NMOS transistor NE2.

The source of an enhancement type NMOS transistor NE1 is connected to the node N7. The gate of the NMOS transistor NE1 is the node N2. In addition, this NMOS transistor NE1
Has a two-layer structure, and both gates are node N
Connected to 2.

The drain of the NMOS transistor NE1 is a node N6 and is connected to the drain of the NMOS transistor NE2. Furthermore, this node N6
It is connected to the gate of an enhancement type NMOS transistor NE3. This NMOS transistor NE
The gate of 3 has a two-layer structure, and both gates are connected to the node N6. This NMOS transistor NE
The source of 3 is the node N4. Also, this NM
The capacitor C2 is connected between the gate and the source of the OS transistor NE3. The drain of the NMOS transistor NE3 is connected to the word line WL.

As described above, the level shift circuit 50 has N
MOS transistors ND1, NE1, NE2, NE3,
It is composed of capacitors C1 and C2. Word line WL
Is connected to the upper gate of the memory cell transistor M. The drain of the first selection transistor SG1 is connected to the source of the memory cell transistor M, and the gate of the first selection transistor SG1 is controlled by the first selection signal SGS. The source of the first selection transistor SG1 is connected to the source line CS.

The source of the second selection transistor SG2 is connected to the drain of the memory cell transistor M,
The gate of the second selection transistor SG2 is controlled by the second selection signal SGD. This second selection transistor S
The source of G2 is connected to the bit line BL. Here, the depletion type transistor ND1 is in a normally-on state.

Here, the capacitors C1 and C2 are capacitors used to enhance the efficiency of the bootstrap operation. That is, when C1 and C2 are absent, the nodes N5 and N6 are boosted by capacitive coupling between the channels and gates of the NMOS transistors NE2 and NE3. But,
In the actual layout, the nodes N5 and N6 have parasitic ground capacitances, and the increase in the channel potential is not all the increase in the gate potential. Therefore, capacitors C1 and C2 are provided in order to reduce the influence of the parasitic ground capacitance, and the capacitance coupling between the channel and the gate is increased. This circuit is advantageous in low voltage and low power consumption operation as compared with a level shift circuit of the type that boosts with a clock.

Next, the NMO in the level shift circuit of FIG.
9A, 9B, and 9C are a circuit diagram, a cross-sectional view, and a top view of the S transistor NE2 or NE3 and the capacitor C1 or C2 connected thereto, respectively. In the circuit diagram shown in FIG. 9A, the source of the enhancement type transistor is the node A. The drain is the node C, and the gate is connected to the node B. A capacitor is connected between the node B and the node C.

In the sectional view shown in FIG. 9B, the NMO
The S-transistor has an upper gate 51 and a lower gate 52, both of which are made of polycrystalline silicon. Between the upper gate 51 and the lower gate 52, an inter-gate insulating film 5 is formed.
3 is formed. A gate insulating film 54 is formed below the lower gate 52. Here, the upper layer gate 51 and the lower layer gate 52 are short-circuited, and the lower layer gate 52 functions as an actual gate. Further, a source impurity region 56 and a drain impurity region 57 are formed in the semiconductor substrate 55 near the end of the gate insulating film 54 below the lower gate 52.

Adjacent to the NMOS transistor is formed an electrode of a capacitor having an upper layer gate 59 and a lower layer gate 60 which are both made of polycrystalline silicon. An inter-gate insulating film 61 is formed between the upper gate 59 and the lower gate 60. Lower gate 6
A gate insulating film 62, which is a high breakdown voltage gate oxide film, is formed under 0. Further, the semiconductor substrate 55 near the end of the gate insulating film 61 below the lower gate 60 in the semiconductor substrate 55.
An N-type impurity region 63 formed integrally with the drain impurity region 57 of the adjacent NMOS transistor is formed therein. Further, the semiconductor substrate 5 below the lower gate 60
A buried N-type impurity region or a depletion-type channel implantation region 64 is formed in FIG.

On the semiconductor substrate 55, P is formed near the surface thereof.
A well is formed, and an element isolation region 58 is provided in the well so as to surround the N-type source impurity region 6 and the N-type impurity region 63. In addition, the source impurity region 56 is connected to the first wiring 65, which is connected to the node A. The second wiring 66 is connected to the drain impurity region 57 and is connected to the node C. Also, the upper gate 5
The third wiring 67 is connected to the first and lower layer gates 52,
It is connected to node B. Further, a fourth wiring 68 is connected to the upper layer gate 51 and the lower layer gate 52 of the capacitor, and is connected to the node B. Further, a fifth wiring 69 is connected to the N-type impurity region 63.

In the top view shown in FIG. 9C, a source impurity region 56, a drain impurity region 57, and an N-type impurity region 63 are formed on the left and right semiconductor substrates 55 of the two gate electrodes, respectively. Here, the lower gate 5
The width WL of 2, 60 is formed larger than the width WU of the upper gates 51, 59. The third wiring 67 and the fourth wiring 68 are connected to the large-sized region and the ends of the upper gates 51 and 59. The upper gate 51,
The gate lengths L of 59 and the lower gates 52 and 60 are equal to each other. In the conventional semiconductor device, the lower layer gate 60
The gate insulating film 62 between the N-type impurity region 63 and the N-type impurity region 63 is used as a capacitor.

Lower layer gate electrode 5 of NMOS transistor
2 is formed to extend to the element isolation region 58 in one direction thereof, and a gate contact 70 to which a potential is applied is formed in the extended portion.

Upper layer gate electrode 5 of NMOS transistor
1 is formed extending in one direction to the element isolation region 58, and a gate contact 71 to which a potential is applied is formed in the extended portion. The gate contact 71 of the upper gate electrode 51 is formed in a region different from the gate contact 70 of the lower gate electrode.

A source contact 72 is provided in the source impurity region 56 and is connected to the first wiring 65. Further, a drain contact 73 is provided in the drain impurity region 57 and is connected to the second wiring 11.

The lower gate electrode 60 of the capacitor is the first
In the direction, the gate contact 74 is formed so as to extend to the element isolation region 58 and a potential is applied to the extended portion.
Is formed.

The upper gate electrode 59 of the capacitor is the first
In the direction, the gate contact 75 is formed so as to extend to the element isolation region 58 and a potential is applied to the extended portion.
Is formed. The gate contact 75 of the upper layer gate electrode 59 is the gate contact 74 of the lower layer gate electrode 60.
And are formed in different regions. A contact 76 is provided in the N-type impurity region 63 and is connected to the fifth wiring 69.

Here, the prior art as described above is disclosed in
FIGS. 10 to 12 of Japanese Patent Application Laid-Open No. 000-285690 describe a row decoder technique suitable for increasing the capacity and lowering the voltage by providing a capacitor in a level shift circuit in a nonvolatile memory.

In FIG. 2 of JP-A-61-251064, a boosting capacitor of a bootstrap circuit used as a clock generator of a DRAM is formed on the gate electrode of a load transistor, A technique for achieving high integration of an integrated circuit is described.

[0023]

The conventional semiconductor device as described above has the following problems.

In the above conventional technique, it is necessary to make the pattern of the capacitor provided in the row decoder as large as possible in order to secure the capacitance, which increases the area of the semiconductor device and hinders high integration. Become. That is, as shown in FIG. 9C, the gate capacitance portion between the gate electrode and the source / drain region has an area similar to that of the high breakdown voltage transistor, and the layout area of this capacitance portion increases the peripheral circuit area. Invite.

An object of the present invention is to solve the above problems of the prior art.

In particular, it is an object of the present invention to provide a semiconductor device having a high level of integration in a level shift circuit area having a two-layer gate structure.

[0027]

To achieve the above object, a feature of the present invention is that a semiconductor substrate having a memory cell region and a level shift circuit region is formed, and the memory cell region is formed on the semiconductor substrate. A first gate insulating film, a first lower gate electrode formed on the first gate insulating film, a first inter-gate insulating film formed on the first lower gate electrode, and a first inter-gate insulating film. A second upper gate electrode formed on the insulating film, a second gate insulating film formed on the level shift circuit region on the semiconductor substrate, and a first potential formed on the second gate insulating film. Second given
A lower gate electrode, a second inter-gate insulating film formed on the second lower gate electrode and accumulating charges as a capacitor insulating film, and a first potential formed on the second inter-gate insulating film. And a second upper gate electrode to which a different second potential is applied.

Another feature of the present invention is that a first MOS transistor having a first gate and a first current path, a lower second gate, and a first inter-gate insulating film on the second gate. , And a third gate on the first inter-gate insulating film and a second current path, and the potential at one end of the first current path of the first MOS transistor is supplied to the second gate. A second MOS transistor, a lower fourth gate, a second inter-gate insulating film on the fourth gate, a fifth gate on the second inter-gate insulating film, and a third current path. And a third MOS transistor in which the potential at one end of the second current path of the second MOS transistor is supplied to the fourth gate, and the first MOS transistor.
One end of the first current path of the transistor and the second MO
The second gate and the third gate of the second MOS transistor connected to the other end or one end of the second current path of the S transistor are capacitor electrodes, and the first inter-gate insulating film is A first capacitor, which is a capacitor insulating film, is connected between one end of the second current path of the second MOS transistor and one end or the other end of the third current path of the third MOS and the transistor. , The third M
A second capacitor in which the fourth gate and the fifth gate of the OS and the transistor are capacitor electrodes, and the second inter-gate insulating film is a capacitor insulating film; and the third MO.
A non-volatile memory cell transistor having an upper gate connected to one end of a third current path of the S transistor, the lower gate being a floating gate, and having a third inter-gate insulating film between the upper gate and the lower gate. It is a semiconductor device provided.

Another feature of the present invention is a semiconductor substrate, a first source and a first drain formed in the semiconductor substrate, and a first gate formed on the semiconductor substrate and connected to a first terminal. And a second gate formed on the first gate via an inter-gate insulating film and connected to a second terminal different from the first terminal, the second gate being the first source or the first source. A first transistor connected to the drain to charge the first gate to a first potential to make the first conductive state, and then brings the first gate into a floating state; and a second source and a second transistor formed in the semiconductor substrate. A second drain, a third gate formed on the semiconductor substrate and connected to a third terminal and the drain of the first transistor, and the third gate.
A fourth gate formed on the gate via an inter-gate insulating film and connected to a fourth terminal different from the third terminal, the fourth gate being connected to the second source or the second drain, When a potential higher than the first potential is applied from the first source of the first transistor, the first
Via the transistor, the third gate is charged, the second source is supplied with a boosted potential, and the second drain is set to the boosted potential; and the third source formed in the semiconductor substrate. A third drain, a fifth gate formed on the semiconductor substrate and having a floating potential, and a fifth gate formed on the fifth gate via an inter-gate insulating film and connected to the second drain of the second transistor. And a memory cell transistor that stores electric charges.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) This embodiment is applied to a level shift circuit of a semiconductor device having a non-volatile memory which operates by applying a high voltage of about 10V to 25V. It is a thing.

FIGS. 2A, 2B, and 2C are a circuit diagram, a cross-sectional view, and a top view, respectively, of the high breakdown voltage enhancement type N-channel transistor and the capacitor portion according to the present embodiment. Here, as the gate structure of the high breakdown voltage transistor used in the peripheral circuit of the nonvolatile memory, a two-layer polycrystalline silicon structure similar to the gate structure of the nonvolatile memory is used for simplification of the manufacturing process. .

In the circuit diagram shown in FIG. 2A, the source of the enhancement type transistor is the node A. The drain becomes the node C, and the upper gate also becomes the node C.
It is connected to the. Further, the lower gate is connected to the node B.

In the sectional view shown in FIG. 2B, both the upper layer gate 1 and the lower layer gate 2 are made of polycrystalline silicon. Between the upper layer gate 1 and the lower layer gate 2,
The inter-gate insulating film 3 is formed and functions as a capacitor insulating film. A gate insulating film 4 is formed below the lower gate 2. Further, a source impurity region 6 and a drain impurity region 7 are formed near the end of the gate insulating film 4 below the lower gate 2 in the semiconductor substrate 5. A P well is formed near the surface of the semiconductor substrate 5, and an N type source impurity region 6 and a drain impurity region 7 are formed therein.
An element isolation region 8 is provided so as to surround the. Further, the first impurity wiring 6 is connected to the source impurity region 6 and is connected to the node A. Drain impurity region 7
Is connected to the second wiring 11 and is connected to the node C. The third wiring 12 is connected to the upper gate 1 and is connected to the node C. Furthermore, the lower gate 2
Is connected to the fourth wiring 13 and is connected to the node B.

In the top view shown in FIG. 2C, a source impurity region 6 and a drain impurity region 7 are formed on the semiconductor substrate 5 on the left and right of the gate electrode, respectively. Here, the width WL of the lower layer gate 2 is formed larger than the width WU of the upper layer gate 1. The fourth wiring 13 is connected to the large-sized region. Also, the upper gate 1
The third wiring 12 is connected to the end of the. The gate lengths L of the upper layer gate 1 and the lower layer gate 2 are equal to each other.

In the semiconductor device of the present embodiment, the gate of this two-layer structure is used as an independent node without being short-circuited. That is, as shown in FIG. 2, the gate of the first layer is used as the gate electrode of the transistor, and the insulating film between the gate of the first layer and the gate of the second layer is used as the capacitor.

The first-layer gate electrode 2 is formed so as to extend to the element isolation region 8 in one direction thereof, and a gate contact 14 to which a potential is applied is formed at the extended portion. The second-layer gate electrode 1 is formed so as to extend to the element isolation region 8 in one direction thereof, and a gate contact 15 to which a potential is applied is formed in the extended portion. The gate contact 15 of the second layer gate electrode 1 is formed in a region different from the gate contact 14 of the first layer gate.

A source contact 16 is provided in the source impurity region 6 and is connected to the first wiring 10. Further, a drain contact 17 is provided in the drain impurity region 7 and is connected to the second wiring 11.

FIG. 1 is a circuit diagram of a part of the level shift circuit and the memory cell area of the present invention. Address signal Addr
ess is input to the plurality of input terminals of the AND circuit AD1.
The output of the AND circuit AD1 becomes the node N7. The node N7 is connected to the source of the depletion type NMOS transistor ND1. The gate of the NMOS transistor ND1 is the node N1. In addition, this NM
The gate of the OS transistor ND1 has a two-layer structure, and both gates are connected to the node N1.

The drain of the NMOS transistor ND1 is an enhancement type NMOS transistor NE.
2 is connected to the lower gate. The source of the NMOS transistor NE2 is the node N3. The upper gate of the NMOS transistor is insulated from the lower gate and connected to the node N3.

The source of the enhancement type NMOS transistor NE1 is connected to the node N7. The gate of the NMOS transistor NE1 is the node N2. In addition, this NMOS transistor NE1
Has a two-layer structure, and both gates are node N
Connected to 2.

The drain of the NMOS transistor NE1 is a node N6 and is connected to the drain of the NMOS transistor NE2. Furthermore, this node N6
It is connected to the lower gate of the enhancement type NMOS transistor NE3. The source of the NMOS transistor NE3 is the node N4, and the drain thereof is connected to the word line WL. Further, the upper gate of the NMOS transistor NE3 is insulated from the lower gate,
It is connected to the word line WL. As described above, the level shift circuit 19 includes the NMOS transistors ND1 and NE.
1, NE2, NE3.

The upper gate of the memory cell transistor M is connected to the word line WL. The source of the memory cell transistor M includes a first selection transistor SG
1 is connected to the drain of the first selection transistor S
The gate of G1 is controlled by the first selection signal SGS. The source of the first selection transistor SG1 is connected to the source line CS.

The source of the second selection transistor SG2 is connected to the drain of the memory cell transistor M,
The gate of the second selection transistor SG2 is controlled by the second selection signal SGD. This second selection transistor S
The source of G2 is connected to the bit line BL.

Here, a sectional view of the NMOS transistor NE3 is shown in FIG. NMOS transistor N
The periphery of E3 is surrounded by the element isolation region 9 as shown in FIG.

Next, NMOS transistors NE1 and N
A cross-sectional view of the MOS transistor NE2 is shown in FIG. Figure 3
In the cross-sectional view shown in, the NMOS transistor NE1 is formed on the left side and the NMOS transistor NE2 is formed on the right side, surrounded by the element isolation region 9 on the semiconductor substrate 5. In the NMOS transistor NE1, both the upper layer gate 20 and the lower layer gate 21 are made of polycrystalline silicon. An inter-gate insulating film 22 is formed between the upper layer gate 20 and the lower layer gate 21 and functions as a capacitor insulating film. A gate insulating film 23 is formed below the lower gate 21. A source impurity region 24 and a drain impurity region 25 are formed near the end of the gate insulating film 23 below the lower gate 21 in the semiconductor substrate 5.

In the NMOS transistor NE2, both the upper layer gate 26 and the lower layer gate 27 are made of polycrystalline silicon. The upper gate 26 and the lower gate 2
An inter-gate insulating film 28 is formed between 7 and functions as a capacitor insulating film. A gate insulating film 29 is formed below the lower gate 27. A source impurity region 30 and a drain impurity region 25 are formed near the edge of the gate insulating film 29 below the lower gate 27 in the semiconductor substrate 5. Here, the drain impurity region 25 is an NMOS
It is shared with the drain impurity region of the transistor NE1.

A P well is formed near the surface of the semiconductor substrate 5, and N type source impurity regions 24 and 30 and a drain impurity region 25 are formed therein. A fifth wiring 31 is connected to the source impurity region 24 and is connected to the node N7. The sixth wiring 32 is connected to the drain impurity region 25, and the node N6
It is connected to the. Further, the seventh wiring 33 is connected to the upper layer gate 20, and is connected to the node N2. The seventh wiring 33 is also connected to the lower gate 21.
The eighth wiring 34 is connected to the source impurity region 30 and is connected to the node N3. The upper wiring 26 has a ninth
The wiring 35 is connected to the node N3. The tenth wiring 36 is connected to the lower layer wiring 27, and the node N
Connected to 5.

Here, the inter-gate insulating films 3, 22, 28 shown in FIGS. 2 and 3 are, for example, ONO which is a laminated film of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
(Oxide-Nitride-Oxide) film.

Although the gate of the second layer of the NMOS transistor transistor NE3 is connected to the drain side WL, it may be connected to the source side node N4 to improve the efficiency. That is, when the drive of the node N4 must be increased, the second layer gate is connected to the drain side WL and the NMOS transistor NE3 is connected.
If the drive capability of the
It can be connected to the 4 side. Also, the transistor N
The second layer gate of E2 is connected to the source side,
The load may be prioritized by connecting to the drain-side node N6.

The selection transistors SG1 and SG2 are shown in FIG.
The transistor has the structure shown in FIG. Alternatively, in the selection transistor, the potential may be applied only to the lower conductive layer. In this case, the lower conductive layer is drawn out on the element isolation region and a potential is applied independently of the upper conductive layer. In this case, in the select transistor, due to the presence of the inter-gate insulating film, the potential is applied only to the lower conductive layer, and the upper conductive layer remains insulated.

In the memory cell transistor M, a lower conductive layer to be a floating gate which is a charge storage layer is formed on a semiconductor substrate via a gate insulating film. An upper conductive layer to be a control gate is formed on the lower conductive layer via an inter-gate insulating film. Thus, the potential of the conductive layer below the memory cell transistor is in a floating state. The memory cell transistor constitutes a nonvolatile memory cell array including one or more transistors having a structure having a floating gate which is a charge storage layer.

As shown in FIG. 3, in the sectional view of the transistors NE1 and NE2 in FIG. 1, the lower gate electrode of the transistor NE1 and the lower gate electrode of the transistor NE2 have the same material and the same film thickness. Inter-gate insulating film of transistor NE1 and transistor NE
The material and thickness of the second inter-gate insulating film are the same, and the material and thickness of the first upper gate electrode of the transistor NE1 and the second upper gate electrode of the transistor NE2 are the same.

The inter-gate insulating film formed of the ONO film has a thickness of, for example, about 0.02 μm to 0.03 μm.
The thin film can be used as a capacitor insulating film, as compared with the normally used gate insulating film below the first layer gate having a thickness of, for example, about 0.05 μm. Therefore, a large capacitor capacity can be secured.

Here, in FIG. 2C, the capacitance of the capacitor can be changed by adjusting the gate length or the gate width of the two layers of the transistor in which the capacitor is formed. By doing so, in the conventional example, it is possible to form the capacitor portion, which is arranged side by side with the high breakdown voltage transistor, on the high breakdown voltage transistor, and it is possible to significantly reduce the layout area.

Further, when the present embodiment is applied while the area of the semiconductor device remains the same as the conventional one, the memory cell capacity can be increased. That is, according to the present embodiment, the capacitor of the level shift circuit can be formed by using the inter-gate insulating film to which the high voltage of the nonvolatile semiconductor memory device is applied, and thus the insulating film having an appropriate thickness as the capacitor insulating film can be formed. As a film, it has a required capacitor capacity and realizes a capacitor in a small area.

The layout of the semiconductor device of this embodiment is shown in FIG. As shown in FIG. 4, a cell region 41 in which a large number of memory cell transistors are arranged in a matrix is provided on a semiconductor chip 49, and a plurality of level shift circuits 19 are arranged on both sides in one direction. A level shifter region 42 is provided, and a row decoder region 43 is provided on one side of the level shifter region 42. In the cell region 41, a plurality of word lines WL and memory cells connected to the word lines are provided.

Next, FIG. 5 shows a timing chart of the level shift operation of the level shift circuit 19 shown in FIG. 1 of the present embodiment. The level shift circuit 19 performs a two-stage bootstrap operation on the Vdd amplitude signal obtained by decoding the address signal by the AND circuit AD1 using the high breakdown voltage enhancement type N-channel transistors NE2 and NE3, and selectively outputs the high voltage. To do.

Here, FIG. 5 corresponds to the case where a block is selected by the row decoder shown in FIG. 4 and the word line WL is set to the write voltage Vpgrm to write to the memory cell.

Power supply voltage Vdd is supplied as an address decode signal to node N7 of the selected block. Further, in the initial state (before time T1), the node N
The power supply potential Vdd is supplied to 1 and N3, and the power supply voltage Vdd is also supplied to the gate of the NMOS transistor ND1. As a result, the NMOS transistor ND1 is turned on because it is a depletion type transistor, and the node N5
Is supplied with the power supply voltage Vdd (potential of the node N7).

The boosted potential VsgHHH is applied to the node N2.
Is supplied. As a result, the NMOS transistor NE
1 is turned on, and the power supply voltage Vdd (node N6
7) is supplied. Further, the ground potential is supplied to the node N4. Since the node N6 becomes the power supply voltage Vdd, the NMOS transistor NE3 is turned on, and the ground potential GND is supplied from the node N4 to each of the word lines WL. Up to this point corresponds to the operation in the initial state before time T1.

Next, the node N2 is changed from the boosted potential VsgHHH to the ground potential GND (time T1). By this, N
The MOS transistor NE1 is cut off, and the node N6
Becomes a floating state. Further, the high voltage Vpp becomes the write voltage Vpgrm, and the node N6 has the NMO.
A voltage "Vpgm-Vt" which is lower by the threshold value of the voltage Vpgrm is supplied through the S transistor NE2.

Subsequently, the node N3 is changed from the power supply voltage Vdd to the ground potential GND (time T2). As a result, NM
The OS transistor NE2 is turned on, and the node N6 becomes the ground potential GND. Since the NMOS transistor NE1 is cut off, no current flows from the node N7 to the node N3.

Next, the node N1 is changed from the power supply voltage Vdd to the ground potential GND (time T3). As a result, the depletion type NMOS transistor ND1 is cut off, and the node N5 becomes in a floating state.

Subsequently, the node N14 is changed from the ground potential GND to the write voltage Vpgrm (time T4). At this time, since the node N5 is in the floating state as at time T3, the potential of the node N5 is boosted by the capacitive coupling between the gate capacitance of the capacitor and the NMOS transistor NE2 and the parasitic capacitance of the other node N5. It At the node N6, the voltage "Vp
gm-Vt "is supplied.

Therefore, the node N5 becomes "(Vpgm-V
t) + Vt = Vpgm ″ or more, the NMOS transistor NE2 is turned on, and the node N5 is limited to the potential of the voltage Vpgm or less. As a result, the node N5 has the voltage Vp.
The potential becomes less than or equal to gm, the node N3 becomes the voltage Vpgrm, and the NMOS transistor NE2 is cut off.
The threshold voltage of E2) "is charged. At this time, the NMOS
Since the transistor NE2 maintains the cutoff state, the node N6 remains floating.

Next, the node N2 is changed from the ground potential GND to the power supply potential Vdd (time T5). This allows NMO
The potential difference between the gate (node N2) and the source (node N6) of the S transistor NE1 is reduced to reduce the breakdown voltage burden of the NMOS transistor NE1. This avoids surface breakdown. Furthermore, NMOS
Since the power supply voltage Vdd is supplied to the drain (node N7) of the transistor NE1, the threshold voltage of the NMOS transistor NE1 is increased by the substrate bias effect, and the leak current can be reduced.

Further, the node N1 is changed from the ground potential GND to the power supply potential Vdd (time T5). As a result, NM
The OS transistor ND1 is turned on, and the node N5 is discharged to the power supply potential Vdd. In this way, the NMOS transistor NE2 is surely cut off. At this time, the node N6 remains in the floating state.

Next, the operation of the substantial data writing period (the period from time T6 to T7) will be described. Node N4
Is changed from the ground potential GND to the write voltage Vpgrm (time T6). At this time, as described at time T5,
The potential of the node N6 is boosted by capacitive coupling between the capacitance of the NMOS transistor NE3 and the capacitor accompanying it and the parasitic capacitance of the other node N6. At this time,
The potential of the node N6 is “voltage Vpgrm + transistor N”
If boosted to a voltage higher than the threshold voltage of E3, NM
The OS transistor NE3 becomes conductive, and the node N4
The write voltage Vpgm is transferred from the word line WL to the word line WL.

Next, the operation of the recovery sequence after data writing will be described. Write voltage V to node N4
pgm is changed to the ground potential GND (time T7). As a result, the word line WL changes from the write voltage Vpgm to the ground potential GND. The potential of the node N6 drops due to capacitive coupling, as in the case of time T6. Also, the node N2
From the power supply potential Vdd to the ground potential GND.

Further, the node N3 is applied with the write voltage Vpg.
The ground potential GND is changed from m (time T8). At this time,
Gate of the NMOS transistor NE2 (node N5)
Is at the power supply potential Vdd at time T5, the potential of the node N3 is "Vdd- (NMOS transistor N
When the voltage becomes equal to or lower than the threshold voltage of E2) ", the NMOS transistor NE2 is turned on. As a result, the node N6 is discharged to the ground potential.

Next, the operation of the recovery sequence to the initial state will be described. The node N2 is set to the boosted potential VsgHHH from the ground potential GND, and the node N14 is set to the ground potential G.
The power supply potential Vdd is changed from ND (time T9). As a result, the NMOS transistor NE1 turns on and the node N6
Becomes the power supply potential Vdd. Further, the high voltage Vpp is changed from the write voltage Vpgm to the power supply potential Vdd. In this way, the initial state is restored.

As described above, with the level shift circuit according to the present embodiment, by using the boosting capacitor attached to NE2 for boosting, a sufficient voltage can be applied to the gate (node N6) of the NMOS transistor NE3 which is a word line transfer transistor. Can be supplied, there is no difficulty in transferring a high voltage to the word line. Also, by using the boost capacitor for boosting that is attached to the NE3,
It facilitates high voltage transfer.

Since the capacitor of the level shift circuit is formed by using the first-layer gate electrode and the second-layer gate electrode of the load MOS transistor, the area occupied by the level shift circuit becomes smaller than the conventional one, and the level shift circuit has a smaller area. High integration of a semiconductor device including is achieved. Also, load MOS
Since the gate electrode of the transistor also serves as one electrode of the capacitor, the manufacturing process for stacking the capacitors is simple. In the present embodiment, since the gate structure of the memory cell transistor and the gate structure of the transistor of the level shift circuit are made common, no additional manufacturing process is required, and the manufacturing method is the same as that of the conventional level shift circuit manufacturing method. Is also simplified and relatively easy to manufacture.

In addition to the example including two selection transistors and one memory cell transistor, a large number of memory cell transistors such as 8, 16 or 32 are connected in series between the two selection transistors. NAN
This embodiment can be applied to the circuit configuration of the D string structure. The present embodiment is not limited to the NAND type flash memory, but can be applied to an AND type flash memory.

According to this embodiment, the area of the entire semiconductor chip can be reduced. Further, if the present embodiment is realized in the same area as a conventional semiconductor chip, the capacity of the semiconductor chip can be increased.

This embodiment can be applied to a memory-embedded semiconductor device equipped with a non-volatile memory for performing data write / erase / read operations by the action of tunnel current using a high voltage of about 15V to 25V. Furthermore, it can be applied to a non-volatile memory for mounting an IC card.

(Modification of First Embodiment) Next, referring to FIG.
, A plurality of second-stage bootstrap circuits (NE3.NE) connected in parallel to the respective word lines.
3-2, ...) are provided. Memory cell transistors (M, M2, ...) And select transistors (SG1, SG2, SG22, SG22, ...) Are provided for each word line for each of the second-stage bootstrap circuits. Has been.

As described above, in the level shift circuit using a large number of second-stage boost operations, the layout pattern is reduced by utilizing the polycrystalline silicon interlayer capacitance of the transistor having the structure of the two-layer polycrystalline silicon layer. be able to.

(Second Embodiment) In the present embodiment,
As shown in FIG. 7, a plurality of level shift circuits according to the first embodiment are provided, each of which serves as a block, and a memory cell transistor is provided in each block. In this case, the selected block and the non-selected block exist at the same time. In this case, each block is provided with the level shift circuit 19 shown in FIG. 1, and the second word line WL2 different from the second block first block is provided with the word line W.
It is connected instead of L1.

The timing chart of this configuration is the same as that of FIG. 5 of the first embodiment. Regarding the selected block, the potential state shown by the solid line in FIG. 5 is shown, and the non-selected block shows the potential state shown by the broken line.

Next, the operation in the non-selected block will be described. The ground potential GND is supplied as an address decode signal to the node N5 of the non-selected block. Further, as in the case of the selected block, the initial state (time T
Before 1), the power supply voltage Vdd is supplied to the nodes N1 and N3. Accordingly, the NMOS transistor ND1 is a depletion type transistor and is turned on, and the ground potential (potential of the node N7) is supplied to the node N5. Since the node N5 is at the ground potential, the NMOS transistor NE2 is cut off.

Further, as in the case of the selected block, the boosted potential VsgHHH is supplied to the node N2, and the ground potential is supplied to the nodes N4, N4-2, .... As a result, the NMOS transistor NE1 is turned on, and the ground potential (potential of the node N7) is supplied to the node N6. Since the node N6 is at the ground potential, the NMOS
The transistors NE3, NE3-2, ... Are cut off. Therefore, the word lines WL2-1, ... Are in a floating state.

Next, the node N2 is changed from the boosted potential VsgHHH to the ground potential GND (time T1). As a result, NM
The OS transistor NE1 is cut off, and the node N6 is in a floating state.

Then, the node N3 is changed from the power supply voltage Vdd to the ground potential GND (time T2). At this time, NMO
Since the S transistor NE2 is in the cut-off state, there is no change in other signals.

Next, the node N1 is changed from the power supply voltage Vdd to the ground potential GND (time T3). At this time, since the depletion type NMOS transistor ND1 is kept in the ON state, there is no change in other signals.

Then, the node N3 is changed from the ground potential GND to the write voltage Vpgm (time T4). At this time,
The node N5 is at ground potential. Since the NMOS transistor NE2 is not turned on, the potential of the node N6 is not boosted. The NMOS transistor NE3 maintains the cutoff state.

Next, the node N2 is changed from the ground potential GND to the power supply potential Vdd (time T5). This allows NMO
The S transistor NE1 is turned on, the node N6 is no longer floating, and is fixed to the ground potential. Since the NMOS transistor NE3 maintains the cut-off state, the word lines WL2, ... In addition, the node N1 is changed from the ground potential GND to the power supply potential V
Set to dd (time T5). At this time, since the depletion type NMOS transistor ND1 is maintained in the ON state, the node N5 remains at the ground potential GND.

Next, the operation of the substantial data writing period (the period from time T6 to T7) will be described. Node N4
-2 changes from the ground potential GND to the write voltage Vpgm (time T6). At this time, the NMOS transistor NE
Since 3 is in the cutoff state, the write voltage Vpgm is not transferred from the node N4-2 to the word line WL2. No data is written.

Next, the operation of the recovery sequence after data writing will be described. The node N4-2 is set to the ground potential GND from the write voltage Vpgm (time T7). At this time, the NMOS transistor NE3 maintains the cutoff state. Further, the node N2 is changed from the power supply potential Vdd to the ground potential GND. As a result, the NMOS transistor NE1 is cut off and the node N6 is brought into a floating state.

Further, the node N3 is applied with the write voltage Vpg.
The ground potential GND is changed from m (time T8). At this time,
Since the NMOS transistor NE2 is cut off, the other signals do not change.

Next, the operation of the recovery sequence to the initial state will be described. The node N2 is changed from the ground potential GND to the boosted potential VsgHHH, and the node N3 is changed to the ground potential GN.
The power supply potential Vdd is changed from D (time T9). As a result, the NMOS transistor NE1 turns on and the node N6
Is at ground potential. Further, the high voltage Vpp is changed from the write voltage Vpgm to the power supply potential Vdd.

Also in this embodiment, the same effect as in the first embodiment can be obtained.

Each embodiment is not limited to the memory-embedded semiconductor device having the nonvolatile semiconductor memory device, but can be applied to the nonvolatile semiconductor memory device.

[0094]

According to the present invention, it is possible to provide a semiconductor device having high integration in a level shift circuit region having a two-layer gate structure.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2A is an NM according to the first embodiment of the present invention.
It is a circuit diagram showing an OS transistor and a capacitor,
(B) is a cross-sectional view showing the NMOS transistor and the capacitor of the first embodiment of the present invention, and (C) is a top view showing the NMOS transistor and the capacitor of the first embodiment of the present invention. is there.

FIG. 3 shows two NMOSs according to the first embodiment of the present invention.
Sectional drawing showing a transistor and a capacitor.

FIG. 4 is a layout diagram showing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is an operation timing chart of the level shift circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram of a modified example of the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a second embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional semiconductor device.

9A is a circuit diagram showing a conventional NMOS transistor and a capacitor, and FIG. 9B is a conventional NMO.
It is sectional drawing showing an S transistor and a capacitor,
(C) is a top view showing a conventional NMOS transistor and a capacitor.

[Explanation of symbols]

1, 20, 26 Upper gate 2, 21, 27 Lower gate 3, 22, 28 Gate insulating film 4,23,29 Gate insulating film 5 Semiconductor substrate 6, 24, 30 Source impurity region 7,25 Drain impurity region 8, 9 element isolation region 10, 31 First wiring 11,32 Second wiring 12, 33 Third wiring 13, 34 Fourth wiring 14,15 Gate contact 16 Source contact 17 Drain contact 19 Level shift circuit 35 fifth wiring 36 6th wiring 40 semiconductor chips 41 cell area 42 level shifter 43 Row decoder

Continued front page    (72) Inventor Takuya Niyama             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5B025 AA03 AB01 AC01 AD03 AD04                       AD10 AE00

Claims (7)

[Claims] 1. A semiconductor substrate having a memory cell region and a level shift circuit region, a first gate insulating film formed in the memory cell region on the semiconductor substrate, and a first gate insulating film formed on the first gate insulating film. A first lower gate electrode, a first inter-gate insulating film formed on the first lower gate electrode, a second upper gate electrode formed on the first inter-gate insulating film, and the semiconductor substrate on the semiconductor substrate. A second gate insulating film formed in the level shift circuit region, a second lower gate electrode formed on the second gate insulating film and given a first potential, and formed on the second lower gate electrode. A second inter-gate insulating film for accumulating charges as a capacitor insulating film, and a second upper gate electrode formed on the second inter-gate insulating film and given a second potential different from the first potential. Equipped with Wherein a Rukoto. 2. The first lower gate electrode and the second lower gate electrode have the same material and the same film thickness, and the first inter-gate insulating film and the second inter-gate insulating film are the same. The semiconductor device according to claim 1, wherein the material and the film thickness are the same, and the material and the film thickness of the first upper gate electrode and the second upper gate electrode are the same. 3. A first MOS transistor having a first gate and a first current path, a lower second gate, a first inter-gate insulating film on the second gate, and the first gate. A second MOS transistor having a third gate on the inter-insulating film and a second current path, and the potential at one end of the first current path of the first MOS transistor is supplied to the second gate. And a lower fourth gate, a second inter-gate insulating film on the fourth gate, a fifth gate on the second inter-gate insulating film, and a third current path. A third MOS transistor in which a potential at one end of a second current path of the MOS transistor is supplied to the fourth gate; one end of a first current path of the first MOS transistor and the second MOS transistor; The other end of the second current path of A first capacitor connected between one end and a second gate and a third gate of the second MOS transistor are capacitor electrodes, and the first inter-gate insulating film is a capacitor insulating film; It is connected between one end of the second current path of the second MOS transistor and one end or the other end of the third current path of the third MOS and the transistor, and the third MOS and the fourth of the transistor. And a fifth gate are capacitor electrodes, the second inter-gate insulating film is a capacitor insulating film, and the upper gate at one end of the third current path of the third MOS transistor. And a lower gate is a floating gate, and a non-volatile memory cell transistor having a third inter-gate insulating film between the upper gate and the lower gate is provided. Semiconductor device. 4. The semiconductor device according to claim 3, wherein the second MOS transistor and the third MOS transistor are enhancement type transistors. 5. The first inter-gate insulating film, the second inter-gate insulating film, and the third inter-gate insulating film have the same material and the same film thickness, and the second gate and the fourth gate are the same. And the lower gate of the non-volatile memory cell transistor have the same material and the same film thickness, and the third gate, the fifth gate and the lower gate of the non-volatile memory cell transistor have the same material and film thickness. 5. The semiconductor device according to claim 3, wherein the two are the same. 6. A semiconductor substrate, a first source and a first drain formed in the semiconductor substrate, a first gate formed on the semiconductor substrate and connected to a first terminal, and a first gate. A first gate and a second gate connected to a second terminal different from the first terminal, the second gate being formed through the inter-gate insulating film.
A first gate connected to the source or the first drain
A first transistor having a first gate which is in a floating state after being charged to a potential of 1 and brought into a conductive state; a second source and a second drain formed in the semiconductor substrate; and a second transistor formed on the semiconductor substrate. A third gate connected to the third terminal and the drain of the first transistor, and a fourth gate formed on the third gate via an inter-gate insulating film and connected to a fourth terminal different from the third terminal. A gate, the fourth gate being connected to the second source or the second drain, and when a potential higher than the first potential is applied from the first source of the first transistor, A second transistor that charges the third gate through the first transistor and is given a boosted potential to the second source so that the second drain has a boosted potential; and a third transistor formed in the semiconductor substrate. And a third drain, a fifth gate which is formed on the semiconductor substrate and has a floating potential, and a fifth gate which is formed on the fifth gate via an inter-gate insulating film. A semiconductor device, comprising: a memory cell transistor having a sixth gate connected to the drain and accumulating charges. 7. The first gate, the third gate, and the fifth gate are made of the same material and have the same film thickness, and the inter-gate insulating film of the first transistor and the gate of the second transistor are formed. The inter-layer insulating film and the inter-gate insulating film of the memory cell transistor have the same material and the same film thickness, and the second gate, the fourth gate and the sixth gate have the same material and the same film thickness. 7. The semiconductor device according to claim 6, wherein