JP2003142487A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which wiring can be protected by covering the exposed surface of buried wiring selectively with a continuous protective layer (thin film) having uniform thickness and the magnetism of the protective layer does not cause the deterioration of the semiconductor characteristics. SOLUTION: Wiring protective layers 30 and 42 each having an amorphous phase are formed selectively on the surfaces of exposed wirings 28 and 40 of a semiconductor device having a buried wiring structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a buried wiring structure formed by burying a conductor such as copper or silver in a fine wiring recess provided on the surface of a semiconductor substrate or the like. The present invention relates to a semiconductor device in which the surface of the wiring is protected by a wiring protection layer and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art As a wiring forming process of a semiconductor device,
A process (a so-called damascene process) in which a metal (conductor) is embedded in a wiring groove and a contact hole is being used. This is because after filling a wiring groove or contact hole previously formed in an interlayer insulating film with a metal such as aluminum, copper or silver in recent years, excess metal is removed by chemical mechanical polishing (CMP) to planarize the metal. It is a process technology.

In this type of wiring, for example, a copper wiring using copper as a wiring material, the surface of the wiring made of copper is exposed to the outside after the flattening, and the heat diffusion of the wiring (copper) is prevented. For example, in order to prevent the wiring (copper) from being oxidized, for example, when a semiconductor device having a multilayer wiring structure is formed by laminating insulating films (oxide films) in an oxidizing atmosphere thereafter, a Co alloy or a Ni alloy is used. It has been studied to selectively cover the surface of the exposed wiring with a wiring protection layer (cover material) made of, for example, to prevent thermal diffusion and oxidation of the wiring. This Co alloy, Ni alloy, etc. are obtained by electroless plating, for example.

[0004]

The wiring protection layer (cover) of this type is required to have a high electromigration resistance. It is said that electromigration is caused by Joule heat generated by concentration of electric current, and is generated from a thin portion or a pinhole portion in the wiring protection layer as a starting point. Therefore, in order to meet this demand, continuous thin films having a uniform film thickness, for example, 50 nm or less, preferably 10
It is desirable to uniformly cover the surface of the exposed wiring with a wiring protection layer made of a thin film having a thickness of about 30 nm.

However, as shown in FIG. 15, for example, Co--W--, which is obtained by, for example, electroless plating, is formed on the surface of a copper wiring 12 formed by burying copper inside an insulating film 10 made of SiO ₂ or the like. When the wiring protection layer (thin film) 14 made of B alloy and having a crystalline phase with a thickness of 50 nm or less is formed, the copper forming the copper wiring 12 is a polycrystalline film having a plurality of crystal orientations. Under the influence of the orientation, for example, the Co-WB alloy crystal 14a having the plane orientation (111) on the copper crystal 12a having the plane orientation (111) and the plane orientation on the copper crystal 12b having the plane orientation (222). The Co-WB alloy crystals 14b of (222) grow (epitaxially grow), respectively. Then, C having different plane orientations
Since the growth rates of the o-W-B alloy crystals 14a and 14b are different, there is a problem that it is difficult to obtain a continuous wiring protective layer (thin and thin) having a uniform film thickness.

That is, when a wiring protection layer (cover material) having a crystalline phase is grown on the surface of copper, this film becomes a film aligned with the crystal face of copper as a base, and a uniform and continuous film is obtained. Cannot be achieved, and sufficient electromigration resistance cannot be obtained. Furthermore, when the wiring is protected by selectively covering the surface of the wiring with a wiring protection layer made of a Co alloy or a Ni alloy obtained by electroless plating, the Co alloy or the Ni alloy is generally a magnetic substance. Magnetism deteriorates semiconductor characteristics.

The present invention has been made in view of the above circumstances, and the exposed surface of the buried wiring can be selectively covered with a continuous wiring protection layer (thin film) having a uniform film thickness to protect the wiring. It is another object of the present invention to provide a semiconductor device and a method for manufacturing the same in which a wiring protection layer for protecting the wiring does not deteriorate semiconductor characteristics.

[0008]

The invention according to claim 1 is characterized in that a wiring protective layer having an amorphous phase is selectively formed on the surface of an exposed wiring of a semiconductor device having a buried wiring structure. And a semiconductor device.

As a result, the surface of the exposed wiring is selectively covered with the wiring protection layer (cover material) having a uniform and continuous amorphous phase without being affected by the crystal orientation of the underlying wiring. Can be protected. For example, as shown in FIG. 1, on the surface of a copper wiring 12 formed by embedding copper inside an insulating film 10 made of SiO ₂ or the like, for example, a Co—W—B alloy obtained by electroless plating is used. 50 nm
Wiring protective layer (thin film) 16 having an amorphous phase having the following film thickness
When the copper wiring 12 is formed, for example, even if the copper forming the copper wiring 12 is a polycrystalline film having a plurality of crystal orientations, the copper crystal 1 having a plane orientation (111) is not affected by the crystal orientation.
Co-W on the copper crystal 12b of 2a or plane orientation (222)
The -B alloy 16a grows uniformly, whereby a continuous wiring protection layer (thin film) 16 having a uniform film thickness can be obtained.

The invention according to claim 2 has an embedded wiring structure using copper, copper alloy, silver or silver alloy as a wiring material.
The semiconductor device is characterized in that a wiring protection layer having an amorphous phase is selectively formed on the surface of the exposed wiring. In this way, by using a low resistance material such as copper or silver as the wiring material, it is possible to increase the speed and density of the semiconductor device.

According to a third aspect of the present invention, there is provided a semiconductor device characterized in that a wiring protection layer made of a non-magnetic film is selectively formed on a surface of an exposed wiring of a semiconductor device having a buried wiring structure. is there. Unlike the crystal, the wiring protection layer having an amorphous phase has an amorphous structure that does not have a three-dimensional order, and an alloy having this amorphous structure is generally non-magnetic (no ferromagnetism occurs). Is. Therefore, by forming the wiring protection layer with an amorphous structure, the wiring protection layer can be a non-magnetic film with each alloy composition.

The invention according to claim 4 has an embedded wiring structure using copper, copper alloy, silver or silver alloy as a wiring material.
The semiconductor device is characterized in that a wiring protection layer made of a nonmagnetic film is selectively formed on the surface of the exposed wiring. In the invention according to claim 5, the wiring protection layer is a Ni alloy,
5. The semiconductor device according to claim 1, wherein the semiconductor device is made of a Co alloy or a Cu alloy. As this Ni alloy, Ni-P, Ni-B, Ni-WP
Alternatively, a Ni-WB alloy or the like may be used. Examples of the Co alloy include Co-P, Co-B, Co-WP or Co-W.
-B alloy etc. are mentioned. Also, as a Cu alloy, C
u-B alloy etc. are mentioned.

According to a sixth aspect of the present invention, the Ni alloy,
The semiconductor device according to claim 5, wherein the wiring protection layer made of a Co alloy or a Cu alloy is formed by electroless plating. The invention according to claim 7 is characterized in that the surface of a semiconductor device having a buried wiring structure is subjected to electroless plating to selectively form a wiring protective layer having an amorphous phase on the surface of the exposed wiring. And a method for manufacturing a semiconductor device.

According to an eighth aspect of the present invention, electroless plating is applied to the surface of a semiconductor device having a buried wiring structure to selectively form a wiring protective layer made of a non-magnetic film on the surface of the exposed wiring. A method of manufacturing a semiconductor device is characterized by the above. In the invention according to claim 9, the wiring protective layer is N
9. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is made of an i alloy, a Co alloy, or a Cu alloy.

According to a tenth aspect of the present invention, a step of burying a conductor in a recess for wiring provided on the surface of a semiconductor device having a buried wiring structure by plating, and the surface of the semiconductor device by chemical mechanical polishing. A method of manufacturing a semiconductor device, comprising a step of flattening and a step of selectively forming a wiring protective layer having an amorphous phase on the surface of exposed wiring of the semiconductor device by electroless plating. is there. According to an eleventh aspect of the present invention, a step of embedding a conductor in a wiring recess provided on the surface of a semiconductor device having a buried wiring structure by plating, and the surface of the semiconductor device is made flat by chemical mechanical polishing. A method of manufacturing a semiconductor device comprising: a step of selectively forming a wiring protection layer made of a nonmagnetic film on a surface of an exposed wiring of the semiconductor device by electroless plating.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 2 shows a sectional structure of a semiconductor device according to an embodiment of the present invention having a two-layer embedded wiring structure. In this example, copper is used as the wiring material. As shown in FIG. 2, inside the insulating film 22 made of, for example, SiO ₂ deposited on the surface of the semiconductor substrate 20, fine recesses 2 for wiring are formed by, for example, the lithography / etching technique.
4 is formed, and the barrier layer 26 made of TaN or the like is formed thereon. Then, copper is embedded in the recess 24 to form a first-layer copper wiring 28, the exposed surface of the copper wiring 28 is selectively covered with a wiring protective layer 30, and the entire surface is further protected by a protective film made of SiN or the like. The wiring structure of the first layer is formed by covering with 32.

Here, the copper wiring 28 is formed on the semiconductor substrate W.
The surface of the insulating film 22 is filled with copper by depositing copper on the surface of the insulating film 22 and copper is deposited on the insulating film 22, and then the insulating film 22 is formed by chemical mechanical polishing (CMP).
It is formed by removing the upper copper and the barrier layer so that the surface of the copper filled in the recess 24 and the surface of the insulating film 22 are substantially flush with each other.

Then, an insulating film 34 made of, for example, SiO ₂ is deposited on the upper surface of the substrate W having the wiring structure of the first layer, and inside the insulating film 34, the wiring protection layer 30 is formed by, for example, the lithography / etching technique. To form a fine recess 36 for wiring, and a barrier layer 38 made of TaN or the like is formed thereon. Then, copper is embedded in the recess 36 to form a second-layer copper wiring 40, and the exposed surface of the copper wiring 40 is selectively covered with a wiring protection layer 42.
Further, the entire surface is covered with a protective film 44 made of SiN or the like to form a second layer wiring structure. The copper wiring 40
Is formed by copper-plating the surface of the semiconductor substrate 20 and then performing chemical mechanical polishing (CMP), as described above.

Here, the wiring protection layers 30 and 42 for selectively covering the exposed surfaces of the copper wirings 28 and 40 to protect the copper wirings 28 and 40 have an amorphous phase, for example, Co-WP.
It is made of an alloy and has a film thickness of 50 nm or less, preferably 10 to
It is composed of a thin film of 30 nm (20 nm in this example). The wiring protection layers 30 and 42 having the amorphous phase are formed by electroless plating. As described above, the wiring protection layers 30 and 42 are made of a Co-WP alloy having an amorphous phase, so that even if the film thickness is as thin as 20 nm, the copper of the underlying copper wirings 28 and 40 is formed. It is possible to form a uniform and continuous film without being affected by the crystal orientation of.

That is, as shown in FIG. 15, the wiring protection layer (thin film) 1 having a crystalline phase on the surface of the copper wiring 12 is formed.
4 is affected by the crystal orientation of copper forming the copper wiring 12, and the copper crystal 12a having, for example, a plane orientation (111) is formed.
On top of which a (111) orientation Co-WB alloy crystal 14a
On the copper crystal 12b having the plane orientation (222), the plane orientation (2
22) Co-WB alloy crystals 14b are grown (epitaxially grown), respectively, but as shown in FIG. 1, a wiring protection layer (thin film) 16 having an amorphous phase is formed on the surface of the copper wiring 12. Then, even if the copper forming the copper wiring 12 is a polycrystalline film having a plurality of crystal orientations, for example, the plane orientation (11
1) copper crystal 12a and plane orientation (222) copper crystal 12b
The Co-WB alloy 16a grows uniformly on the top surface of the wiring layer, and as a result, a continuous wiring protection layer (thin film) having a uniform film thickness.
You can get 16.

In this way, the copper wirings 28 and 40 which are the bases are formed.
Of the copper wiring 28, 40 by selectively covering the surface of the copper wiring 28, 40 with a wiring protection layer (covering material) 30, 42 having a uniform and continuous amorphous phase without being affected by the crystal orientation of copper. Four
By protecting 0, sufficient electromigration resistance can be obtained.

Moreover, the wiring protection layer 3 having an amorphous phase
Unlike crystals, 0 and 42 have an amorphous structure that does not have a three-dimensional order. Since an alloy having this amorphous structure is generally nonmagnetic (no ferromagnetism occurs), the wiring protection layer 30 , 42 as non-magnetic films, it is possible to prevent magnetism from affecting the semiconductor device.

FIG. 3 shows a process of forming the wiring protection layers 30 and 42 by electroless plating, and FIG. 4 shows an overall configuration of a plating apparatus for performing the electroless plating. The plating apparatus includes a loading / unloading unit 50, a plating pretreatment tank 52 for performing plating pretreatment, a plating tank 54 for performing plating treatment and activation treatment,
Further, a transfer robot 56 that transfers the substrate is provided between them. Here, the plating pretreatment bath 52 has a cleaning function, and the plating bath 54 has a cleaning / drying function.

First, the CMP process is completed, the substrate stored in the cassette is carried into the loading / unloading section 50, one substrate is taken out from the cassette by the transport robot 56 and transported to the pre-plating treatment bath 52. This plating pretreatment tank 52
The surface of the copper wirings 28, 40 to be the base is subjected to pretreatment (surface cleaning) for plating and then rinsed with water. Then, the substrate after the pretreatment for plating is conveyed to a plating bath 54, where it is subjected to activation treatment with an activating solution, and subsequently, electroless plating is performed on the surface of the substrate to form the copper wirings 28, 40. The wiring protection layers 30 and 42 made of a Co-WB alloy and having an amorphous phase are selectively formed on the exposed surface to the outside, and then washed with water and dried. Then, the substrate after this drying is returned to the cassette of the load / unload unit 50.

Here, in this example, the wiring protection layers 30 and 4 are provided.
2, a Co-WB alloy is used. That is,
By using a plating solution containing a compound containing Co ions, a complexing agent, a pH buffering agent, a pH adjusting agent, an alkylamine borane as a reducing agent, and W, and immersing the surface of the substrate in this plating solution, The wiring protection layers 30 and 42 made of a Co-WB alloy are formed.

Here, B is 5 to 50 at% with respect to Co.
By containing the above, Co-WB having an amorphous phase
The wiring protection layers 30 and 42 made of an alloy can be obtained. This is the same for Co-B alloys, and by containing P in an amount of 5 to 50 at% or more with respect to Co, wiring protection made of Co-P or Co-WP alloy having an amorphous phase. Layers can be obtained. Furthermore, B with respect to Ni
Alternatively, by containing P in an amount of 5 to 50 at% or more, a wiring protective layer made of Ni-B, Ni-WB, Ni-P, or Ni-WP alloy having an amorphous phase can be obtained.

The plating solution may contain one or two of a heavy metal compound or a sulfur compound as a stabilizer, if necessary.
Or more, or at least one of surfactants is added, and the pH is preferably 5 to 14, using a pH adjuster such as aqueous ammonia or quaternary ammonium hydroxide.
It is more preferably adjusted to 6 to 10. The temperature of the plating solution is, for example, 30 to 90 ° C, preferably 40 to 80 ° C.
Is. As a supply source of cobalt ions of the plating solution,
Examples thereof include cobalt salts such as cobalt sulfate, cobalt chloride, and cobalt acetate. The amount of cobalt ions added is, for example, about 0.001 to 1 mol / L, preferably about 0.01 to 0.3 mol / L.

Examples of the complexing agent include carboxylic acids such as acetic acid and salts thereof, oxycarboxylic acids such as tartaric acid and citric acid and salts thereof, aminocarboxylic acids such as glycine and salts thereof. Further, they may be used alone or in combination of two or more kinds. The total amount of complexing agent added is, for example, 0.001 to 1.5 mol / L,
It is preferably about 0.01 to 1.0 mol / L. p
Examples of the H buffer include ammonium sulfate, ammonium chloride, boric acid and the like. The addition amount of the pH buffer is, for example, 0.01 to 1.5 mol / L, preferably 0.1 to 1 mol / L.

Examples of the pH adjusting agent include aqueous ammonia, tetramethylammonium hydroxide (TMAH) and the like. The pH is 5 to 14, preferably pH 6
Adjust to -10. Examples of the alkylamine borane as the reducing agent include dimethylamine borane (DMA
B), diethylamine borane, etc. can be mentioned.
The addition amount of the reducing agent is, for example, about 0.01 to 1 mol / L, preferably about 0.01 to 0.5 mol / L.

Examples of the compound containing tungsten include tungstic acid and salts thereof, or heteropolyacids such as tungstophosphoric acid (eg, H ₃ (PW ₁₂ P ₄₀ ) nH ₂ O) and salts thereof. be able to. The amount of the compound containing tungsten added is, for example, 0.
001 to 1 mol / L, preferably 0.01 to 0.1 m
It is about ol / L. In addition to the above components, known additives can be added to this plating solution. Examples of this additive include one or more kinds of heavy metal compounds such as lead compounds and sulfur compounds such as thiocyan compounds as bath stabilizers, and anionic, cationic and nonionic surfactants. You can

In this example, the wiring protection layers 30, 42 are
Although a Co-WB alloy is used as the wiring protection layers 30 and 42, Co-B, Co-P, and Co-W- are used as the wiring protection layers 30 and 42.
P, Ni-B, Ni-WB, Ni-P or Ni-W
A wiring protection layer made of a -P alloy may be formed. Further, although an example in which copper is used as the wiring material is shown, copper alloy, silver, silver alloy, or the like may be used instead of copper.

FIG. 5 is a schematic diagram of the plating bath 54 shown in FIG. As shown in FIG. 5, the plating bath 54 is
A holding means 11 for holding the semiconductor substrate W on the upper surface thereof, and a dam member (plating solution holding means) that abuts on the peripheral portion of the plated surface (upper surface) of the semiconductor substrate W held by the holding means 11 and seals the peripheral portion. Mechanism) 31 and a shower head (electroless plating treatment liquid (dispersion) supply means) for supplying a plating liquid (electroless plating treatment liquid) to the surface to be plated of the semiconductor substrate W whose peripheral portion is sealed by the dam member 31. 41 is provided. The plating tank 54 is further installed near the outer periphery of the upper part of the holding means 11 and supplies a cleaning liquid to the surface to be plated of the semiconductor substrate W, and a recovery container 61 for recovering the discharged cleaning liquid or the like (plating waste liquid). And a plating solution recovery nozzle 65 for sucking and recovering the plating solution held on the semiconductor substrate W, and a motor (rotational driving means) M for rotationally driving the holding means 11.

The holding means 11 has a semiconductor substrate W on its upper surface.
It has a substrate mounting portion 13 for mounting and holding. The substrate mounting portion 13 is configured to mount and fix the semiconductor substrate W, and specifically includes a vacuum suction mechanism (not shown) that vacuum-sucks the semiconductor substrate W on its back surface side. On the other hand, on the back surface side of the substrate mounting portion 13, there is provided a back surface heater (heating means) 15 which is planar and warms and heats the plated surface of the semiconductor substrate W from the lower surface side. The back surface heater 15 is composed of, for example, a rubber heater. The holding means 11 is configured to be rotationally driven by a motor M and can be moved up and down by an elevating means (not shown). The dam member 31 is cylindrical and has a seal portion 33 that seals the outer peripheral edge of the semiconductor substrate W in the lower portion thereof, and is installed so as not to move vertically from the position shown in the figure.

The shower head 41 has a structure in which a large number of nozzles are provided at the tip of the shower head 41 so that the supplied plating solution is dispersed in a shower shape and supplied substantially uniformly to the surface to be plated of the semiconductor substrate W. The cleaning liquid supply means 51 has a structure in which the cleaning liquid is ejected from the nozzle 53. The plating solution recovery nozzle 65 is configured to be vertically movable and swivelable, and its tip has a dam member 31 at the peripheral portion of the upper surface of the semiconductor substrate W.
It is configured to descend to the inside of and to suck the plating solution on the semiconductor substrate W.

Next, the operation of this plating tank will be described. First, the holding means 11 is lowered from the state shown in the figure to form a gap of a predetermined size between the holding means 11 and the dam member 31, and the semiconductor substrate W is mounted and fixed on the substrate mounting portion 13. As the semiconductor substrate W, for example, a φ8 inch wafer is used. Next, as shown in FIG. 5, the holding means 11 is raised so that its upper surface abuts the lower surface of the dam member 31, and at the same time, the outer circumference of the semiconductor substrate W is dammed with the dam member 3.
The sealing is performed by the seal portion 33 of No. 1. At this time, the surface of the semiconductor substrate W is in an open state.

Next, the backside heater 15 is used to form the semiconductor substrate W.
By directly heating itself, the plating solution is ejected from the shower head 41 to pour the plating solution onto almost the entire surface of the semiconductor substrate W. Since the surface of the semiconductor substrate W is surrounded by the dam member 31, the injected plating solution is entirely contained in the semiconductor substrate W.
Retained on the surface of. The amount of the plating solution to be supplied may be as small as 1 mm (about 30 ml) on the surface of the semiconductor substrate W. The depth of the plating solution held on the surface to be plated may be 10 mm or less, and may be 1 mm as in this example. If only a small amount of plating solution needs to be supplied, a small heating device for heating the plating solution will suffice.

If the semiconductor substrate W itself is heated in this way, the temperature of the plating solution, which requires a large amount of power consumption for heating, does not have to be raised so high, so that the power consumption can be reduced. This is preferable because it can prevent the change of the material of the plating solution. Since the power consumption for heating the semiconductor substrate W itself may be small and the amount of the plating solution accumulated on the semiconductor substrate W is small, the backside heater 15 can easily keep the temperature of the semiconductor substrate W, and the backside heater 15 can be kept warm. The capacity is small and the device can be made compact.
If a means for directly cooling the semiconductor substrate W itself is used,
It is also possible to change the plating conditions by switching between heating and cooling during plating. Since a small amount of plating solution is held on the semiconductor substrate, temperature control can be performed with good sensitivity.

Then, the semiconductor substrate W is momentarily rotated by the motor M to uniformly wet the surface to be plated, and then the surface to be plated is plated while the semiconductor substrate W is stationary. Specifically, the semiconductor substrate W is set to 100 for 1 sec.
The surface to be plated of the semiconductor substrate W is uniformly wetted with the plating solution by rotating at rpm or less, and then allowed to stand still to perform electroless plating for 1 min. The instantaneous rotation time is at least 1
Set to 0 sec or less.

After the above plating process is completed, the tip of the plating solution recovery nozzle 65 is lowered to the vicinity of the inside of the dam member 31 at the peripheral portion of the surface of the semiconductor substrate W to suck the plating solution. At this time, if the semiconductor substrate W is rotated at a rotational speed of, for example, 100 rpm or less, the plating solution remaining on the semiconductor substrate W can be collected by centrifugal force in the dam member 31 at the peripheral edge of the semiconductor substrate W, The plating solution can be recovered efficiently and with a high recovery rate. Then, the holding means 11 is lowered to separate the semiconductor substrate W from the dam member 31, the rotation of the semiconductor substrate W is started, and the cleaning liquid (ultra pure water) is applied from the nozzle 53 of the cleaning liquid supply means 51 to the plated surface of the semiconductor substrate W. The electroless plating reaction is stopped by spraying to cool the surface to be plated and at the same time diluting and washing. At this time, the cleaning liquid sprayed from the nozzle 53 may be applied to the dam member 31 to simultaneously clean the dam member 31. The plating waste liquid at this time is
It is collected in the collection container 61 and discarded.

The plating solution used once is not reused but is thrown away. As described above, the amount of the plating solution used in this apparatus can be made much smaller than the conventional one, so that the amount of the plating solution to be discarded is small even if it is not reused. In some cases, the plating solution recovery nozzle 65 may not be installed, and the used plating solution may be recovered together with the cleaning solution in the recovery container 61 as a plating waste solution. And motor M
After the semiconductor substrate W is rotated at a high speed by spin-drying, the semiconductor substrate W is taken out from the holding means 11.

FIG. 6 is a schematic configuration diagram of another plating bath. 6 is different from the plating bath 54 shown in FIG. 5 in that instead of providing the back surface heater 15 in the holding means 11, the lamp heater (heating means) 1 is provided above the holding means 11.
7, the lamp heater 17 and the shower head 4 are installed.
It is a point that 1-2 is integrated. That is, for example, a plurality of ring-shaped lamp heaters 17 having different radii are installed concentrically, and a large number of nozzles 43-2 of the shower head 41-2 are opened in a ring shape from the gaps between the lamp heaters 17. It should be noted that the lamp heater 17 may be composed of a single spiral lamp heater, or may be composed of other lamp heaters having various structures and arrangements.

Even with such a configuration, the plating solution can be supplied from the nozzles 43-2 to the surface of the semiconductor substrate W to be plated in a substantially uniform manner, and the lamp heater 17 heats / heats the semiconductor substrate W. Can be done directly and evenly. In the case of the lamp heater 17, not only the semiconductor substrate W and the plating solution but also the surrounding air is heated, so that the semiconductor substrate W also has a heat retaining effect.

In order to directly heat the semiconductor substrate W by the lamp heater 17, a relatively large power consumption lamp heater 17 is required. Therefore, instead of the relatively low power consumption lamp heater 17 shown in FIG. The semiconductor substrate W may be heated mainly by the rear surface heater 15 in combination with the rear surface heater 15 shown, and the lamp heater 17 may mainly maintain the temperature of the plating solution and the surrounding air. Further, the temperature may be controlled by providing a means for directly or indirectly cooling the semiconductor substrate W.

FIG. 7 shows another embodiment of the present invention. As shown in the figure, the present plating apparatus includes a loading / unloading area 520 for delivering and receiving a wafer cassette containing a semiconductor wafer,
A process area 530 for performing process processing and a cleaning / drying area 540 for cleaning and drying the semiconductor wafer after the process processing are provided. The cleaning / drying area 540 is arranged between the loading / unloading area 520 and the process area 530. A partition 521 is provided in the carry-in / carry-out area 520 and the cleaning / drying area 540 to clean the cleaning / drying area 5
A partition wall 523 is provided between 40 and the process area 530.

The partition wall 521 is provided with a passage (not shown) for transferring the semiconductor wafer between the loading / unloading area 520 and the cleaning / drying area 540, and a shutter 522 for opening and closing the passage. There is. In addition, the partition wall 523
Also, a passage (not shown) for transferring the semiconductor wafer between the cleaning / drying area 540 and the process area 530.
And a shutter 524 for opening and closing the passage. Cleaning / drying area 540 and process area 5
30 can supply and exhaust air independently.

The semiconductor wafer wiring plating apparatus having the above-described structure is installed in a clean room, and the pressure in each area is (the pressure of the loading / unloading area 520)> (the pressure of the cleaning / drying area 540)> (the process area 530). Pressure) and the pressure in the carry-in / carry-out area 520 is set lower than the pressure in the clean room. This prevents air from flowing from the process area 530 to the cleaning / drying area 540, prevents air from flowing from the cleaning / drying area 540 to the carry-in / carry-out area 520, and further air from the carry-in / carry-out area 520 into the clean room. To prevent it from leaking.

In the carry-in / carry-out area 520, a load unit 520a and a unload unit 520b for accommodating a semiconductor wafer accommodating cassette are arranged. In the cleaning / drying area 540, two water washing units 541 and a drying unit 542 for performing post-plating processing are arranged, and a transfer unit (transfer robot) 543 for transferring semiconductor wafers is provided. As the water washing section 541, for example, a pencil type with a sponge on the front end or a roller type with a sponge is used. As the drying unit 542, for example, a unit in which a semiconductor wafer is spun at high speed to dehydrate and dry is used.

In the process area 530, a pretreatment bath 531 for pretreatment of semiconductor wafer plating and a plating bath 532 for copper plating treatment are arranged, and a transport unit (transport robot) for transporting semiconductor wafers. ) 543 is provided.

FIG. 8 shows the flow of air flow in the plating apparatus for semiconductor wafer wiring. In the washing / drying area 540, fresh external air is taken in from the pipe 546 and pushed by the fan through the high-performance filter 544, so that the ceiling 5
Washing part 5 as clean air downflow from 40a
41, around the drying unit 542. Most of the supplied clean air is returned from the floor 540b to the ceiling 540a side by the circulation pipe 545, and again the high performance filter 54 is supplied.
It is pushed in by a fan through 4 and circulates in the washing / drying area 540. Part of the airflow is exhausted from the water washing section 541 and the drying section 542 through the duct 552.

Although the process area 530 is called a wet zone, particles are not allowed to adhere to the surface of the semiconductor wafer. Therefore, the process area 53
Particles are prevented from adhering to the semiconductor wafer by being pushed into the space 0 from the ceiling 530a by a fan and flowing down-flow clean air through the high-performance filter 533.

However, if the total flow rate of the clean air that forms the downflow depends on the supply / exhaust from the outside,
A huge amount of air supply and exhaust is required. For this reason, only the exhaust to the extent that the pressure in the room is kept negative is external exhaust from the duct 553, and most of the downflow airflow is made into the pipes 534 and 535.
It is designed to be covered by a circulating air flow.

When the circulating air flow is used, the process area 5
Since the clean air that has passed through 30 contains the chemical liquid mist and gas, the clean air is passed through the scrubber 536 and the mito separator 53.
Remove through 7,538. As a result, the ceiling 530a
The air that has returned to the side circulation duct 534 does not contain the chemical mist or gas, is pushed again by the fan, passes through the high-performance filter 533, and circulates in the process area 530 as clean air.

A part of the air that has passed through the process area 530 from the floor portion 530b is discharged to the outside through the pipe 553, and the air containing the chemical mist and gas is discharged to the outside through the duct 553. From the duct 539 of the ceiling 530a, fresh air corresponding to these exhaust amounts is supplied to the process area 530 to such an extent that the negative pressure is maintained.

As described above, the pressures of the loading / unloading area 520, the cleaning / drying area 540 and the process area 530 are as follows: (pressure of loading / unloading area 520)> (pressure of cleaning / drying area 540)> (process Area 530 pressure). Therefore, the shutters 522, 524
When (see FIG. 7) is opened, the air flow between these areas flows in the order of the loading / unloading area 520, the cleaning / drying area 540, and the process area 530, as shown in FIG. Further, the exhaust gas is collected in the collective exhaust duct 554 through the ducts 552 and 553 as shown in FIG.

FIG. 10 is an external view showing an example in which the plating apparatus for semiconductor wafer wiring according to the present invention is arranged in a clean room. The side of the loading / unloading area 520 where the cassette delivery port 555 and the operation panel 556 are located is the partition wall 5.
It is exposed in a working zone 558 having a high degree of cleanliness of a clean room partitioned by 57, and the other side faces are housed in a utility zone 559 having a low degree of cleanliness.

As described above, the cleaning / drying area 540 is arranged between the loading / unloading area 520 and the process area 530, and the loading / unloading area 520 and the cleaning / drying area 5 are arranged.
Since partition walls 521 are provided between the cleaning and drying areas 40 and between the cleaning / drying area 540 and the process area 530, they are carried into the semiconductor wafer wiring plating apparatus from the working zone 558 through the cassette transfer port 555 in a dry state. The semiconductor wafer is plated in a semiconductor wafer wiring plating apparatus, and is carried out to the working zone 558 in a cleaned and dried state. Therefore, particles and mist are not attached to the surface of the semiconductor wafer, and the semiconductor wafer is kept in a clean room. Highly clean working zone 5
58 is not contaminated with particles, chemicals or cleaning liquid mist.

Although FIGS. 7 and 8 show an example in which the plating apparatus for semiconductor wafer wiring is provided with the carry-in / carry-out area 520, the cleaning / drying area 540 and the process area 530. An area for arranging the CMP device may be provided adjacent to the process area 530, and a cleaning / drying area 540 may be arranged between the process area 530 or the area for arranging the CMP device and the loading / unloading area 520. good. The point is that the semiconductor wafer may be carried in a dry state into a semiconductor wafer wiring plating apparatus, and the semiconductor wafer after the plating process may be washed and discharged in a dry state.

In the above example, the substrate plating apparatus has been described as an example of a semiconductor wafer wiring plating apparatus, but the substrate is not limited to the semiconductor wafer, and the portion to be plated is also formed on the substrate surface. It is not limited to a section. In addition, in the above example, Cu plating was described as an example,
It is not limited to Cu plating.

(Example) TaN was deposited on a silicon substrate, 100 nm copper was deposited thereon by sputtering, and 700 nm copper was deposited by electrolytic copper plating.
A sample annealed (heat-treated) for 1 hour in a N ₂ environment at 350 ° C. was prepared. Then, after performing a pretreatment for plating, washing with water, and an activation treatment, using an electroless plating apparatus, the following Table 1 is used.
An electroless plating process using an electroless plating solution having the composition shown in was performed to deposit a Co—WB alloy (wiring protection layer) on the surface of the sample (substrate) by about 50 nm. After that, the sample was washed with water and dried. The content ratio of each component in this film (Co-WB alloy) is Co: 85 at%, W: 1.5 a.
t% and B: 13.5 at%.

[Table 1]

(Comparative Example) As a comparative example, the surface of a sample similar to that described above was subjected to an electroless plating treatment using an electroless plating solution having the composition shown in Table 2, and a Co-WB alloy of about 5 was obtained.
0 nm was deposited. After that, the sample was washed with water and dried. The content ratio of each component in this film (Co-WB alloy) is Co: 89.5 at%, W: 10 at%, B: 0.
It was 5 at%.

[Table 2]

FIG. 11 is a photograph of the surface of the sample before the plating treatment taken by SEM (scanning electron microscope) in this example.
FIG. 11B shows a photograph after plating treatment in (a), and FIG. 12 shows data showing the relationship between the diffraction intensity and 2θ when X-ray diffraction is performed. It can be seen from FIG. 11B that a uniform and continuous thin film of Co—WB alloy, which is not affected by the crystal orientation of the underlying copper shown in FIG. 11A, can be obtained. Further, according to FIG. 12, clear Co (11
1), Co (222) peaks are not observed, and therefore
It can be seen that the thin film made of this Co-WB alloy has an amorphous phase.

On the other hand, in the comparative example, a photograph of the surface of the sample before the plating treatment taken by the SEM (scanning electron microscope) is shown in FIG. 13 (a), and a photograph after the plating treatment is shown in FIG. 13 (b).
FIG. 14 shows data showing the relationship between the diffraction intensity and 2θ when X-ray diffraction is performed. From this FIG. 13B, it can be seen that a thin film made of a non-uniform and discontinuous Co—WB alloy that matches the crystal orientation of the underlying copper shown in FIG. 13A is obtained. Further, from FIG. 14, it is clear that Co (11
1) and the peaks of Co (222) are observed. Therefore, it is understood that the thin film made of this Co-WB alloy has a crystalline phase.

[0063]

As described above, according to the present invention,
Protects the wiring by selectively covering the surface of the exposed wiring with a wiring protection layer (covering material) that has a uniform and continuous amorphous phase without being affected by the crystal orientation of the underlying wiring By selectively covering the surface of the exposed wiring with the wiring protection layer having a quality to protect the wiring, the wiring protection layer can be made to be a nonmagnetic film.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a state in which a thin film made of an alloy having an amorphous phase is deposited (grown) on a copper wiring.

FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a process of forming a wiring protection layer by electroless plating.

FIG. 4 is an overall layout diagram of a plating apparatus for forming a wiring protection layer by electroless plating.

5 is a schematic configuration diagram showing an example of the plating tank shown in FIG.

FIG. 6 is a schematic configuration diagram showing another example of a plating tank.

FIG. 7 is a diagram showing a planar configuration of a plating apparatus for semiconductor wafer wiring according to the present invention.

FIG. 8 is a diagram showing the flow of airflow in the plating apparatus for semiconductor wafer wiring of the present invention.

FIG. 9 is a diagram showing the flow of air between the areas of the semiconductor wafer wiring plating apparatus of the present invention.

FIG. 10 is an external view showing an example in which the semiconductor wafer wiring plating apparatus of the present invention is arranged in a clean room.

FIG. 11 is SEM photographs of samples before and after the plating process according to the example.

FIG. 12 is a graph showing the relationship between the diffraction intensity and 2θ when X-ray diffraction was performed after the plating treatment according to the example.

FIG. 13 is SEM photographs of samples before and after being subjected to a plating treatment according to a comparative example.

FIG. 14 is a graph showing a relationship between diffraction intensity and 2θ when X-ray diffraction is performed after the plating treatment according to the comparative example.

FIG. 15 is a cross-sectional view schematically showing a state when a thin film made of an alloy having a crystalline phase is deposited (grown) on a copper wiring.

[Explanation of symbols]

10 Insulating film 12, 28, 40 Copper wiring 12a, 12b Copper crystal 16, 30, 42 Wiring protection layer (cover material) 22,34 Insulation film 24,36 recess 26,38 Barrier layer 32,44 protective film 50 Load / unload section 52 Pretreatment tank for plating 54 plating tank

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shinmei Wang             11-1 Haneda Asahi-cho, Ota-ku, Tokyo Co., Ltd.             Inside the EBARA CORPORATION (72) Inventor Moriji Matsumoto             Yuzawa Ebara 1-1-6 Zenyokozaka, Fujisawa City, Kanagawa Prefecture             -Inside Zelite Co., Ltd. (72) Inventor Makoto Kanayama             Yuzawa Ebara 1-1-6 Zenyokozaka, Fujisawa City, Kanagawa Prefecture             -Inside Zelite Co., Ltd. F term (reference) 5F033 HH07 HH11 HH12 HH14 HH15                       HH32 JJ07 JJ11 JJ12 JJ14                       JJ15 JJ32 KK01 KK07 KK11                       KK12 KK14 KK15 KK32 LL06                       MM02 MM05 MM12 MM13 NN06                       NN07 PP27 PP28 QQ48 RR04                       RR06 TT02 XX05

Claims (11)

[Claims] 1. A semiconductor device having a wiring protection layer having an amorphous phase selectively formed on a surface of an exposed wiring of a semiconductor device having a buried wiring structure. 2. A buried wiring structure using copper, copper alloy, silver or silver alloy as a wiring material, wherein a wiring protective layer having an amorphous phase is selectively formed on the surface of the exposed wiring. Semiconductor device. 3. A semiconductor device, wherein a wiring protection layer made of a non-magnetic film is selectively formed on a surface of an exposed wiring of a semiconductor device having a buried wiring structure. 4. A wiring protection layer having a buried wiring structure using copper, copper alloy, silver or silver alloy as a wiring material, and a wiring protection layer made of a non-magnetic film is selectively formed on the surface of the exposed wiring. Semiconductor device. 5. The semiconductor device according to claim 1, wherein the wiring protection layer is made of a Ni alloy, a Co alloy, or a Cu alloy. 6. The semiconductor device according to claim 5, wherein the wiring protection layer made of the Ni alloy, the Co alloy or the Cu alloy is formed by electroless plating. 7. A semiconductor device having a buried wiring structure, wherein the surface of the semiconductor device is subjected to electroless plating to selectively form a wiring protective layer having an amorphous phase on the surface of the exposed wiring. Production method. 8. A semiconductor device, wherein a surface of a semiconductor device having a buried wiring structure is electrolessly plated to selectively form a wiring protective layer made of a nonmagnetic film on the surface of the exposed wiring. Manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the wiring protection layer is made of a Ni alloy, a Co alloy or a Cu alloy. 10. A step of burying a conductor in a wiring recess provided on the surface of a semiconductor device having a buried wiring structure by plating, a step of flattening the surface of the semiconductor device by chemical mechanical polishing, and And a step of selectively forming a wiring protective layer having an amorphous phase on the surface of the exposed wiring of the semiconductor device by electroless plating. 11. A step of embedding a conductor in a wiring recess provided on the surface of a semiconductor device having a buried wiring structure by plating, a step of flattening the surface of the semiconductor device by chemical mechanical polishing, and And a step of selectively forming a wiring protective layer made of a nonmagnetic film on the surface of the exposed wiring of the semiconductor device by electroless plating.