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JP2003151805A - Chip element component and its manufacturing method - Google Patents

Chip element component and its manufacturing method

Info

Publication number
JP2003151805A
JP2003151805A JP2001350645A JP2001350645A JP2003151805A JP 2003151805 A JP2003151805 A JP 2003151805A JP 2001350645 A JP2001350645 A JP 2001350645A JP 2001350645 A JP2001350645 A JP 2001350645A JP 2003151805 A JP2003151805 A JP 2003151805A
Authority
JP
Japan
Prior art keywords
chip
ceramic body
coat layer
glass
glass coat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001350645A
Other languages
Japanese (ja)
Inventor
Atsushi Kishimoto
敦司 岸本
Hideaki Niimi
秀明 新見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2001350645A priority Critical patent/JP2003151805A/en
Publication of JP2003151805A publication Critical patent/JP2003151805A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Thermistors And Varistors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a chip electronic component that is improved in durability by means of a glass coating layer formed as a protective layer, can secure continuity between internal and external electrodes, and is excellent in yield and electric characteristics, and to provide a method of manufacturing the component. SOLUTION: On at least a part of the surface of a chip-type sintered laminate 15, glass coating layers 16 each having a thicknesses of 0.05-5 μm are provided. In addition, on surfaces of both end sections of the laminate 15, external electrodes 19 of which the mean thickness is three times or more larger than that of the layer 16 and baked at a temperature lower than the softening point of the layer 16 and higher than an operating temperature are provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、チップ型電子部品
およびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type electronic component and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より、素子を外部雰囲気より保護す
るために、その外周部に保護膜を設けることが行われて
いる(特開平5−251210号公報、特開平5−28
3206号公報)。
2. Description of the Related Art Conventionally, in order to protect an element from the outside atmosphere, a protective film has been provided on the outer peripheral portion thereof (Japanese Patent Application Laid-Open Nos. 5-251210 and 5-2815).
3206 publication).

【0003】特開平5−251210号公報では、サー
ミスタ素地チップを研磨し、角隅部及び稜線部分を丸く
してから、サーミスタ素地チップの表面にガラス皮膜を
形成し、次いで、電極材料ペースト塗膜を焼付ける際、
その焼付け温度より、ガラスの作業点温度を低くするこ
とにより、サーミスタ素地チップに保護膜を設けてい
る。
In Japanese Unexamined Patent Publication (Kokai) No. 5-251210, a thermistor base chip is ground to round corners and ridges, and then a glass film is formed on the surface of the thermistor base chip, and then an electrode material paste coating film is formed. When baking
By lowering the working temperature of the glass below the baking temperature, a protective film is provided on the thermistor base chip.

【0004】また、特開平5−283206号公報で
は、導電性セラミックス素体の全面に厚さ0.1μm〜
2μmの絶縁性無機物層を被覆し、そのセラミックス素
体の両端に金属粉末と無機結合材を含む導電性ペースト
を塗布して、無機物層の融点または軟化点より低い温度
で焼成することにより、焼付け電極層の接触部分以外の
セラミック素体の表面に保護膜を設けている。
Further, in JP-A-5-283206, a thickness of 0.1 μm to the entire surface of the conductive ceramic body is
Baking by coating a 2 μm insulating inorganic layer, applying a conductive paste containing metal powder and an inorganic binder to both ends of the ceramic body, and firing at a temperature lower than the melting point or softening point of the inorganic layer. A protective film is provided on the surface of the ceramic body other than the contact portion of the electrode layer.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
特開平5−251210号公報に記載のチップ型電子部
品では、電極ペースト焼付け時にガラスが電極表面に浮
き上がったり、セラミックス素体同士または素体と焼成
治具との張りつきが生じて、不良品が発生し歩留りが低
下するという問題を生じている。
However, in the conventional chip-type electronic component disclosed in Japanese Unexamined Patent Publication No. 5-251210, glass floats on the surface of the electrode during baking of the electrode paste, or the ceramic bodies are burned together or with the body. There is a problem that sticking to the jig occurs, defective products are generated, and the yield is reduced.

【0006】また、特開平5−283206号公報で
は、導電性ペースト焼付け後も、電極層とセラミックス
素体との間が導通接続されない不良品が発生し歩留りが
低下するという問題を生じている。
Further, in Japanese Unexamined Patent Publication No. 5-283206, there is a problem that even after baking the conductive paste, a defective product in which the electrode layer and the ceramic body are not electrically connected to each other is produced and the yield is reduced.

【0007】本発明は、電極ペースト焼付け時に保護層
としてのガラスが電極表面に浮き上がったり、セラミッ
クス素体同士または素体と焼成治具との張りつきが防止
され、電極ペースト焼付け後も、電極層とセラミックス
素体との間の導通接続が安定化された、歩留りが良好で
電気特性に優れたチップ型電子部品およびその製造方法
を提供することを目的とする。
According to the present invention, glass as a protective layer is prevented from floating on the surface of the electrode during baking of the electrode paste, and sticking of the ceramic bodies to each other or between the body and the firing jig is prevented. An object of the present invention is to provide a chip-type electronic component having a stable electrical connection with a ceramic body, a good yield, and excellent electrical characteristics, and a method for manufacturing the same.

【0008】[0008]

【課題を解決するための手段】本発明のチップ型電子部
品は、上記の課題を解決するために、チップ型のセラミ
ックス素体と、上記セラミックス素体の少なくとも一部
表面に被覆された厚さ0.05μm〜5μmのガラスコ
ート層と、前記セラミックス素体の両端部表面上に、前
記ガラスコート層の3倍以上の平均厚さを備え、かつ、
前記ガラスコート層の軟化点以上、作業温度以下の焼付
けにより形成される物性を備えた外部電極とを有するこ
とを特徴としている。
In order to solve the above-mentioned problems, a chip-type electronic component of the present invention comprises a chip-type ceramic element body and a thickness of at least a part of the surface of the ceramic element body. A glass coat layer having a thickness of 0.05 μm to 5 μm, and an average thickness that is three times or more the thickness of the glass coat layer on both end surfaces of the ceramic body, and
An external electrode having physical properties formed by baking the glass coat layer at a softening point or higher and a working temperature or lower.

【0009】前記セラミックス素体は、チタン酸バリウ
ムを主成分とする正の抵抗温度特性を有する半導体セラ
ミックスからなり、一方端部表面に形成された前記外部
電極に電気的に接続される内部電極と、他方端部表面に
形成された前記外部電極に電気的に接続される内部電極
とが、前記セラミックス素体内部に交互に埋設されてな
ることが好ましい。
The ceramic body is made of a semiconductor ceramic containing barium titanate as a main component and having a positive resistance temperature characteristic, and an internal electrode electrically connected to the external electrode formed on one end surface of the ceramic body. It is preferable that the internal electrodes electrically connected to the external electrodes formed on the other end surface are alternately embedded inside the ceramic body.

【0010】本発明のチップ型電子部品の製造方法は、
前記の課題を解決するために、チップ型のセラミックス
素体の少なくとも一部表面に、ガラスコート層を厚さ
0.05μm〜5μmにて被覆し、前記セラミックス素
体の両端部表面上に、外部電極を、前記ガラスコート層
の3倍以上の平均厚さを有し、かつ、前記ガラスコート
層の軟化点以上、作業温度以下で焼付けて形成すること
を特徴としている。
The manufacturing method of the chip type electronic component of the present invention is as follows.
In order to solve the above problems, at least a part of the surface of a chip-type ceramic body is coated with a glass coating layer with a thickness of 0.05 μm to 5 μm, and both ends of the ceramic body are covered with an external material. It is characterized in that the electrode has an average thickness three times or more that of the glass coat layer and is formed by baking at a softening point of the glass coat layer or higher and a working temperature or lower.

【0011】上記構成および方法によれば、ガラスコー
ト層の厚さを、0.05μm〜5μmで、外部電極の平
均厚さを、ガラスコート層の厚さに対して3倍以上に設
定することにより、ガラスコート層を保護膜として機能
させながら、ガラスコート層のガラス浮きを回避し、か
つ、外部電極とセラミックス素体との間の抵抗を低減で
きる。よって、上記構成および方法では、歩留りを向上
できると共に、優れた電気特性を備えることが可能とな
る。
According to the above structure and method, the thickness of the glass coat layer is set to 0.05 μm to 5 μm, and the average thickness of the external electrodes is set to 3 times or more the thickness of the glass coat layer. This makes it possible to prevent the glass coating layer from floating and to reduce the resistance between the external electrode and the ceramic body while allowing the glass coating layer to function as a protective film. Therefore, with the above configuration and method, it is possible to improve the yield and provide excellent electrical characteristics.

【0012】なお、ガラスコート層の厚さが0.05μ
m未満であると、例えば外部電極に対し、めっきする際
にセラミックス素体にもめっき成長が起こり、ガラスコ
ート層は保護膜としての役割を果たさなくなる。
The glass coat layer has a thickness of 0.05 μm.
When it is less than m, for example, when the external electrode is plated, the ceramic body also undergoes plating growth, and the glass coat layer does not serve as a protective film.

【0013】また、ガラスコート層の厚さが5μmより
厚いと、ガラスコート層のガラスと、外部電極の電極材
料が混在しきれず、セラミックス素体と外部電極との間
の抵抗が大幅に増加する。また、外部電極の平均厚さ
が、ガラスコート層の3倍を下回ると、外部電極のため
の電極材料の焼付け時に、ガラスコート層にガラス浮き
という不都合が発生する。
When the thickness of the glass coat layer is thicker than 5 μm, the glass of the glass coat layer cannot be mixed with the electrode material of the external electrode, and the resistance between the ceramic body and the external electrode is significantly increased. . Further, if the average thickness of the external electrode is less than three times that of the glass coat layer, the glass coat layer may have a disadvantage that the glass floats when the electrode material for the external electrode is baked.

【0014】さらに、外部電極のための電極材料の焼付
け温度については、ガラスコート層のガラスの軟化点未
満であると、ガラスコート層のガラスと電極材料とが混
在しきれず、セラミックス素体と外部電極との間の抵抗
が大幅に増加する一方、上記ガラスの作業温度より高く
なると、電極材料の焼付け時にガラス浮きが生じてしま
う。
Further, regarding the baking temperature of the electrode material for the external electrode, if the glass of the glass coating layer is below the softening point of the glass, the glass of the glass coating layer and the electrode material cannot be completely mixed, and the ceramic body and the outside On the other hand, when the resistance between the electrode and the electrode is significantly increased, and when the temperature is higher than the working temperature of the glass, the glass floats when the electrode material is baked.

【0015】前記チップ型電子部品において、前記セラ
ミックス素体が、室温抵抗値の低減が激しく要求され
る、正の抵抗温度特性(PTC)を有する半導体セラミ
ックスからなる場合、保護層として機能するガラスコー
ト層を安定に備えたことにより、耐環境性に優れ、ま
た、外部電極とセラミックス素体との間の抵抗を低減で
きて電気特性に優れたチップ型電子部品を有するので、
優れた耐久性や電気特性を特に安定して発揮できて、有
効となる。
In the chip-type electronic component, when the ceramic body is made of semiconductor ceramics having a positive resistance temperature characteristic (PTC), which is required to be reduced in room temperature resistance value, a glass coat functioning as a protective layer. Since the layer is provided stably, it has excellent environmental resistance, and also has a chip-type electronic component that can reduce the resistance between the external electrode and the ceramic body and has excellent electrical characteristics.
It is effective because it can exhibit excellent durability and electrical characteristics in a particularly stable manner.

【0016】[0016]

【発明の実施の形態】以下に、本発明の実施の形態を図
1に基づいて説明する。本実施の形態ではチップ型電子
部品としてチップ型PTC(Positive Temperature Coe
fficient)サーミスタを例に挙げて説明する。
DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIG. In this embodiment, a chip-type electronic component is a chip-type PTC (Positive Temperature Coe).
fficient) Thermistor will be described as an example.

【0017】まず、チップ型PTCサーミスタのセラミ
ックス素体の原料として、BaCO 3 、TiO2 、Sm
2 3 の各粉体を(Ba0.9998Sm0.0002)TiO3
なるように調合した。次に、得られた粉体混合物に純水
を加えてジルコニアボールとともに16時間混合粉砕
し、乾燥後、1200℃で2時問仮焼した。
First, the ceramic of the chip type PTC thermistor
BaCO as a raw material 3, TiO2, Sm
2O3Each powder of (Ba0.9998Sm0.0002) TiO3When
It was mixed so that Next, pure water was added to the obtained powder mixture.
And crush with zirconia balls for 16 hours
Then, after drying, it was calcined at 1200 ° C. for 2 hours.

【0018】この仮焼粉に、有機バインダ、分散剤、及
び水を加えて、ジルコニアボールとともに数時間混合し
た後、グリーンシートを形成した。次に、そのグリーン
シートの一方の表面上に、内部電極となるNiペースト
を印刷法等の手法により塗布した。
An organic binder, a dispersant, and water were added to the calcined powder and mixed with zirconia balls for several hours, and then a green sheet was formed. Next, Ni paste serving as an internal electrode was applied to one surface of the green sheet by a method such as a printing method.

【0019】その後、層状に塗布された各Niペースト
がグリーンシートを介して対向し、かつ互いに接触しな
い(導通しないように離間させる)ように各グリーンシ
ートを積み重ね、さらに保護用グリーンシートを上下
(グリーンシートの厚さ方向)にそれぞれ配設して積層
体を調製した。
Thereafter, the Ni pastes applied in layers are stacked so that the Ni pastes face each other via the green sheets and are not in contact with each other (separated so as not to conduct electricity), and further the protective green sheets are vertically arranged ( A laminate was prepared by arranging the green sheets in the thickness direction of the green sheet).

【0020】上記積層体を、その厚さ方向に圧着し、一
定の寸法に切断して得た、略直方体形状の生チップを、
乾式バレル研磨を行って、生チップの角隅部及び稜線部
分の角部が丸くなった丸め済生チップを得た。
A raw chip of a substantially rectangular parallelepiped shape obtained by pressing the above-mentioned laminated body in the thickness direction thereof and cutting it into a certain size,
Dry barrel polishing was performed to obtain rounded raw chips with rounded corners and ridges.

【0021】この丸め済生チップの両端面部(各Niペ
ーストがそれぞれ露出している各端面部)に浸漬等によ
りNiペーストをそれぞれ付着させ、乾燥させて、各端
面Niをそれぞれ形成した。
Ni paste was attached to both end surfaces (each end surface where each Ni paste is exposed) of this rounded green chip by dipping or the like and dried to form each end surface Ni.

【0022】その後、内部に層状の各Niペースト、お
よび各端面Niをそれぞれ有する丸め済生チップを、1
200℃でH2 /N2 =3%の還元雰囲気にて焼成し、
図1(a)に示すように、略直方体形状の焼成積層体
(セラミックス素体)15を得た。
Then, 1 rounded green chip having each layered Ni paste and each end face Ni inside is formed.
Firing at 200 ° C. in a reducing atmosphere of H 2 / N 2 = 3%,
As shown in FIG. 1A, a fired laminated body (ceramic body) 15 having a substantially rectangular parallelepiped shape was obtained.

【0023】上記焼成積層体15は、各Niペーストに
対応した、互いに離間してくし状に入り込んで平行に対
面した各内部電極11、12および、各端面Niにそれ
ぞれ対応し、各内部電極11、12にそれぞれ電気的に
接続された各端面電極13、14を有している。言い換
えると、上記焼成積層体15は、チタン酸バリウム系の
PTCサーミスタといった電気的な機能を備えた電気回
路素子であり、通常は、外部との接続のための一対の端
子電極を備えたものである。
The firing laminate 15 corresponds to the internal electrodes 11 and 12 corresponding to the respective Ni pastes, which are spaced apart from each other and faced in parallel in a comb shape, and the respective end faces Ni. , 12 respectively having end face electrodes 13 and 14 electrically connected to them. In other words, the fired laminated body 15 is an electric circuit element having an electrical function such as a barium titanate-based PTC thermistor, and usually has a pair of terminal electrodes for external connection. is there.

【0024】次に、軟化点が、500℃〜800℃、作
業温度が800℃〜1150℃で後述の電極材料の焼付
け温度より低い軟化点かつ高い作業温度を有するガラス
を含有する水溶液に上記焼成積層体15の全体を浸漬さ
せた後、乾燥し、さらに500℃〜600℃で熱処理す
ることにより、図1(b)に示すように、厚さ約0.5
μm〜5μmのガラスコート層16を上記焼成積層体1
5の外表面上の全体に形成した、焼結チップ17を得
た。
Next, the above-mentioned baking is performed on an aqueous solution containing glass having a softening point of 500 ° C. to 800 ° C., a working temperature of 800 ° C. to 1150 ° C., and a softening point lower than the baking temperature of the electrode material described later and a high working temperature. After the entire laminated body 15 is immersed, it is dried and further heat-treated at 500 ° C. to 600 ° C. to have a thickness of about 0.5 as shown in FIG.
The glass coating layer 16 having a thickness of μm to 5 μm is formed on the fired laminate 1
Sintered chips 17 formed on the entire outer surface of No. 5 were obtained.

【0025】軟化点とは、用いたガラスが107.5 ポイ
ズ(106.5 Pa・s)単位の粘度になる温度である。
作業温度とは、用いたガラスが104 ポイズ(103
a・s)単位の粘度になる温度である。ガラスの軟化点
及び作業温度はガラスの組成により変化させた。
The softening point is the temperature at which the glass used has a viscosity of 10 7.5 poise (10 6.5 Pa · s).
The working temperature is 10 4 poise (10 3 P)
This is the temperature at which the viscosity reaches a.s). The softening point and working temperature of the glass were changed depending on the composition of the glass.

【0026】ガラス組成としては、SiO2 、Li
2 O、Na2 O、K2 Oを用いて、主にSiとアルカリ
金属元素の比により、軟化点及び作業温度を変えた。ま
た、ガラスコート層16の厚さは、ガラス含有水溶液濃
度を変化させる、あるいは、ガラス浸漬・乾燥・熱処理
を繰り返すことで、変化させた。
The glass composition is SiO 2 , Li.
Using 2 O, Na 2 O and K 2 O, the softening point and working temperature were changed mainly by the ratio of Si to the alkali metal element. Further, the thickness of the glass coat layer 16 was changed by changing the concentration of the glass-containing aqueous solution or repeating the glass immersion, drying and heat treatment.

【0027】ガラスコート層16を形成した焼結チップ
17の両端部(各端面電極13、14に対応した面上)
にAgの粉末、バインダー等からなる電極材料のペース
トを浸漬または印刷により付着させてから乾燥させ、8
00℃で焼付けを行い、図1(c)に示すように、上記
両端部に各外部電極19をそれぞれ形成した。
Both ends of the sintered chip 17 on which the glass coat layer 16 is formed (on the surfaces corresponding to the end electrodes 13 and 14)
The electrode material paste consisting of Ag powder, binder, etc. is applied by dipping or printing and then dried.
Baking was performed at 00 ° C. to form the external electrodes 19 on both ends, as shown in FIG.

【0028】この焼付け時に、各外部電極19と各端面
電極13、14との間では、電極材料と、ガラスコート
層16のガラスとが互いに入り込んで混在した状態にな
り、各端面電極13、14上において、上記ガラスコー
ト層16が、島状ガラス部16aとなるので、各外部電
極19の電極膜と各端面電極13、14とがそれぞれ互
いに接触・導通されるようになる。
At the time of this baking, the electrode material and the glass of the glass coat layer 16 are intermingled and mixed between each external electrode 19 and each end surface electrode 13, 14 and each end surface electrode 13, 14 is mixed. In the above, since the glass coat layer 16 becomes the island-shaped glass portion 16a, the electrode films of the external electrodes 19 and the end face electrodes 13 and 14 come into contact with each other and are electrically connected to each other.

【0029】また、このとき、焼付け温度が、ガラスコ
ート層16に用いたガラスの軟化点以上、かつ作業温度
以下であるので、焼結チップ17の電極材料のペースト
の形成部位以外の表面上には、ガラスコート層16が隙
間無く覆うように保護層として形成されている。
At this time, since the baking temperature is not less than the softening point of the glass used for the glass coat layer 16 and not more than the working temperature, the surface of the sintered tip 17 other than the electrode material paste forming portion is not covered. Is formed as a protective layer so that the glass coat layer 16 can be covered without gaps.

【0030】この後、通常の方法により、上記各外部電
極19上に、Niめっき、Snめっきを順次施した金属
めっき層20を形成して、丸め加工も施された本実施の
形態に係るチップ型PTCサーミスタ18を得た。
Thereafter, a metal plating layer 20 which is sequentially plated with Ni and Sn is formed on each of the external electrodes 19 by a normal method, and the chip according to the present embodiment is also rounded. A type PTC thermistor 18 was obtained.

【0031】前記ガラスコート層と外部電極の厚さ、及
びガラスコート層の軟化点及び作業温度を変化させ、得
られた各チップ型PTCサーミスタについて、外観評
価、室温抵抗測定を行った。結果を表1に示す。
The thickness of the glass coat layer and the external electrode, the softening point of the glass coat layer and the working temperature were changed, and the appearance of each chip type PTC thermistor was evaluated and the room temperature resistance was measured. The results are shown in Table 1.

【0032】[0032]

【表1】 [Table 1]

【0033】表1において、*を付記したNo.7〜1
1は、本発明の請求の範囲外(比較例)である。No.
7、8は、ガラスコート層の厚さが、本発明の請求の範
囲外であり、No.9は、外部電極の厚さが、本発明の
請求の範囲外であり、No.10、11は電極材料焼付
け温度が、本発明の請求の範囲外である。
In Table 1, No. marked with * is added. 7-1
1 is outside the scope of claims of the present invention (comparative example). No.
In Nos. 7 and 8, the thickness of the glass coat layer was outside the scope of the claims of the present invention, and No. In No. 9, the thickness of the external electrode is outside the scope of the claims of the present invention, and No. 9 The electrode material baking temperatures of 10 and 11 are outside the scope of the claims of the present invention.

【0034】表1から明らかなように、ガラスコート層
および外部電極の厚さと、電極材料の焼付け温度が本発
明の請求の範囲内であるNo.1〜6(実施例)は、め
っき時のセラミックス素体へのめっき成長がなく、電極
材料焼付け時のガラス浮きもなく、室温抵抗が低いとい
う優れた各特性を備えたものである。
As is clear from Table 1, the thicknesses of the glass coating layer and the external electrode and the baking temperature of the electrode material are within the scope of the claims of the present invention. Nos. 1 to 6 (Examples) have excellent properties such as no plating growth on the ceramic body during plating, no glass float during baking of the electrode material, and low room temperature resistance.

【0035】一方、ガラスコート層の厚さが本発明の請
求の範囲外のチップ型PTCサーミスタ、No.7、8
は、No.7では、めっき時にセラミックス素体へのめ
っき成長が生じ、No.8では、室温抵抗が増加した。
On the other hand, the chip-type PTC thermistor having the thickness of the glass coat layer outside the scope of the claims of the present invention, No. 7, 8
No. In No. 7, plating growth on the ceramic body occurred during plating, and No. 7 In 8, the room temperature resistance increased.

【0036】また、外部電極の厚さが本発明の請求の範
囲外のチップ型PTCサーミスタ、No.9は、ガラス
浮きが観察され、室温抵抗も大幅に増加している。ま
た、電極材料の焼付け温度が本発明の請求の範囲外のチ
ップ型PTCサーミスタ、No.10、11は、No.
10では、外部電極とセラミックス素体の端面電極との
導通がとれず、室温抵抗の大幅な増加が見られ、No.
11では、ガラス浮きが観察され、室温抵抗も大幅に増
加している。
Further, the chip type PTC thermistor having the thickness of the external electrode outside the scope of the claims of the present invention, No. In No. 9, glass float was observed, and the room temperature resistance was significantly increased. In addition, a chip type PTC thermistor having a baking temperature of the electrode material outside the scope of the claims of the present invention, No. Nos. 10 and 11 are Nos.
In No. 10, the electrical connection between the external electrode and the end face electrode of the ceramic body was not established, and the room temperature resistance was significantly increased.
In No. 11, glass float was observed, and the room temperature resistance was also significantly increased.

【0037】なお、本発明に係るチップ型電子部品は、
前記実施の形態や実施例に限定されるものではなく、そ
の要旨の範囲内で種々に変更することができ、前記PT
Cサーミスタ以外、特に、積層コンデンサ、バリスタ、
フェライト等のチップ型のセラミックス電子部品にも適
用することができる。
The chip-type electronic component according to the present invention is
The present invention is not limited to the above-mentioned embodiments and examples, but can be variously modified within the scope of the gist thereof.
Other than C thermistors, especially multilayer capacitors, varistors,
It can also be applied to chip-type ceramic electronic components such as ferrite.

【0038】また、このようなチップ型電子部品の大き
さ(各寸法)については、特に限定されないが、20m
m(長さ)×20mm(幅)×10mm(高さ)以下が
好ましく、10mm(長さ)×10mm(幅)×5mm
(高さ)以下のものがより好ましい。さらに、外部電極
19の厚さについては、50μm以下が望ましい。外部
電極の厚さを50μm超に形成しても特に効果がなく不
経済である。
The size (dimensions) of such a chip-type electronic component is not particularly limited, but is 20 m.
m (length) x 20 mm (width) x 10 mm (height) or less is preferable, and 10 mm (length) x 10 mm (width) x 5 mm
(Height) or less is more preferable. Furthermore, the thickness of the external electrode 19 is preferably 50 μm or less. Even if the thickness of the external electrode is more than 50 μm, there is no particular effect and it is uneconomical.

【0039】本発明に係るチップ型電子部品、特にチッ
プ型PTCサーミスタは、例えば過電流防止装置、携帯
電話等の通信装置といった電子装置に好適に用いること
ができる。上記電子装置においては、耐環境性といった
耐久性に優れ、かつ、各端面電極13、14と、それら
にそれぞれ対応する各外部電極19との間が低抵抗とい
った改善された電気特性を備えることが可能となる。
The chip-type electronic component according to the present invention, particularly the chip-type PTC thermistor, can be suitably used for an electronic device such as an overcurrent prevention device and a communication device such as a mobile phone. The electronic device may have excellent durability such as environment resistance, and may have improved electrical characteristics such as low resistance between each of the end face electrodes 13 and 14 and each of the external electrodes 19 corresponding thereto. It will be possible.

【0040】[0040]

【発明の効果】本発明のチップ型電子部品は、以上のよ
うに、セラミックス素体の少なくとも一部表面に被覆さ
れた厚さ0.05μm〜5μmのガラスコート層と、セ
ラミックス素体の両端部表面上に、前記ガラスコート層
の3倍以上の平均厚さを備え、かつ、前記ガラスコート
層の軟化点以上、作業温度以下の焼付けにより形成され
る物性を備えた外部電極とを有する構成である。
As described above, the chip-type electronic component of the present invention has a glass coating layer having a thickness of 0.05 to 5 μm coated on at least a part of the surface of the ceramic body and both end portions of the ceramic body. An external electrode having an average thickness three times or more that of the glass coat layer on the surface and having physical properties formed by baking at a softening point of the glass coat layer or higher and a working temperature or lower. is there.

【0041】本発明のチップ型電子部品の製造方法は、
以上のように、チップ型のセラミックス素体の少なくと
も一部表面に、ガラスコート層を厚さ0.05μm〜5
μmにて被覆し、前記セラミックス素体の両端部表面上
に、外部電極を、前記ガラスコート層の3倍以上の平均
厚さを有し、かつ、前記ガラスコート層の軟化点以上、
作業温度以下で焼付けて形成する方法である。
The manufacturing method of the chip type electronic component of the present invention is as follows.
As described above, the glass coat layer having a thickness of 0.05 μm to 5 is formed on at least a part of the surface of the chip type ceramic body.
μm, and the external electrodes on both end surfaces of the ceramic body have an average thickness of 3 times or more that of the glass coat layer, and a softening point of the glass coat layer or more,
This is a method of baking at a working temperature or lower.

【0042】それゆえ、上記構成および方法は、外部電
極を形成するための電極ペースト焼付け時にガラスコー
ト層が外部電極の表面に浮き上がったり、セラミックス
素体同士またはセラミックス素体と焼成治具との張り付
いたりすることが防止されると共に、電極ペースト焼付
け後も、外部電極とセラミックス素体との間の導通接続
を安定化できて、歩留りの向上と優れた電気特性を発揮
できるという効果を奏する。
Therefore, in the above-described structure and method, the glass coat layer floats up on the surface of the external electrode during the baking of the electrode paste for forming the external electrode, or the ceramic bodies are adhered to each other or the ceramic body and the firing jig are attached to each other. Adhesion is prevented, and the conductive connection between the external electrode and the ceramic body can be stabilized even after the electrode paste is baked, so that the yield can be improved and excellent electrical characteristics can be exhibited.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)ないし(c)は、本発明のチップ型電子
部品およびその製造方法を示す各概略模式図である。
FIG. 1A to FIG. 1C are schematic diagrams showing a chip-type electronic component and a method for manufacturing the same according to the present invention.

【符号の説明】[Explanation of symbols]

11、12 内部電極 13、14 端面電極 15 焼成積層体(セラミックス素体) 16 ガラスコート層 17 焼結チップ 18 チップ型積層PTCサーミスタ 19 外部電極 20 金属めっき層 11, 12 Internal electrode 13, 14 Edge electrode 15 Fired laminated body (ceramic body) 16 Glass coat layer 17 Sintered chips 18 chip type laminated PTC thermistor 19 External electrode 20 Metal plating layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】チップ型のセラミックス素体と、 上記セラミックス素体の少なくとも一部表面に被覆され
た厚さ0.05μm〜5μmのガラスコート層と、 前記セラミックス素体の両端部表面上に、前記ガラスコ
ート層の3倍以上の平均厚さを備え、かつ、前記ガラス
コート層の軟化点以上、作業温度以下の焼付けにより形
成される物性を備えた外部電極とを有することを特徴と
するチップ型電子部品。
1. A chip-type ceramic body, a glass coat layer having a thickness of 0.05 μm to 5 μm, which covers at least a part of the surface of the ceramic body, and both end surfaces of the ceramic body, A chip having an average thickness three times or more that of the glass coat layer, and an external electrode having physical properties formed by baking at a softening point of the glass coat layer or higher and a working temperature or lower. Mold electronic components.
【請求項2】前記セラミックス素体は、チタン酸バリウ
ムを主成分とする正の抵抗温度特性を有する半導体セラ
ミックスからなり、一方端部表面に形成された前記外部
電極に電気的に接続される内部電極と、他方端部表面に
形成された前記外部電極に電気的に接続される内部電極
とが、前記セラミックス素体内部に交互に埋設されてな
ることを特徴とする請求項1記載のチップ型電子部品。
2. The ceramic body is made of a semiconductor ceramic containing barium titanate as a main component and having a positive resistance temperature characteristic, and is electrically connected to the external electrode formed on one end surface. 2. The chip type according to claim 1, wherein electrodes and internal electrodes electrically connected to the external electrodes formed on the other end surface are alternately embedded inside the ceramic body. Electronic components.
【請求項3】チップ型のセラミックス素体の少なくとも
一部表面に、ガラスコート層を厚さ0.05μm〜5μ
mにて被覆し、 前記セラミックス素体の両端部表面上に、外部電極を、
前記ガラスコート層の3倍以上の平均厚さを有し、か
つ、前記ガラスコート層の軟化点以上、作業温度以下で
焼付けて形成することを特徴とするチップ型電子部品の
製造方法。
3. A glass coat layer having a thickness of 0.05 .mu.m to 5 .mu.m on at least a part of the surface of the chip type ceramic body.
m, and external electrodes are provided on the surfaces of both end portions of the ceramic body.
A method for manufacturing a chip-type electronic component, which has an average thickness three times or more that of the glass coat layer, and is formed by baking at a softening point of the glass coat layer or higher and a working temperature or lower.
JP2001350645A 2001-11-15 2001-11-15 Chip element component and its manufacturing method Pending JP2003151805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2003151805A true JP2003151805A (en) 2003-05-23

Family

ID=19163103

Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP2003151805A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004015016A (en) * 2002-06-11 2004-01-15 Murata Mfg Co Ltd Electronic chip component and its manufacturing method
JP2004128488A (en) * 2002-09-10 2004-04-22 Murata Mfg Co Ltd Chip-type electronic component
JP2012212931A (en) * 2006-04-18 2012-11-01 Epcos Ag Electric ptc thermistor component and manufacturing method therefor
US20160276104A1 (en) * 2015-03-20 2016-09-22 Murata Manufacturing Co., Ltd. Electronic component and method for producing the same
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WO2025109818A1 (en) * 2023-11-22 2025-05-30 株式会社村田製作所 Multilayer ceramic capacitor
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US12334235B2 (en) 2021-12-21 2025-06-17 Panasonic Intellectual Property Management Co., Ltd. Multilayer varistor
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004015016A (en) * 2002-06-11 2004-01-15 Murata Mfg Co Ltd Electronic chip component and its manufacturing method
JP2004128488A (en) * 2002-09-10 2004-04-22 Murata Mfg Co Ltd Chip-type electronic component
JP2012212931A (en) * 2006-04-18 2012-11-01 Epcos Ag Electric ptc thermistor component and manufacturing method therefor
US20160276104A1 (en) * 2015-03-20 2016-09-22 Murata Manufacturing Co., Ltd. Electronic component and method for producing the same
US10418191B2 (en) * 2015-03-20 2019-09-17 Murata Manufacturing Co., Ltd. Electronic component with outer electrode including sintered layers, glass layer, and metal layers and method for producing the same
US12400774B2 (en) 2021-11-11 2025-08-26 Panasonic Intellectual Property Management Co., Ltd. Multilayer varistor and method of manufacturing the same
US12334235B2 (en) 2021-12-21 2025-06-17 Panasonic Intellectual Property Management Co., Ltd. Multilayer varistor
WO2024100941A1 (en) * 2022-11-11 2024-05-16 株式会社村田製作所 Electronic component
JP7529183B1 (en) * 2022-11-11 2024-08-06 株式会社村田製作所 Electronic Components
WO2025109818A1 (en) * 2023-11-22 2025-05-30 株式会社村田製作所 Multilayer ceramic capacitor
WO2025109892A1 (en) * 2023-11-22 2025-05-30 株式会社村田製作所 Multilayer ceramic capacitor

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