JP2003158246A - Storage element and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a ferroelectric memory element capable of preventing deterioration in characteristics of a ferroelectric film, improving reliability, and achieving high integration, and a method of manufacturing the same. SOLUTION: A field effect transistor 19 is provided on a silicon substrate 1, and a plug 4 provided in a contact hole 18 formed in an interlayer insulating layer 6a on the silicon substrate 1 is provided.
To the first insulating film 7 on the interlayer insulating layer 6a.
The lower electrode 8 is buried in the opening 9a of the second insulating film 14, and the ferroelectric film 10 is formed on the second insulating film 14 and the lower electrode 8.
Is formed thereon, and the upper electrode 11 is further formed thereon to form the capacitor 21. The second insulating film 14 has a hydrogen barrier property and has the same processability as the lower electrode 8 when the lower electrode 8 is processed. A ferroelectric memory element 20 in which the lower electrode 8 and the second insulating film 14 are substantially on the same plane.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory element having a capacitor structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, a memory element using a ferroelectric film is
JP-A-2000-164817, JP-A-2000-174
No. 224 and Japanese Patent Laid-Open No. 2000-183297. For example, a memory cell having the configuration shown in FIG. 16 is shown.

In this ferroelectric memory element 70a, a charge transfer consisting of a gate electrode 55, a source region 52 and a drain region 53, a conductive plug / source electrode 54, a drain electrode 72, etc. is formed on a silicon substrate 51 having a predetermined thickness. An insulated gate field effect transistor 69 is provided for the source region 5 in the conductive plug 54 embedded in the contact hole 68 formed in the interlayer insulating layer 56a having a predetermined thickness.
2 is connected.

Then, a lower electrode 58, a ferroelectric film 60 and an upper electrode 61 having a predetermined thickness are sequentially formed on the interlayer insulating layer 56a to form a capacitor 71a connected in series with a field effect transistor 69. There is.

Further, a barrier film 65a having a predetermined thickness and an interlayer insulating film 62 are formed on the capacitor 71a, the wiring layer 63 is connected to the upper electrode 61 through the opening of the insulating film, and the entire insulating layer is formed. It is covered with 56b.

In this ferroelectric memory element 70a,
In order to easily form the capacitor 71a with a laminated structure of a plurality of layers, the area of the lower electrode 58 is increased, and the areas of the ferroelectric film 60 and the upper electrode 61 laminated on the lower electrode 58 are gradually decreased, so to speak, a so-called hidantan type. It is structured.

However, since the area of the lower electrode 58 is larger than the area of the upper electrode 61 and the like laminated on the lower electrode 58, the size of the memory cell is determined by the area of the lower electrode 58. I cannot increase my degree. In addition, the large area of the lower electrode 58 is accompanied by an increase in parasitic capacitance, which easily causes a problem such as a decrease in driving speed.

Therefore, it is possible to increase the degree of integration of the ferroelectric memory element (and reduce the parasitic capacitance) as shown in FIG.
A ferroelectric memory element as shown in (1) is known.

According to the ferroelectric memory element 70b, the insulating film 57 is formed on the interlayer insulating layer 56a, and the lower electrode 58 is embedded in the opening formed in the insulating film. Since the ferroelectric film 60 is formed from the electrode 58 to the insulating film 57, the size of the lower electrode 58 can be reduced, and the memory cell size can be reduced to improve the integration degree. Since the area is small, the parasitic capacitance can be reduced. This storage element 70
The manufacturing method of b will be described below.

First, as shown in FIG. 18A, a source region 52, a drain region 53, a gate insulating film 73 and a gate electrode 55 are formed on a silicon substrate 51 by a conventional method, and an interlayer insulating layer 56a is further formed. The source electrode / conductive plug 54 and the drain electrode 72 are formed in the contact hole 68 of the insulated gate field effect transistor 69 (MOSFET: Metal Oxide Semicond
uctor Field Effect Transistor).

Next, as shown in FIG. 18B, an insulating film 57 made of SiO ₂ is formed to a predetermined thickness on the interlayer insulating layer 56a. The insulating film 57 is formed, for example, by CVD (Chemical Vapor) using a gas such as monosilane (SiH ₄ ).
por Deposition: Chemical vapor deposition: The same shall apply hereinafter).

Next, as shown in FIG. 18C, an opening 59a having a predetermined size is formed in the insulating film 57 on the conductive plug 54 on the source region 52 side by photolithography.
Is formed by a dry etching method such as RIE (Reactive Ion Etching, reactive ion etching: hereinafter the same) method and an ion milling method, or a wet etching method using an acid or the like. Here, the size of the opening 59a (that is,
The size of the lower electrode 58 described later) is the lower electrode 5 of FIG.
Keep it smaller than size 8.

Next, as shown in FIG. 19D, PVD (Physical Vapor Deposition) such as sputtering and vapor deposition is formed on the insulating film 57 including the opening 59a. The lower electrode material 58A made of Pt is formed to a predetermined thickness by a method, a plating method, an electroless plating method, or the like.

Next, as shown in FIG. 19 (e), an unnecessary portion of the conductive film 58A other than the opening 59a is covered with an insulating film 57.
CMP (Chem (Chem
icalMechanical Polishing, chemical mechanical polishing: the same shall apply hereinafter). As a result, the lower electrode 58 is embedded in the opening 59a of the insulating film 57 so as to form a substantially flat surface.

Next, as shown in FIG. 19F, for example, SBT is formed on the entire upper surfaces of the insulating film 57 and the lower electrode 58.
A ferroelectric film 60 made of (strontium bismastantal: hereinafter the same) is formed by a sol-gel method, a sputtering method or C
It is formed to a predetermined thickness by the VD method or the like.

Next, as shown in FIG. 20G, an upper electrode material 61A made of, for example, Pt is formed on the ferroelectric film 60.
Is formed to a predetermined thickness by a PVD method such as a sputtering method or a vapor deposition method or a plating method.

Next, as shown in FIG. 20H, unnecessary portions of the upper electrode material 61A and the ferroelectric film 60 are sequentially and selectively removed by a dry etching method such as RIE to form the upper electrode 61 and The ferroelectric film 60 is formed in a predetermined pattern. At this time, the size of the upper electrode 61 is made substantially the same as that of the lower electrode 58, and the size of the ferroelectric film 60 is made larger than the sizes of the upper electrode 61 and the lower electrode 58.

Next, as shown in FIG. 20 (i), A is formed so as to cover the upper electrode 61, the ferroelectric film 60 and the insulating film 57.
A barrier film 65a made of l ₂ O ₃ is formed to a predetermined thickness,
Further, the insulating layer 62 is formed thereon with a predetermined thickness by a PVD method such as a sputtering method or an evaporation method, or a reduced pressure, plasma or atmospheric pressure CVD method.

Next, as shown in FIG. 21J, the insulating film 6 is formed on the upper electrode 61 by photolithography.
2 and a part of the barrier film 65a are removed to form the opening 59b.
To form.

Next, as shown in FIG. 21K, the wiring layer 63 is deposited in a predetermined pattern on the opening 59b, and then,
As shown in FIG. 17, an insulating layer 56b having a predetermined thickness is formed on the wiring layer 63 and the insulating film 62, and the upper electrode 61-
The charge storage capacitor 71b including the ferroelectric film 60 and the lower electrode 58 is the field effect transistor 6 for charge transfer.
A ferroelectric memory element 70b having a memory cell structure connected to 9 is manufactured.

According to the ferroelectric memory element 70b thus obtained, the size of the lower electrode 58 can be reduced by embedding the lower electrode 58 of the capacitor 71b in the insulating film 57. The cell size can be reduced to increase the degree of integration. Moreover, since the area of the lower electrode 58 is small, the parasitic capacitance can be reduced.

[0022]

In the ferroelectric memory element 70b shown in FIG. 17, the lower electrode 58 is replaced by the insulating film 57.
However, since the ferroelectric film 60 protrudes from the upper surface of the lower electrode 58 to the upper surface of the insulating film 57 (especially when it protrudes largely), the ferroelectric film 60 is embedded in the insulating film 57 during the CVD shown in FIG. The hydrogen taken in and remaining in the ferroelectric film 60 penetrates into the ferroelectric film 60 from the interface with the ferroelectric film 60, so that the characteristics of the ferroelectric film 60 are easily deteriorated. This is because even if the lower electrode 58 is made of a material having a good barrier property against hydrogen gas, the ferroelectric film 60 is formed on the lower electrode 58.
Since it is in direct contact with the insulating film 57 in the region where there is no, it occurs inevitably.

In order to prevent this, the size of the ferroelectric film 60 may be made equal to or smaller than that of the lower electrode 58, but this reduces the effective area of the capacitor and is not suitable. is there. Further, since the memory cell size is defined by the size of the lower electrode 58, the degree of freedom in design and design is poor, and as a result, the degree of integration cannot be improved.

Further, as shown in FIGS. 19D to 19E, a part of the conductive film 58A to be the lower electrode is polished and removed by the CMP method, and the lower electrode 58 is opened in the insulating film 57. In the step of forming the structure embedded in the portion 59a, the insulating film 57 is formed more than Pt which is the material of the conductive film 58A.
Since the hardness of SiO ₂ which is the material of the above is small (due to the difference in polishing rate), the insulating film 57 is excessively removed by polishing more than the lower electrode material 58A during polishing. As a result, as shown in FIG. 22, a large step 74 of, for example, 100 to 150 nm is likely to occur between the lower electrode 58 and the insulating film 57.

Therefore, the insulating film 57 is formed from above the lower electrode 58.
In the step of forming the ferroelectric film 60 on the upper side, for example, when heat treatment is performed at 700 ° C. to 750 ° C. when the sol-gel method is used, this heat treatment causes voids 75 in the step 74, and the lower electrode 58 and ferroelectric film 60
Due to poor adhesion with the wiring layer 63 (see FIG. 21 (k))
Dielectric breakdown is likely to occur when the device is operated as a ferroelectric memory element after the formation of.

The present invention has been made in view of the above situation, and an object thereof is to prevent deterioration of characteristics of a dielectric film, improve reliability, and achieve high integration. It is to provide the manufacturing method.

[0027]

That is, according to the present invention, a charge transfer element is provided on a semiconductor substrate, and an interlayer insulating layer is formed on the semiconductor substrate so as to cover the charge transfer element. A conductive material connected to the charge transfer element is embedded in the formed opening, an insulating film is provided on the interlayer insulating layer, and an opening formed in the insulating film is connected to the conductive material. One electrode is embedded, a dielectric film is formed on the first electrode and the insulating film, and the insulating film is
At least the dielectric film side has a protective layer having at least one physical property of having hydrogen barrier resistance and having workability equivalent to this when processing the first electrode, The first electrode and the insulating film are substantially flush with each other, a second electrode is formed on the dielectric film, and the charge transfer is performed by the first electrode, the dielectric film, and the second electrode. The present invention relates to a storage element including a capacitor connected to the element.

The present invention also provides a step of forming an interlayer insulating layer on the semiconductor substrate provided with the charge transfer element so as to cover the charge transfer element, and the charge transfer element in the opening formed in the interlayer insulating layer. Burying the conductive material connected to
A step of providing an insulating film on the interlayer insulating layer, and embedding a first electrode connected to the conductive material in an opening formed in the insulating film, and during the embedding, depositing on the interlayer insulating layer. The constituent material of at least one of the first electrode and the insulating film is removed from the surface side, or the constituent material of the first electrode is selectively applied to the opening of the insulating film to form the insulating film. A step of embedding the first electrode in the opening so as to be substantially flush with the insulating film, a step of forming a dielectric film on the first electrode and the insulating film, and at least the dielectric film of the insulating film. Forming a protective layer on the body film side, which has at least one physical property of having a hydrogen barrier resistance and having workability equivalent to that of the first electrode during processing; And a step of forming a second electrode thereon, A serial first electrode and said dielectric film by said second electrode constitute a capacitor connected to said charge transfer device, a manufacturing method of the memory element is also intended to provide.

According to the present invention, the insulating film having the first electrode buried in the opening has the protective layer having hydrogen barrier resistance at least on the side of the dielectric film. The protective layer can effectively prevent hydrogen remaining in the insulating film from penetrating into the dielectric film, and prevent deterioration of the characteristics of the dielectric film due to the penetration of hydrogen.

Further, since the insulating film has the protective layer having a workability equivalent to that of the first electrode at the time of processing the first electrode, the insulating film has at least the dielectric film side. There is no difference in the amount of processing with the insulating film (specifically, the protective layer), and the first electrode and the insulating film (specifically, the protective layer) are substantially flush with each other. ,
As a result, no step is formed between the first electrode and the insulating film, and dielectric breakdown due to poor adhesion is less likely to occur.

Further, since the dielectric film is formed on the first electrode and the insulating film, the effective area of the capacitor is sufficient and the memory cell size is restricted by the size of the first electrode. You can increase the degree of freedom without being
High integration can be achieved.

[0032]

According to the present invention, a field effect transistor for charge transfer is provided on the semiconductor substrate, and the interlayer insulating layer is formed on the semiconductor substrate so as to cover the field effect transistor. The conductive material connected to the field effect transistor is embedded in the opening formed in the insulating layer, and the electric field is formed by the first electrode, the ferroelectric film as the dielectric film, and the second electrode. A capacitor connected to the effect transistor is formed, and these transistors and capacitors are a dynamic random access memory (DRAM).
It is preferable to configure the memory cell of

Further, the insulating film may have the protective layer on the side of the dielectric film, or may be composed of only the protective layer. For example, the insulating film may be composed of a laminated film of the protective layer and a silicon oxide layer, a laminated film of the protective layer, a silicon oxide layer and a silicon nitride layer, or only the protective layer. .

In order to sufficiently secure the hydrogen barrier resistance, the ratio of the thickness of the protective layer to the total thickness of the insulating film (the former / the latter) is 6/1 to 1/1. Is preferred.

The protective layer is made of Al ₂ O ₃ , ZrO ₂ , Y ₂
At least 1 selected from O ₃ and lanthanoid oxides
It is preferably composed of seeds.

Further, it is preferable that a protective film is formed to cover the second electrode and the dielectric film in order to prevent hydrogen from penetrating from the insulating layer on the second electrode.

A plurality of storage elements according to claim 1 are arranged side by side, the dielectric film is formed in common with these storage elements, and the second electrode of each storage element is formed on the dielectric film. If the storage element is provided respectively, since it is not necessary to process the dielectric film for each storage element, it is possible to reduce the damage to the dielectric film that occurs during processing, there is no influence of processing residues, Further, the degree of integration of storage elements or memory cells is improved, and various memory operations are possible.

Further, the constituent material of the first electrode is deposited on the surface including the opening of the insulating film formed on the interlayer insulating layer, and the constituent material is mainly removed from the surface by the removing treatment. It is preferable to embed the first electrode in the opening.

Further, the first electrode is patterned on the interlayer insulating layer, the constituent material of the insulating film is deposited on the surface including the pattern, and the constituent material is mainly removed from the surface by the removing treatment. Then, the first electrode can be embedded in the opening.

The first electrode may be formed by plating the constituent material of the first electrode by electroless plating or the like in the opening of the insulating film formed on the interlayer insulating layer.

Further, it is preferable that the removal treatment is performed by chemical mechanical polishing, grinding or etch back.

Preferred embodiments of the present invention will be described below with reference to the drawings.

First Embodiment A ferroelectric memory element according to the present embodiment is shown in FIG.
As shown in FIG. 3, the insulating film in which the lower electrode 8 of the capacitor 21 is embedded is a first insulating film 7 made of silicon oxide (SiO ₂ ) and a second insulating film 14 as a protective layer of Al ₂ O ₃ or the like.
And a second insulating film 14 is in contact with the ferroelectric film 10. Other configurations are the same as those of the conventional example shown in FIG. 17, and corresponding parts are shown in FIG. 1 by subtracting the numeral 50 from the reference numerals in FIG.

This ferroelectric memory element 20 will be described by its manufacturing process.

First, as shown in FIG. 2A, a source region 2, a drain region 3, a gate insulating film 23, and a gate electrode 5 are formed on a silicon substrate 1 by a conventional method, and an interlayer insulating layer 6a is formed. The source electrode / conductive plug 4 is formed in the contact hole 18 and the drain electrode 22 is formed, and the insulated gate field effect transistor 1 is formed.
9 (MOSFET).

Next, as shown in FIG. 2B, a first insulating film 7 made of SiO ₂ is formed to a predetermined thickness on the interlayer insulating layer 6a. The first insulating film 7 is formed by, for example, atmospheric pressure using a gas such as monosilane (SiH ₄ ) or reduced pressure, plasma CVD, or the like, but may be formed by a PVD method such as a sputtering method or an evaporation method.

Next, as shown in FIG. 2C, a second insulating film 14 made of alumina (Al ₂ O ₃ ) is formed on the first insulating film 7 by a PVD method such as a sputtering method or a vapor deposition method. It is formed to a predetermined thickness.

Here, as the material of the second insulating film 14,
First, hydrogen gas generated in the first insulating film 7 by a chemical reaction when monosilane (SiH ₄ ) gas is used when the first insulating film 7 is formed by CVD and remaining in the first insulating film 7 is used as the ferroelectric film 10.
It must exhibit a hydrogen barrier resistance so that it does not enter into.

Secondly, since it is required that the lower electrode 8 and the second insulating film 14 are substantially flush with each other in the removing step by CMP or the like which will be described later, the polishing rate or the etching rate difference between them is required. That is, that is, that acts as a stopper for preventing the first insulating film 7 from being polished or etched.

Thirdly, the crystallization of the ferroelectric film 10 is favorably promoted when the ferroelectric film 10 is formed, which will be described later.

Alumina (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), yttrium oxide (Y
₂ O ₃ ), lanthanoid (rare earth element) oxides such as lanthanum, cerium, praseodymium, and neodymium, and mixtures thereof.

The total thickness (total thickness) of the first insulating film 7 and the second insulating film 14 is almost the same as the lower electrode 8 (200 mm).
The ratio of the thickness of the second insulating film 14 to the total thickness (former / latter) is preferably 6/1 to 1/1 (first insulating film 7 / second insulating film). The thickness ratio of the film 14 is preferably 5/1 to 0, and for example, the total thickness is 200 to
When the thickness is 300 nm, the second insulating film 14 is preferably 50 nm or more). Outside this range, the second insulating film 14
If the thickness is too thin, the above hydrogen barrier resistance becomes poor or disappears. Therefore, it is preferable to set the thickness to 1/6 or more (for example, 50 nm or more) of the total thickness. However, the entire thickness may be occupied by the second insulating film 14. However, in order to prevent the influence of the base (invasion of hydrogen or ions from the insulating layer 6a), a silicon nitride film (Si ₃
N ₄ etc.) may be provided.

In the present embodiment, for example, the first insulating film 7
Is 200 nm, and the thickness of the second insulating film 14 is 100 n.
m.

Next, as shown in FIG. 3D, the first insulating film 7 and the second insulating film 14 on the plug 4 on the source region 2 side.
First, the opening 9a is formed in a predetermined size by a dry etching method such as an RIE method and an ion milling method, or a wet etching method using an acid so that the upper surface of the plug 4 is exposed. The size of the opening 9a (that is, the size of the lower electrode 8) is smaller than the size of the lower electrode 58 shown in FIG.

Next, as shown in FIG. 3E, the opening 9
P is formed on the second insulating film 14 containing a by, for example, a PVD method such as a sputtering method and an evaporation method, or an electroless plating method.
A conductive film (lower electrode material) 8A made of t is formed.

Next, as shown in FIG. 3 (f), CMP
The conductive film 8A is polished or ground by a (chemical mechanical polishing) method to remove unnecessary portions of the conductive film 8A in the upper portion other than the opening 9a so as to be substantially flush with the upper surface of the second insulating film 14. Then, the lower electrode 8 is embedded in the opening 9a. Instead of this CMP method, an etch back method by dry etching may be adopted.

At the time of this CMP or etch back, since the polishing or etching rate of the second insulating film 14 is equal to the polishing or etching rate of the conductive film (lower electrode material) 8A, the second
The insulating film 14 acts as a stopper for polishing or etching the first insulating film 7, and at the end of this step, the second insulating film 14 is removed in the same manner as the conductive film 8A, and is almost flush with the upper surface of the second insulating film 14. The lower electrode 8 having a flat buried structure on the same surface can be obtained.

For example, when Pt is used for the lower electrode 8 and Al ₂ O ₃ is used for the second insulating film 14, the second insulating film 14 and the lower electrode 8 are substantially flat with no step. It almost disappears.

Next, as shown in FIG. 4G, for example, SBT is formed on the entire upper surfaces of the second insulating film 14 and the lower electrode 8.
A ferroelectric film 10 made of (strontium bismastantal) is formed to a predetermined thickness by a sol-gel method, a sputtering method, a CVD method or the like.

Next, as shown in FIG. 4H, an upper electrode 11 made of, for example, Pt is formed on the ferroelectric film 10 to a predetermined thickness by a PVD method such as a sputtering method or a vapor deposition method or a plating method. To form.

Next, as shown in FIG. 4I, unnecessary portions of the upper electrode material 11A are removed by dry etching such as RIE to form the upper electrode 11. At this time, the size of the upper electrode 11 is made substantially the same as the size of the lower electrode 8.

Next, as shown in FIG. 5J, unnecessary portions of the ferroelectric film 10 are removed by a dry etching method such as RIE to form a ferroelectric film 10 having a predetermined pattern.
At this time, the size of the ferroelectric film 10 is larger than the sizes of the upper electrode 11 and the lower electrode 8.

Next, as shown in FIG. 5 (k), Al of the same material as the second insulating film 14 is formed so as to cover the upper electrode 11, the ferroelectric film 10 and a part of the second insulating film 14. _A barrier film 15a made of ₂ O ₃ or the like is formed to have a predetermined thickness.

The barrier film 15a has a function of preventing residual hydrogen in the insulating film 12 made of SiO ₂ formed by the CVD method described later from entering the ferroelectric film 10 and deteriorating the physical properties. In addition, bismuth evaporates from strontium bismuth tantalum, which is a constituent material of the ferroelectric film 10, by heat when the upper electrode 8, the insulating film 12 and the like are formed on the ferroelectric film 10, and the ferroelectric film 10 is formed. It also has the effect of preventing changes in the characteristics of.

Next, as shown in FIG. 5 (l), an insulating film 12 made of SiO ₂ is formed on the barrier film 15a and the second insulating film 14 under reduced pressure, plasma or atmospheric pressure CVD method, or sputtering method. Alternatively, it is formed to a predetermined thickness by a PVD method such as a vapor deposition method.

Next, as shown in FIG. 6 (m), the insulating film 12 is formed on the upper electrode 11 by photolithography.
And a part of the barrier film 15a is removed to form the opening 9b.

Next, as shown in FIG. 6 (n), the opening 9
The wiring layer 13 is applied to b in a predetermined pattern, and then, as shown in FIG.
As shown in (A), an insulating layer 6b and a moisture-resistant protective film (not shown) are formed to a predetermined thickness on the wiring layer 13 and the insulating film 12, and the upper electrode 11-the ferroelectric film is formed. 10-A ferroelectric memory element 20 having a memory cell structure in which a charge storage capacitor 21 including a lower electrode 8 is connected to a charge transfer field effect transistor 19 is manufactured.

Further, as shown in FIG. 1B, in the memory cell equivalent circuit of the ferroelectric memory element 20, the upper electrode 11 of the capacitor 21 is connected to the diffusion layer 17 of the select transistor (not shown) and the voltage is applied. Is selectively fixed, the electric charges transferred from the field effect transistor 19 can be stably accumulated in the capacitor 11.

According to the present embodiment, since the second insulating film 14 as the protective layer having the hydrogen barrier resistance is provided at least on the ferroelectric film 10 side of the first insulating film 7, the second insulating film 14 is provided. The two insulating films 14 form the first insulating film 7 to the ferroelectric film 1
It is possible to prevent hydrogen from penetrating into the ferroelectric film 10 and
The performance deterioration of can be prevented.

Further, at the time of processing the lower electrode material (conductive film) 8A, the second insulating film 14 having a workability equivalent to that of the first insulating film 7 is provided on at least the ferroelectric film 10 side. In addition, it is possible to surely process the lower electrode 8 and the second insulating film 14 so that the lower electrode 8 and the second insulating film 14 are substantially flush with each other without any difference in the processing amount between the lower electrode material 8A and the second insulating film 14. As a result, the adhesion of the ferroelectric film 10 to the lower electrode 8 and the second insulating film 14 becomes good (the voids described above do not occur), and the dielectric breakdown that occurs when the adhesion is defective can be prevented. .

Further, in the step of FIG. 4G, when a ferroelectric film material is formed on the lower electrode 8 and crystallized to form a ferroelectric film, the crystallization on the lower electrode 8 is performed. Since the state is the same as the crystallized state on the second insulating film 14, the lower electrode 8
On both the top and the second insulating film 14, the ferroelectric film has a large grain and the crystallization is good. Therefore, the interface characteristics between the second insulating film 14 and the ferroelectric film 10 are improved, the leakage of charges does not occur, and the ferroelectric characteristics are improved. Especially, when the memory cell size is miniaturized. It is possible to secure sufficient ferroelectric characteristics.

Further, in the ferroelectric memory element 20,
By embedding the lower electrode 8 of the capacitor 21 in the insulating film 7, the size of the lower electrode 8 can be reduced, so that the memory cell size can be reduced and the degree of integration can be increased. In this case, since the ferroelectric film 10 is formed larger than the lower electrode 8, the pattern can be arbitrarily designed without being restricted by the lower electrode 8, which is also advantageous for high integration. . Moreover, since the area of the lower electrode 8 is small, the parasitic capacitance can be reduced.

Second Embodiment FIGS. 7 to 11 show a second embodiment of the present invention.

According to the present embodiment, first, FIG.
As shown in FIG. 2A, the silicon substrate 1
Then, the field effect transistor 19 is manufactured by the gate electrode 5, the source region 2, the drain region 3, the conductive plug 4 embedded in the contact hole 18, and the like.

Next, as shown in FIG. 7B, a conductive film (lower electrode material) 8A made of Pt is formed to a predetermined thickness on the interlayer insulating layer 6a in which the conductive plug 4 is buried. As a method for forming this, for example, a PVD method such as a sputtering method or an evaporation method, a plating method, an electroless plating method, or the like is used.

Next, as shown in FIG. 7C, an unnecessary portion is removed by an etching method using a photoresist, and the lower electrode 8 made of Pt is formed in a predetermined pattern.

Next, as shown in FIG. 8D, a first insulating film 7 made of SiO ₂ is formed to a predetermined thickness on the lower electrode 8 and the interlayer insulating layer 6a. The first insulating film 7 is
For example, it is formed by pressure reduction using a gas such as monosilane (SiH ₄ ), plasma or atmospheric pressure CVD method, or PVD method such as sputtering method or vapor deposition method.

Next, as shown in FIG. 8E, on the first insulating film 7, for example, the same alumina (Al) as described above is formed.
The second insulating film 14 made of ₂ O ₃ ) is formed to a predetermined thickness by a PVD method such as a sputtering method or a vapor deposition method.

Next, as shown in FIG. 8F, the second insulating film 14 and the first insulating film 7 laminated on the lower electrode 8 are removed to remove the first and second insulating films 7 and 14. Processing is performed so that the upper surface and the upper surface of the lower electrode 8 are substantially flush with each other. For this processing, for example, a CMP (chemical mechanical polishing) method, an etch back method by dry etching, or the like is used.

The subsequent steps from FIG. 9 (g) to FIG. 11 (o) are respectively shown in FIG. 4 (g) to FIG. 6 (n) and FIG. 1 (A) in the above-described first embodiment. Since the steps are the same as the above steps, their description will be omitted here.

In the present embodiment, the ferroelectric film 10
Is in contact with the second insulating film 14 occupying most of the underlying insulating film, it is possible to sufficiently prevent the residual hydrogen in the interlayer insulating layer 6a from entering the ferroelectric film 10, and The crystal state of the dielectric film 10 also becomes good. Second insulating film 1
The material, thickness, etc. of No. 4 are the same as those of the above-mentioned first embodiment.

Further, only the second insulating film 14 and the first insulating film 7 laminated on the lower electrode 8 are removed so that the upper surface of the second insulating film 14 and the upper surface of the lower electrode 8 are substantially flush with each other. Therefore, it is possible to obtain the same characteristic improvement as described above, and it is possible to significantly reduce the grinding removal amount of the lower electrode material.

Further, since the grinding or etching rate of the second insulating film 14 and the grinding or etching rate of the lower electrode material are equal, the ground surface or the etched surface, that is, the lower electrode 8 and the second electrode.
The surface formed by the insulating film 14 can be surely flattened.

Further, when the lower electrode 8 is formed in a predetermined pattern on the interlayer insulating layer 6a in the step of FIG. 7C and the insulating films 14 and 7 thereon are ground or the like, the lower electrode 8 is directly formed into the insulating film. Since it can be embedded in the opening, the adherence of the lower electrode 8 and the precision of the embedding pattern are improved, and the embedding work is facilitated.

Besides, in the present embodiment, the same operation and effect as those described in the above-mentioned first embodiment occur.

Third Embodiment FIG. 12A shows a third embodiment of the present invention.

The present embodiment is similar to the above-described first embodiment except that the barrier film 15b is formed between the first insulating film 7 and the interlayer insulating layer 6a to have a predetermined thickness. There is. Here, the material of the barrier film 15b is, for example, Si ₃
The condition such as N ₄ and the thickness may be about 50 nm like the second insulating film 14 described above.

The barrier film 15b made of Si ₃ N ₄ is
It is possible to prevent ions or hydrogen gas existing in the interlayer insulating layer 6a from entering the ferroelectric film 10 and deteriorating the characteristics.

In addition, in the present embodiment, the same operation and effect as those described in the above-mentioned first embodiment are produced.

Fourth Embodiment FIG. 12 (B) shows a fourth embodiment of the present invention.

In the present embodiment, the interlayer insulating layer 6a is formed.
Between the ferroelectric film 10 and the ferroelectric film 10, the first insulating film 7 is not provided, and only the second insulating film 14 made of Al ₂ O ₃ or the like is formed to have a predetermined thickness. This is similar to the first embodiment.

As described above, even if only the second insulating film 14 is formed, it is possible to prevent the characteristic deterioration of the ferroelectric film 10 due to the penetration of residual hydrogen in the interlayer insulating layer 6a.

Besides, in the present embodiment, the same operation and effect as those described in the above-mentioned first embodiment occur.

Fifth Embodiment FIG. 13 and FIGS. 14 (a) to 15 (e) show a fifth embodiment of the present invention.

In this embodiment, as shown in FIG. 13A, the lower electrode 8 is provided not only on the source region 2 but also on the drain region 2. 3 is connected to a conductive plug 4 on which a ferroelectric film 10 is commonly formed, and an upper electrode 11
Is also provided in a one-to-one correspondence with each lower electrode 8. Therefore, it is the same as the above-described first embodiment, except that a plurality of memory elements including the capacitor 21 and the field effect transistor 19 are configured by using the common ferroelectric film 10.

To manufacture such a memory element, first, as shown in FIG. 14A, the lower electrodes 8 are respectively formed in the openings of the insulating films 7 and 14 by the same steps as described above. Embed so as to form the same surface.

Next, as shown in FIG. 14B, on the upper surface of the second insulating film 14 and the upper surface of the lower electrode 8, for example, SB
A ferroelectric film 10 made of T (strontium bismuth tantalum) is formed to a predetermined thickness by a sol-gel method, a sputtering method, a CVD method or the like.

Next, as shown in FIG. 14C, the upper electrode material 11A made of, for example, Pt is formed on the ferroelectric film 10.
Is formed to a predetermined thickness by a PVD method such as a sputtering method or a vapor deposition method or a plating method.

Next, as shown in FIG. 15D, the unnecessary portion of the upper electrode 11 and the unnecessary portion of the ferroelectric film 10 are R
It is removed using a dry etching method such as IE. At this time, the size of the upper electrode 11 is substantially the same as that of the lower electrode 8. Further, instead of dividing the ferroelectric film 10 for each element unit of the ferroelectric memory element, a plurality of (4 in this example
The ferroelectric film 10 is processed and removed so that the ferroelectric film 10 remains in common to the block (collection of memory elements) of the ferroelectric memory elements.

Next, as shown in FIG. 15E, Al of the same material as the second insulating film 14 is formed so as to cover part of the upper electrode 11, the ferroelectric film 10 and the second insulating film 14. _A barrier film 15a made of ₂ O ₃ or the like is formed to have a predetermined thickness.

Then, after the steps similar to the steps of FIGS. 5 (l) to 6 (n) in the first embodiment described above, as shown in FIG. 13 (A), a wiring layer made of aluminum is formed. 13 and SiO ₂ on the insulating film 12 made of SiO _2.
An interlayer insulating layer 6b made of is formed to a predetermined thickness, and a moisture resistant protective film (not shown) or the like is further formed to a predetermined thickness to produce an element block made of a plurality of ferroelectric memory elements 20. .

Here, as shown in FIG. 13B, in the memory cell equivalent circuit of the ferroelectric memory element 20, the diffusion layer (not shown) of the selection transistor causes the diffusion layer (not shown) on the upper electrode 11 side of each capacitor. In addition to the voltage being selectively fixed, the charge transferred from each field effect transistor 19 is transferred to an arbitrary capacitor 21 by selecting gate electrodes such as G ₁ and G ₂ to transfer the charge selectively. It can be stably stored inside (this can be realized without crosstalk even though the ferroelectric film 10 is provided in common to each capacitor). For example, a crosspoint type memory can be obtained. Can be configured.

According to the present embodiment, since the ferroelectric film 10 is provided in common for each memory element, it is not necessary to divide the film into individual pieces, thus reducing the waste of the ferroelectric material.
In addition to being able to improve the degree of integration, it is possible to reduce adverse effects such as processing residues, reduce damage to the ferroelectric film 10 during processing, prevent characteristic deterioration thereof, and improve reliability.

The embodiments of the present invention described above can be further modified based on the technical idea of the present invention.

For example, as a method of burying the lower electrode 8 described above, a CMP method or an etch back method is preferable, but a method of selectively electroless plating and burying only the opening of the insulating film can also be implemented.

Further, the second insulating film 14 and the barrier film 15b.
The thickness and material of the ferroelectric film 10, the electrodes 8 and 11, etc.
The forming method and the like may be arbitrarily changed as long as they have a predetermined effect. The ferroelectric film 10 is a preferable material, but may be another known dielectric film.

[0107]

As described above, according to the present invention, the insulating film having the first electrode buried in the opening has the protective layer having hydrogen barrier resistance at least on the dielectric film side. Therefore, this protective layer can effectively prevent hydrogen remaining in the insulating film from entering the dielectric film, and prevent deterioration of the characteristics of the dielectric film due to the penetration of hydrogen. it can.

Further, since the insulating film has the protective layer having a workability equivalent to that of the first electrode at the time of processing the first electrode, the insulating film has at least the dielectric film side. There is no difference in the amount of processing with the insulating film (specifically, the protective layer), and the first electrode and the insulating film (specifically, the protective layer) are substantially flush with each other. ,
As a result, no step is formed between the first electrode and the insulating film, and dielectric breakdown due to poor adhesion is less likely to occur. Further, since the dielectric film is formed on the first electrode and the insulating film, the effective area of the capacitor is sufficient and the memory cell size is restricted by the size of the first electrode. Therefore, the degree of freedom can be increased and the degree of integration can be increased.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (A) showing a ferroelectric memory element according to a first embodiment of the present invention and an equivalent circuit diagram (B) thereof.

FIG. 2 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 3 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 4 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 5 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 6 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 7 is a sectional view sequentially showing a manufacturing process of a ferroelectric memory element according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 9 is a cross-sectional view sequentially showing the manufacturing process of the ferroelectric memory element.

FIG. 10 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 11 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 12 is a sectional view showing a ferroelectric memory element according to a third embodiment of the present invention (A) and a sectional view showing a ferroelectric memory element according to a fourth embodiment of the present invention (B). Is.

FIG. 13 is a sectional view (A) of a ferroelectric memory element according to a fifth embodiment of the present invention and an equivalent circuit diagram (B) thereof.

FIG. 14 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 15 is a cross-sectional view showing the manufacturing process of the ferroelectric memory element in sequence.

FIG. 16 is a sectional view showing a conventional ferroelectric memory element.

FIG. 17 is a cross-sectional view showing another conventional ferroelectric memory element.

FIG. 18 is a sectional view sequentially showing the manufacturing process of the ferroelectric memory element.

FIG. 19 is a sectional view sequentially showing the manufacturing process of the ferroelectric memory element.

FIG. 20 is a sectional view sequentially showing the manufacturing process of the ferroelectric memory element.

FIG. 21 is a cross-sectional view showing the manufacturing steps of the ferroelectric memory element in sequence.

FIG. 22 is a cross-sectional view for explaining a problem that occurs during manufacturing of the ferroelectric memory element.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Source region, 3 ... Drain region, 4 ... Conductive plug, 5 ... Gate electrode, 6a, 6b ...
Interlayer insulating layer, 7 ... First insulating film, 8 ... Lower electrode, 9a, 9
b ... Opening part, 10 ... Ferroelectric film, 11 ... Upper electrode, 12
... Insulating film, 13 ... Wiring layer, 14 ... Second insulating film, 15a,
15b ... Barrier film, 18 ... Contact hole, 19 ... Field effect transistor, 20 ... Ferroelectric memory element, 21 ...
Capacitor, 22 ... Drain electrode

Claims (21)

[Claims] 1. A charge transfer element is provided on a semiconductor substrate, an interlayer insulating layer is formed on the semiconductor substrate so as to cover the charge transfer element, and the charge transfer element is provided in an opening formed in the interlayer insulating layer. A conductive material connected to the conductive material is embedded, an insulating film is provided on the interlayer insulating layer, and a first electrode connected to the conductive material is embedded in an opening formed in the insulating film, the first electrode And a dielectric film formed on the insulating film, wherein the insulating film has hydrogen barrier resistance at least on the side of the dielectric film, and has workability equivalent to that when processing the first electrode. And a protective layer having at least one of the above physical properties, the first electrode and the insulating film are substantially flush with each other, a second electrode is formed on the dielectric film, and One electrode, the dielectric film, and the second electrode Te, memory element a capacitor connected to said charge transfer device is configured. 2. A field effect transistor for charge transfer is provided on the semiconductor substrate, the interlayer insulating layer is formed on the semiconductor substrate so as to cover the field effect transistor, and the field insulating transistor is formed on the interlayer insulating layer. The conductive material connected to the field effect transistor is embedded in the opening, and the first electrode, the ferroelectric film as the dielectric film, and the second electrode
The storage element according to claim 1, wherein a capacitor connected to the field effect transistor is configured by the electrode. 3. The insulating film has the protective layer on the side of the dielectric film, or consists only of the protective layer.
The storage element according to claim 1. 4. The insulating film is composed of a laminated film of the protective layer and a silicon oxide layer, a laminated film of the protective layer, a silicon oxide layer and a silicon nitride layer, or only the protective layer. The storage element according to claim 3. 5. The memory element according to claim 1, wherein a ratio (former / latter) of the thickness of the protective layer to the total thickness of the insulating film is 6/1 to 1/1. 6. The protective layer comprises Al ₂ O ₃ , ZrO ₂ , Y ₂ O.
The memory element according to claim 1, comprising at least one selected from ₃ and lanthanoid oxides. 7. The memory element according to claim 1, wherein a protective film is formed to cover the second electrode and the dielectric film. 8. The storage element according to claim 1, which is used in a dynamic random access memory. 9. A plurality of memory elements according to claim 1 are arranged side by side, the dielectric film is formed in common with these memory elements, and the second electrode of each memory element is formed on the dielectric film. A memory element provided with each. 10. A semiconductor substrate provided with a charge transfer element,
Forming an interlayer insulating layer so as to cover the charge transfer element; embedding a conductive material connected to the charge transfer element in an opening formed in the interlayer insulating layer; and forming a conductive material on the interlayer insulating layer. Providing an insulating film, and embedding a first electrode connected to the conductive material in the opening formed in the insulating film, and at the time of embedding, the first electrode and the first electrode deposited on the interlayer insulating layer. At least one constituent material of the insulating film is removed from the surface side, or the constituent material of the first electrode is selectively applied to the opening of the insulating film, and the opening of the insulating film is covered with the first material. A step of embedding one electrode so as to be substantially flush with the insulating film; a step of forming a dielectric film on the first electrode and the insulating film; and a step of forming a dielectric film on at least the dielectric film side of the insulating film. Having a hydrogen barrier property, and the first The method includes the step of forming a protective layer having at least one of the physical properties of having a workability equivalent to that of the pole during processing, and the step of forming a second electrode on the dielectric film. With the electrode, the dielectric film, and the second electrode,
Configuring a capacitor connected to the charge transfer device,
Storage element manufacturing method. 11. A field effect transistor for charge transfer is provided on the semiconductor substrate, the interlayer insulating layer is formed on the semiconductor substrate so as to cover the field effect transistor, and the opening formed in the interlayer insulating layer. And burying the conductive material connected to the field effect transistor, and forming a capacitor connected to the field effect transistor by the first electrode, the ferroelectric film as the dielectric film, and the second electrode. The method for manufacturing a memory element according to claim 10, which is configured. 12. The constituent material of the first electrode is deposited on the surface of the insulating film formed on the interlayer insulating layer and including the opening, and the constituent material is mainly removed from the surface by the removing treatment. 11. The method of manufacturing a memory element according to claim 10, wherein the first electrode is embedded in the opening. 13. The first electrode is patterned on the interlayer insulating layer, the constituent material of the insulating film is deposited on the surface including the pattern, and the constituent material is mainly removed from the surface by the removal treatment. 11. The method of manufacturing a memory element according to claim 10, wherein the first electrode is embedded in the opening. 14. The constituent material of the first electrode is plated in the opening of the insulating film formed on the interlayer insulating layer,
The method of manufacturing a memory element according to claim 10, wherein the first electrode is formed. 15. The method of manufacturing a storage element according to claim 10, wherein the removing process is performed by chemical mechanical polishing, grinding, or etch back. 16. The method of manufacturing a memory element according to claim 10, wherein the insulating film having the protective layer on the side of the dielectric film or formed of only the protective layer is formed. 17. The insulating film is formed of a laminated film of the protective layer and a silicon oxide layer, a laminated film of the protective layer, a silicon oxide layer and a silicon nitride layer, or only the protective layer. The method for manufacturing a memory element according to claim 16. 18. The ratio (former / latter) of the thickness of the protective layer to the total thickness of the insulating film is 6/1 to 1/1.
The method for manufacturing a memory element according to claim 16. 19. The protective layer is formed of Al ₂ O ₃ , ZrO ₂ , Y ₂
The method for manufacturing a memory element according to claim 10, wherein the memory element is formed of at least one selected from O ₃ and a lanthanoid oxide. 20. The method of manufacturing a memory element according to claim 10, wherein a protective film is formed to cover the second electrode and the dielectric film. 21. The method of manufacturing a storage element according to claim 10, wherein a dynamic random access memory is manufactured.