JP2003158207A - Nonvolatile semiconductor memory device and method for operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a novel cell structure in which all the operations of writing, erasing and reading of data can be conducted, even without operating a transistor for forming a channel and therefore characteristics are hardly lowered even by microminiaturization with advantage in reduction of a cell area. SOLUTION: The nonvolatile semiconductor memory device comprises a memory cell containing a pn junction diode DI formed by bringing a first conductivity semiconductor W into contact with a second conductivity semiconductor IR, and a capacitor CAP having the second conductivity semiconductor IR of the cathode side of the pn junction diode used as one electrode, and other electrode CE opposed to the one electrode via a capacitor dielectric film CD having a plurality of dielectric films BTM, CHS and TOP for the one electrode and including a charge storage means (e.g. a charge trap) therein.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device whose data storage operation is based on inputting and outputting charges to and from a charge storage means in a laminated dielectric film, and an operating method thereof.

[0002]

2. Description of the Related Art A conventional non-volatile memory device such as a flash EEPROM controls a gate electrode during operation,
It has a so-called memory transistor that controls the channel below it. The gate electrode faces a semiconductor region in which a channel is formed (hereinafter referred to as a channel formation region) with a plurality of stacked dielectric films interposed.
This laminated dielectric film has a charge storage capability, and is a so-called floating gate (FG) type, MONOS (Metal-Oxide) depending on the type of the charge storage means.
-Nitride-Oxide-Semiconduc
type), MNOS (Metal-Nitride-)
Oxide-Semiconductor) type etc.

Generally, writing is performed by injecting charges from the substrate side into the charge storage means. At the time of reading, by operating the transistor under an appropriate bias condition, the difference in the threshold voltage of the memory transistor depending on the presence or absence of the accumulated charges or the amount of the charges is converted into, for example, the potential change of the drain impurity region. The potential change of the drain impurity region is
The voltage is amplified and read out to a voltage that can be output to the outside.

[0004]

However, in this non-volatile memory device, it is necessary to form a channel at least at the time of reading, and in addition to the channel forming region, a source impurity region for supplying carriers to the channel and carriers from the channel are formed. A drain impurity region to suck out was required. The source impurity region and the drain impurity region have opposite conductivity types to the channel formation region,
A source impurity region is arranged on one side and a drain impurity region is arranged on the other side across the channel formation region. In such a non-volatile semiconductor memory device, both a source impurity region and a drain impurity region are required for reading,
Therefore, there is a limit to the reduction of the dimension in the channel direction.

Further, if the effective channel length is shortened to improve the memory density, so-called fine shape effect including reduction in breakdown voltage between the source and drain becomes conspicuous and the device characteristics deteriorate. Therefore, the structure of the conventional nonvolatile semiconductor memory device having the memory transistor is not suitable for the progress of miniaturization.

An object of the present invention is that all operations of data writing, erasing and reading can be performed without operating a transistor for forming a channel, which is advantageous for reducing a cell area, and even if it is miniaturized, the characteristics are reduced. A non-volatile semiconductor memory device having a novel structure that does not easily deteriorate, and an operating method thereof.

[0007]

In order to achieve the above object, a non-volatile semiconductor memory device according to a first aspect of the present invention is formed by contacting a first conductivity type semiconductor and a second conductivity type semiconductor. And a second conductivity type semiconductor on the cathode side of the pn junction diode as one electrode,
There is provided a memory cell including one capacitor each of which is opposed to the other electrode via a capacitor dielectric film including a plurality of dielectric films and including a charge storage unit inside.

In this non-volatile semiconductor memory device, for example, a second conductivity type semiconductor is formed in a part of the surface region of the first conductivity type semiconductor, and a capacitor dielectric having a charge storage capability with respect to the second conductivity type semiconductor. The body electrode may be interposed so that the other electrode of the capacitor partially overlaps. This structure requires a relatively small footprint.

A method of operating a nonvolatile semiconductor memory device according to a second aspect of the present invention is a pn junction diode formed by contact between a first conductivity type semiconductor and a second conductivity type semiconductor, and a cathode of the pn junction diode. A second non-volatile capacitor having a second conductive type semiconductor on one side as one electrode, and a capacitor in which the other electrode is opposed to the one electrode via a capacitor dielectric film including a plurality of dielectric films and including charge storage means inside A method of operating a non-volatile semiconductor memory device, wherein a voltage having a polarity and a value that charges are injected into or extracted from the capacitor dielectric film during writing or erasing is applied between the one electrode and the other electrode. Then, at the time of data reading, a predetermined voltage is applied to the other electrode to cause a current flowing through the pn junction diode or the current due to the accumulated charge. To detect the position change.

In this method of operating a non-volatile semiconductor memory device, the amount of charge stored in the capacitor dielectric film changes in accordance with the stored data by applying the above voltage during writing or erasing. Capacitors have different coupling capacities when the amount of stored charge is different. At the time of reading, when a predetermined voltage is applied to the other electrode of the capacitor, the potential of the second conductivity type semiconductor on the cathode side of the pn junction diode also changes according to the difference in the coupling capacitance of the capacitor. The pn junction diode is biased so that the potential of the second conductivity type semiconductor on the cathode side changes across a critical point where breakdown of the pn junction occurs. Due to the voltage application at the time of reading, breakdown of the pn junction may or may not occur depending on the logic of the stored data. The presence or absence of a current in the first conductivity type semiconductor or the second conductivity type semiconductor at this time is detected, or the presence or absence of a potential change in the first conductivity type semiconductor or the second conductivity type semiconductor at this time is detected.

A method of operating a non-volatile semiconductor memory device according to a third aspect of the present invention includes at least a first conductivity type semiconductor and a second conductivity type semiconductor region formed in a surface region of the first conductivity type semiconductor. A dielectric film that is composed of a plurality of dielectric films in contact with a semiconductor surface including a boundary between a first conductivity type semiconductor region and a second conductivity type semiconductor region, and includes charge storage means inside, and a dielectric film capable of storing charges. A method of operating a non-volatile semiconductor memory device having a control electrode facing a surface of the semiconductor with a body film interposed therebetween, comprising:
A dielectric capable of accumulating charges in a pn junction diode formed by contacting the first conductivity type semiconductor and the second conductivity type semiconductor by applying a predetermined voltage to the control electrode while biasing the conductivity type semiconductor. An electric current is caused to flow according to the accumulated charges in the film, and the electric current or a potential change caused by the electric current is detected.

This operating method (reading method) is applicable not only to the 1-capacitor-1 diode type non-volatile semiconductor memory device according to the first aspect but also to a non-volatile semiconductor memory device having a memory transistor. In this case, for example, one side of the source and the drain may be in a floating state, and reading may be performed only on the other side.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 (A) is a sectional view showing a basic cell structure according to an embodiment of the present invention, and FIG. 1 (B) is an equivalent circuit diagram thereof. As shown in FIG. 1A, a second-conductivity-type, for example, n-type impurity region IR is formed in a surface region of a well W of the first-conductivity type, for example, p-type. On the p well W, a laminated body of the capacitor dielectric film CD and the upper electrode CE of the capacitor is formed so as to overlap at least a portion including the boundary region with the n-type impurity region IR. In such a structure, in the equivalent circuit shown in FIG.
A capacitor CAP having R as one electrode, an upper electrode CE as the other electrode, and a dielectric film CD between them as a capacitor dielectric film, and a diode DI formed by a junction between the n-type impurity region IR and the p well W. Are connected in series. In addition, the upper electrode CE of the capacitor, the diode DI
The anode (p well W) and the cathode (n-type impurity region IR) are configured to be able to individually apply voltage.

The capacitor dielectric film CD may be composed of a plurality of dielectric films including charge storage means inside, and here it is composed of a so-called ONO film type laminated film. Specifically, the capacitor dielectric film CD is composed of the bottom dielectric film BTM, the charge storage film CHS, and the top dielectric film TOP in this order from the lower layer side. The bottom dielectric film BTM is made of a dielectric material having a relatively low charge trap density such as silicon dioxide or silicon oxynitride, and functions as a first potential barrier layer for the charge storage film CHS. The charge storage film CHS is made of, for example, silicon nitride or silicon oxynitride and has a charge trap density of bottom dielectric film BTM.
It is composed of a much higher dielectric. The top dielectric film TOP is made of a dielectric material having a charge trap density sufficiently lower than that of the charge storage film CHS, such as silicon dioxide or silicon oxynitride, and functions as a second potential barrier layer for the charge storage film CHS.

The capacitor dielectric film CD may be, for example, an NO type laminated film in which silicon nitride and silicon dioxide are laminated. In this case, the charge storage means serves as a charge trap formed in silicon nitride or in the boundary region between silicon nitride and silicon dioxide as in the ONO type. Alternatively, between the bottom dielectric film BTM and the top dielectric film TOP,
For example, a conductor made of doped polycrystalline silicon or the like that is in an electrically floating state may be formed. In this case, the conductor serves as the charge storage means. Alternatively, a configuration may be adopted in which a large number of conductive fine particles such as polycrystalline silicon or silicon germanium are discretely arranged on the bottom dielectric film BTM, and the conductive fine particles are covered with the dielectric film. In this case, the conductive fine particles serve as charge storage means.

FIGS. 1C-1 and 1C-2 are explanatory views of the local charge injection operation used at the time of writing or erasing. In the charge injection shown in FIG. 1C-1, n
0V or a negative voltage (-Vke) is applied to the type impurity region IR, and a positive voltage (+ Vpe) is applied to the capacitor electrode CE. Due to this electric field, electrons are injected from the n-type impurity region IR into the charge trap in the capacitor dielectric film CD by FN tunneling (or direct tunneling) the bottom dielectric film BTM. At this time, depending on the overlap between the n-type impurity region IR and the capacitor electrode CE,
The electron injection region is determined.

In the charge injection operation shown in FIG. 1C-2,
A voltage with which the capacitor electrode CE has a negative polarity is applied to the n-type impurity region IR. Here, the n-type impurity region I
A positive voltage (+ Vkh) is applied to R, and the capacitor electrode CE
A negative voltage (-Vph) is applied to. This electric field causes n
The surface of the type impurity region IR becomes deeply depleted, and the energy band bends sharply. Band at this time-
Electrons tunnel to the valence band due to the band-to-band tunnel effect and flow inside the n-type impurity region IR, resulting in the generation of holes. The generated holes slightly drift toward the p-well W side, and the electric field is accelerated there, and a part of the holes become hot holes. The hot holes are efficiently injected into the charge traps in the capacitor dielectric film CD while maintaining the momentum and losing almost no energy, and at high speed.

Although not shown in the drawing, the electric charge is extracted from the n-type impurity region IR by FN tunneling (or direct tunneling) by generating an electric field opposite to that shown in FIG. Alternatively, the n-type impurity region IR and the p-well W are set to the same potential and are pulled out over the entire surface. Further, it may be pulled out to the capacitor electrode CE side.

Regarding writing and erasing, there are various combinations of these charge injection methods and charge extraction operations. For example,
The state after FN electron injection in FIG. 1C-1 (charge amount Q <
0) is stored as "1" data storage, and the state after BTBH injection in FIG. 1C-2 (charge amount Q> 0) is stored as "0" data storage. In this case, in erasing, for example, only when "1" data is stored, BTBH injection is performed to shift to a "0" data storage state, or only when "0" data storage is performed, FN electron injection is performed and "1" is stored. By shifting to the data storage state, the data storage state is aligned to one side. Also,
Writing may be performed by associating the case where the charge amount Q is positive or negative and the case where the charge amount Q = 0 with binary data. in this case,
In erasing, an operation of pulling out an electric charge or an operation of injecting an electric charge of opposite polarity to return the electric charge amount Q to zero is performed.

1 (D-1) and 1 (D-2),
It is explanatory drawing of a read-out operation. Figure 2 shows a typical MOS
It is a voltage-current characteristic view of a transistor. FIG. 3 is a voltage-current characteristic diagram showing the reading principle of the diode according to the present embodiment.

As shown in FIG. 2, in the enhancement type memory transistor, the threshold value Vth at which the drain current Id starts to flow in the region where the gate voltage Vg is positive varies depending on the logic of the stored data. Therefore, the read gate voltage is set so that the change can be detected, and the memory transistor is turned on or off according to the stored data to perform the read.

On the other hand, in this embodiment, a region (breakdown voltage: VB) where a breakdown current starts to flow due to surface breakdown when the pn junction is reverse biased is used for reading. As is well known, there are various breakdown phenomena due to surface breakdown, such as Zener breakdown and avalanche breakdown. In this embodiment, the n-type impurity region IR of the capacitor is changed according to the accumulated charge amount Q of the capacitor.
The coupling capacity for changes. Therefore, the accumulated charge amount Q
The breakdown voltage VB1 when the stored data is "1" (negative) is larger than the breakdown voltage VB0 when the stored data "Q" is positive (or large) stored data "0". In reading, this breakdown voltage difference is used.

Specifically, FIG. 1 (D-1), (D-2)
As shown in, the voltage Vkr is applied to the n-type impurity region IR to hold it in the floating state.
A voltage Vr is applied to the capacitor electrode CE such that the potential of the voltage Vd is between the two breakdown voltages VB1 and VB0. At this time, in the case of "1" data storage, the expansion of the depletion layer on the surface of the n-type impurity region IR immediately below the capacitor is suppressed, a large electric field is applied to the depletion layer, and the reverse current of the diode is reversed as shown in FIG. (Breakdown current) Idi flows. "0"
In the case of data storage, since the coupling capacitance of the capacitor is small, the depletion layer electric field on the surface of the n-type impurity region IR is small, and the reverse current Idi of the diode does not flow. The current Idi flowing from the n-type impurity region IR to the p-well W is detected on the n-type impurity region side or the p-well side, or the potential change of the n-type impurity region or the p-well caused by this current is detected. Thereby, the stored data can be read.

In the storage element composed of the capacitor and the diode, the capacitor electrode CE needs to overlap in the vicinity of the boundary between the two opposite conductivity type semiconductor regions IR and W forming the diode. As long as this requirement is satisfied, the memory element can be formed in a range in which the element size in the cross-sectional direction of FIG.
Therefore, the occupied area can be significantly reduced as compared with the memory transistor type storage element. Further, since the transistor is not operated, the element characteristics are not deteriorated due to the effect of the fine shape, and the device can be effectively operated even if it is further miniaturized.

FIG. 4 is an equivalent circuit diagram of a memory cell array in which a large number of storage elements are arranged. Memory cells M11 to M44 each including a capacitor CAP and a diode DI are arranged in a matrix. The n-type impurity regions IR of the memory cells in the column direction are bit lines BL1, BL2, BL3, BL
It is electrically connected to any one of 4, .... The bit line may be composed of the n-type impurity region IR itself, or may be composed of an upper layer wiring connecting the n-type impurity regions IR for each cell or for every predetermined number (for example, 64). Good. The upper electrodes CE of the capacitors of the memory cells in the row direction correspond to the word lines WL1, WL2, WL3, W
It is electrically connected to any one of L4, .... The word line may be composed of the upper electrode CE itself of the capacitor, or may be composed of an upper layer wiring for connecting the upper electrode of the capacitor common to each cell or between a plurality of cells.

In the following, in the second to fifth embodiments, the memory element structure and element pattern for realizing the equivalent circuit of FIG. 4 will be described.

Second Embodiment FIG. 5 is a plan view of a memory cell array according to the second embodiment. 6 is a sectional view taken along the line AA of FIG.

In this memory cell array, as shown in FIG. 5, the dielectric isolation layer ISO is formed in a parallel stripe pattern elongated in the column direction, whereby the semiconductor substrate S is formed.
The p wells W formed in the UB are electrically separated in units of columns. The parallel striped word lines WL1 to WL4 that are long in the row direction are arranged orthogonal to the dielectric isolation layer ISO. Each word line is made of, for example, doped polycrystalline silicon, with a capacitor dielectric film CD interposed,
Face each p-well W after separation. This word line corresponds to the upper electrode CE of the capacitor shown in the first embodiment.

An n-type impurity region IR is formed in the inter-word line region of each p well W. n of the n-type impurity region
The type impurities diffuse below the edge of the word line, and the word line and the n-type impurity region IR overlap each other at this portion, thereby forming a capacitor. A plug made of a conductive material is arranged on every two n-type impurity regions IRa in the column direction, whereby a bit contact BC is formed. The bit contact BC is embedded in the interlayer insulating film IF and connected to the bit line on the interlayer insulating film IF. The bit lines are arranged in parallel stripes that are long in the column direction above the region between the dielectric isolation layers ISO.
The capacitor in the overlapping portion of the word line and the n-type impurity region IRa that is electrically connected to the bit line and is active during device operation becomes the capacitor CAP that contributes to the memory element. In FIG. 5, this overlapping part is described as a memory part. The n-type impurity region IRf forming the other overlapping portion is not connected to the bit line and is always in a floating state and therefore does not contribute to the element operation. In addition, the diode DI is formed by the n-type impurity region IRa and the p well W.
Are formed.

To form this memory cell array, a p-well W is formed on the semiconductor substrate SUB and, for example, LOCO is formed.
S (LOCcal Oxidation of Sil
icon) and STI (Shallow Trench)
Isolation) to form the dielectric isolation layer ISO.

A capacitor dielectric film CD is formed on the entire surface. Specifically, in the case of the MONOS type, for example, the well surface is heat-treated by high-temperature heat treatment (RTO) for a short time to form silicon dioxide (bottom dielectric film BTM). Low pressure organic chemical vapor deposition (LP-) on the bottom dielectric film BTM.
By CVD, a silicon nitride film (charge storage film CHS) is deposited thicker than the final film thickness. In this CVD, for example, a gas in which dichlorosilane (DCS) and ammonia NH ₃ are mixed is used. After that, the surface of the silicon nitride film is thermally oxidized to form a silicon oxide film (top dielectric film TOP) having a desired thickness. This thermal oxidation is performed, for example, in a steam atmosphere,
In the meantime, the underlying charge storage film CHS is reduced to a desired thickness. As a result, charge traps having a deep trap level (energy difference from the conduction band of the silicon nitride film) are formed with high density centering on the interface between the charge storage film CHS and the top dielectric film TOP. Both the deep charge trap and the charge trap in the silicon nitride film contribute as a charge trap as a charge storage means.

On the capacitor dielectric film CD, a doped polycrystalline silicon which becomes a word line is deposited by CVD. By continuously patterning the doped polycrystalline silicon film and the capacitor dielectric film CD, a laminated body having the word line pattern of FIG. 7A is formed.

This laminate and a dielectric isolation layer I (not shown)
An n-type impurity is introduced at a high concentration on the well surface using SO as a self-alignment mask. This impurity introduction is performed by, for example, ion implantation, thermal diffusion, or the like. When activation annealing is performed,
As shown in FIG. 7B, n-type impurity regions IRa, IR
f is formed. It is desirable that the profile (concentration and depth) of the n-type impurity region be optimized under the condition that surface breakdown easily occurs. In the case of ion implantation, the implantation angle can be adjusted to optimize the capacitor area.

After that, although not particularly shown, an interlayer insulating film IF is deposited, and a contact is opened in this to be filled with a plug or the like to form a bit contact BC. In addition, the bit line BL that connects the bit contacts BC in the column direction
1, BL2, ... Are formed on the interlayer insulating film IF.

FIG. 8A is a plan view of one memory cell showing a modified example of this embodiment. In addition, FIG.
It is sectional drawing of the aa line of FIG. 8 (A). In this memory cell, all the word lines are formed with the minimum dimension F, and the bit contacts BC are formed by self-aligned contacts (SAC).

When this self-aligned contact is viewed in the column direction, as shown in FIG. 8B, the insulating layer ID is formed on each word line in the same pattern as the word line, and
Sidewalls SW made of a dielectric are formed on the side surfaces of the laminated body made of the insulating layer ID made of the dielectric, the word line WL, and the capacitor dielectric film CD. Then, the bit contact BC is formed in a state of being electrically and spatially separated by these dielectric layers ID and SW. Both ends of the bit contact BC in the column direction overlap the word line, but the spatial distance between them is the dielectric layer I.
It is determined by the thickness of D and SW, and is not affected by misalignment during mask alignment. That is, it is a self-aligned contact SAC. A dielectric isolation layer exists on both sides of the bit contact BC in the column direction.

Next, the writing, erasing and reading operations of the memory cell will be described by taking the data storage in the memory cell M21 as an example. Here, the case where the accumulated charge amount Q becomes negative due to local FN electron injection is defined as “1” data storage, and the case where the accumulated charge amount is substantially zero is defined as “0” data storage (and erase state). The case where FN electrons are extracted from the entire surface is shown. It is also possible to operate in page units, and in that case, it can be realized by setting the same bias as that of the memory cell M21 in other memory cells in the same row.

The equivalent circuit diagram of FIG. 9 shows the bias application conditions during writing. A predetermined voltage, for example, 0V is applied to the bit line BL2 connected to the memory cell M21 for storing "1" data, and the other bit lines BL1, BL3, ...
Is applied to the word line WL1 with a predetermined write voltage, for example, 15V so that the diode does not break down and FN electron injection does not occur due to the voltage difference from the applied voltage of the word line WL1. . A write inhibit voltage, for example, 4V is applied to the other word lines WL2, .... As a result, in the memory cell M21, electrons are emitted from the n-type impurity region IRa of the capacitor dielectric film C.
Injected into D and accumulated in the charge trap, "1" data is stored.

The equivalent circuit diagram of FIG. 10 shows the bias application conditions during erase. Erasing is performed in block units or in a memory cell array at a time, and all bit lines BL1, BL2, B
A predetermined voltage, for example, 10 V is applied to the p-well W with L3, ... Floating, and a predetermined voltage is applied to the word lines WL1, WL2, ... Of the selected block, or all word lines in the case of array erase. Erase voltage, eg 0
Apply V. Also, if there are unselected blocks,
An erase inhibit voltage, for example, 10V is applied to the word line. As a result, in the memory cells M21 to M32, ..., Stored electrons in the capacitor dielectric film CD are extracted from the entire surface to the substrate side to be in an erased state.

The equivalent circuit diagram of FIG. 11 shows the bias application conditions during reading. Read target memory cell M21
To the bit line BL2 connected to
V is applied to the other bit lines BL1, BL3, ..., A voltage that does not cause breakdown or writing of the diode, for example, 0 V is applied, and a predetermined read voltage, for example, 0 V is applied to the word line WL1, and other words are applied. A read inhibit voltage, for example, 5V is applied to the lines WL2, .... As a result, in the memory cell M21, surface breakdown occurs in the surface region of the n-type impurity region IRa, and the diode DI
A reverse current Idi flows through the inside. This current or a potential change caused by the current is detected, and if necessary, amplified to a voltage that can be taken out to the outside and output.

FIG. 12 shows a plan view of an SSL type memory cell as a comparative example. In this memory cell, the distance between the dielectric isolation layers ISO is set to three times the minimum dimension F of the process or more, and in the p well W region thereof, the n-type source impurity region functioning as the source line SL and the bit line BL functioning. It is necessary to dispose the n-type drain impurity region to be parallel to each other. A well surface region between the two impurity regions serves as a channel formation region. In the hot electron injection writing, the electrons supplied from the source line SL side having a lower potential are accelerated by the electric field and injected into a local portion on the drain (bit line BL) side having a higher potential, which serves as a memory portion. In this memory cell, when the bit contact BC and the source contact SC are included, the cell area is about 12F ² . When a contact is formed for each of a large number of memory cells and the contact area is small enough to be ignored, the cell area is about 8F ² .

On the other hand, the memory cell of this embodiment is
Since the n-type impurity region on the source side is unnecessary, the area of the memory cell shown in FIG. 5 is as small as about 5F ² . Further, as described in the first embodiment, the characteristics are not easily deteriorated even when the size is reduced.

Third Embodiment FIG. 13A shows a plan view of two memory cells in the memory cell array according to the third embodiment. Also, FIG.
FIG. 3B shows a cross-sectional view taken along the line BB of FIG. In this memory cell array, as in the comparative example shown in FIG. 12, the distance between the dielectric isolation layers ISO is 3F or more,
Two cells adjacent to each other in the row direction are formed in the p well W between them. Word line WL intersecting dielectric isolation layer ISO
1 is used as a self-alignment mask to introduce an n-type impurity into the p-well W, whereby an n-type impurity region IR is formed separately below the word line. The upper n-type impurity region IR in the drawing is connected to the upper bit line BL1 via the bit contact BC, and the lower n-type impurity region IR is connected to the upper bit line BL2 via the bit contact BC. .

By the way, in the second embodiment shown in FIG.
The memory portion (capacitor area) is defined by the lateral diffusion amount of impurities when the n-type impurity region IRa is formed.
The capacitor area may be insufficient. If the capacitor area is too small, for example, the amount of increase in the potential of the n-type impurity region IRa at the time of voltage application to the word line during reading may be insufficient, and the operation margin for reliable reading may be too small.

On the other hand, in the present embodiment, the capacitor area defined by the overlapping area of the n-type impurity region IRa and the word line WL1 has a length in the row direction as shown in FIG. 13 (A). Since it is as long as 3F or more, it is considerably wider than that in the second embodiment. Therefore, there is an advantage that element design for reliable operation is easy.

The cell area in this embodiment is about 6
Although the F ^2, in the comparative example of FIG. 11, considering that it is possible two-bit / cell storage can also charge injection to the source line side, the cell area per bit is equivalent to the comparative example. However, in the comparative example, the operation of switching the voltages of the bit line and the source line at the time of writing or reading is necessary in the operation sequence of 2-bit storage. At this time, it takes time to charge and discharge a relatively large capacity of the bit line and the source line, and as a result, there is a disadvantage that the operation speed cannot be increased. On the other hand, in the present embodiment, two memory cells shown in FIG. 13A can be written simultaneously, and in the case where a potential change due to a read current is detected on the bit line side, the read operation is performed. 2 bits can be done at the same time. Therefore, it is suitable for increasing the operating speed.

In this embodiment, it is more desirable to form the bit contact BC by the self-aligned contact SAC similar to that shown in FIGS. 8A and 8B because the cell area can be reduced.

Further, in this embodiment, the FN electron injection shown in FIG. 1C-1 and the case shown in FIG.
In addition to the BTBH injection of -2), channel hot electron (CHE) injection is also possible. For example, in FIG.
While holding the bit line BL2 of (A) at a low voltage such as 0 V, a higher voltage is applied to the bit line BL1.
Further, a predetermined positive voltage is applied to the word line WL1. At this time, a channel is formed on the surface of the well W below the word line WL1, electrons supplied from the n-type impurity region IR on the left side of FIG. 13B are accelerated in the channel, and the n-type impurity region on the right side of FIG. It becomes hot electrons on the IR side and is locally injected into the memory portion 1 of the capacitor dielectric film CD. On the contrary, when it is desired to inject electrons into the memory section 2, the voltage state of the bit line is reversed from the above case.

Fourth Embodiment FIG. 14 shows a plan view of a memory cell array of the fourth embodiment. Further, FIG. 15 shows a cross-sectional view taken along the line CC of FIG. In this memory cell array, the bit lines BL,
The n-type impurity regions IR forming BL2, BL3, BL4, ... Are formed in long lines in the column direction and are not divided in the middle. Therefore, the bit contact BC can be provided for each of a large number (for example, 64) of memory cells and is not shown in FIG. Also, the word line WL
1, WL2, WL3, WL4, ... Are formed by upper layer wiring on the interlayer insulating film IF. Therefore, the upper electrode CE of the capacitor is provided for each cell in a size of, for example, 1F × 1F. The upper electrode CE of the capacitor is
A capacitor dielectric film CD is interposed on the lower surface of each of the n-type impurity regions IR, and the n-type impurity regions IR are stacked on one side in the width direction by a certain width.

On the other hand, the semiconductor substrate SUB has a p well W
Is not formed, and the dielectric isolation layer ISO is not formed. This is related to the fact that the word line is composed of the upper layer wiring. That is, in the first to third embodiments, since the word lines are arranged in a line shape that is long in the row direction with the capacitor dielectric film CD interposed, assuming that the dielectric isolation layer ISO is not formed, the adjacent cells are not formed. Depending on how the voltage applied to the bit line between them is applied, a parasitic transistor may be turned on between adjacent cells and a leak path may occur. In the present embodiment, however, the upper electrode CE with the capacitor dielectric film CD interposed is separated for each cell, and the word line is formed of the upper layer wiring in order to connect them. Therefore, the dielectric isolation layer I
A parasitic transistor is not formed without SO, and interference between cells is structurally prevented.

Since the p well W is not formed, it is necessary to detect the potential change of the bit line in the floating state at the time of reading. Other basic operations and bias application conditions are the same as in the first embodiment.

16A to 16C are cross-sectional views of the memory cell array during manufacture. First, FIG. 16 (A)
As shown in, the n-type impurity region IR functioning as a bit line is formed in the surface region of the semiconductor substrate SUB by, for example, ion implantation.

Next, as shown in FIG. 16B, a laminated body of the capacitor dielectric film CD and the upper electrode CE is formed by using, for example, the same material and method as in the first embodiment. Although not particularly shown, the pattern of the laminated body at this stage is parallel stripes that are long in the column direction. Further, the pattern of the stacked body is overlapped with each n-type impurity region IR by a certain amount on one side in the width direction.

In FIG. 16C, an interlayer insulating film IF is deposited and flattened, and the space between the patterns of the laminated bodies CD and CE is completely filled with an insulating material. After that, a conductive film to be a word line is deposited on this interlayer insulating film IF and patterned. At the time of etching at this time, the portions CE and CD exposed on the base are etched to divide the linear laminate at regular intervals. As a result, the upper electrode CE of the capacitor having an isolated pattern is formed for each cell.

In this embodiment, the p well W and the dielectric isolation layer ISO may be formed. 17 (A) to (C)
Shows the manufacturing method in this case. FIG. 17A is a sectional view immediately after patterning of the upper electrode CE of the capacitor. In this memory cell array, a p well W is formed in a semiconductor substrate SUB, and an n type impurity region I is formed in the well.
R is formed, and the capacitor dielectric film C is formed on the well.
The upper electrode CE of a linear capacitor long in the column direction is formed with D interposed.

As shown in FIG. 17B, the exposed well surface is etched while leaving the mask layer used for this patterning, for example, the resist R. This etching is performed until the depth of the etching groove T is deeper than the well and the bulk of the semiconductor substrate SUB is exposed. If the resist R alone is insufficient as a mask layer, a film made of a material having high etching resistance may be interposed between the resist R and the upper electrode CE.

Thereafter, the interlayer insulating film IF is deposited and planarized in the same manner as described above, but at this time, the etching trench T is filled with an insulating material, and trench isolation (dielectric isolation layer ISO) is formed. This dielectric isolation layer ISO
By this, the p well W is separated, and a different voltage can be applied to each column.

In the present embodiment, as shown in FIG. 14, the memory cell area can be further reduced to 4F ^2, and since the transistor is not operated, it is easy to miniaturize.
There are similar advantages to the embodiment. In this embodiment, the upper electrode CE of the capacitor is provided for each cell in an isolated pattern,
Since the word line is an upper layer wiring that connects the upper electrode CE, it is not necessary to form the dielectric isolation layer ISO, and the capacitance of the capacitor can be set arbitrarily. This is because the capacitor area is determined by the area of overlap between the n-type impurity region IR and the upper electrode CE, but this area can be arbitrarily changed by pattern design. Therefore, in the device structure of the present embodiment, the structure and characteristics are easily optimized, and in particular, the device design in which surface breakdown is likely to occur during reading is easy, and the operation is stable. In addition, the dielectric isolation layer IS
Also in the case of forming O, a photomask is not required in the above manufacturing method, and etching of silicon or the like may be added after etching of the upper electrode CE or the like.

Fifth Embodiment FIG. 18 shows a plan view of a memory cell array of the fifth embodiment. Further, FIG. 19 shows a cross-sectional view taken along the line DD of FIG. In this memory cell array, the upper electrode CE of the capacitor is shared by two cells adjacent in the row direction. Therefore, the memory section is located on the side closer to each other between the two adjacent n-type impurity regions IR. Other configurations are the same as those in the fourth embodiment. Further, the manufacturing method itself is the same as that of the fourth embodiment, only the etching pattern of the upper electrode CE of the capacitor is different. Furthermore, in this case as well,
The dielectric isolation layer ISO is manufactured by the same method as in the fourth embodiment.
Can be formed.

In this embodiment, as shown in FIG. 18, the memory cell area can be made as small as 4F ^2, and since there is no transistor operation, it is easy to miniaturize, which is the same advantage as in the first to third embodiments. Further, similarly to the fourth embodiment, the formation of the dielectric isolation layer ISO is not essential, and since the capacitance of the capacitor can be set arbitrarily, it is easy to optimize the structure and characteristics, and particularly the operation during reading is stable.
In this case as well, CHE injection is possible as in the case of FIGS. 13A and 13B.

Sixth Embodiment This embodiment relates to multi-valued storage. Multi-value storage can be applied to any of the cell structures of the above-described first to fifth embodiments. In the multi-value storage operation, a plurality of charge amounts to be stored in the capacitor dielectric film CD are set and the threshold value is changed in multiple steps, whereby a plurality of binary data is stored. In particular,
During writing, the voltage value applied to the upper electrode and the lower electrode of the capacitor CAP is finely controlled to gradually inject charges. Alternatively, first, an amount of charge close to the saturation value is injected, and the voltage value applied to the upper electrode and the lower electrode of the capacitor CAP during erasing is finely controlled so that the accumulated charge is gradually extracted or the opposite polarity charge is discharged. Inject little by little.

The four-value storage operation will be described below as an example.
FIG. 20A shows a characteristic change according to the amount of charges accumulated in the capacitor dielectric film CD. In addition, FIG. 20B shows the threshold change. For example, when electrons are injected into the capacitor dielectric film CD to control the threshold value Vth, if Q4 in FIG. 20A represents an erased state in which almost no electrons are injected, except for the bit that maintains Q4. A predetermined amount of electrons are injected into all the other bits to bring them into the state of Q3. Then, electrons are injected into all the other bits except a bit that maintains Q3 and Q4 by a predetermined amount to bring them into the state of Q2. Finally, a predetermined amount of electrons are injected into all the other bits except the bit that maintains Q2, Q3, and Q4 to bring them into the state of Q1. The control of these charge amounts is controlled by the write voltage and its application time. As a result, as shown in FIG. 20B, the threshold Vth has a distribution divided into four in the entire memory cell array.

Reading is performed by setting the reading gate voltage during this threshold distribution. Specifically, for example, when reading is performed from the one with the higher threshold, the read gate voltage is placed between the first distribution “11” and the second distribution “10” from the highest one as shown in FIG. First, "11" is read by setting Vread. Next, the read gate voltage Vread is set between the second distribution "10" and the third distribution "01" to read "10". Finally,
The read gate voltage Vread is set between the third distribution "01" and the erased state distribution "00" to read "01". This completes the reading of 2-bit data.

The above read operation is the same when writing is performed while verifying the threshold value by performing each time a write pulse is applied. If writing is performed finely while performing this verify operation, the threshold distribution can be made steep. Further, the multi-value storage operation is not limited to 2 bits (4 values) and may be 3 bits or more, and in this case, the same operation is performed.

[0065]

According to the non-volatile semiconductor memory device and the method of operating the same according to the present invention, all the data writing, erasing and reading operations can be performed without operating the transistor forming the channel. It is possible to provide a non-volatile semiconductor memory device having a novel structure that is advantageous for reduction in size and whose characteristics are not easily deteriorated even when miniaturized, and an operating method thereof.

[Brief description of drawings]

1A is a cross-sectional view showing a basic cell structure according to an embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram thereof.
(C-1) and (C-2) are explanatory views of a local charge injection operation used at the time of writing or erasing. (D-
1) and (D-2) are explanatory views of the read operation.

FIG. 2 is a voltage-current characteristic diagram of a general MOS transistor used for explaining the read principle according to the embodiment of the present invention.

FIG. 3 is a voltage-current characteristic diagram showing a reading principle of the diode according to the embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a memory cell array in which a large number of memory elements according to the embodiment of the present invention are arranged.

FIG. 5 is a plan view of a memory cell array according to a second embodiment of the present invention.

6 is a cross-sectional view taken along the line AA of FIG. 5 according to the second embodiment of the present invention.

7A and 7B are cross-sectional views of the memory cell array according to the second embodiment of the present invention during manufacture.

8A and 8B are a plan view and a sectional view showing a configuration of a memory cell according to a modified example of the second embodiment of the present invention.

FIG. 9 is an equivalent circuit diagram showing a bias application condition example at the time of writing in the memory cell array according to the embodiment of the present invention.

FIG. 10 is an equivalent circuit diagram showing an example of bias application conditions during erase in the memory cell array according to the embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram showing an example of bias application conditions during reading in the memory cell array according to the embodiment of the present invention.

FIG. 12 is a plan view of a memory transistor of a comparative example of the first embodiment of the present invention.

FIG. 13A is a plan view of two memory cells of the memory cell array according to the third embodiment of the present invention. (B)
[Fig. 4] is a sectional view taken along line BB in (A).

FIG. 14 is a plan view of a memory cell array according to a fourth embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along the line CC of FIG. 14 in the memory cell array according to the fourth embodiment of the present invention.

16A to 16C are cross-sectional views of the memory cell array according to the fourth embodiment of the present invention during manufacturing.

FIGS. 17A to 17C are cross-sectional views of the memory cell array according to the fourth embodiment of the present invention during manufacture when a dielectric isolation layer is formed.

FIG. 18 is a plan view of a memory cell array according to a fifth embodiment of the present invention.

FIG. 19 relates to the fifth embodiment of the present invention and is D- in FIG.
It is sectional drawing in the D line.

FIG. 20 is a current-voltage characteristic diagram and a threshold distribution diagram showing a charge injection operation according to the sixth embodiment of the present invention.

[Explanation of symbols]

CAP ... Capacitor, DI ... Diode, SUB ... Semiconductor substrate (first conductivity type semiconductor), W ... P well (first conductivity type semiconductor), ISO ... Dielectric isolation layer, IR, IRa, I
Rf ... N-type impurity region (second conductivity type semiconductor), CD ... Capacitor dielectric film, BTM ... Bottom dielectric film, CHS ...
Charge storage film, TOP ... Top dielectric film, CE ... Capacitor upper electrode, IF ... Interlayer insulating film, ID ... Insulating layer, SW
… Insulating sidewalls, BC… Bit contacts, M
11 etc .... memory cell, BL1 etc .... bit line, WL1 etc.
Word line.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F083 EP18 EP22 ER03 ER04 ER11                       ER22 ER29 ER30 JA04 MA02                       MA03 MA06 MA20 NA01 PR29                       ZA21                 5F101 BA45 BA46 BB02 BC02 BC04                       BC08 BD20 BD32 BD33 BD35                       BD37 BE02 BE05 BE07 BF05                       BH19

Claims (17)

[Claims] 1. A pn junction diode formed by contact between a semiconductor of a first conductivity type and a semiconductor of a second conductivity type, and a second conductivity type semiconductor on the cathode side of the pn junction diode as one electrode, with respect to the one electrode. A non-volatile semiconductor memory device having a memory cell including a capacitor having a plurality of dielectric films and a capacitor having a capacitor dielectric film inside and having the other electrode facing each other. 2. The second conductivity type semiconductor is formed in a surface region of the first conductivity type semiconductor, and a laminate of the capacitor dielectric film and the other electrode is a second conductivity type semiconductor and a first conductivity type semiconductor. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed on the surfaces of both semiconductors including a boundary between the two. 3. A bit line including the second conductivity type semiconductor, wherein a plurality of memory cells each including the pn junction diode and the capacitor are arranged in a matrix and shared or electrically connected between cells in a column direction. 3. The nonvolatile semiconductor memory device according to claim 2, further comprising: a word line that is shared between cells in a row direction and that functions as another electrode of the capacitor or a wiring connecting the other electrodes. 4. The second memory cell of two memory cells adjacent in the row direction.
4. The non-volatile semiconductor memory device according to claim 3, wherein the conductive type semiconductor partially overlaps the word line on both sides in the width direction of the word line. 5. A laminated body of the capacitor dielectric film and the other electrode is shared between two memory cells adjacent in the row direction, and the laminated body is formed with the second conductivity type semiconductor on both ends in the row direction. The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory devices partially overlap each other. 6. A pn junction diode formed by contact between a semiconductor of a first conductivity type and a semiconductor of a second conductivity type, and a second conductivity type semiconductor on the cathode side of the pn junction diode is used as one electrode, with respect to the one electrode. A method of operating a non-volatile semiconductor memory device having a memory cell including one capacitor each of which is formed of a plurality of dielectric films and has the other electrode facing each other via a capacitor dielectric film having a charge storage means inside. Then, a voltage having a polarity and a value by which charges are injected or extracted in the capacitor dielectric film at the time of writing or erasing is applied between the one electrode and the other electrode, and at the time of data reading, the other electrode A non-volatile semiconductor that applies a predetermined voltage to a current and detects a current flowing through a pn junction diode or a potential change caused by the current according to the accumulated charge. Method of operation of the memory device. 7. The current flowing during the read is the first current
7. The method of operating a nonvolatile semiconductor memory device according to claim 6, wherein the current is a current caused by a surface breakdown between a conductive semiconductor and the second conductive semiconductor. 8. The current flowing during the read is the first current
8. The method for operating a nonvolatile semiconductor memory device according to claim 7, wherein the Zener breakdown current is between a conductive type semiconductor and the second conductive type semiconductor. 9. The current flowing during the read is the first current
8. The method of operating a non-volatile semiconductor memory device according to claim 7, wherein the avalanche breakdown current is between a conductivity type semiconductor and the second conductivity type semiconductor. 10. The current flowing at the time of reading is relatively large when negative charges are accumulated in the charge accumulating means, and relatively small when positive charges are accumulated. Non-volatile semiconductor memory device operating method. 11. The pn during the writing or erasing.
7. The method of operating a non-volatile semiconductor memory device according to claim 6, wherein charges are locally injected into a part of the capacitor dielectric film near the junction. 12. At the time of writing or erasing, the value of the voltage applied between the one electrode and the other electrode is variously changed to set a plurality of charge amounts to be accumulated in the capacitor dielectric film, and two or more bits are set. 7. The method for operating a non-volatile semiconductor memory device according to claim 6, wherein the multi-valued information is stored. 13. A laminated body of the capacitor dielectric film and the other electrode is shared between two memory cells adjacent in the row direction, and the laminated body is formed with the second conductivity type semiconductor on both ends in the row direction. Part of them overlap each other, and the value of the voltage applied between the one electrode and the other electrode at the time of writing or erasing the adjacent memory cells is changed variously and accumulated in the capacitor dielectric film. 7. The method of operating a non-volatile semiconductor memory device according to claim 6, wherein a plurality of charge amounts to be set are set and multi-valued information of 2 bits or more is stored. 14. A semiconductor including a first conductivity type semiconductor, a second conductivity type semiconductor region formed in a surface region of the first conductivity type semiconductor, and a semiconductor including at least a boundary between the first conductivity type semiconductor and the second conductivity type semiconductor region. A dielectric film composed of a plurality of dielectric films in contact with the surface and having charge storage means inside, and a control electrode facing the semiconductor surface with the dielectric film capable of charge storage interposed. A method of operating a nonvolatile semiconductor memory device according to claim 1, wherein a predetermined voltage is applied to the control electrode while the second conductivity type semiconductor is biased during reading, and the first conductivity type semiconductor and the second conductivity type semiconductor are applied. A non-volatile semiconductor memory in which an electric current is caused to flow in a pn junction diode formed by contact with the electric current according to the accumulated charge in the dielectric film capable of accumulating the electric charge, and the electric current or a potential change caused by the electric current is detected. How the device operates. 15. The operation of a nonvolatile semiconductor memory device according to claim 14, wherein the current flowing at the time of reading is a current caused by a surface breakdown between the first conductivity type semiconductor and the second conductivity type semiconductor. Method. 16. The method of operating a nonvolatile semiconductor memory device according to claim 15, wherein the current flowing at the time of reading is a Zener breakdown current between the first conductivity type semiconductor and the second conductivity type semiconductor. 17. The method of operating a nonvolatile semiconductor memory device according to claim 15, wherein the current flowing at the time of reading is an avalanche breakdown current between the first conductivity type semiconductor and the second conductivity type semiconductor.