JP2003174596A - Output circuit for solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output circuit for a solid-state image pickup device capable of reducing current consumption. <P>SOLUTION: The output circuit for the solid-state image pickup device is provided with an output amplifier biased by a current and a current breaker for interrupting the bias current applied to the output amplifier. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit of a solid-state image pickup device, and more particularly to an output circuit of a solid-state image pickup device in consideration of power consumption.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional CCD (Charge).
It is an example of a circuit diagram of an output amplifier of a Coupled Device type image sensor.

The charges transferred from the CCD transfer register 32 are converted into a potential difference according to the capacitance of the diode 34 by, for example, a floating diffusion method. The potential of the floating diffusion (FD) unit 33 is impedance-converted by the source follower 36a using the N-ch transistor 37a whose size is reduced in order not to increase the capacity of the FD unit 33 as an active transistor, and the source follower 36b in the next stage is converted. Is input to.
The output of the second source follower 36b is directly output to the outside. 16V, 0V, -8V for driving CCD
Since the voltage of the source follower circuit is used,
The voltage is also 16V. Note that source followers of three or more stages may be provided, and a power supply voltage (Vdd) such as 5 V may be used for the source followers of the final stage.

The load of each source follower is a constant current source, and FIG. 4 (A) shows a depletion type transistor 3.
8 is an example in which the gate of 8 is connected to the source to form a constant current source 39. FIG. 4B is an example in which a constant voltage (CG) is applied to the gate of the enhancement type transistor 48 to form a constant current source 49. is there.

[0005]

In the conventional output amplifier, the current source of the source follower amplifier always keeps flowing current. However, in the case of the image sensor, as is well known, the effective pixel is not always output, and there is a considerable period during which the invalid pixel is output. Although it is not an effective pixel such as an optical black pixel, even if the number of pixels used for signal processing in the subsequent stage is subtracted, the current is consumed up to the amount of completely useless pixel output for a considerable period. Become.

As described above, in the conventional output amplifier, the power consumption of the CCD image sensor, such as the consumption of current to the completely useless pixel output, is hardly considered. Therefore, in digital camera applications,
Since the power consumption is large, there is a problem that the battery is consumed greatly.

An object of the present invention is to provide an output circuit for a solid-state image pickup device, which can reduce current consumption.

[0008]

According to one aspect of the present invention, an output circuit for a solid-state image pickup device is provided with an output amplifier biased by a current and a current interrupting means for interrupting a bias current applied to the output amplifier. Have and.

[0009]

1 is a circuit diagram of an output amplifier 1 of a CCD type image sensor according to a first embodiment of the present invention.

The output amplifier 1 comprises a floating diffusion (FD) 3, a diode 4, a depletion type N-ch transistor 5, and a plurality of stages of source followers 6a and 6b. Output amplifier 1
The power supply voltage is Vdd = 16V and GND = 0V. The input signals RS and _SLP are at 3V level.

The output amplifier 1 has a high level (HighL).
When a reset pulse (RS) of “Ever” is supplied to the gate of the depletion type N-ch transistor 5, the potential of the FD 3 is charged to Vdd (16V). After that, when the reset pulse (RS) returns to Low Level, the N-ch transistor 5 is turned off. FD3
Becomes a floating state, and charges are transferred from the CCD transfer register 2.

The output amplifier 1 converts the charges transferred from the CCD transfer register 2 into a potential difference according to the capacitance of the diode 4 by, for example, the floating diffusion method. After that, the output amplifier 1 impedance-converts the converted potential difference by the source follower 6a and inputs it to the source follower 6b at the next stage. Finally, the output of the source follower 6b in the second stage is directly output to the outside as the output OS.

The source follower 6a is an active transistor 7a which is an N-ch transistor having a reduced size.
The depletion type transistor 8 includes a constant current source 9 having a gate and a source connected to each other, and a current cutoff N-ch transistor 10. The constant current source 9 works as a load of the source follower 6a.

N-ch transistor 10 for cutting off current
Is arranged between the constant current source 9 and the GND. The gate of the N-ch transistor 10 for cutting off the current is LowLe.
When the control signal _SLP of vel or High Level is applied and the control signal _SLP becomes the voltage of Low Level, the N-ch transistor 10 for current cutoff is turned off, and the current of the source follower 6a is cut off.

The source follower 6b is a constant current source 9 in which the gate and source of the active transistor 7b, which is an N-ch transistor, and the depletion type transistor 8 are connected.
And an N-ch transistor 10 for cutting off the current. The constant current source 9 works as a load of the source follower 6b. In this embodiment, the output of the source follower 6b is directly output as the output OS.

Similar to the source follower 6a, the N-ch transistor 10 for cutting off the current is arranged between the constant current source 9 and the GND. N-ch transistor for current interruption 1
LowLevel or HighLev for the 0 gate
The control signal_SLP of el is applied, and the control signal_SL is applied.
When P becomes the voltage of LowLevel, N- for current interruption
The ch transistor 10 is turned off, and the source follower 6
The current of b is cut off.

The control signal _SLP is an external Logic I signal.
The voltage of HighLevel generated by C is, for example, 3.3V. The control signal_SLP is, for example, C
The voltage is set to the Low Level voltage during the CD horizontal blanking period, and to the High Level voltage during the other periods. That is, while the CCD is outputting the pixels to be used for signal processing later from the valid pixels and the invalid pixels, the control signal _SLP is HighLevel.
It becomes the voltage of 1 and it is LowLevel during the other periods.
Is set to be the voltage of.

Since the high level voltage of the control signal_SLP is as low as 3.3V, the current cutoff N-ch transistor 10 is set to a low threshold voltage (Vth) which is sufficiently turned on at the low voltage.

FIG. 2 shows a CC according to the second embodiment of the present invention.
It is a circuit diagram of the output amplifier 11 of a D-type image sensor.

In the second embodiment, the source follower 1
The constant current source 19 of 6a and 16b is composed of an enhancement type N-ch transistor 18. The rest of the configuration is the same as that of the first embodiment, so the description is omitted.

The constant current source 19 is composed of an enhancement type N-ch transistor 18 whose gate is supplied with a control signal CG. The control signal CG is set to a voltage at which a predetermined current flows when the control signal _SLP has a High Level voltage, that is, when the current cutoff N-ch transistor 10 is on.

As described above, according to the first and second embodiments of the present invention, the LowLevel control signal _SLP is supplied except when the pixels to be used for signal processing later are output from the effective pixels and the ineffective pixels. To turn off the N-ch transistor 10 for shutting off the current, and the source follower 6a (16
The bias currents of a) and 6b (16b) can be cut off. Therefore, the power consumption of the output circuit can be reduced.

FIG. 3 shows a CC according to the third embodiment of the present invention.
It is a circuit diagram of an output amplifier of a D-type image sensor.

The output amplifier 21 comprises a floating diffusion (FD) 3, a diode 4, a depletion type N-ch transistor 5, and a plurality of stages of source followers 26a and 26b.

In the output amplifier 21, the High-level reset pulse (RS) is a depletion type N-c.
When supplied to the gate of the h-transistor 5, the potential of the FD 3 is charged to Vdd (16V). After that, when the reset pulse (RS) becomes Low Level, the N-ch transistor 5 is turned off. The FD 3 is in a floating state, and the charge is transferred from the CCD transfer register 2.

The output amplifier 21 is the CCD transfer register 2
The electric charge transferred from is converted into a potential difference according to the capacitance of the diode 4 by, for example, a floating diffusion method. After that, the output amplifier 21 impedance-converts the converted potential difference by the source follower 26a and inputs it to the source follower 26b at the next stage. Finally 2
The output of the source follower 26b in the second stage is the same output OS
To the outside.

The source followers 26a and 26b are N-
It is configured to include an active transistor 7 which is a ch transistor and an enhancement type transistor 28 which is a current source.

The gate of the enhancement-type transistor 28 is connected to the gate and drain of the other enhancement-type N-ch transistor 30 and constitutes a so-called current mirror circuit. That is, the current flows through the source followers 26a and 26b with reference to the current flowing through the so-called diode-connected transistor 30 in which the drain and the gate are commonly connected.

For example, assuming that the W / L ratio of the diode-connected transistor 30 is Z1 and the W / L ratio of the current source transistor 28 of the source followers 26a and 26b is Z2, the current flowing through the diode-connected transistor 30 is A current of Z2 / Z1 times flows through the current source transistor 28 of the source followers 26a and 26b.

A control signal _S is externally supplied to the drain of the diode-connected transistor 30 via a resistor 29.
LP is supplied.

The control signal _SLP is generated by an external Logic IC as in the first and second embodiments,
The voltage of HighLevel is 3.3V, for example. The control signal_SLP is set, for example, to have a High Level voltage during the horizontal blanking period of the CCD and to have a Low Level voltage during other periods. That is, while the CCD outputs the pixels to be used for signal processing later from the valid pixels and the invalid pixels, the control signal _SLP becomes the voltage of High Level,
The other periods are set to have the Low Level voltage.

The current flowing through the diode-connected transistor 30 is determined by the High Level output voltage, the resistance value, and the characteristics of the transistor.

At this time, the control signal_SLP is LowLev.
At el (0V), the current flowing through the diode-connected transistor 30 becomes zero, and the current flowing through the source followers 26a and 26b becomes zero by the current mirror circuit. Therefore, the control signal _SLP can control the current flowing through the source followers 26a and 26b.

As described above, according to the third embodiment of the present invention, by supplying the control signal _SLP to the gate of the diode-connected N-ch transistor, the bias current flowing in the source follower for an unnecessary period is cut. You can Therefore, the power consumption of the output circuit can be reduced.

In the embodiment of the present invention, the output amplifier is configured by using the two-stage source followers, but the present invention is not limited to this, and the output amplifier can be configured by, for example, three-stage source followers. In that case, Vdd of the source follower at the final stage can be set to 5V or the like. Also in the above embodiment, the Vdd of the source follower in the second stage is 5V.
It can also be set to etc.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0037]

As described above, according to the present invention,
It is possible to provide an output circuit for a solid-state imaging device that can reduce current consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output amplifier 1 of a CCD image sensor according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output amplifier 11 of a CCD image sensor according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an output amplifier 21 of a CCD type image sensor according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of an output amplifier of a conventional CCD image sensor.

[Explanation of symbols]

1, 11, 21, 31, 41 ... Output amplifier, 2, 32 ... CCD transfer register, 3, 33 ... FD section, 4, 34 ... Diode, 5, 8, 35, 38 ... Depletion type transistor, 6, 16, 26, 36 ... Source follower, 7, 37 ... Active transistor, 28, 48 ... Enhancement type transistor, 9, 19, 29, 39, 49 ... Constant current source, 10, 20 ... Current blocking transistor, 30 ... Diode connected transistor

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5C021 PA02 XA03                 5C024 CY42 GY01 HX02 HX40                 5C051 AA01 BA03 DA02 DB01 DB04                       DB07 DC02 DC03 DC07 DE01

Claims (4)

[Claims] 1. An output circuit for a solid-state image pickup device, comprising: an output amplifier biased by a current; and a current cutoff unit for cutting off a bias current applied to the output amplifier. 2. The output for a solid-state image pickup device according to claim 1, wherein the output amplifier is composed of at least one source follower, and the current cutoff unit is a transistor incorporated in a current path forming the source follower. circuit. 3. The output circuit for a solid-state image pickup device according to claim 2, wherein the current cutoff unit cuts off a current according to a control signal supplied to the gate of the transistor from the outside. 4. The output amplifier is composed of at least one source follower, and the source follower has a current source transistor that allows a current corresponding to the voltage applied to the gate to flow, and further, The output circuit for a solid-state image pickup device according to claim 1, further comprising control means for controlling a gate voltage.