JP2003186693A - Microcontroller with emulation function - Google Patents

Abstract

(57) [Summary] [Problem] To prevent leakage of resources during debugging. SOLUTION: A debug function control circuit 1500 of a microcontroller having an emulation function is provided by JTAG.
A debug IF input / output circuit 1560 connected to the ICE
, A function restriction mode register 1584, an access key register 1582, a protection check circuit 1580.
And a resource access circuit 1520. When a debug command is input from JTAG-ICE, if the operation mode stored in function restriction mode register 1584 is not the restriction mode, protect check circuit 1580 transmits the input debug command to resource access circuit 1520. Protect check circuit 158
If the access key input from the JTAG-ICE matches the access key stored in the access key register 1582, 0 is set to rewrite the operation mode to the permission mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to holding data in a microcontroller, and more particularly to a technique for restricting data reading during debugging of a microcontroller.

[0002]

2. Description of the Related Art In recent years, CPUs (Central Processing Uni
t), memory, and peripheral I / O (Input / Output) are built in one chip, and the performance and functionality of the microcontroller are increasing. In the program development of such a microcontroller, on-chip debug ICE (In-Circuit
Emulator) is provided and debugging is carried out.

According to this on-chip debug ICE,
ICE CPU instead of target system CPU
The program under development is executed and the operation of the program is analyzed. The ICE CPU is the debug target C
It is necessary to execute the operation executed by the PU and the operation for debugging, and it is necessary to exceed the processing speed of the CPU to be debugged.

However, with the recent advances in performance and functionality of microcontrollers, the processing speed of the CPU of the target system has increased, and there are cases in which such a development environment using the CPU for ICE cannot be realized. . Also, due to the high performance and miniaturization of the CPU, I
The CE and the target system cannot be easily connected.

In order to solve such a problem, therefore, a microcontroller has been realized in which a debugging function of a program is realized by a microcontroller and a dedicated interface for debugging is added to the microcontroller. The ICE corresponding to such a microcontroller is JTAG (IEEE1149.1) -I.
Called CE. Unlike the normal on-chip debug ICE, the JTAG-ICE does not execute emulation of the target system and only transmits / receives debug data to / from the target system via the debug interface. A JTAG-ICE system for debugging such a target system will be described with reference to the drawings.

Referring to FIG. 7, the microcontroller 1
00 is a CPU 110 and a RAM (Random Access Memo).
ry) 120, ROM (Read Only Memory) 130,
The debug function control circuit 150 and the debug IF (Interf
ace) terminal 160, peripheral I / O 170, bus 140 connecting these, bus control circuit 180 controlling bus 140, and external bus terminal 190. JTAG-
The ICE 200 is connected to the outside of the microcontroller 100, which is the development target, via the debug IF terminal 160.

The JTAG-ICE 200 outputs a debug command to the debug function control circuit 150 in response to a user request. The debug function control circuit 150
The CPU is controlled by the CPU control circuit 154 based on the debug command input from the JTAG-ICE 200.
110 to execute a predetermined program, and by using the resource access circuit 152, RAM 120, ROM 130
And access to peripheral I / O.

FIG. 8 shows the internal structure of the debug function control circuit 150. As shown in FIG. 8, the debug control circuit 15
0 includes a resource access circuit 152, a CPU control circuit 154, and a debug IF input / output circuit 156. J
The debug command received from the TAG-ICE 200 is input to the debug IF input / output circuit 156 via the debug IF terminal 160.

The resource access circuit 152 includes a bus 14
It is connected to resources (RAM 120, ROM 130, peripheral I / O 170) via 0 and controls access to resources. The CPU control circuit 154 is connected to the CPU 110 via the bus 140 and controls the CPU 110. The debug IF input / output circuit 156 has a debug IF terminal 16
The resource access circuit 152 and the CPU control circuit 154 are controlled on the basis of a debug command from the JTAG-ICE 200 connected to 0 and connected via the debug IF terminal 160. Debug IF input / output circuit 156
Decodes the debug command, and returns JTAG-I
The type of debug command transmitted from the CE 200 is determined.

The debug IF input / output circuit 156 sends a control signal to the CPU control circuit 154 when the debug command is a command relating to the processing of the CPU 110 such as the change and reference of the register value of the CPU 110. C
The PU control circuit 154, based on the received control signal,
An instruction signal is output to the CPU 110 via the bus 140. The CPU 110 sends a response signal (for example, a response signal to a reference command of a specific register value) to the bus 14
It is transmitted to the CPU control circuit 154 via 0. CPU
The control circuit 154 transmits a response signal to the debug IF input / output circuit 156. The debug IF input / output circuit 156 is
The response signal corresponding to the control signal is used as a response to the command for debugging via the debug IF terminal 160.
It transmits to TAG-ICE200.

The debug IF input / output circuit 156, when the debug command is a command relating to processing such as referring to the contents of the internal memory, the resource access circuit 152.
Control signal to. Resource access circuit 152
Outputs an instruction signal to the corresponding resource (RAM 120, ROM 130, peripheral I / O 170) via the bus 140 based on the received control signal. Resource (RA
M120, ROM 130, peripheral I / O 170) sends a response signal to the resource access circuit 1 via the bus 140.
52. The resource access circuit 152 sends a response signal to the debug IF input / output circuit 156. The debug IF input / output circuit 156 transmits the response signal corresponding to the control signal as a response to the debug command to the JTAG-ICE 200 via the debug IF terminal 160.

In this way, debugging is executed using JTAG-ICE. At this time, the contents of the ROM 130 of the microcontroller 100 mounted on the product can be read. Japanese Unexamined Patent Publication No. 2000-347942 discloses an information processing device that prevents unauthorized reading of the contents of the ROM 130 by a third party.

The information processing apparatus disclosed in this publication prevents unauthorized access using a normal on-chip debug ICE. This information processing device supports debugging of the information processing device, and an input / output control circuit connected to the memory and controlling input / output signals of signals required for debugging between the emulator and the information processing device. Includes on-chip debug circuitry and security circuitry.
The security circuit receives a reset signal that resets the information processing device when the power is turned on, receives a circuit that invalidates the function of the on-chip debug circuit, and a code that removes the read prohibition of the information stored in the memory, And a circuit for enabling the function of the chip debug circuit. The memory stores a security release program that is a user program that can be individually set by the user, and information that is protected from unauthorized access by an emulator provided externally.

According to this information processing device, when the function of the on-chip debug circuit is disabled, when the code for canceling the read prohibition is input to the released I / O register by the user, the security circuit operates. , Enable the function of the on-chip debug circuit. As a result, a third party who does not know the code for releasing the read prohibition cannot activate the function of the on-chip debug circuit and cannot read the contents of the ROM mounted on the target system.

[0015]

When the device disclosed in the above publication is applied to JTAG-ICE, the following problems occur. That is, JTAG-ICE
Is the IC of the target system with the miniaturization of the CPU.
It was developed because E and the target system cannot be easily connected. However, the device disclosed in the above-mentioned publication requires an I / O opened to the user for inputting a code for canceling the read prohibition in addition to transmitting and receiving a debug command and a response signal to the debug command. This is JTAG-ICE
Connection with the target system becomes more difficult. Further, in the device disclosed in the above publication, since the security release program is executed by the user program,
It was necessary to develop such a program.

The present invention has been made to solve the above-mentioned problems, and a microcontroller having an emulation function capable of reliably preventing resource leakage at the time of debugging with a simple system. Is to provide.

[0017]

A microcontroller according to a first aspect of the present invention includes a processor for controlling the microcontroller, processor control means for reading data representing an internal state of the processor, and operation of an emulation function. A mode storage unit for storing the mode and an input / output unit connected to the processor control unit for inputting / outputting information to / from a device provided outside the microcontroller, the processor control unit and the mode storage unit And a control means for controlling the input / output means. The input / output means includes means for the equipment to input a control command for the processor control means and means for outputting data to the equipment. When the control command is input from the device to the input / output unit, the control unit transmits the control command to the processor control unit when the operation mode stored in the mode storage unit satisfies the first predetermined condition. Means for controlling the processor control means so as to receive the data from the processor control means, means for controlling the input / output means so as to output the received data to the equipment, and the input / output means from the equipment When the mode change command is input, when the input mode change command satisfies the predetermined second condition, the mode storage unit is controlled to change the operation mode.

According to the first aspect of the present invention, as the emulation function, the processor control means reads out data representing the internal state of the processor. When a control command for reading data representing the internal state of the processor is transmitted to the controller from an external device, the processor control means reads the data representing the internal state of the processor, and this data is stored in the controller. To a device external to the. As such a controller, for example, JTAG
-There is an ICE. When the control command is transmitted, the control means confirms the operation mode of the emulator stored in the mode storage means, and if the operation mode is not a mode for limiting the emulation function, the control means sends the control command to the processor control means. Send. Thus, the data representing the internal state of the processor is not output to the external device when the operation mode is the mode that limits the emulation function. When the mode change command is input using the input / output unit that transmits the data indicating the internal state of the processor to the external device, the control unit matches the input mode change command with a predetermined command, for example. At times, the operation mode stored in the mode storage means is changed from the limited mode to the permitted mode or from the permitted mode to the limited mode. This makes J
In a TAG-ICE system or the like, it is possible to control whether the emulation function is permitted or restricted by using a signal line for transmitting / receiving debug data. As a result, with a simple system, it is possible to provide a microcontroller having an emulation function that can surely prevent resource leakage during debugging.

A microcontroller according to a second aspect of the present invention is a storage device for storing data, storage device control means for reading data from the storage device, and mode storage means for storing the operation mode of the emulation function. And an input / output unit connected to the storage device control unit for inputting / outputting information to / from a device provided outside the microcontroller, and controlling the storage device control unit, the mode storage unit, and the input / output unit. And a control means for controlling the operation. The input / output unit includes a unit for the device to input a control command for the storage device control unit and a unit for outputting the data to the device. When a control command is input from the device to the input / output unit, the control unit transmits the control command to the storage device control unit when the operation mode stored in the mode storage unit satisfies the first predetermined condition. And means for controlling the storage device control means so as to receive data from the storage device control means, means for controlling the input / output means so as to output the received data to the device, and input / output means When a mode change command is input from the device to the device, means for controlling the mode storage means to change the operation mode when the input mode change command satisfies the second predetermined condition. including.

According to the second invention, as the emulation function, the storage device control means reads out the data stored in the storage device. When a control command for reading the data stored in the storage device is transmitted to the controller from an external device, the storage device control unit reads the data stored in the RAM or ROM, which is the storage device, This data is output to a device outside the controller. As such a controller, for example, JT
There is AG-ICE. When the control command is transmitted, the control means confirms the operation mode of the emulator stored in the mode storage means. For example, if the operation mode is not a mode for limiting the emulation function, the control command is sent to the storage device control means. To send. Thus, the data stored in the storage device is not output to the external device when the operation mode is the mode that limits the emulation function. When the mode change command is input by using the input / output unit that transmits the data stored in the storage device to the external device, the control unit, for example, when the input mode change command matches the predetermined command, , The operation mode stored in the mode storage means,
Change from restricted mode to allowed mode, or from allowed mode to restricted mode. As a result, JTAG
In an ICE system or the like, it is possible to control whether the emulation function is permitted or restricted by using a signal line for transmitting / receiving debug data. As a result, with a simple system, it is possible to provide a microcontroller having an emulation function that can surely prevent resource leakage during debugging.

In the microcontroller according to the third aspect of the invention, in addition to the configuration of the first or second aspect of the invention, the mode storage means has either a permission mode for operating the emulation function or a limitation mode for not operating the emulation function. And means for storing the The first condition is that the operation mode stored in the mode storage means is the permission mode.

According to the third invention, the emulation function can be executed only when the permission mode is stored in the mode storage means, and the external device stores the data in the data indicating the internal state of the processor or in the storage device. The output data can be output.

In addition to the structure of the third invention, the microcontroller according to the fourth invention further includes cancellation information storage means for storing information for canceling the restriction mode.
The second condition is that the input mode change command is a command corresponding to the information stored in the release information storage means.

According to the fourth invention, a mode change command (for example, a release key) input by using the input / output means.
However, when the information matches the information (for example, the release key) stored in the release information storage means, the operation mode stored in the mode storage means is changed from the restriction mode to the permission mode.
A person who cannot input the release key cannot execute the emulation function, and cannot output the data representing the internal state of the processor or the data stored in the storage device to the external device.

In addition to the configuration of the third aspect, the microcontroller according to the fifth aspect of the present invention further includes release information storage means for storing information for releasing the restricted mode.
The second condition is that the number of times the input mode change command is a command corresponding to the information stored in the release information storage means satisfies a predetermined number of times.

According to the fifth invention, a mode change command (for example, a release key) inputted by using the input / output means.
However, when the information (for example, the release key) stored in the release information storage means matches a predetermined number of times, the operation mode stored in the mode storage means is changed from the restriction mode to the permission mode. A person who cannot input the release key a predetermined number of times cannot execute the emulation function and cannot output the data representing the internal state of the processor or the data stored in the storage device to the external device.

In addition to the configuration of the third invention, the microcontroller according to the sixth invention stores a mode change command for changing the operation mode of the emulator and release information corresponding to the mode change command. The release information storage means is further included. The control means further includes means for controlling the input / output means to output the release information to the device. The second condition is that the input mode change command is the mode change command corresponding to the release information stored in the release information storage means.

According to the sixth aspect, the mode change command (eg, release key) corresponding to the release information (eg, public key) output using the input / output means is stored in the release information storage means. When it coincides with (for example, a release key), the operation mode stored in the mode storage means is changed from the restriction mode to the permission mode. A person who cannot input the release key corresponding to the public key cannot execute the emulation function, and cannot output the data representing the internal state of the processor or the data stored in the storage device to the external device.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same parts are designated by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

<First Embodiment> A debug function control circuit 1500 of a microcontroller according to the present embodiment will be described with reference to FIG. The microcomputer according to the present embodiment has a debug function control circuit 1500 instead of the debug function control circuit 150 of the microcontroller 100 shown in FIG. The other hardware configuration is the same as that shown in FIG. Those functions are also the same as the functions described with reference to FIG. 7. Therefore, detailed description thereof will not be repeated.

As shown in FIG. 1, debug function control circuit 1500 includes resource access circuit 1520 and CPU control circuit 1540 connected to bus 140, and resource access circuit 1520 and CPU control circuit 1540.
A protect check circuit 1580 connected to the access check register 1580, an access key register 1582 connected to the protect check circuit 1580, and a protect check circuit 1580.
Function limit mode register 1584 connected to the protection check circuit 1580 and the debug IF connected to the protection check circuit 1580.
Input / output circuit 1560 and debug IF input / output circuit 156
And a debug terminal 160 connected to 0.

Among these devices, the functions of the resource access circuit 1520, the CPU control circuit 1540 and the debug IF input / output circuit 1560 are the same as those of the resource access circuit 152 described with reference to FIG. , CPU control circuit 154 and debug I
Each is the same as the F input / output circuit 156. Therefore, description thereof will not be repeated.

The protect check circuit 1580 indicates that the value stored in the function restriction mode register 1584 is not in the function restriction mode (the value of the register is "0").
Control signal is transmitted to the resource access circuit 1520 and the CPU control circuit 1540. When the power is turned on, the protect check circuit 1580 stores a value (register value is “1”) in the function restriction mode register 1584 indicating that the function is in the function restriction mode. When the access key input by the user via the debug IF terminal 160 and the debug IF input / output circuit 1560 and the prestored access key match, the protect check circuit 1580 causes the function limit mode register 1584 to store the function limit mode. A value indicating that it is not (the value of the register is “0”) is stored.

The access key register 1582 stores the access key read from the internal memory (RAM 120, ROM 130) in order to cancel the function restriction by the protect check circuit 1580. Since the JTAG-ICE is used when writing the access key in the internal memory, resource access by the JTAG-ICE is possible when the access key is not stored in the internal memory.

In the function restriction mode register 1584, a value indicating that the function is in the function restriction mode (the value stored in the register is “1”) and a value indicating that the function is not in the function restriction mode (in the register) by the protect check circuit 1580. One of the stored values is "0") is stored.

The protect check circuit 1580 includes a resource access circuit 1520 and a CPU control circuit 154.
It is determined whether or not the operation of 0 is executed. The debug IF input / output circuit 1560 decodes the debug command received from the JTAG-ICE 200 and sends a control signal for the resource access circuit 1520 and the CPU control circuit 1540 to the protect check circuit 1580.

The protect check circuit 1580 refers to the value stored in the function restriction mode register 1584, and if the operation mode is not the function restriction mode, the debug check circuit 1580.
The control signal received from the input / output circuit 1560 is transmitted to the resource access circuit 1520 and the CPU control circuit 1540. The protect check circuit 1580 refers to the value stored in the function restriction mode register 1584, and if the operation mode is the function restriction mode, the control signal received from the debug IF input / output circuit 1560 controls the resource access circuit 1520 and the CPU. Do not send to circuit 1540.

As a result, when in the function limited mode, the control signals are transmitted to the resource access circuits 1520 and C.
Since it is not transmitted to the PU control circuit 1540, the debug function is not executed and the internal memory (RAM 120, ROM 1
The data stored in 30) and the data indicating the internal state of the CPU are not read out to the outside.

Referring to FIG. 2, the program executed by controller 100 according to the present embodiment has the following control structure for the debug process.

Step (hereinafter, step is abbreviated as S)
At 100, the debug function control circuit 1500 is reset by powering on the controller 100 or the like. At S102, the protect check circuit 15
The value 80 of the function restriction mode register 1584 is "1".
Set to. At S104, protect check circuit 1580 confirms the input of the reset release signal to debug IF input / output circuit 1560. In S106, it is determined whether the reset release signal is input to debug IF input / output circuit 1560. Debug IF input / output circuit 1
When the reset release signal is input to 560 (YES in S106), the process proceeds to S108. If not (NO in S106), the process returns to S104,
The input of the reset release signal to the debug IF input / output circuit 1560 is waited for.

At S108, the protect check circuit 1
580 transmits a memory access control signal to the resource access circuit 1520. In S110, the resource access circuit 1520 causes the internal memory (RAM 120, R
The access key is read from the OM 130).

In S112, the resource access circuit 15
20 transmits the access key to the protection check circuit 1580. In S114, protect check circuit 1580 confirms the validity of the access key. S11
At 6, it is determined whether the access key is valid. At this time, if all bits of the access key are “1” or the like, it is determined that the access key is not valid. If the access key is valid (YES in S116), the process proceeds to S118. If not (S116
NO), the process proceeds to S130.

At S118, the protect check circuit 1
580 stores a valid access key.

At S120, the protect check circuit 1
580 confirms the input of the access key to the debug IF input / output circuit 1560. In S122, it is determined whether or not the access key has been input. When the access key is input (YES in S122), the process proceeds to S124. If not (NO in S122), the process is returned to S120 and debug IF input / output circuit 1560 is executed.
Wait until the access key is input to.

At S124, the debug IF input / output circuit 1
560 sends the detected access key to the protection check circuit 1580. In S126, protect check circuit 1580 compares the input access key with the stored access key. In S128, it is determined whether the access keys match. If the access keys match (YES in S128), the process proceeds to S13.
Moved to 0. If not (N at S128)
O), the process is returned to S104.

At S130, the protect check circuit 1
The 580 sets the value of the function restriction mode register 1584 to "0".

The operation of the controller according to the present embodiment based on the above structure and flowchart will be described.

When the controller 100 is powered on, the debug function control circuit 1500 is reset (S100). The protect check circuit 1580 sets the value of the function restriction mode register 1584 to "1" (S102). When the user inputs a reset release signal using the JTAG-ICE connected to the debug IF terminal 160 (YES in S106), the protection check circuit 1580 transmits a memory access control signal to the resource access circuit 1520 (S108). .

The resource access circuit 1520 reads the access key from the internal memory (S110), and the resource access circuit 1520 reads the protection check circuit 15 from the internal memory.
The read access key is transmitted to 80 (S112).
Protect check circuit 1580 determines the validity of the received access key, and if the access key is valid (YES in S116), protect check circuit 1580 stores the access key (S118).

When the user inputs an access key using JTAG-ICE connected to debug IF terminal 160 (YES in S122), the input access key is transmitted to protection check circuit 1580 (S1).
24). The protect check circuit 1580 compares the input access key with the stored access key (S
126), if the access keys match (Y in S128)
ES), the protection check circuit 1580 sets the value of the function restriction mode register 1584 to "0" (S).
130).

After the protect check circuit 1580 sets the value of the function restriction mode register 1584 to "0", the JTAG-I is passed through the debug IF terminal 160.
The control command input from the CE is decoded by the protect check circuit 1580, and the control signal is transmitted to the resource access circuit 1520 or the CPU control circuit 1540. Resource access circuit 1520 or CP
The U control circuit 1540 transfers data stored in the internal memory from the internal memory to the CP via the bus 140.
Receive data representing the internal state of U.

The protect check circuit 1580 converts the received data into the debug IF input / output circuit 1560.
And via the debug IF terminal 160 to the JTAG-ICE provided outside the controller. As a result, the internal state of the processor and the contents of the data stored in the internal memory can be known.

As described above, according to the microcontroller of this embodiment, when the target system is emulated using JTAG-ICE, the signal line connecting the JTAG-ICE and the microcontroller which is the target system. Using, the user enters the access key, and unless that access key matches the access key stored inside the controller,
Emulation function is limited. In order to cancel this restriction, it is possible to cancel the restriction by using a signal line connected to the debug IF terminal and inputting a regular access key without using a newly provided external terminal.
As a result, with a simple system, it is possible to provide a microcontroller having an emulation function that can reliably prevent resource leakage during debugging or the like.

<Second Embodiment> The second embodiment of the present invention will be described below.
The microcontroller according to the embodiment will be described.

Referring to FIG. 3, debug function control circuit 1500 of the microcontroller according to the present embodiment has access key register 1582 of debug function control circuit 1500 according to the above-described first embodiment. Absent. The other hardware configuration is the same as that of the first embodiment described above. Therefore, detailed description thereof will not be repeated here.

Referring to FIG. 4, the program executed by debug function control circuit 1500 of the controller according to the present embodiment has the following control structure. In the flowchart shown in FIG. 4, the same steps as those in FIG. 2 described above are designated by the same step numbers. The processing is the same. Therefore, detailed description thereof will not be repeated here.

When the reset release signal is input in S200, protect check circuit 1580 transmits a memory access control signal to resource access circuit 1520. At this time, an address is designated. In S202, resource access circuit 1520 reads the designated address (start address of the access key check program) in the internal memory. In S204, the resource access circuit 1520 causes the protection check circuit 1580 to operate.
The contents of the designated address are transmitted to. In S206, the protect check circuit 1580 confirms the contents of the designated address. In S208, it is determined whether the designated address is valid. If the designated address is valid (YES in S208), the process proceeds to S210.
If not (NO in S208), the process proceeds to S13.
Moved to 0.

At S210, the protection check circuit 1
580 sends an execution address change command to the CPU control circuit 1540. As a result, the execution program is changed from the normal program to the access key check program.

At S212, the debug IF input / output circuit 1
560 indicates the detected access key by the CPU control circuit 15
Send to 40. In S214, the CPU compares the input access key with the access key in the program in the program executed inside the CPU. After that, the process proceeds to S128.

The operation of the microcontroller according to the present embodiment based on the above structure and flowchart will be described. In the following description, the description of the same operation as that of the microcontroller according to the first embodiment described above will not be repeated here.

When the user inputs a reset release signal using JTAG-ICE (YES in S106), protect check circuit 1580 transmits a memory access control signal to resource access circuit 1520 (S).
200). The resource access circuit 1520 reads the designated address of the internal memory (S202). At this time, the program start address for the access key check is specified.

The resource access circuit 1520 sends the contents of the designated address to the protection check circuit 1580 (S204). Protect check circuit 1580
Confirms the contents of the designated address (S206), and if the address is valid (YES in S208), the protect check circuit 1580 causes the CPU control circuit 154 to operate.
The execution address change command is transmitted to 0 (S21
0). As a result, the program executed by the CPU is changed from the normal program to the access key checking program.

When the user inputs the access key using JTAG-ICE (YES in S122), debug IF input / output circuit 1560 transmits the input access key to CPU control circuit 1540 (S212). CP
In the program executed by U, the input access key is compared with the access key in the program (S214). If the access keys match (YES in S218), protect check circuit 1580 sets the value of function restriction mode register 1580 to "0" (S130).

As described above, the microcontroller according to the present embodiment can determine whether or not the access keys match in the program executed by the CPU.

<Third Embodiment> The third embodiment of the present invention will be described below.
The embodiment will be described. The hardware configuration of the microcontroller according to the present embodiment is the same as the above-mentioned second configuration.
This is the same as the hardware configuration of the microcontroller of the embodiment. Therefore, detailed description thereof will not be repeated here.

Referring to FIG. 5, the program executed by the microcontroller according to the present embodiment has the following control structure for debug processing. In the flowchart shown in FIG. 5, the same steps as those in FIG. 4 described above are designated by the same step numbers. The processing for them is also the same. Therefore, detailed description thereof will not be repeated here.

At S300, the CPU resets the counter (C = 1). When the input access key and the access key in the program match in the program executed by the CPU, 1 is added to the counter value in S302. In S304, the CPU determines whether the counter value is larger than the specified number of times. If the counter value is greater than the specified number of times (YES in S304
S), the process proceeds to S130. If not (NO in S304), the process returns to S120.

The operation of the microcontroller according to the embodiment of the present invention will be described based on the above structure and flowchart.

When the user inputs an access key using JTAG-ICE (YES in S122), the input access key is compared with the access key in the program in the program executed by the CPU ( S
214). If the access keys match (Y in S218)
ES), and 1 is added to the counter value (S302). When the counter value exceeds the specified number of times (YES in S304
S), the protect check circuit 1580 sets the value of the function restriction mode register 1584 to "0" (S13).
0).

As described above, according to the microcomputer of this embodiment, if the access key is input and the number of times the input access keys match does not exceed the predetermined number, the value of the function restriction mode register is set. Not changed This makes it possible to further prevent data leakage during debugging.

<Fourth Embodiment> The fourth embodiment of the present invention will be described below.
The embodiment will be described. The hardware configuration of the microcomputer according to the present embodiment is the same as the hardware configuration of the microcontroller according to the second embodiment described above. Therefore, detailed description thereof will not be repeated here.

Referring to FIG. 6, the program executed by the microcontroller according to the present embodiment has the following control structure for debug processing. In the flowchart shown in FIG. 6, the same steps as those shown in FIG. 4 are designated by the same step numbers.
The processing for them is also the same. Therefore, detailed description thereof will not be repeated here.

At S400, the CPU creates a public key by a program executed by the CPU. In S402, the CPU transmits a public key output command to debug IF input / output circuit 1560. In step S404, the debug IF input / output circuit 1560 sets the public key to the debug IF.
Output from terminal 160 to JTAG-ICE. When the access key is input by the user, in S406, the CPU
Compares the input access key and the access key based on the public key in the program executed by the CPU. In S128, it is determined whether the access keys match. If the access keys match (S12)
If YES, the process proceeds to S130. If not (NO in S128), the process returns to S400. At S130, the protect check circuit 1580
Sets the value of the function restriction mode register 1584 to "0".

The operation of the microcontroller according to the present embodiment based on the above structure and flowchart will be described.

When the user inputs a reset release signal using JTAG-ICE connected to debug IF terminal 160 (YES in S106), the specified address in the internal memory is read (S202). The contents of the designated address are confirmed (S206), and if the address is valid (YES in S208), the CPU control circuit 154
The execution address change command is sent to 0, and the CPU
Execute the access key check program (S21
0).

A public key is created by the program executed by the CPU (S400), and the CPU sends a public key output command to the debug IF input / output circuit 1560. The debug IF input / output circuit 1560 uses the public key to debug I
Output from the F terminal 160 to JTAG-ICE.

The user inputs the access key corresponding to the public key output from JTAG-ICE. When the access key is input from JTAG-ICE (S12
2), the input access key is compared with the access key based on the public key in the program executed by the CPU (S406). If the access keys match (YES in S128), protect check circuit 1580 sets the value of function restriction mode register 1584 to "0".

As described above, according to the microcontroller of this embodiment, the emulation function is not restricted by inputting the access key corresponding to the public key transmitted from the microcontroller to the JTAG-ICE. , Can be emulated. As a result, it is possible to reliably prevent resource leakage during debugging or the like.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a control block diagram of a debug function control circuit in a microcontroller according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure of control of debug processing executed by the microcontroller according to the first embodiment of the present invention.

FIG. 3 is a control block diagram of a debug function control circuit in a microcontroller according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure of control of debug processing executed by the microcontroller according to the second embodiment of the present invention.

FIG. 5 is a flowchart showing a procedure of control of debug processing executed by the microcontroller according to the third embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure of control of debug processing executed by the microcontroller according to the fourth embodiment of the present invention.

FIG. 7 is a diagram showing an overall configuration of a JTAG-ICE system related to the present invention.

FIG. 8 is a control block diagram of a debug function control circuit in the microcontroller related to the present invention.

[Explanation of symbols]

100 Micro controller, 110 CPU, 12
0 RAM, 130 ROM, 140 bus, 150, 1
500 debug function control circuit, 152, 1520 resource access circuit, 154, 1540 CPU control circuit, 156, 1560 debug IF input / output circuit, 16
0, 1600 debug IF terminal, 170 peripheral I /
O, 180 bus control circuit, 190 external bus terminal, 2
00 JTAG-ICE, 1580 Protect check circuit, 1582 Access key register, 1584
Function-restricted mode register.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B042 GA13 HH07 HH50                 5B048 AA13 DD08 DD10 FF01                 5B062 AA07 EE03 EE10 GG01 GG05                       JJ08

Claims (6)

[Claims] 1. A micro controller having an emulation function, a processor for controlling the micro controller, processor control means for reading data representing an internal state of the processor, and operation of the emulation function. A mode storage unit for storing a mode; an input / output unit connected to the processor control unit for inputting / outputting information to / from a device provided outside the microcontroller; and the processor control unit. A control unit for controlling the mode storage unit and the input / output unit, wherein the input / output unit is a unit for the device to input a control command to the processor control unit; And a means for outputting to the input / output means from the device. When the control command is input and the operation mode stored in the mode storage means satisfies a predetermined first condition, the control command is transmitted to the processor control means and the processor control means is transmitted. Means for controlling the processor control means to receive the data from the device, means for controlling the input / output means to output the received data to the device, and the input / output means When a mode change command is input from the device, the mode storage means is controlled so as to change the operation mode when the input mode change command satisfies a predetermined second condition. A microcontroller, including :. 2. A microcontroller having an emulation function, the storage device storing data, a storage device control unit for reading data from the storage device, and an operation mode of the emulation function. Mode storage means for inputting / outputting information to / from the storage device control means for inputting / outputting information to / from a device provided outside the microcontroller, the storage device control means and the mode Storage means and control means for controlling the input / output means, wherein the input / output means allows the equipment to input a control command for the storage device control means, and the data to the equipment. And a means for outputting the control command from the device to the input / output means. Then, when the operation mode stored in the mode storage means satisfies the predetermined first condition, the control command is transmitted to the storage device control means, and the data is transmitted from the storage device control means. Means for controlling the storage device control means so as to receive, and means for controlling the input / output means so as to output the received data to the device,
When a mode change command is input to the input / output unit from the device, the mode storage is changed so that the operation mode is changed when the input mode change command satisfies a second predetermined condition. A means for controlling the means. 3. The mode storage means includes means for storing either a permission mode in which the emulation function is operated or a restriction mode in which the emulation function is not operated, and the first condition is The controller according to claim 1, wherein the operation mode stored in the mode storage means is the permission mode. 4. The controller further includes release information storage means for storing information for releasing the restriction mode, wherein the second condition is that the input mode change command is the release information storage means. The controller according to claim 3, wherein the controller is a command corresponding to the information stored in. 5. The controller further includes release information storage means for storing information for releasing the restriction mode, wherein the second condition is that the input mode change command is the release information storage means. The controller according to claim 3, wherein the number of times the command is the command corresponding to the information stored in (4) satisfies a predetermined number of times. 6. The controller includes a mode change command for changing an operation mode of the emulator,
Release information storage means for storing release information corresponding to the mode change command, and the control means includes means for controlling the input / output means to output the release information to the device. Further including, the second condition is that the inputted mode change command is a mode change command corresponding to the release information stored in the release information storage means. controller.