JP2003188381A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the ESD surge resistance of a semiconductor device, e.g. an IGBT or a power MOSFET, having an insulated gate electrode and functioning as a switching transistor. <P>SOLUTION: At a lower part of an emitter electrode pad (7) and a gate electrode pad (8) and the surface layer part of a drift layer (4) on the outer circumference of an inner cell part (6), a surge protective region (16) having a cross-sectional shape identical to that of an emitter cell (5) and not provided with an emitter conductive layer (5c) is arranged contiguously to the inner cell part (6) in stripe or mesh shape at a pitch equal to or not larger than two times that of the emitter cells (5) in the inner cell part (6). A surge protective region (16) is connected electrically with the emitter electrode under ohmic contact state. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a vertical structure having an insulated gate electrode for controlling a main current on a semiconductor substrate, such as an insulated gate bipolar transistor (hereinafter referred to as an IGBT) or a power MOSFET. The present invention relates to a high output, high breakdown voltage semiconductor device that functions as a transistor.

[0002]

2. Description of the Related Art A semiconductor device, such as an IGBT or a power MOSFET, having an insulated gate electrode and functioning as a transistor for high output and high breakdown voltage is utilized as a power semiconductor device capable of voltage control. Among them, semiconductor devices used especially for automobiles are used for driving loads such as lamps and relays, and various surge voltages due to static electricity, inductive loads, etc. are applied to their output terminals. Therefore, these semiconductor devices are required to have high breakdown voltage and high surge withstand capability.

Conventionally, as a measure for increasing the surge withstand capability, the collector-emitter (power MOSFE) of an IGBT has been conventionally used.
In the case of T, a built-in clamp diode is provided between the drain and the source (Japanese Patent Laid-Open No. 64-81270), a part of the body layer is deepened to widen the width of the body layer, and a high concentration layer is formed in the body layer directly under the source. A method of forming the transistor to suppress the operation of the parasitic transistor has been developed, and the surge resistance has been gradually improved.

However, these methods are not always sufficient measures against surges with a very fast rise such as ESD (electrostatic discharge) (for example, dV / dt = 3kV, tr, tf = 100ps). , Further improvement of surge withstand capability against ESD has been demanded.

[0005]

FIG. 7 shows a typical structure of a conventional n-channel vertical IGBT, and shows the main part of the AA 'cross section near the electrode pad including the chip outer peripheral part 9 of the chip plane shown in FIG. It is a schematic representation. N ⁺ buffer layer 3 on the p ⁺ collector layer 2 is a semiconductor substrate, n ^- drift layer 4 is formed by vapor deposition or the like, n ^- the surface layer portion of the drift layer 4, p ⁺ diffusion layer 5a, An emitter cell (hereinafter, also simply referred to as a cell) 5 including a p-type semiconductor region formed of the p diffusion layer 5b and functioning as a channel region and an n ⁺ emitter layer 5c formed therein and functioning as an emitter region is an internal cell. A large number are selectively formed in the portion 6. The emitter cell 5 plays a role of passing a collector current during a normal switching operation. In addition, the emitter electrode pad 7, the gate electrode pad 8 and the chip outer peripheral portion 9
A p ⁺ well diffusion layer 12 is selectively formed in the lower part of the same by the same process as the emitter cell formation.

On the other hand, the chip outer peripheral portion 9 has a field plate (FP) structure 10 capable of maintaining a breakdown voltage by relaxing an electric field in the periphery. The field plate 10a is a conductive ring made of polysilicon, and a plurality of rings circulate around the periphery of the chip to maintain the potential of the silicon surface. Further, on the outer side thereof, an equipotential ring (EQR) 11 directly connected to the n ⁻ drift layer 4 is provided.

Conventionally, the p ⁺ well diffusion layer 12 arranged under the emitter electrode pad 7, the gate electrode pad 8 and the chip outer peripheral portion 9 in such a semiconductor device is contacted to have the same potential as the emitter electrode pad 7. Was kept at. This is because when a high voltage is applied to the collector 13,
By preventing a high electric field from being directly applied to the oxide film 15 under each electrode pad portion 14 to destroy the oxide film 15, and relaxing the electric field between the emitter cell 5 and the p ⁺ well diffusion layer 12 around the emitter cell 5. This is to prevent the breakdown voltage of the cells at specific locations such as the electrode pad portion 14 and the chip outer peripheral portion 9 from lowering as compared with the cells located inside.

The p ⁺ well diffusion layer 12 as shown in FIG.
Since the bottom surface is flat, when a high voltage is applied to the collector 13, the equipotential surface of the depletion layer extending from the bottom of the collector 13 is substantially parallel to the bottom surface. Therefore, the electric field strength is lower than that of the curved portion, which is convenient for maintaining a high breakdown voltage. However, from the viewpoint of surge withstand capability (surge absorption capacity) when a surge having a very fast rise such as ESD is applied, this p ⁺ well diffusion layer 12
Because of its flat structure, the breakdown cannot occur uniformly in the flat area that occupies most of it. At most, the breakdown occurs in the part where the electric field strength is high around the p ⁺ well diffusion layer 12 and only the surge current is absorbed. In other words, it has a very low surge absorption capacity for its size.

To make matters worse, such a large area p ⁺
Since the well diffusion layer 12 has a large parasitic capacitance (junction capacitance), the well diffusion layer 12 is charged with a large amount of electric charge when a surge having a rapid rising such as ESD is applied. Then, when the cell causes an avalanche break, it is discharged at once, and a large amount of surge current flows in the cell, especially in the vicinity of the p ⁺ well diffusion layer 12 together with the original surge current that enters from the collector 13. As a result, in the vicinity of the p ⁺ well diffusion layer 12, that is, in the vicinity of the emitter electrode pad 7, the gate electrode pad 8 and the chip outer peripheral portion 9.
There was a problem that cells in the vicinity were easily destroyed.

The present invention has been devised to solve such a problem, and the electrode pad portion 14 and the chip outer peripheral portion 9 are provided.
The nearby cells are easily destroyed by the ESD surge because the flat p ⁺ well diffusion layer 12 disposed therebelow does not avalanche break uniformly and the parasitic capacitance thereof is discharged, that is, once during the charging process. Focusing on the fact that the absorbed surge current is returned to the cells inside the chip again, the entire p ⁺ well diffusion layer 12 is efficiently avalanche broken to absorb the surge current. Accordingly, it is intended to provide a semiconductor device in which cell breakdown due to current concentration in a part of cells is avoided and the surge resistance of the entire chip is improved.

[0011]

In order to achieve the above object, a semiconductor device of the present invention comprises a well of a second conductivity type having a flat bottom surface under the emitter electrode pad, the gate electrode pad and the outer peripheral portion of the chip. A conventional emitter cell including a second conductive type second semiconductor region functioning as a channel region instead of the layer and a first conductive type semiconductor region formed in each of the second semiconductor regions and functioning as an emitter region. A surge protection region having the same cross-sectional shape and having only the second conductivity type and not having the first conductivity type semiconductor region inside is adjacent to at least the emitter cell below both the emitter and gate electrode pads and below the chip outer peripheral structure. It is formed in a portion, a portion between the emitter cell and the chip outer peripheral structure, and the like. These surge protection regions are electrically connected to the emitter electrode and have the same or similar arrangement as the emitter cell.
Stripes with a pitch less than twice or the same or 2
It was arranged to be arranged adjacent to the outer periphery of the emitter cell in a mesh shape with a pitch of twice or less.

As described above, by arranging a large number of second conductivity type surge protection regions having the same cross-sectional shape as the emitter cell adjacent to the outer periphery of the emitter cell, when an ESD surge is applied to the collector, these regions are provided. Avalanche break occurs uniformly in almost all of the surge protection region and the internal emitter cell portion. As a result, the destruction of the emitter cell due to the current concentration in a part of the emitter cell is avoided, the surge current is absorbed almost uniformly in the entire region, and the surge resistance of the entire chip is improved.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below by taking an n-channel vertical structure IGBT as an example. (First Embodiment) FIG. 1 is a diagram showing a first embodiment in which the present invention is applied to an IGBT, and is a cross-sectional structure taken along the line AA 'in the vicinity of an electrode pad including a chip outer peripheral portion 9 on the chip plane shown in FIG. Is a schematic representation of the main part of FIG. Portions corresponding to those of the conventional FIG. 7 are denoted by the same reference numerals.

An n ⁺ buffer layer 3 and an n ⁻ drift layer 4 are formed on the p ⁺ collector layer 2 which is a semiconductor substrate by a vapor phase growth method or the like, and p ⁺ diffusion is carried out in the surface layer portion of the n ⁻ drift layer 4. An emitter cell 5 including a p-type semiconductor region formed of the layer 5a and the p diffusion layer 5b and functioning as a channel region, and an n ⁺ emitter layer 5c formed therein and functioning as an emitter region is selectively provided in the internal cell portion 6. Are formed in large numbers.
The emitter cell 5 plays a role of passing a collector current during a normal switch operation.

On the other hand, the chip outer peripheral portion 9 has a field plate (FP) structure 10 capable of maintaining the breakdown voltage by relaxing the electric field in the periphery. The field plate 10a is a conductive ring made of polysilicon, and a plurality of rings circulate around the periphery of the chip to maintain the potential of the silicon surface. Further, on the outer side thereof, an equipotential ring (EQR) 11 directly connected to the n ⁻ drift layer is provided.

In this embodiment, the emitter electrode pad 7,
In place of the conventional flat bottom p ⁺ well diffusion layer 12 below the gate electrode pad 8, the p ⁺ type surge protection has the same cross-sectional shape as the emitter cell 5 and does not have the n ⁺ emitter layer 5c inside. Region (hereinafter referred to as p-type well) 16
Were arranged in a striped pattern at the same pitch as the internal cell portions 6 and adjacent to the outer edge of the internal cell portions 6, concentrically.
Similarly, at the lower part of the field plate portion 10, the same p
A plurality of mold wells 16 were arranged around the inner cell portion 6 at the same pitch as the arrangement of the inner cell portion 6 and adjacent to the outer edge of the inner cell portion 6. All of these p-type wells 16 are connected to the emitter pad 7 in an ohmic contact state.

The p-type well 16 is formed in the n ⁻ drift layer 4
The avalanche break is likely to occur because the convex portion in contact with is p ⁺ type. Further, since the n ⁺ emitter layer 5c is not provided inside, the parasitic transistor operation or the latch-up operation is hard to occur, and the structure can prevent the destruction of itself and the reduction of the surge resistance.

With this structure, when an ESD surge having a fast rise is applied to the collector 13, the p-type well 16 in the electrode pad portion 14 and the field plate portion 10 is applied.
Then, avalanche break occurs in almost all of the emitter cells 5 in the internal cell portion 6 and the surge current is absorbed.
This is a p-type well 16 having the same sectional shape as the emitter cell 5.
Are arranged at the same pitch as that of the internal cell portion 6, so that the electric field strengths at the edges of the cells and the wells become substantially the same, and avalanche breaks occur substantially evenly in the entire chip. According to the calculation result, the maximum current flowing through the internal cell portion 6 is 220 A in the conventional structure,
In this embodiment, it is 20 A or less. As described above, according to the present embodiment, it is possible to avoid the current concentration in a part of the emitter cells 5 and improve the surge withstand capability of the entire chip against ESD.

The p-type well 1 disposed below the internal cell portion 6, the electrode pad portion 14, and the field plate portion 10
Instead of the stripe shape, 6 may be arranged in a mesh shape at the same pitch as the internal cell portions 6. In that case, since the electric field strengths at the respective edge portions become closer to each other, the surge withstand capability is further improved.

Further, the p-type wells 16 may be arranged at a pitch larger than the arrangement pitch of the emitter cells 5 in the internal cell portion 6 and not more than twice. With this arrangement, the electric field strength at the edge of the p-type well 16 is increased, and the breakdown voltage of the portion where the p-type well 16 is arranged is lower than that of the internal cell portion 6. Therefore, the avalanche break of the emitter cell 5 containing the parasitic transistor is further improved. It can be effectively prevented and surge resistance can be further improved. However, if the pitch is excessively widened, the density of the p-type well 16 that absorbs the surge current decreases, and the efficiency of absorbing the surge current decreases, so it is preferable to make it twice or less.

(Second Embodiment) FIG. 2 shows the present invention in an IG.
It is a figure which shows 2nd Embodiment applied to BT, Comprising: It represents typically the principal part of AA 'cross-section structure near the electrode pad containing the chip peripheral part 9 of the chip plane shown in FIG.
Since the configuration of this embodiment is similar to that of the first embodiment,
The same components as those in FIG. 1 are designated by the same reference numerals, and only different components will be described.

In this embodiment, a chip outer peripheral portion 9 is a field plate (FP) 10a made of polysilicon,
Zener diode 17 also made of polysilicon
It has a breakdown voltage design structure that uses both. The field plate 10a is a conductive ring, and a plurality of field plates 10a circulate around the periphery of the chip to maintain the potential of the silicon surface.

The innermost field plate 10b is grounded to have the same potential as the emitter electrode pad 7, and the outermost field plate 10c is connected to the equipotential ring 11. Further, each field plate has a structure in which a plurality of Zener diodes 17 connected in reverse are connected to each other. This Zener diode 1
The potential distribution 7 is formed so as to be proportional to the square of the horizontal distance from the innermost peripheral field plate 10b, and the depletion layer extending from the lower portion of the emitter cell 5 is extended in the lateral direction in the same manner as the depth direction. It has a structure that can realize electric field relaxation in the lateral direction and high breakdown voltage.

In contrast to this structure, in the present embodiment, under the emitter electrode pad 7 and the gate electrode pad 8,
The p-type well 16 was arranged as in the first embodiment. Further, outside the inner cell portion 6 and below the field plate portion 10, the same stripe-shaped p is formed around the inner cell portion 6.
A plurality of mold wells 16 were arranged adjacent to the outer edge of the internal cell portion 6 at the same pitch as the internal cell portion 6. These p-type wells 16 are connected to the emitter electrode pads 7 in ohmic contact.

Also in this embodiment, the p-type wells 16 having the same cross-sectional shape as the emitter cells 5 are arranged at the same pitch as the internal cell portions 6, so that the electric field strengths at the edges of these cells and each well are almost the same. Will be the same. Therefore, when an ESD surge is applied to the collector 13, an avalanche break occurs in almost all of them and the surge current is absorbed almost evenly, so that the surge withstand capability of the entire chip is improved. .

Further, in the case of this embodiment, since the p-type well 16 is arranged below the grounded field plate 10b in the inner portion of the field plate portion 10, the electric field is the strongest without the p-type well 16. There is also an effect of avoiding breakdown at the edge portion of the inner field plate 10b.

In this case as well, the p-type well 16 formed in the internal cell section 6, the electrode pad section 14, and the p-type well section 18 is used.
May be arranged in a mesh shape at the same pitch as the internal cell portions 6 instead of the stripe shape. In that case, since the electric field strengths at the respective edge portions become closer to each other, the surge withstand capability is further improved.

For the same reason as described in the first embodiment, the p-type wells 16 may be arranged at a pitch larger than the arrangement pitch of the emitter cells 5 in the internal cell portion 6 and not more than twice. With this arrangement, the avalanche break of the emitter cell 5 can be prevented more effectively and the surge withstand capability is further improved.

(Third Embodiment) FIG. 3 shows an embodiment of the present invention.
It is a figure which shows 3rd Embodiment applied to BT, Comprising: It is a figure showing typically the principal part of AA 'cross section structure near the electrode pad containing the chip peripheral part 9 of the chip plane shown in FIG.
Since the configuration of this embodiment is similar to that of the second embodiment, the same components as those in FIG. 2 are denoted by the same reference numerals, and only different components will be described.

In the present embodiment, in the surface layer portion of the n ⁻ drift layer 4 where the p-type well 16 is not provided, below the field plate portion 10 in the configuration of the second embodiment,
It has a configuration in which several field limiting rings (FLR) 19 each composed of a p-type diffusion layer in which the potential is not fixed are added around the periphery of the chip. The field limiting ring 19 has a structure in which the depletion layer extending from the emitter cell 5 is extended in the lateral direction as well as in the depth direction to relax the electric field in the lateral direction and increase the breakdown voltage.

In this embodiment, the p-type well 16 is arranged below the emitter electrode pad 7 and the gate electrode pad 8 in the same manner as in the first embodiment. Further, below the field plate portion 10, between the internal cell portion 6 and the field limiting ring portion 20, the same stripe-shaped p-type well 16 is formed around the internal cell portion 6 by the same pitch as the internal cells. Then, a plurality of cells were arranged adjacent to the outer edge of the inner cell 6. These p-type wells 1
6 is connected to the emitter electrode pad 7 in an ohmic contact state.

Therefore, also in the case of this embodiment, the p-type well 16 having the same sectional shape as the emitter cell 5 is formed in the internal cell portion 6
Since they are arranged at the same pitch, the electric field strengths at the edges of the cells and the wells are almost the same. Therefore E
When the SD surge is applied to the collector 13, an avalanche break occurs in almost all of them and the surge current is absorbed almost evenly, and the surge withstand capability of the entire chip is improved.

Further, p is provided below the grounded field plate 10b in the inner portion of the field plate portion 10.
Since the p-type well 16 is arranged, the electric field becomes the strongest without the p-type well 16.
The breakdown at the edge portion of is also avoided as in the second embodiment. Also in this case, the p-type well 1 formed in the internal cell part 6, the electrode pad part 14, and the p-type well part 18
6 may be arranged in a mesh shape at the same pitch as the internal cell portions 6 instead of the stripe shape. In that case, the electric field strengths at the respective edge portions become closer to each other, which is more preferable for improving the surge withstand capability. The result comes.

For the same reason as described in the first embodiment, the p-type wells 16 may be arranged at a pitch larger than the arrangement pitch of the emitter cells 5 in the internal cell portion 6 and not more than twice. With this arrangement, the avalanche break of the emitter cell 5 can be prevented more effectively and the surge withstand capability is further improved.

(Fourth Embodiment) FIG. 4 shows an embodiment of the present invention.
It is a figure which shows 4th Embodiment applied to BT, Comprising: It represents typically the principal part of AA 'cross-section structure near the electrode pad containing the chip peripheral part 9 of the chip plane shown in FIG.
The configuration of the present embodiment is the same as that of the configuration of the third embodiment, namely, the field plate 10a and the Zener diode 17
Is not provided. The field limiting ring 19 is provided as in the case of the third embodiment. The same components as those in FIG. 3 are denoted by the same reference numerals.

Also in this embodiment, as in the third embodiment, the p-type well 16 is arranged below the emitter electrode pad 7 and the gate electrode pad 8 as in the first embodiment. . Further, as in the third embodiment, several field limiting rings 19 which are not fixed in potential are provided on the outer peripheral portion of the chip, and the p-type is also provided between the field limiting ring 19 and the internal cell portion 6. The wells 16 are arranged in stripes.

Therefore, also in this embodiment, the p-type well 16 having the same sectional shape as the emitter cell 5 is formed in the internal cell portion 6
Since they are arranged at the same pitch, the electric field strengths at the edges of the cells and the wells are almost the same. Therefore E
When the SD surge is applied to the collector 13, an avalanche break occurs in almost all of them and the surge current is absorbed almost evenly, and the surge withstand capability of the entire chip is improved.

Also in this case, the p-type well 16 formed in the internal cell portion 6, the electrode pad portion 14, and the p-type well portion 18 is
Instead of the stripe shape, they may be arranged in a mesh shape at the same pitch as the internal cell portions 6, and in that case, the electric field strengths at the respective edge portions become closer to each other, resulting in further improved results in the surge withstand capability. The same applies.

For the same reason as described in the first embodiment, the p-type wells 16 may be arranged at a pitch larger than the arrangement pitch of the emitter cells 5 in the internal cell portion 6 and not more than twice. With this arrangement, the avalanche break of the emitter cell 5 can be prevented more effectively and the surge withstand capability is further improved.

(Fifth Embodiment) FIG. 5 shows the present invention in an IG.
It is a figure which shows 5th Embodiment applied to BT, Comprising: The principal part of AA 'cross-section structure of electrode pad vicinity including the chip peripheral part 9 of the chip plane shown in FIG. 6 is typically represented. In the configuration of this embodiment, the field limiting ring unit 20 in the configuration of the fourth embodiment is set to RESURF (Reduce
d Surface Field) has been replaced with a pressure resistant design structure. RESURF is an equipotential ring (EQR) in which the collector has the same potential as the p-type diffusion layer 21 whose potential is not fixed.
11 is continuously arranged between the internal cell portion 6 fixed to the ground potential and the depletion layer is extended in the lateral direction as well as in the depth direction to relax the electric field and increase the withstand voltage. Is. Also in this case, the same components as those in FIG. 4 are designated by the same reference numerals.

Also in this embodiment, as in the fourth embodiment, the p-type well 16 is arranged below the emitter electrode pad 7 and the gate electrode pad 8 in the same manner as in the first embodiment. . Furthermore, the internal cell unit 6 and the RESURF unit 2
The stripe-shaped p is also formed by going around the internal cell portion 6 between
Form the wells 16 at the same pitch as the inner cells 6
A plurality of them are arranged adjacent to the outer edge of. These p-type wells 16 are connected to the emitter electrode pads 7 in ohmic contact.

Therefore, also in this embodiment, the p-type well 16 having the same sectional shape as the emitter cell 5 is formed in the internal cell portion 6.
Since they are arranged at the same pitch, the electric field strengths at the edges of the cells and the wells are almost the same. Therefore E
When the SD surge is applied to the collector 13, an avalanche break occurs in almost all of them and the surge current is absorbed almost evenly, and the surge withstand capability of the entire chip is improved.

Also in this case, the internal cell portion 6 and the electrode pad portion 1
4. The p-type well 16 formed in the p-type well portion 18 may be arranged in a mesh shape having the same pitch as the internal cell portion 6 instead of the stripe shape. In that case, the electric field strength of each edge portion is more uniform. It is similar to the point that the surge withstand capability is further improved because the surge tolerance is improved.

For the same reason as described in the first embodiment, the p-type wells 16 may be arranged at a pitch larger than the arrangement pitch of the emitter cells 5 in the internal cell portion 6 and not more than twice. With this arrangement, the avalanche break of the emitter cell 5 can be prevented more effectively and the surge withstand capability is further improved.

(Other Embodiments) The various embodiments described above are
Although it was about the n-channel vertical structure IGBT, the n-channel vertical structure power MOSFET is also
Basically, the p ⁺ collector layer 2 on the collector side in FIG.
It has the same configuration as the IGBT except that is not provided. And the problem of surge tolerance against ESD is this p
⁺ It is a common problem that is not related to the existence of the collector layer 2. Therefore, the power M
It can be applied to the OSFET as it is and has the same effect.

Regarding the channel type, the n-type channel semiconductor device has been described above.
The present invention can be applied to a channel type semiconductor device, that is, a semiconductor device in which the p-type conductivity type and the n-type conductivity type in the above description are exchanged, by replacing the p-type well 16 with the n-type well. , And the same effect as the case of the n-channel type.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a main part showing a first embodiment of the present invention.

FIG. 2 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 3 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

FIG. 4 is a view corresponding to FIG. 1 showing a fourth embodiment of the present invention.

FIG. 5 is a view corresponding to FIG. 1 showing a fifth embodiment of the present invention.

FIG. 6 is a plan view of an IGBT chip

FIG. 7 is a diagram corresponding to FIG. 1 showing a conventional technique.

[Explanation of symbols]

In the drawing, 1 is a chip, 2 is a p ⁺ collector layer, 3 is an n ⁺ buffer layer, 4 is an n ⁻ drift layer, 5 is an emitter cell, 5a
Is a p ⁺ diffusion layer, 5b is a p diffusion layer, 5c is an n ⁺ emitter layer,
7 is an emitter electrode pad, 8 is a gate electrode pad, 10
a is a field plate, 11 is an equipotential ring, 12 is a p ⁺ well diffusion layer, 16 is a p-type well, 17 is a Zener diode, 19 is a field limiting ring,
21 is RESURF.

Claims (10)

[Claims] 1. A first conductive type first semiconductor layer formed on a semiconductor substrate to function as a drift layer, and a plurality of second semiconductor layers formed in the first semiconductor layer to function as a channel region.
A second semiconductor region of conductivity type, a third semiconductor region of first conductivity type formed in each of the second semiconductor regions and functioning as an emitter region, and a chip outer periphery provided around the plurality of second semiconductor regions. A vertical structure having an insulated gate having a structure, an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region, and a gate electrode formed through a gate oxide film. In a semiconductor device functioning as a transistor, the second semiconductor region and the third semiconductor region are not provided in the first semiconductor layer located below the pad portion of the emitter electrode and the gate electrode, and A semiconductor device formed as a surge protection region electrically connected to an emitter electrode. 2. A plurality of the surge protection regions, which are formed in a stripe shape, are adjacent to the outer peripheral portions of the plurality of second semiconductor regions, and are arranged at the same pitch as that of the second semiconductor regions or at a pitch equal to or less than twice. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged concentrically. 3. The surge protection region, which is formed in the same island shape as the second semiconductor region, is adjacent to the outer peripheral portions of the plurality of second semiconductor regions and has the same arrangement as the second semiconductor region. 2. The semiconductor device according to claim 1, wherein the semiconductor devices are arranged in a mesh shape with a pitch equal to or less than twice. 4. The surge protection region includes a plurality of second surge protection regions.
4. The semiconductor device according to claim 1, which is also formed between an outer peripheral portion of a semiconductor region and the outer peripheral structure of the chip. 5. The surge protection region is also formed in a lower portion of the chip outer peripheral structure at least in a portion adjacent to the outer peripheral portions of the plurality of second semiconductor regions. The semiconductor device according to any one of claims. 6. The semiconductor device according to claim 1, wherein the chip outer peripheral structure includes a field plate and an equipotential ring. 7. The semiconductor device according to claim 1, wherein the chip outer peripheral structure includes a field plate, a Zener diode and an equipotential ring. 8. The chip outer peripheral structure includes a field plate, a Zener diode, a field limiting ring, and an equipotential ring, according to claim 1. Semiconductor device. 9. The semiconductor device according to claim 1, wherein the chip outer peripheral structure includes a field limiting ring and an equipotential ring. 10. The chip outer peripheral structure is RESURF.
5. The semiconductor device according to claim 1, wherein the semiconductor device comprises an equipotential ring.