JP2003114639A - Image display device - Google Patents

Abstract

(57) [Problem] To provide an image display device excellent in image quality while correcting a voltage decrease based on electric resistance of wiring with a simple configuration. SOLUTION: For input image data, correction data calculating means 14 for calculating correction data for correcting the effect of a voltage drop caused by resistance of a row wiring, and converting the number of gradations of the correction data. And a modulation means 8 for converting a signal whose pulse width has been modulated based on the correction data output from the gradation number conversion means converted by the gradation number conversion means 15 into each column. Output to wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device provided with image forming elements arranged in a matrix, for example, a plurality of surface-conduction type elements arranged in matrix and receiving electron beam irradiation thereof. It is applied to a television receiver or a display device that receives a display signal from a television signal or a computer using a display panel having a phosphor screen that emits light and displays an image, and in particular the electric power that the matrix wiring of the display panel has. The present invention relates to a signal processing unit including an image data correction unit that corrects a voltage drop of a drive voltage caused by a resistance, and a gradation number conversion unit that converts a gradation number of image data or correction data.

[0002]

2. Description of the Related Art Conventionally, as this type of image display device,
In order to correct the decrease in brightness due to the voltage drop due to the wiring resistance of the electrical connection wiring to the electron-emitting device, the correction data is calculated by statistical calculation, and the electron beam required value and the correction value are combined. An image display device having the same is disclosed in
No. 248,920.

FIG. 18 is a schematic block diagram of an image display device according to the prior art.

A configuration relating to data correction will be described below.

First, the luminance data for one line of the digital image signal is added up by the adder 206, and the correction rate data corresponding to this added value is read from the memory 207. on the other hand,
The digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing.

The multiplier 208 multiplies the brightness data for each column wiring by the correction data read from the memory 207, and the obtained corrected data is transferred to the modulation signal generator 209 to be converted into corrected data. A corresponding modulation signal is generated in the modulation signal generator 209, and an image is displayed on the display panel based on this modulation signal.

Here, like the summing process of the luminance data for one line of the digital image signal in the summing device 206, statistical calculation processing such as calculating the sum or average of the digital image signals is performed. Correction is performed based on this value.

On the other hand, regarding the dither processing of the image signal,
For example, as described in JP-A-63-213084, it is known to obtain a multi-valued image signal using a dither matrix.

[0009]

However, in the above-mentioned conventional structure, a large-scale device such as a multiplier for each column wiring, a memory for outputting correction data, and a summing device for giving an address signal to the memory is required. I needed hardware.

Further, there is a problem that the correction causes the bits of the digital data to be cut off, resulting in deterioration of the gradation of the image.

The present invention has been made to solve the above-mentioned problems of the prior art. The object of the present invention is to correct the voltage decrease based on the electric resistance of the wiring with a simple structure and to improve the image quality. An object of the present invention is to provide an excellent image display device and image display method.

[0012]

In order to achieve the above object, in the image display device of the present invention, firstly, a plurality of matrix wirings connected to a plurality of row wirings and column wirings are arranged. In an image display device including an image forming element, a scanning unit that is connected to the row wiring and sequentially scans the row wiring, and a modulation unit that is connected to the column wiring, the input image data is corrected. Correction image data calculation means for calculating correction image data that is image data that has a smooth distribution in the horizontal or vertical direction of the screen with respect to the input of the same non-zero image data. (When the same image data except 0 is input to all the elements, the distribution of the corrected image data has a smooth distribution in the horizontal or vertical direction) A means for calculating the corrected image data Gradation number conversion means for converting the number of gradations of the corrected image data output from the corrected image data calculation means, wherein the modulation means is a corrected image converted by the gradation number conversion means. It is characterized in that a modulated voltage signal is output to each column wiring based on the data.

Secondly, a plurality of image forming elements connected to a plurality of row wirings and column wirings and arranged in a matrix, and a scanning unit connected to the row wirings and sequentially scanning the row wirings, In the image display device including the modulation unit connected to the column wiring, inputting the same non-zero image data has a gentle distribution in the horizontal or vertical direction of the screen (the same image data except 0 is Correction data calculation means for calculating correction data when the distribution of correction data is smooth in the horizontal or vertical direction when input to all elements, and gradation number conversion for converting the gradation number of the correction data Means and an adding means for adding the correction data whose number of gradations has been converted and the input image data, and the modulating means outputs a modulation voltage signal to each column wiring in accordance with the output of the adding means. And it features.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions of the components described in this embodiment,
Unless otherwise specified, the material, the shape, the relative arrangement, and the like are not intended to limit the scope of the present invention thereto.

In the following embodiments, an image display device using a surface conduction electron-emitting device (hereinafter referred to as SCE) will be described in detail as an example.

(First Embodiment) An image display apparatus according to a first embodiment of the present invention will be described below with reference to the drawings.

First, an overview of the display panel of the image display device according to the embodiment of the present invention, electrical connection of the display panel, and S
The characteristics of CE will be briefly described.

The image display device is a simple matrix comprising a scanning circuit for scanning and selecting the row electrodes line-sequentially and a pulse width modulation means for varying the pulse width of the output voltage to the column electrodes according to the size of the image data. It has a display configuration.
In the following, the row wiring may be referred to as scanning wiring and the column wiring may be referred to as modulation wiring.

(Overview of Image Display Device) FIG. 2 is a perspective view of an image display device (display panel) according to an embodiment of the present invention, in which a part of the panel is cut away to show the internal structure. ing.

In the figure, 1005 is a rear plate, and 1006.
Is a side wall, and 1007 is a face plate, which form an airtight container for maintaining a vacuum inside the display panel.

On the rear plate 1005, the element substrate 10 is attached.
01 is fixed, but N × M SCEs 1002 as image forming elements are formed on the substrate 1001. The row wiring 1003, the column wiring 1004, and the SCE are connected as shown in FIG.

Here, the above-mentioned substrates 1001 and SCE100
2, a portion constituted by the row wiring 1003 and the column wiring 1004 is called a multi electron source.

On the lower surface of the face plate 1007, phosphors 1008 of three primary colors of red, green and blue are formed corresponding to each pixel.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed, and by applying a high voltage to the Hv terminal electrically connected to the metal back 1009,
A high voltage is applied between the rear plate and the face plate.

(Characteristics of SCE) As shown in FIG. 4, SCE is a characteristic of (emission current Ie) vs. (element applied voltage Vf),
And (device current If) vs. (device applied voltage Vf) characteristics. Note that the emission current Ie is significantly smaller than the device current If and it is difficult to illustrate the same scale,
The two graphs are shown on different scales.

That is, the emission current Ie has the following three characteristics.

First, when a voltage equal to or higher than the threshold voltage Vth is applied to the element, the emission current Ie rapidly increases. On the other hand,
The emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the SCE has a high speed response, the emission time of the emission current Ie can be controlled by the application time of the voltage Vf.

In the image display device using the display panel shown in FIG. 2, if the first characteristic is utilized, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the selected element according to the desired emission brightness. However, the threshold voltage Vt is applied to the non-selected element.
A simple matrix display can be performed by applying a voltage of less than h and sequentially scanning to select elements.

By utilizing the second characteristic,
By modulating the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled, and gradation display by amplitude modulation can be performed.

Further, by utilizing the third characteristic,
By modulating the time of applying the voltage Vf to the element,
The emission time of the phosphor can be controlled, and gradation display by pulse width modulation (PWM) can be performed.

(Display Panel Driving Method) FIG. 5 shows an example of voltages applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel according to the embodiment of the present invention is driven.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light.

In order to cause the pixels in the i-th row to emit light,
The scanning wiring of the i-th row is selected and its voltage supply terminal D
The selection potential Vs is applied to xi. Further, the voltage supply terminals Dxk (k = 1, 2, ... N, where k ≠ i) of the other scanning wirings are set in the non-selected state and the non-selection potential Vns is applied.

In this example, the selection potential Vs is set to -0.5V _SEL which is half the voltage V _SEL shown in FIG.
ns is the GND potential.

A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is conventionally i-th row, j-th
The pulse width modulation signal according to the size of the image data of each pixel is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel of the column.

In this embodiment, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring in order to correct the decrease in luminance due to the influence of the voltage drop is displayed. The pulse width modulation signal is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel at the i-th row and the j-th column of the image and the correction amount thereof.

In this embodiment, the voltage Vpwm is +
It was set to 0.5V _SEL .

(Regarding Voltage Drop in Scan Wiring) As described above, the object of the present invention is to increase the potential on the scan wiring due to the voltage drop in the scan wiring of the display panel, and thus the voltage applied to the SCE. Is reduced, S
That is, the emission current from CE is reduced. The mechanism of this voltage drop will be described below.

Although depending on the design specifications and manufacturing method of the SCE, the device current for one device of the SCE is about several 100 μA when the voltage V _SEL is applied.

Therefore, in the case where only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the device current flowing from the modulation wiring to the scanning wiring of the selected row is 1. Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state, so that the current The sum is several hundred mA
The number becomes A and a voltage drop occurs on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scan wiring, SC
The voltage applied across E decreases. Therefore SCE
The emission current emitted from the device was reduced, and as a result, the emission brightness was reduced.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

The pulse width modulation signal supplied to each column is shown in FIG.
In the case of outputting a pulse width modulation signal whose pulse width depends on the size of the input data and whose rising edge is synchronized with respect to the input data as shown in, it depends on the input image data Since the number of pixels that are lit is large at the beginning of one horizontal scanning period and then the pixels are turned off in order from a place with low brightness, the number of lit pixels decreases with time in one horizontal scanning period. .

Therefore, the magnitude of the voltage drop generated on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulation signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulation signal.

The voltage drop in the scanning wiring, which is the fundamental problem of the present invention, has been described above.

Next, a method of correcting the influence of the voltage drop, which is a feature of the embodiment of the present invention, will be described.

(Calculation Method of Voltage Drop) In order to obtain the correction amount for reducing the influence of the voltage drop, first of all, as the first step, hardware for predicting the magnitude of the voltage drop and its change with time is required. It is said that However, the display panel of the image display device according to the embodiment of the present invention is generally provided with thousands of modulation wirings, and the voltage drop at the intersection of all the modulation wirings and the scanning wirings is calculated. It is very difficult, and it is not realistic to make the hardware that calculates it in real time.

Therefore, the voltage drop amount is obtained by blocking the position of the same row and also blocking in the size direction of the image data.

Such blocking is based on the following characteristics of voltage drop.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scanning wiring is a spatially continuous amount on the scanning wiring and is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes at each time corresponding to one gradation of pulse width modulation. Either becomes smaller or maintains its size. That is, the driving method as shown in FIG. 5 does not increase the magnitude of the voltage drop in one horizontal scanning period.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degeneration model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 6
(A) is a figure for explaining a block and a node at the time of performing degeneracy in an embodiment of the invention.

In order to simplify the drawing, in the figure, S connected to the selected scanning wiring, each modulation wiring and their intersections.
Only CE is listed.

At a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

Further, as shown in the figure, a block is defined by grouping n modulation wirings, selected scanning wirings intersecting with them, and SCEs arranged at the intersections thereof as one group. In this example, it is divided into 4 blocks.
It was divided into two blocks.

A position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the same row in the degenerate model. Here, the divided blocks are composed of SCEs connected to the regions of the scanning wiring divided by the nodes (reference points).

In this example, node 0 is placed at the block boundary position.
~ 5 nodes of node 4 were set.

FIG. 6B is a diagram for explaining the degenerate model.

In the degenerate model, n modulation wirings included in one block in FIG. 9A were degenerated to one, and the scanning wirings were connected so as to be located at the center of the block.

A current source is connected to the modulation wiring of each centralized block, and the sum total (statistical amount) IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3) is a current represented by the following equation.

[0068]

[Equation 1] In addition, the potentials at both ends of the scanning wiring are Vs in the example of FIG.
On the other hand, the GND potential in FIG. 6B is that in the degenerate model, the current flowing into the scanning wiring selected from the modulation wiring is modeled by the above current source, so that the voltage of each part on the scanning wiring is This is because the amount of drop can be calculated by calculating the voltage (potential difference) of each unit with the power supply unit as the reference potential.

Further, the SCE is omitted because, when viewed from the selected scan wiring, if an equivalent current flows from the column wiring, the generated voltage drop itself changes regardless of the presence or absence of SCE. Because there is no. Therefore, here, by setting the current value flowing from the current source of each block to the current value (Equation 1) of the sum of the element currents in each block, SCE
Was omitted.

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring of one section (here, one section is the intersection of the scanning wiring with a certain column wiring and its adjacent area. In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[0072]

[Equation 2] That is,

[Equation 3] However, aij is a voltage generated at the i-th node when a unit current is injected only into the j-th block in the degenerate model (hereinafter, this is defined as aij).

The above aij is derived by Kirchhoff's law, and may be calculated once and stored as a table.

Further, the summation currents IF0 to IF3 of each block defined by the equation 1 are approximated by the equation 4.

[0075]

[Equation 4] However, in the above formula, Counti is a variable that takes 1 when the i-th pixel on the selected scanning line is in the lighting state and takes 0 when it is in the unlit state.

IFS is the voltage V _SEL across the SCE1 element.
Is a quantity obtained by multiplying the element current IF flowing when the voltage is applied by a coefficient α having a value between 0 and 1.

That is, it is defined by the following equation.

[0078]

[Equation 5] Equation 4 assumes that a device current proportional to the number of lights in each block flows into the selected scan line from the column line of each block. At this time, a coefficient α is added to the element current IF of one element.
The element current IFS for one element is obtained by multiplying by the following reason.

Originally, in order to calculate the voltage drop amount, it is necessary to repeatedly calculate the voltage increase of the scanning wiring due to the voltage drop and the decrease amount of the device current due to it, but this convergence calculation is performed by hardware. It is not realistic to calculate.

Therefore, in the embodiment of the present invention,
Approximately αIF is used as the convergent value of IF. Specifically, the IF when the amount of voltage drop is maximum (when all white)
The rate of decrease (= α1) and the rate of decrease of IF (= α2) when the voltage drop amount is (minimum = 0) are estimated in advance, and the average value of α1 and α2 or 0.8xα1 is obtained. .

FIG. 6C shows an example of the result of calculating the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

By using the degenerate model as described above, it is possible to calculate the voltage drop for each node at a desired time point with respect to arbitrary image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degeneration model.

The voltage drop that occurs on the selected scan wiring changes with time within one horizontal scanning period. For this, at several times (reference times) during one horizontal scanning period.
For that, the lighting state at that time was obtained, and it was predicted by calculating the voltage drop for the lighting state using a degenerate model.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

Now, as one example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. And

That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output for one horizontal scanning period, and when the input data is 128, the one horizontal scanning period is output. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the rise time (start time) of the pulse width modulation signal can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than zero.

Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

By thus comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 means immediately after the start time (rise in this case) of the pulse width modulation signal. Is defined as representing the time of day.

The time slot = 64 is defined as a time when 64 gradations have elapsed from the start time of the pulse width modulation signal.

In the present example, the pulse width modulation is an example in which the pulse width from the rising time is used as the reference, and the pulse width is modulated based on the falling time of the pulse. However, it goes without saying that the same can be applied, although the advancing direction of the time axis is opposite to the advancing direction of the time slot.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the degeneracy model. You can

FIG. 7 shows an example in which the voltage drop is repeatedly calculated for certain image data, and the time change of the voltage drop in the scanning wiring is calculated (the voltage drop and the time change thereof shown here are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The voltage drop at each time was calculated discretely by applying the degenerate model to each of the four time points of 8, 192.

In FIG. 7, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easy to see, and the voltage drop calculated by this degenerate model is □, ○, △. It was calculated discretely at the position of each node shown in.

The present inventors examined a method of calculating correction data for correcting image data from the amount of voltage drop as the next step after the magnitude of voltage drop and its change over time can be calculated.

FIG. 8 is a graph in which the emission current emitted from the SCE in the lighting state is estimated when the voltage drop shown in FIG. 7 occurs on the selected scan wiring.

The vertical axis represents the amount of the emission current at each position at each time in percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the horizontal axis represents the horizontal position. There is.

As shown in FIG. 8, at the horizontal position (reference point) of the node 2, the emission current when the time slot = 0 is Ie0, and the emission current when the time slot = 64 is Ie.
e1, emission time when time slot = 128 is Ie
2 and the emission current when the time slot is 192 is Ie3.

FIG. 8 is calculated from the graph of the voltage drop amount of FIG. 7 and the “driving voltage vs. emission current” of FIG. Specifically, it is simply a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage V _SEL is applied.

Therefore, the figure only means the current emitted from the SCE in the lighting state, and the SCE in the non-lighting state does not emit the current.

A method of calculating correction data for correcting image data from the amount of voltage drop will be described below.

FIGS. 9A, 9B, and 9C are views for explaining a method of calculating correction data of the voltage drop amount from the time change of the emission current of FIG. The figure is 64
It is an example of calculating the correction data for the image data.

The emission amount of luminance is nothing but the emitted charge amount obtained by temporally integrating the emission current by the emission current pulse.
Therefore, in the following, when considering the variation of the brightness due to the voltage drop, the description will be given based on the amount of the emitted charges.

The emission current when there is no influence of the voltage drop is IE, and the time corresponding to one gradation of the pulse width modulation is Δt.
Then, when the image data is 64, the emission charge amount Q0 to be emitted by the emission current pulse is obtained by multiplying the amplitude IE of the emission current pulse by the pulse width (64 × Δt).
It can be expressed as follows.

[0110]

[Equation 6] However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scan wiring.

The emission charge amount by the emission current pulse considering the influence of the voltage drop can be calculated approximately as follows.

That is, the time slot of node 2 =
The emission currents of 0 and 64 are Ie0 and Ie1, respectively, and 0
If it is approximated that the emission current between .about.64 changes linearly between Ie0 and Ie1, the emission charge amount Q1 during this period can be calculated as follows, ie, the trapezoidal area of FIG. .

[0113]

[Equation 7] Next, as shown in FIG. 9C, it is assumed that the influence of the voltage drop can be removed when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop.

When the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot is considered to change, but here, for simplification,
As shown in FIG. 9C, it is assumed that the emission current is Ie0 at time slot = 0 and the emission current is Ie1 at time slot = (64 + DC1).

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the emission charge amount Q2 due to the emission current pulse after correction can be calculated as follows.

[0117]

[Equation 8] If this is equal to Q0, then

[Equation 9] If you solve this for DC1,

[Equation 10] Becomes

In this way, the correction data when the image data was 64 was calculated.

That is, the size of the position of node 2 is 6
For the image data of No. 4, as shown in Expression 9, CDa
The correction amount may be added by ta = DC1.

Similarly, for the image data of size 192, the correction amount can be obtained for each of the three periods as shown in FIG.

When the pulse width is 0, of course, there is no influence of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

Incidentally, as described above, 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

An example of discrete correction data for certain input image data obtained by this method is shown in FIG. 11 (a). In the figure, the horizontal axis corresponds to the horizontal display position, and the position of each node is described. The vertical axis represents the size of the correction data.

The discrete correction data is calculated for the positions of the nodes indicated by □, ○, ●, and Δ in the figure and the size of the image data Data (image data reference value = 0, 64, 128, 192). There is something.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node and does not give the correction data at any horizontal position (column wiring number). Absent. At the same time, correction data for image data having some predetermined reference image data size at each node position and not providing correction data according to the actual image data size are not provided. Absent.

Then, a method of calculating correction data for arbitrary image data of each column wiring by linearly interpolating the correction data calculated discretely will be described.

FIG. 11B shows the image data Dat at the position x between the node n and the node n + 1.
It is the figure which showed the method of calculating the correction data equivalent to a.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the node n and the node n + 1.

Data, which is the input image data, has a value between two image data reference values Dk and Dk + 1 for which correction data has already been calculated discretely.

Now, the correction data for the reference value Dk of the k-th image data of the node n is CData [k] [n].
The correction data CA for the image data Dk at the position x is CData [k] [n] and CD
The value of ata [k] [n + 1] can be used to calculate as follows by linear approximation.

[0131]

[Equation 11] Further, the correction data CB of the image data Dk + 1 at the position x can be calculated as follows.

[0132]

[Equation 12] By linearly approximating the correction data of CA and CB, the correction data C for the image data Data at the position x is obtained.
D can be calculated as follows.

[0133]

[Equation 13] As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, the calculation can be easily performed by the method described in Expressions 10 to 12. The broken line connecting the nodes in FIG. 11A is the result of interpolating the discrete correction data by the above calculation. As can be seen from the figure, in the voltage drop correction method of the present invention, no voltage drop occurs when the image data is 0, so the same correction data is calculated for the position x (of course, the correction data may be 0). For the same image data whose image data is not 0, correction data having a gentle distribution is calculated for the position x, that is, the horizontal direction of the screen. However, when the direction of the scanning line is the vertical direction of the screen, the correction data has a gentle distribution in the vertical direction of the screen.

If the correction data calculated in this way is added to the image data to correct the image data and pulse width modulation is performed according to the corrected image data, the image quality due to the voltage drop, which has been a problem in the past, has been solved. Can be reduced and the image quality can be improved.

(Explanation of Functions of Entire System and Main Parts) FIG. 1 is a block diagram showing an outline of a circuit configuration of an image display device according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 is a display panel, and Dx1 to Dx.
xM and Dx1 ′ to DxM ′ are terminals of scan wirings of the display panel, Dy1 to DyN are terminals of modulation wirings of the display panel,
Hv is a high voltage terminal for applying an acceleration voltage between the face plate and the rear plate, and Va is a high voltage power supply.

Reference numeral 2 is a scanning circuit, 3 is a synchronizing signal separating circuit, 4 is a timing generating circuit, and 7 is a converting circuit for converting the YPrPb signal into RGB by the synchronizing separating circuit. Further, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, 8 is a pulse width modulation means for outputting a modulation signal to the modulation wiring of the display panel, and 12 is image data and correction data. An adder for adding and outputting the corrected image data Dout, 14 is a correction data calculating means, and 15 is a gradation number converting means.

Further, in the figure, R [7: 0], G
[7: 0], B [7: 0] are 8-bit width RGB input image data, gR [7: 0], gG [7: 0], gB.
[7: 0] is 8-bit width image data that has been subjected to the inverse γ conversion processing, and Data [7: 0] is serial 8-bit width image data that has undergone parallel / serial conversion by the data array conversion unit. .

CD [9: 0] has 10-bit width correction data, DZ [7: 0] has gradation number-converted 8-bit width correction data, and Dout [7: 0] has correction data added. The image data has a width of 8 bits.

(Adder 12) The adder 12 is means for adding the correction data CD and the image data Datb from the correction data calculating means. Image data D can be obtained by adding
ata is corrected and transferred to the shift register as image data Dout.

The image data Data and the correction data C
Although overflow may occur in the adder when D is added, in contrast to this, in this example, as a configuration for preventing overflow, the maximum value when the image data Data and the correction data CD are added is set. Accordingly, the bit width of the adder and the bit width of the subsequent modulation means were determined.

More specifically, in the case of the image display device of this example, the maximum correction data is 120 when the image data is all 255, so the maximum value of the output of the adder = 2.
Since 55 + 120 = 375, the number of output bits of the adder is 9 bits, and the number of bits of the modulation means is also 9 bits, so that the number of bits of each part is determined.

As another configuration for preventing overflow, the maximum value of the correction data to be added is estimated in advance and image data is set so that overflow does not occur when the maximum value is added. The range that can be taken may be made small in advance.

In order to reduce the size of the image data, for example, the input image data may be limited when it is A / D converted, or a multiplier may be provided to make the input image data 0. The magnitude may be limited by multiplying the gain by 1 or more.

A limiter may be provided in the correction data output section.

(Delay Circuit 19) The image data SData rearranged by the data array converter is input to the correction data calculation means and the delay circuit (delay means) 19. The correction data interpolating unit of the correction data calculating means refers to the horizontal position information x and the image data SData from the timing control circuit and calculates the correction data CD suitable for them.

The delay circuit 19 is provided to absorb the time required for calculating the correction data, and when the correction data is added to the image data by the adder, the correction data corresponding to the correction data is correctly added to the image data. It is a means to delay so that it is done. The same means can be configured by using a flip-flop.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 12A, the modulation means is a pulse width modulation circuit (PWM circuit) provided with a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring.

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 12 (b).

FIG. 3C shows an example of the output waveform of the modulation means 3
Show one.

In the figure, the upper waveform is the waveform when the input data to the modulating means is 0, the central waveform is the waveform when the input data to the modulating means is 256, and the lower waveform is the modulating means. This is a waveform when the input data to 511 is 511.

In this example, the input data D to the modulation means is
The number of bits 1 to DN is set to 9 bits in consideration of the fact that overflow does not occur, as described above.

In the above description, when the input data of the modulation means is 511, there is a part that a modulation signal having a pulse width corresponding to one horizontal scanning period is output.
More specifically, as shown in FIG. 7C, although it is a very short time, a period in which the pulse is not driven and before the pulse is driven is provided to allow a timing margin.

(Correction Data Calculation Means) The correction data calculation means is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. The correction data calculation means is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

The discrete correction data calculation unit is means for calculating the amount of voltage drop from the input video signal and calculating the correction data discretely from the amount of voltage drop. In order to reduce the amount of calculation and the amount of hardware, the means introduces the concept of the above-mentioned degenerate model and calculates correction data discretely.

The correction data calculated discretely is interpolated by a correction data interpolating unit (correction data interpolating means), and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) The discrete correction data calculation unit divides the image data into blocks, calculates a statistic amount (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic amount. Function as a voltage drop amount calculation unit that calculates the change over time, a function that converts the voltage drop amount for each time into a light emission brightness amount, and the light emission brightness amount is integrated in the time direction to calculate the total light emission brightness amount. function,
And means for calculating correction data for the reference value of the image data at discrete reference points from them.

(Correction Data Interpolation Unit) The correction data interpolation unit is a means for calculating correction data suitable for the position (horizontal position) where the image data is displayed and the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

(Operation Timing of Each Part) FIG. 15 shows a timing chart of the operation timing of each part.

In the figure, Hsync is a horizontal synchronizing signal, and DotCLK is a PLL in the timing generation circuit.
A clock generated by the circuit from the horizontal synchronizing signal Hsync, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion,
Dout is image data that has been subjected to voltage drop correction, TSF
T is a shift clock for transferring the image data Dout to the shift register 5, Dataload is a load pulse for latching data in the latch circuit 6, and Pwms
start is the start signal of the above-mentioned pulse width modulation, the modulation signal X
D1 is an example of a pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the figure, in the horizontal scanning period I, when the input image data is represented by R_I, G_I, and B_I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. , Is output as digital image data Data_I according to the pixel arrangement of the display panel.

R_I, G_I and B_I are input to the correction data calculating means in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, the correction data interpolating unit interpolates the discrete correction data in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array converting unit, and the correction data is calculated. To be done. The interpolated correction data is immediately subjected to gradation number conversion by the gradation number conversion unit 15 and supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CDz to obtain the corrected image data D.
Transfer out to the shift register. The shift register sets the image data Do for one horizontal period according to Tsft.
ut is stored, serial-parallel conversion is performed, and parallel image data ID1 to IDN are output to the latch circuit 6. The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register according to the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such an image display device, the amount of voltage drop in the scanning wiring, which has been a problem in the past, can be corrected, and the deterioration of the displayed image caused by it can be improved. It was possible to display a very good image.

Further, the correction data can be calculated very easily by calculating the correction data discretely and interpolating between the points calculated discretely. It was very effective, as it could be achieved with simple hardware.

Further, there is a feature that the influence of an error when the correction data is calculated is conspicuous at a small portion of the image data. On the contrary, in the area where the size of the image data is large, the size of the image data itself is large, so that the influence of the error when the correction data is calculated is not noticeable.

In view of such characteristics, from the viewpoint of reducing the correction error, the interval for setting the image data reference value is set finely in a small area of the image data,
On the contrary, in the area where the size of the image data is large, it is preferable to set a rough interval for setting the image data reference value.

(Second Embodiment) In the first embodiment, the reference value of the discrete image data is set for the input image data, and the reference point is set on the row wiring. The correction data for the image data having the size of the image data reference value at the reference point was calculated.

Further, the correction data calculated in accordance with the horizontal display position of the input image data and its size is calculated by interpolating the correction data calculated discretely, and the correction data is added to the image data to correct the correction data. Was realized.

On the other hand, the same correction can be performed by the following configuration in addition to the above configuration.

The correction result of the image data with respect to the discrete horizontal position and the image data reference value (that is, the sum of the discrete correction data and the image data reference value: that is, the corrected image data) is calculated, and further calculated discretely. The correction result may be interpolated, the correction result corresponding to the horizontal display position of the input image data and its size may be calculated, and the modulation may be performed according to the correction result.

With this configuration, it is not necessary to add the image data and the correction data after the interpolation, because it is calculated as the result of the addition of the image data and the correction data in the discrete calculation. The corrected image data calculated in this way also has a distribution similar to that shown in FIG. That is, when the image data is 0, no voltage drop occurs, so the position x
For the same image data whose image data is not 0, the corrected image data having a smooth distribution is calculated for the position x, that is, the horizontal direction of the screen. However, when the direction of the scanning line is the vertical direction of the screen, the corrected image data has a gentle distribution in the vertical direction of the screen.

(Gradation Number Converting Means) Next, the gradation number converting means which is a main part of the embodiment of the present invention will be described.

As described above, the correction data of the voltage drop is 1 when the image data is 8 bits.
The correction data was calculated with 0-bit accuracy. That is, the MSB of the correction data corresponds to the most significant bit (hereinafter, referred to as MSB) of the image data, and the correction data is calculated with high precision by 2 bits after the decimal point.

In the case of this embodiment, the 10-bit correction data needs to be converted into 8-bit correction data because the number of gradations of the modulation means is 8 bits.

Therefore, in the present embodiment, the 10-bit data is converted to 8-bit by using the dither method in order to express the pseudo gradation of 10 bits by the 8-bit correction data.

That is, as shown in FIG. 23 (a), the gradation number converting means of this embodiment converts the 10-bit correction data CD [9: 0] into the 8-bit correction data DZ [7] by the dither method. : 0].

In the figure, reference numeral 2121 denotes a dither table, 2
122 is an adder.

The dither table 2121 corresponds to the horizontal address position and the vertical address position of the correction data.
Output dither data Q0.

The horizontal address position and the vertical address position of the correction data are the horizontal address position and the vertical address position of the image data to be corrected by the correction data.

More specifically, H = '1' when the horizontal address position of the correction data is odd, H = '0' when the horizontal address position is even, and V = when the vertical address position is odd. If V = "0" when it is "1" or an even number, the dither data Q0 defined by Fig. 14B is output depending on the states of H and V.

The output Q0 of the dither table is the adder 212.
2 is added to the correction data CD [9: 0], and the correction data CDz [9: 0] after the addition has the lower 2 bits truncated by the truncating means, and the 8-bit correction data D
Z [7: 0] (that is, CDz [9: 2]).

If such a gradation number converting means is used, 1
Not only can 0-bit correction data be converted to 8-bit correction data in terms of the number of gradations, but the area gradation can also be used to artificially represent the number of gradations equivalent to 10 bits with 8-bit image data. Therefore, the correction can be performed very well.

The method of reflecting the lower 2 bits of the correction data in the upper 8 bits by the dither method may not be the method of performing the dither in the spatial direction as described above.
The present inventors have confirmed that the method of expanding in the time direction is also effective.

To apply dither in the time direction, the process shown in FIG.
In the example, the dither data is changed depending on the horizontal address position and the vertical address position, but the dither data Q0 may be changed depending on the horizontal address position and the frame (odd frame / even frame). , It may be changed according to the vertical address position and frame,
Even a combination of them can be configured.

The dither method may be a random dither method in which a random random number sequence is added to the correction data and then quantization is performed instead of the above-mentioned dither table. Further, as described with reference to FIG. 14, a systematic dither method in which a dither matrix (dither table) such as a Bayer matrix is added to the correction data and the lower bits are discarded may be used.

Further, even if it is not the dither method, it is not particularly limited to this as long as it is a method of converting gradation and halftone can be expressed. For example, the error diffusion method may be used.

As described above, by making the minimum resolution of the correction data smaller by the dither method and making the correction, it is possible to make the later-described interference pattern caused by the correction inconspicuous. .

(Advantage of Calculating Correction Data with High Accuracy) FIG. 16 is a diagram for explaining an interference pattern confirmed when the accuracy of the correction data is calculated with the same number of bits as the image data. is there.

FIG. 16A shows an image for one screen of an image to be displayed, which is input image data in which a white window is arranged in the center of a gray background.

FIG. 17B shows the line AA ′ shown in FIG.
In the image data for one horizontal scanning period on the scanning line indicated by, the horizontal axis represents the horizontal position of the screen, and the vertical axis represents the size of the image data.

FIG. 16C shows image data when the image data shown in FIG. 16B is corrected, where the horizontal axis is the horizontal position and the vertical axis is the size of the corrected image data. Is represented.

FIG. 19D is an image of a screen when modulation is performed using the image data corrected as shown in FIG.

FIG. 19E is a diagram for explaining an interference pattern generated when the white window pattern as shown in FIG. 11A is moved in the horizontal direction.

As described with reference to FIG. 1, the image display device of the present embodiment has the scanning circuits 2 and 2'at both ends of the scanning wiring of the display panel. Therefore, the voltage drop of the scanning wiring is larger toward the center and the correction data of the voltage drop is larger toward the center of the screen. For example, the image data of FIG. 16B becomes the image data as shown in FIG. Will be corrected.

However, when further examining FIG. 16C, it can be said that the correction data is very smooth by the above-mentioned linear approximation, but when it is enlarged, the correction data is shown in FIG. As shown in the figure, it is composed of a stepwise pattern in which the minimum resolution of the modulation means is used as a unit. The fact that the correction data is applied in the form of a staircase pattern is almost unknown when a still image is displayed as shown in FIG. If made with a bit).

On the other hand, as shown in FIG. 16 (e), when the white window pattern continuously moves in the horizontal direction, it is visually confirmed that the vertical line pattern moves to the side of the window accordingly. did it. At this time, the vertical line pattern is the stepwise pattern of the correction data described above.

In this correction method, the voltage drop correction data is calculated and corrected in real time with respect to the image data in one horizontal scanning period. Therefore, even in this stepwise pattern, the white window continuously moves. Move at the same time in the horizontal direction.

When the vertical line pattern is a moving image, it is confirmed that
What is not confirmed in the case of a still image is due to human visual characteristics, and moving objects have higher visibility than stationary objects.

In this embodiment, the case where the number of gradations of the modulation means is 256 is explained, but it is 6
In the case of 4 gradations, it may be confirmed even in a still image.

Similarly, in an image display device in which the emission brightness of the display panel is higher, the brightness amount corresponding to one gradation of the modulation means becomes large, so that it may be confirmed even in a still image.

In view of the above contents, the inventors calculated the accuracy of the correction data with higher accuracy and further reduced the minimum resolution of the correction data to make the vertical line-shaped interference pattern inconspicuous. confirmed.

In the present embodiment, the correction data is calculated with 10 bits and converted into 8-bit correction data having a pseudo gradation equivalent to 10 bits by the dither method.

Further, when 8-bit correction data and 8-bit image data were added and the modulation was applied according to the addition, vertical line-shaped interference patterns could hardly be confirmed.

It should be noted that the above-mentioned interference pattern is confirmed when displaying a special image as described above (especially an image having a small high spatial frequency), but when displaying a normal television image. I don't care.

However, the present inventors have confirmed that the above-mentioned disturbing feeling may occur due to computer images and the like, and thought that it is important to display an image that does not cause discomfort even in such a case. Further, when the scale of hardware is estimated, the increase in hardware due to it is not a big problem. Therefore, the image display device according to the embodiment of the present invention was manufactured by providing the gradation number conversion means described above.

Although the number of bits of the modulation means is 8 bits, the number of bits of image data is 8 bits, and the number of bits of the correction data before gradation number conversion is 10 bits, there is no particular limitation.

In this example, the number of bits of the image data is 8 bits and the number of bits of the modulation means is 8. However, the number of bits of the image data is not limited to this, and the number of bits of the image data is larger than that of the modulation means. May be less.

In this example, the number of bits of the integer part of the correction data is set to 8 bits, but the number of bits of the integer part may be determined according to the size of the correction data itself.

For example, when a display panel with a very large voltage drop is used, the correction data may exceed 255. In such a case, the integer part may be calculated as 9 bits.

More generally, this embodiment includes the following configurations.

The number of bits of the modulation means is K bits (K is K>
If the number of bits of image data is K bits, the following is obtained.

(1) From K-bit image data to (k +
L) bit (k, L is a positive integer) correction data is calculated.

However, the image data is data having an integer part of K bits and a decimal part of 0 bits. The correction data is data having a k-bit integer part and an L-bit decimal part.

(2) The number of gradations of the (k + L) -bit correction data is converted to calculate k-bit correction data.

However, the gradation number converted k-bit correction data is data having a k-bit integer part and a 0-bit fractional part, and the decimal point of the (k + L) -bit correction data is dithered or the like. The data is expanded and converted into k-bit data by the number of gradations.

(3) The K-bit image data and the gradation-number-converted k-bit correction data are added in consideration of the above-mentioned decimal point. As a result of the addition, the corrected image data becomes K′-bit image data.

(4) Modulation is performed based on the corrected K'bit image data.

In the above (1), the number of bits of the integer part of the correction data is k bits (k is an integer of 0 <k). However, it may be determined according to the maximum value of the correction data, and K = k. It may be.

For example, if the maximum value when the correction becomes maximum is 63, the number of bits of the integer part of the correction data may be 6 bits, and it is not necessary to calculate the correction data of 8 bits as described above. May be.

On the contrary, the maximum value when the correction becomes maximum is 3
If it is 00, the number of bits of the integer part of the correction data is 9
Bit needed.

(Third Embodiment) FIG. 17 is a block diagram of an image display device according to a third embodiment of the present invention.

The difference between the third embodiment and the first embodiment is as follows.

(1) In order to perform the processing of the inverse γ processing section described in the first embodiment with higher quality, 8-bit input 1
It is composed of a 0-bit output memory.

(2) 10-bit image data and 10-bit correction data are added by a 10-bit adder.

(3) The 10-bit image data resulting from the addition is converted into 8-bit by the gradation number conversion unit. At this time 1
The lower 2 bits are expanded by dither and reflected in the upper 8 bits so that 0-bit pseudo gradation is expressed.

In this embodiment, 1 is set by dither.
As for the method of converting the number of gradations of 0-bit data to 8 bits, the number of gradations can be converted by the method described with reference to FIG. 14 as in the first embodiment.

When an image is displayed by such an image display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and it is possible to improve the deterioration of the displayed image due to it. It was possible to display a very good image.

Further, by increasing the number of bits of the inverse γ conversion processing section, the error in the inverse γ processing can be reduced.

Further, the correction data calculated by the 10-bit voltage drop and the 10-bit image data after the inverse γ processing are added, and the number of gradations is converted to the addition result, and 10 bits are converted into 8 bits. By performing the gradation number conversion on the bit data, when compared with the alternative configuration described below,
It has an excellent effect.

The following configuration can be considered as an alternative configuration of the present embodiment.

(1) The gradation number conversion is performed on the image data that has been subjected to the inverse γ processing on 10 bits, and the conversion from 10 bits to 8 bits is performed.

(2) The gradation data is converted from the 10-bit correction data, and the conversion from 10 bits to 8 bits is performed.

(3) The 8-bit image data whose gradation number has been converted and the 8-bit correction data are added and corrected.

In contrast to the above configuration, the configuration of the present embodiment is characterized in that the number of gradations is converted after the addition process is performed. By performing the addition process with higher accuracy, an error due to calculation occurs. It is excellent in that it does not exist.

Further, by converting the addition result calculated with high accuracy by the gradation number converting means 16, it is possible to display as a pseudo gradation corresponding to 10 bits, and it is possible to display a higher quality image. There was another effect of being able to do it.

Further, in the configuration of this embodiment, the number of bits of the image data after the inverse γ processing is 10 bits, the number of bits of the correction data is 10 bits, and the number of bits of the input signal to the modulating means is 8 bits. But I'm not particular about this.

[0242]

As described above, according to the present invention, excellent image quality can be realized with a simple structure while correcting the voltage decrease based on the electric resistance of the wiring.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic circuit configuration of an image display device according to a first embodiment of the invention.

FIG. 2 is a perspective view of the image display device according to the embodiment of the present invention.

FIG. 3 is a schematic plan view showing a state of wiring of a display element.

FIG. 4 is a characteristic diagram of a surface conduction electron-emitting device.

FIG. 5 is a diagram showing a driving method of a display panel.

FIG. 6 is a diagram illustrating a degenerate model according to the embodiment of this invention.

FIG. 7 is a graph showing a discretely calculated voltage drop amount.

FIG. 8 is a graph showing the amount of change in emission current calculated discretely.

FIG. 9 is a diagram illustrating a method of calculating correction data according to the embodiment of this invention.

FIG. 10 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 11 is a diagram for explaining a correction data interpolation method according to the embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration and an operation of a modulation unit of the image display device according to the exemplary embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of correction data calculation means of the image display device according to the exemplary embodiment of the present invention.

FIG. 14 is an explanatory diagram of a dither method.

FIG. 15 is a timing chart of the image display device according to the embodiment of the present invention.

FIG. 16 is a diagram for explaining an interference pattern.

FIG. 17 is a block diagram of an image display device according to a third embodiment of the present invention.

FIG. 18 is a schematic block diagram of an image display device according to a conventional technique.

[Explanation of symbols]

1 Display panel 2,2 'scanning circuit 3 Sync signal separation circuit 4 Timing generation circuit 5 shift registers 6 Latch circuit 7 RGB conversion circuit 8 Modulation means 10 controller 12 adder 14 Correction data calculation means 15, 16 gradation number conversion means 17 Reverse γ processing unit 19 Delay circuit 1001 substrate 1002 cold cathode device 1003 line wiring 1004 column wiring 1005 rear plate 1006 Side wall (frame) 1007 face plate 1008 fluorescent film 1009 metal back

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 641P 642 642A (72) Inventor Hiroshi Saito 3-30 Shimomaruko, Ota-ku, Tokyo No. 2 Canon F-term (reference) 5C080 AA08 AA18 BB05 CC03 DD05 DD22 EE01 EE19 EE29 EE30 FF12 GG08 GG11 GG12 HH17 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK43

Claims (18)

[Claims] 1. A plurality of image forming elements connected to a plurality of row wirings and column wirings and arranged in a matrix, a scanning unit connected to the row wirings and sequentially scanning the row wirings, and a plurality of column wirings. An image display device comprising: a connected modulation means, comprising: a corrected image data calculation means for calculating corrected image data, which is image data obtained by correcting input image data, and the corrected image data calculation means , A means for calculating the corrected image data having a smooth distribution in the horizontal or vertical direction of the screen with respect to the input of the same image data which is not 0, and the floor of the corrected image data outputted by the corrected image data calculating means. A gradation number converting means for converting the key number, and the modulating means generates a modulation voltage signal based on the corrected image data converted by the gradation number converting means. Image display device and outputs to the column wiring. 2. The gradation number conversion means performs gradation by area gradation so that lower bits of the data are not truncated when the corrected image data after the gradation number conversion is input to the modulation means. A number is converted, The number is converted.
The image display device according to. 3. The gradation number conversion means converts the corrected image data, which is (k + L) bits, into k-bit data for k-bit input image data. The image display device according to 2 (however, k,
L is a positive integer). 4. The corrected image data calculating means is means for correcting the effect of a voltage drop caused by at least the resistance of the row wiring on the input image data. , 2 or 3 image display device. 5. The correction image data is smaller on the same line in the vicinity where the scanning means is connected, and is larger as the distance from the connecting portion of the scanning means increases. The image display device according to one. 6. The corrected image data calculation means has a discrete reference value in the size direction of the image data, and calculates the corrected image data for the image data having the size of the reference value. 6. The corrected image data obtained according to the size of the input image data is calculated by interpolating the corrected image data obtained in the direction of the size of the image data. The image display device according to. 7. The corrected image data calculation means calculates the corrected image data for discrete positions on the same line, and interpolates the corrected image data for discrete positions,
The image display device according to claim 6, wherein corrected image data for an arbitrary position is calculated. 8. A plurality of image forming elements connected to a plurality of row wirings and column wirings and arranged in a matrix, a scanning unit connected to the row wirings and sequentially scanning the row wirings, and a plurality of column wirings. In an image display device including a connected modulation means, correction data calculation means for calculating correction data having a smooth distribution in the horizontal or vertical direction of the screen with respect to input of the same non-zero image data, and the correction data And a gradation number conversion means for converting the gradation number of the data; and an addition means for adding the correction data whose gradation number has been converted and the input image data, wherein the modulation means responds to the output of the addition means. And outputting a modulated voltage signal to each column wiring. 9. The gradation number conversion means uses the area gradation to prevent the lower bits of the data from being truncated when the correction data after the gradation number conversion is input to the modulation means. Is converted.
The image display device according to. 10. The gradation number conversion means converts the correction data, which is (k + L) bits, into k-bit data for k-bit input image data. Image display device described in (However, k, L
Is a positive integer). 11. The correction data calculating means is means for correcting the influence of a voltage drop caused by at least the resistance of the row wiring on the input image data. 9. The image display device according to 9 or 10. 12. The correction data, on the same line,
The image display device according to any one of claims 8 to 11, wherein the image display device is smaller as it is closer to the scanning means connected thereto and is larger as it is farther from the connecting portion of the scanning means. 13. The correction data calculation means has a discrete reference value in the size direction of the image data, calculates the correction data for the image data having the size of the reference value, and discretely 13. The image according to claim 8, wherein the obtained correction data is interpolated in the size direction of the image data to calculate the correction data corresponding to the size of the input image data. Display device. 14. The correction data calculating means calculates the correction data for discrete positions on the same row, and interpolates the correction data for discrete positions to correct for arbitrary positions. The image display device according to claim 13, wherein data is calculated. 15. The image display device according to claim 2, wherein the area gradation is dither. 16. The modulator according to claim 1, wherein the modulator is a pulse width modulator that modulates a pulse width according to gradation information. Image display device. 17. The image display device according to claim 1, wherein the image forming element is an electron emitting element that emits electrons according to an applied modulation signal. 18. The image display device according to claim 17, wherein the electron-emitting device is a surface conduction electron-emitting device.