JP2003132691A - Nonvolatile semiconductor memory and data reading method - Google Patents

Abstract

(57) [Problem] To provide a nonvolatile semiconductor memory capable of realizing appropriate data reading by a signal indicating that stable reading of the memory is possible at power-on. SOLUTION: A memory block 4 composed of a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read boosting means comprising a charge pump 2 for reading the contents of the memory array. A SELR signal is output in response to the rise of the read boosting means comprising the charge pump 2 after the power supply voltage rises, and the SELR signal is output after a predetermined time measured by the timer circuit 91 from the power supply voltage rise. R indicating a state of ensuring a stable boosted output by the read boosting means including the charge pump 2
A D signal is output, and a read enable signal indicating that the contents of the memory array can be read is generated by the read enable generation circuit 92 based on the SELR signal and the RD signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory and a data reading method, and more particularly to a non-volatile semiconductor memory when a data processing device reads data from a non-volatile semiconductor memory using a non-volatile transistor at power-on. The present invention relates to a nonvolatile semiconductor memory and a data reading method capable of reading data while a read pump in the memory is sufficiently activated.

[0002]

2. Description of the Related Art A conventional nonvolatile semiconductor memory starts a read pump required for memory reading at power-on, and uses only a rising completion signal from the read pump to connect data connected to the nonvolatile semiconductor memory. It was informed to the processor that the memory could be read. Further, the data processing device connected to the non-volatile semiconductor memory immediately after the power is turned on reads the data from the non-volatile semiconductor memory based on the signal output from the non-volatile semiconductor memory indicating whether or not the memory can be read. Had started.

[0003]

In such a conventional technique, when the power is turned on, the rising completion signal from the read pump in the non-volatile memory may output an unstable level, and the read pump still starts up. However, there is a problem that the data processing device connected to the non-volatile semiconductor memory may start the memory read, and the data processing device may run out of control.

The present invention has been made in order to solve such a problem, and realizes appropriate data reading by a signal indicating that stable reading of the memory is possible at the time of power-on. An object is to provide an obtained nonvolatile semiconductor memory.

[0005]

In the nonvolatile semiconductor memory according to the first invention, a memory array in which a plurality of memory cells composed of nonvolatile transistors are arranged in a matrix,
A read-out boosting means for reading out the contents of the memory array, wherein a first signal means for outputting a first signal in response to a rise of the read-out boosting means after raising the power supply voltage, and a power supply voltage raising means Second signal means for outputting a second signal indicating the stable secured state of the boosted output in the stable secured state of the boosted output by the boosting means for reading after being raised, and by the first signal and the second signal A read adaptation signal indicating that the contents of the memory array can be read is generated.

In the non-volatile semiconductor memory according to the second aspect of the present invention, there are provided a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read boosting means for reading the contents of the memory array. A first signal means for outputting a first signal in response to the rising of the reading boosting means after the power supply voltage rises, and a boosted output by the reading boosting means after a predetermined time has elapsed from the power supply voltage rise. Second signal means for outputting a second signal indicating a stable secured state is provided, and a read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal. Is.

In the non-volatile semiconductor memory according to the third aspect of the present invention, a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read charge pump necessary for reading the contents of the memory array are provided. A first signal having a circuit for measuring a predetermined time after the power supply voltage is raised, and notifying that the charge-up of the read charge pump is completed after the power supply voltage is raised,
A second signal that is output from a circuit that measures a predetermined time after the power supply voltage is raised and that indicates completion of measurement for a predetermined time,
A read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal.

In the non-volatile semiconductor memory according to the fourth aspect of the present invention, there are provided a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read boosting means for reading the contents of the memory array. A first signal means for outputting a first signal in response to the rising of the reading boosting means after the power supply voltage rises, and a boosted output by the reading boosting means after a predetermined time has elapsed from the power supply voltage rise. Second signal means for outputting a second signal indicating a stable state is provided, and a read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal, and the power supply is also provided. The predetermined time from the voltage rise is adjusted according to the level of the power supply voltage.

According to a fifth aspect of the present invention, there is provided a data reading method, which comprises a memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read boosting means for reading the contents of the memory array. In reading the contents of the memory array of the semiconductor memory to the data processing device, the first signal output in response to the rise of the read boosting means after the power supply voltage is raised, and the read booster after the power supply voltage is raised. A read adaptive signal indicating readability is generated by the second signal indicating the stable ensuring state of the boosted output, which is output in the stable ensuring state of the boosted output by the means, and the contents of the memory array are transmitted to the data processing device. The reading is made possible.

A data reading method according to a sixth aspect of the present invention comprises a memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read boosting means for reading the contents of the memory array. When the contents of the memory array of the semiconductor memory are read to the data processing device, a first signal that is output in response to the rising of the reading boosting means after the power supply voltage is raised, and a predetermined signal after the power supply voltage is raised A read adaptation signal indicating readability is generated by the second signal indicating the stable secured state of the boosted output, which enables the content of the memory array to be read to the data processing device, and the power supply voltage rises. The predetermined time from the rise is adjusted according to the level of the power supply voltage.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. An embodiment of the present invention will be described below. FIG. 1 is a block diagram showing the overall configuration of a nonvolatile semiconductor memory according to an embodiment of the present invention.

The nonvolatile semiconductor memory according to the embodiment of the present invention is roughly divided into a microsequencer 1, a charge pump 2, a memory decoder 3, a memory block group 4, an address / data / control signal latch circuit 5.
Consists of. Address A (16: 0) bus, data (15: 0) bus, and various control signals are input / output from the outside of the memory.

FIG. 2 shows a list of operation modes of the nonvolatile semiconductor memory according to the embodiment of the present invention. Next, each operation mode will be described. For reading, data of an arbitrary address in the nonvolatile semiconductor memory is read. The status register read reads status information of automatic erasing / writing. The status register read enters the mode with the command 70H input from the data D (15: 0) bus and returns with FFH. Status register clear clears the contents of the status register. To clear the status register, a command 50H input from the data D (15: 0) bus is used to enter the mode, and FFH is returned.

In automatic writing, a setup mode is entered by a command 40H input from the data D (15: 0) bus, and write data and an address are fetched in the next cycle to enter a mode. After automatic writing,
Write the write status to the status register.
In the automatic batch erasing, the setup mode is entered by the command 20H input from the data D (15: 0) bus, and the mode entry is performed by the confirmation command 20H in the next cycle. After the automatic batch erase is completed, write the batch erase status to the status register. In the automatic batch erase, the automatic block erase enters the setup mode by the command 20H input from the data D (15: 0) bus, and enters D0H / block address in the next cycle to enter the mode. After the automatic block erase, write the automatic block erase status to the status register.

The lock bit program uses the data D (1
(5: 0) The command 77H input from the bus enters the setup mode, and in the next cycle, the block address is fetched and mode entry is performed. After the lock bit program is completed, write the status to the status register. In the lock bit read, the command 71H input from the data D (15: 0) bus enters the setup mode, and in the next cycle, the block address is fetched and mode entry is performed to read the lock bit data.

[Micro Sequencer] FIG. 3 shows a block diagram of the micro sequencer 1. The micro sequencer 1 includes a command board 6, a status register 7, an automatic erase sequencer 8, an automatic write sequencer 69, a test mode sequencer 9, a power reset circuit 10, a clock generation circuit 11, a decoder / charge pump control signal generation circuit 12, and a read enable. It comprises a signal generation circuit 92 and a timer circuit 91.

The automatic erasing sequencer 8 controls the automatic erasing operation according to an instruction from the command board 6. The charge pump 2, the memory decoder 3, and the memory block group 4 are controlled by the decoder / charge pump control signal generation circuit 12
Done through. The timer circuit 91 is called to measure various times necessary for the automatic erasing sequencer, such as issuing an erasing pulse and setting the pump start-up time. Also, the status state at the time of automatic erasing is written in the status register 7. The automatic write sequencer 69 controls the automatic write operation according to the instruction from the command port 6. The charge pump 2 and the memory decoder 3 are controlled via the decoder / charge pump control signal generation circuit 12. The timer circuit 91 is called to measure various times necessary for the automatic erasing sequencer, such as issuing a write pulse and setting the pump start-up time. Further, the status state at the time of the automatic writing operation is written in the status register 7. The test mode sequencer 9 controls the operation in the test mode according to the instruction from the command port 6. The charge pump 2, the memory decoder 3, and the memory block group 4 are controlled via the decoder / charge pump control signal generation circuit 12. The timer circuit 91 is called to measure the time required in various test sequences such as the issuance of a write pulse, the issuance of an erase pulse, and the pump start-up time setting. Power reset circuit 10
Detects the rising edge of the power supply and outputs a reset signal to the internal circuit, or sets all the internal circuits to the reset state by an external reset input input from the command board 6. The clock generation circuit 11 is 10 MH
A clock pulse corresponding to z is output to the automatic erase sequencer 8, automatic write sequencer 69 and test mode sequencer 9. When all the circuits are brought into a non-operating state by the power reset circuit 10, the function of the clock generation circuit 11 also stops and the clock signal also stops. The status register 7 holds a status state at the time of automatic erasing / writing, and outputs the value to the outside via the command board 6 if necessary. The decoder / charge pump control signal generation circuit 12 receives the outputs of the automatic erase sequencer 8, automatic write sequencer 69, and test mode sequencer 9 and generates control signals for controlling the charge pump 2, the memory decoder 3, and the memory block group 4. . The readable signal generation circuit 92 receives a signal from the power reset circuit 10 and the charge pump 2 at the time of power-on, and outputs a flash memory readable signal to the external data processing device 1
Generate for 07.

[Charge Pump] FIG. 4 shows a block diagram of the charge pump 2. The charge pump 2 includes a negative voltage pump 13, a positive voltage pump 14, a read pump 15,
It comprises a voltage switching circuit 16. The charge pump 2 is
The output of each charge pump is controlled by the micro sequencer 1 and supplied to the memory decoder 3 and the memory block group 4 by the voltage switching circuit 16. The negative voltage pump 13 is a negative pump for erasing, and generates a negative erasing voltage during automatic erasing. The positive voltage pump 14 is a positive charge pump for writing / erasing, and generates a positive writing voltage during writing and a positive erasing voltage during erasing.
The read pump 15 is a positive charge pump for read / verify, generates a positive read voltage during a read operation, and generates a positive verify voltage during a write / write verify. Further, during a period in which the read pump is activated such as when the power is turned on, a signal is output to the read enable signal generation circuit 92 to inform whether or not the memory can be read.

[Memory Decoder] FIG. 5 shows a block diagram of the memory decoder 3. The memory decoder 3 includes a Y (column) address input buffer latch 19, an X (row) address latch 18, a block address latch 17, and a Y address.
It comprises a (column) address predecoder 22, an X (row) address predecoder 21, and a block address predecoder 20. The Y (column) address input buffer latch 19, the X (row) address latch 18, and the block address latch 17 latch the 17-bit address A (16: 0) sent from the microsequencer 1. The latched addresses are the Y (column) address predecoder 22 and the X (row) address predecoder 2.
1, block address predecoder 20 performs address predecoding processing, and outputs the predecoded address to memory block group 4.

[Memory Block] FIG. 5 shows a block diagram of the memory block group 4. The memory block group 4 includes a memory block <4>: 23, which is composed of an 8 KB memory cell array.
Memory block <0> consisting of 32 KB memory cell array: 24, Memory block <1> consisting of 32 KB memory cell array: Memory block <2> consisting of 25,32 KB memory cell array <2>: Memory block <3> consisting of 26,32 KB memory cell array: It is composed of 27. Each memory block includes a sense amplifier / write transistor circuit, a data switching circuit, an X decoder, and a Y decoder.

FIG. 6 shows the address space of the memory block group 4. The memory block <0>: 24 is "00" in hexadecimal notation.
The memory block <1>: 25 has a hexadecimal notation of “08”.
It has an address space of 000H "to" 0FFFFH ". The memory block <2>: 26 is" 10 "in hexadecimal notation.
The memory block <3>: 27 has a hexadecimal notation of “18”.
The memory block <4>: 23 has a hexadecimal notation of “00H” to “1FFFFH”.
It has an address space of 000H "to" 01FFFH ".
The memory block <4>: 23 is accessed by using the control signal (memory block <4> access signal) output from the microsequencer 1 in combination.

FIG. 7 shows an X decoder, a Y decoder, a memory cell array, a sense amplifier / sense amplifier in the block shown in FIG.
It is a figure which extracts and shows a writing circuit. Y decoder 70
Receives the output from the Y address predecoder 21,
256 control signals (CS0) for selecting one bit line from 256 bit lines (BL0 to BL255)
~ CS255) is output. The X decoder 71 receives the output from the X address predecoder 22, and selectively controls one word line from the 128 word lines (WL0 to WL127). Memory cells (Tr0-0 to Tr0) each including a nonvolatile transistor having a floating gate
-255, Tr1-0 to Tr1-255, Tr2-0
Tr2-255, Tr3-0-Tr3-255, ..., T
r127-0 to Tr127-255) are arranged in a matrix. Of these, memory cells (Tr0-0 to Tr127-0, Tr0-1 to Tr12) arranged in the same row
7-1, Tr0-2 to Tr127-2, Tr0-255
To Tr127-255), the same bit line (BL0 to BL0 to
BL255) is connected to the source terminal, and different word lines (WL0 to WL127) are connected to the gain terminal.

To read the memory data, one bit line and one word line are selected from the bit lines (BL0 to BL255) and the word lines (WL0 to WL127) according to the outputs of the X address predecoder 22 and the Y address predecoder 21, respectively. Is selected and the content of the memory cell formed of a nonvolatile transistor having a floating gate connected to the selected bit line and word line is output to the data bus via the sense amplifier in the sense amplifier / write circuit 72. .

FIG. 8 is a diagram showing the X decoder, the Y decoder, the dummy memory cell array, the lock bit cell array, and the sense amplifier / write circuit extracted from the block shown in FIG. The Y decoder 98 receives the output from the Y address predecoder 22 and receives 64 bit lines (D
64 control signals (CSS1 to CSS64) for selecting one bit line from BL1 to DBL64) are generated. The X decoder 99 is the X address predecoder 21.
128 word lines (WL0-W
One word line is selectively controlled from L127). Also,
The lock bit line (LBL) is a nonvolatile transistor (Tr0 that indicates a locked / unlocked state for each memory block).
0-0) is a connected bit line. In addition, a dummy memory cell and a lock bit memory cell (Tr00-
0-Tr00-64, Tr10-0-Tr10-64,
Tr20-0 to Tr20-255, Tr30-0 to Tr
30-64, ..., Tr1270-0 to Tr1270-6
4) are arranged in a matrix. Of these, memory cells (Tr00-0 to Tr1270-) arranged in the same row
0, Tr00-1 to Tr1270-1, Tr00-2 to
Tr1270-2, ..., Tr00-64 to Tr1270
-64) has the same bit line (DBL1 to DBL64)
Are connected to the source terminal, and different word lines (WL0 to WL127) are connected to the gain terminal. DBL1 to DBL64 are dummy bit lines, and L
BL is a lock bit line.

Dummy memory cell data is read by X
Address predecoder 22, Y address predecoder 2
According to the output of 1, bit lines (DBL1 to DBL64)
One bit line and one word line are selected from each of the word lines (WL0 to WL127), and the content of the memory cell including the nonvolatile transistor having a floating gate connected to the selected bit line and word line is It is output to the data bus via the sense amplifier in the sense amplifier / write circuit 72.

[Structure] First, the read enable signal generation circuit 92.
The configuration will be described with reference to FIG. The read enable signal generation circuit 92 receives the RD signal 95 from the timer circuit 91 and the SELR signal 94 from the charge pump 2 and outputs a read enable signal 96 to the data processing device. The power reset circuit 10 has a timer start signal 97 when the power is turned on.
Is output to the timer circuit 91. The read enable signal generation circuit 92 includes a power supply level detection circuit 98, which detects the level of the power supply voltage and outputs the result to the timer circuit 91. The timer circuit 91 is a power supply level detection circuit 98
The information to adjust the timing of setting the RD signal 95 to the H level.

[Operation at Power-Up] Next, the operation of the read enable signal generation circuit 92 at power-up will be described.
This will be described with reference to FIGS. 9 and 10. FIG. 10 is a diagram showing the logical value of each signal from when the power is turned on to when the lead pump rises. Each shows the case where the power supply voltage is a high voltage and a low voltage.

First, the case where the power supply voltage is high will be described. First, at time T1, the power is turned on. When the power is turned on, the power reset circuit 10 operates and outputs the timer start signal 97 to the timer circuit 91 to operate the timer circuit 91. The timer circuit 91 controls the time (T2
The time is measured during -T1), and at time T2, the RD signal 95 (H level) is output to the readable signal generation circuit 92. The charge pump 2 starts the read pump at the same time as the power is turned on, and at the time T3, the read pump ends and the read pump is finished.
Readable signal generation circuit 92 by setting R signal 94 to L level
Output to. Here, the SELR signal 94 shows an unstable output level immediately after the power is turned on. The read enable signal generation circuit 92 receives input signals from the timer circuit 91 and the charge pump 2 and outputs a read enable signal 96 to the data processing device 107. The read enable signal 96 is
At time T3, the L level changes to the H level.

Next, the case where the power supply voltage is low will be described. First, at time T1, the power is turned on. When the power is turned on, the power reset circuit 10 operates and outputs the timer start signal 97 to the timer circuit 91 to operate the timer circuit 91. The timer circuit 91 controls the time (T2
The time is measured during -T1), and at time T2, the RD signal 95 (H level) is output to the readable signal generation circuit 92. The charge pump 2 starts the read pump at the same time as the power is turned on, and at the time T3, the read pump ends and the read pump is finished.
Readable signal generation circuit 92 by setting R signal 94 to L level
Output to. Here, the SELR signal 94 shows an unstable output level immediately after the power is turned on. The read enable signal generation circuit 92 receives input signals from the timer circuit 91 and the charge pump 2 and outputs a read enable signal 96 to the data processing device 107. The read enable signal 96 is
At time T3, the L level changes to the H level. Here, the higher the power supply voltage is, the faster the rise time of the lead pump is. Therefore, the time for the RD signal 95 to change to the H level is set shorter than that for the low voltage. This time setting changes the time measured by the timer circuit 91 according to the level of the power supply voltage by the power supply level detection circuit 98. As described above, immediately after the rise of the power supply voltage, even if the read pump from the charge pump 2 outputs the unstable level of the SELR signal 94 which is the start-up end signal, the measurement after the constant time is measured by the timer circuit 91. From the result with the RD signal 95 which is the end signal, the read enable signal 9
Since 6 is generated and output to the data processing device 107, the data processing device 107 does not run out of control.

FIG. 11 shows a nonvolatile semiconductor memory 106 and a data processing device 107 for accessing the memory. Between the non-volatile semiconductor memory 106 and the data processing device 107, address A (16: 0) and data D (15: 0),
It is connected by a control signal and a read enable signal. A memory address accessed by the data processing device 107 is input to the address A (16: 0) bus. Data D
In the (15: 0) bus, in the read mode, the data of the read memory address is stored in the nonvolatile semiconductor memory 106.
Command data from the data processing device 107 is output to the nonvolatile semiconductor memory 106 when a command is input during automatic erasing or automatic writing. The ICE signal 110 is L level in the command input and read mode.
It changes to active, and the IWE signal 111 becomes L active together with the ICE signal 110 at the time of command input. I
The OE signal 112 changes the read data to the data D (15:
0) Output to the bus. The IRP signal 113 is L
By becoming active, the nonvolatile semiconductor memory 106 is changed to the reset power down state. IB
The YTE signal 114 is set to L when performing a byte access operation.
Become active. The read enable signal 96 is input from the nonvolatile semiconductor memory 106 to the data processing device 107,
Indicates that the readout pump started up when the power was turned on.

FIG. 12 shows the timing when the data processing device 107 reads the data of the non-volatile semiconductor memory 106 when the power is turned on. The data processing device 107
When the power is turned on, wait for the read enable signal 96 output from the nonvolatile semiconductor memory 106 to become H level,
Data reading from the nonvolatile semiconductor memory 106 is started. First, ICE is changed to L level, and the address to be read is output to the address bus A (16: 0). The nonvolatile semiconductor memory 106 receives the output of the ICE signal from the data processing device 107 and receives the address data A (16:
0) is read and the data is read. The read memory data is output to the D (15: 0) bus and taken into the data processing device 107 at the timing when the IOE signal of the data processing device 107 becomes L level.

In the embodiment according to the present invention, the logical product of the signal notifying that the charge-up of the read charge pump is completed after the power supply voltage is raised and the signal notifying the end of measurement by measuring a fixed time after the power supply is turned on. To generate.

Further, in the embodiment according to the present invention, the logical product of the signal notifying that the charge-up of the read charge pump is completed after the rise of the power supply voltage and the constant measurement end signal whose time changes according to the level of the power supply voltage. To generate.

Further, in the embodiment according to the present invention,
It has a signal notifying that the charge-up of the read charge pump is completed after the power supply voltage is raised, and means for measuring a fixed time after the power supply is turned on. It is determined whether or not the memory content can be read by the data processing device connected to the memory by the logical product signal of the signals that determine and indicate the end of measurement.

In the embodiment of the present invention, the logical product of the signal notifying that the charge-up of the read charge pump is completed after the power supply voltage is raised and the signal notifying the end of measurement by measuring a fixed time after the power supply is turned on. Thus, it is possible to determine whether or not the memory contents can be read even if there is an unstable time immediately after the power is turned on.

Further, in the embodiment according to the present invention, the logic of the signal notifying that the charge-up of the read charge pump is completed after the rise of the power supply voltage and the fixed time measurement end signal whose time changes according to the level of the power supply voltage. Based on the product, it is possible to determine whether or not the memory contents can be read even if there is an unstable time immediately after the power is turned on.

Further, in the embodiment according to the present invention, the signal notifying that the charge-up of the read charge pump is completed after the power supply voltage is raised and the signal notifying the end of measurement by measuring a fixed time after the power supply is turned on. The AND signal can determine whether the memory contents can be read by the data processing device connected to the memory.

According to the embodiment of the present invention, a memory block <4>: 23, a memory block <0>: 24, and a memory, each of which is composed of a memory array in which a plurality of memory cells composed of nonvolatile transistors are arranged in a matrix. Memory block group 4 having blocks <1>: 25, memory blocks <2>: 26, and memory blocks <3>: 27
And a read boosting means composed of a charge pump 2 for reading the contents of the memory array, the SEL according to the rise of the read boosting means composed of the charge pump 2 after the power supply voltage is raised.
It comprises a first signal means for outputting a first signal consisting of an R signal 94, and an RD signal 95 indicating the stable secured state of the boosted output by the stable boosted output state by the read boosting means after the rise of the power supply voltage. A second signal means for outputting a second signal is provided, and the content of the memory array is read by a logical product of the logical operation result of the first signal composed of the SELR signal 94 and the second signal composed of the RD signal 95. Since the read adaptation signal including the read enable signal 96 indicating the possibility is generated, the nonvolatile semiconductor capable of realizing appropriate data read by the signal indicating that the memory can be stably read at the time of power-on. Memory can be provided.

Further, according to the embodiment of the present invention, a memory block <4>: 23 and a memory block <0>: 24 formed of a memory array in which a plurality of memory cells made of nonvolatile transistors are arranged in a matrix. , Memory block <1>: 25, memory block <2>: 26,
A memory block group 3 having a memory block <3>: 27, and a read boosting means composed of a charge pump 2 for reading the contents of the memory array.
SE in response to the rising of the reading booster
The first signal means for outputting the first signal composed of the LR signal 94 and the boosted output in the stable secured state of the boosted output by the read boosting means after a predetermined time measured by the timer circuit 91 from the rise of the power supply voltage. A second signal that outputs a second signal composed of an RD signal 95 indicating a stable secured state
A signal means for providing the first SELR signal 94
A read adaptive signal consisting of a read enable signal 96 indicating that the contents of the memory array can be read is generated by a logical product of a signal and a second signal consisting of the RD signal 95 as a logical operation result. A non-volatile semiconductor memory that can realize appropriate data reading can be provided by a signal indicating that stable reading of the memory is possible at the time of raising.

Further, according to the embodiment of the present invention, a memory block <4>: 23 and a memory block <0>: 24 each formed of a memory array in which a plurality of memory cells each made of a non-volatile transistor are arranged in a matrix. , Memory block <1>: 25, memory block <2>: 26,
The contents of the memory array of the semiconductor memory including the memory block group 4 having the memory block <3>: 27 and the read boosting means including the charge pump 2 for reading the contents of the memory array are provided to the data processing device. In reading, a first signal, which is a SELR signal 94, which is output in response to the rising of the reading booster composed of the charge pump 2 after the power supply voltage is raised,
As a result of logical operation with the second signal composed of the RD signal 95 indicating the stable ensuring state of the boosted output, which is output in the stable ensuring state of the boosted output by the boosting unit for reading including the charge pump 2 after the rise of the power supply voltage. Since a read adaptation signal indicating readability is generated by the AND of the above, and the contents of the memory array can be read to the data processing device, stable reading of the memory can be performed when the power is turned on. It is possible to provide a data reading method capable of realizing appropriate data reading by a signal indicating that there is a certain value.

Further, according to the embodiment of the present invention, the memory block <4>: 23 and the memory block <0>: 24 each including a memory array in which a plurality of memory cells each including a non-volatile transistor are arranged in a matrix. , Memory block <1>: 25, memory block <2>: 26,
The contents of the memory array of the semiconductor memory including the memory block group 4 having the memory block <3>: 27 and the read boosting means including the charge pump 2 for reading the contents of the memory array are provided to the data processing device. In reading, a first signal, which is a SELR signal 94, which is output in response to the rising of the reading booster composed of the charge pump 2 after the power supply voltage is raised,
An RD signal 95 indicating a stable secured state of the boosted output, which is output in a stable secured state of the boosted output by the boosting unit for reading including the charge pump 2 after a predetermined time measured by the timer circuit 91 from the rise of the power supply voltage.
A read adaptation signal indicating readability is generated by a logical product as a result of a logical operation with the second signal consisting of, and the contents of the memory array can be read to the data processing device, and the power supply voltage is raised. Since the predetermined time measured by the timer circuit 91 from 1 is adjusted according to the level of the power supply voltage,
It is possible to provide a data read method capable of realizing appropriate data read by a signal indicating that stable reading of the memory is possible at power-on.

[0042]

According to the first aspect of the present invention, it is provided with a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read boosting means for reading the contents of the memory array. The first signal means for outputting a first signal in response to the rising of the reading boosting means after the power source voltage is raised, and the stable state of the boosted output by the reading boosting means after the power source voltage is raised in the stable state. A second signal means for outputting a second signal indicating a stable secured state of the boosted output is provided, and a read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal. As a result, a signal indicating that stable reading of the memory is possible when the power is turned on realizes proper data reading. That it is possible to provide a nonvolatile semiconductor memory.

According to the second aspect of the invention, in a memory array having a plurality of memory cells each composed of a non-volatile transistor arranged in a matrix, and a read boosting means for reading the contents of the memory array. A first signal means for outputting a first signal in response to the rising of the reading boosting means after the power supply voltage rises, and a stable ensuring state of the boosted output by the reading boosting means after a predetermined time from the power supply voltage rise. A second signal means for outputting a second signal shown is provided, and a read adaptation indicating that the contents of the memory array can be read is generated by the first signal and the second signal. Non-volatile to realize proper data reading by more accurate signal that indicates stable reading of memory It is possible to provide a conductor memory.

According to the third invention, a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, a read charge pump necessary for reading the contents of the memory array, and a power supply voltage rising A circuit for measuring a predetermined time after the power supply voltage rises, and a first signal for notifying that the charge-up of the read charge pump is completed after the power supply voltage rises, and a circuit for measuring a predetermined time after the power supply voltage rises are output. A second signal for notifying the completion of measurement for a predetermined time, and a read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal.
It is possible to provide a non-volatile semiconductor memory that can realize appropriate data reading by a more accurate signal indicating that stable reading of the memory is possible at power-on.

According to a fourth invention, in the second or third invention, a memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read operation for reading the contents of the memory array are provided. A first signal means for outputting a first signal in response to the rising of the reading boosting means after the power supply voltage has risen, and the reading boosting means after a predetermined time elapses from the rising of the power supply voltage. Second signal means for outputting a second signal indicating a stable secured state of the boosted output by the means, and generating a read adaptation signal indicating that the contents of the memory array can be read by the first signal and the second signal. At the same time, the predetermined time from the rise of the power supply voltage is adjusted according to the level of the power supply voltage. The more accurate signal from indicating that stable reading of memory are possible, it is possible to provide a nonvolatile semiconductor memory capable of realizing a proper data readout.

According to the fifth invention, a semiconductor memory comprising a memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read boosting means for reading the contents of the memory array. When reading the contents of the memory array of
A first signal that is output in response to the rising of the reading boosting means after the power supply voltage is raised, and a stability of the boosting output that is output in a stable state of the boosting output by the reading boosting means after the power supply voltage is raised. A read adaptation signal indicating readability is generated by the second signal indicating the secured state, and the contents of the memory array can be read out to the data processing device, so that the memory is stable when the power is turned on. It is possible to provide a data read method capable of realizing appropriate data read by the signal indicating that the read can be performed.

According to the sixth aspect of the present invention, a semiconductor memory is provided with a memory array in which a plurality of memory cells composed of non-volatile transistors are arranged in a matrix, and a read boosting means for reading the contents of the memory array. When reading the contents of the memory array of
By the first signal output in response to the rising of the reading boosting means after the power supply voltage is raised, and the second signal indicating the stable ensuring state of the boosted output that is output after a predetermined time has passed from the power supply voltage rise, A read adaptation signal indicating readability is generated to enable the data processing device to read the contents of the memory array, and the predetermined time from the rise of the power supply voltage is adjusted according to the level of the power supply voltage. Therefore, it is possible to provide a data read method capable of realizing appropriate data read by a more accurate signal indicating that the memory can be read stably when the power is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram showing functional blocks of a nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a list of operation modes of the nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a micro sequencer among the functional blocks in FIG.

FIG. 4 is a block diagram showing a configuration of a charge pump in the functional blocks in FIG.

5 is a block diagram showing a configuration of a memory decoder / memory block in the functional blocks in FIG. 1. FIG.

FIG. 6 is an explanatory diagram showing an address space of a memory block in the functional blocks in FIG.

7 is a block diagram of the block in FIG.
It is a block diagram which extracts and shows a Y decoder, a memory cell array, and a sense amplifier / writing circuit.

FIG. 8 is a block diagram of the block in FIG.
It is a block diagram which extracts and shows a Y decoder, a dummy memory cell array, a lock bit cell array, and a sense amplifier / writing circuit.

FIG. 9 is a block diagram showing connections of a power reset circuit, a timer circuit, a charge pump, a data processing device, and a read enable signal generation circuit in the embodiment according to the present invention.

FIG. 10 is a diagram illustrating a read enable signal and a SEL when the power supply voltage is a high voltage and a low voltage according to the embodiment of the present invention.
It is a wave form diagram which shows the timing of R signal and RD signal.

FIG. 11 is a block diagram showing a connection relationship between a nonvolatile semiconductor memory and a data processing device for accessing the memory according to the embodiment of the present invention.

FIG. 12 is a waveform diagram showing the read timing of the data processing device immediately after the power is turned on in the embodiment according to the present invention.

[Explanation of symbols]

1 micro sequencer, 2 charge pump, 3 memory decoder, 4 memory block, 5 address / data / control signal latch circuit.

Claims (6)

[Claims] 1. A device comprising a memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read booster for reading the contents of the memory array. The first signal means for outputting a first signal in response to the rising of the reading boosting means and the stable securing state of the boosting output by the reading boosting means after the rise of the power supply voltage indicate the stable securing state of the boosting output. A second signal means for outputting a second signal is provided, and a read adaptation signal indicating that the contents of the memory array can be read is generated by the first signal and the second signal. Semiconductor memory. 2. A memory array comprising a plurality of memory cells each composed of a non-volatile transistor arranged in a matrix, and a read booster for reading the contents of the memory array. Outputs a first signal means for outputting a first signal in response to the rising of the reading boosting means, and a second signal indicating a stable state of the boosted output by the reading boosting means after a lapse of a predetermined time from the rise of the power supply voltage. And a second signal means for generating a read adaptive signal indicating that the contents of the memory array can be read by the first signal and the second signal. 3. A memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, a read charge pump required to read the contents of the memory array, and a predetermined time is measured after the power supply voltage is turned on. And a circuit for indicating that the charge-up of the read charge pump is completed after the power supply voltage is raised.
A signal and a second signal output from a circuit for measuring a predetermined time after power-on of the power supply voltage to notify completion of measurement for a predetermined time, and the contents of the memory array can be read by the first signal and the second signal. A non-volatile semiconductor memory is characterized in that a read adaptation signal indicating is generated. 4. A memory array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix, and a read booster for reading the contents of the memory array. Outputs a first signal means for outputting a first signal in response to the rising of the reading boosting means, and a second signal indicating a stable state of the boosted output by the reading boosting means after a lapse of a predetermined time from the rise of the power supply voltage. Second signal means for generating a read adaptation signal indicating that the contents of the memory array can be read by the first signal and the second signal, and a predetermined time from the rise of the power supply voltage to the power supply voltage. The non-volatile semiconductor memory according to claim 2 or 3, wherein the non-volatile semiconductor memory is adjusted according to the level. 5. The contents of the memory array of a semiconductor memory including a memory array in which a plurality of memory cells each made of a non-volatile transistor are arranged in a matrix, and a read booster for reading the contents of the memory array. In reading the data into the data processing device, the first signal that is output in response to the rising of the reading boosting means after the power supply voltage is raised and the boosting output by the reading boosting means after the power supply voltage is raised are stably secured. A read adaptation signal indicating readability is generated based on the second signal indicating the stable secured state of the boosted output that is output, and the contents of the memory array can be read to the data processing device. And a data reading method. 6. The contents of the memory array of a semiconductor memory including a memory array in which a plurality of memory cells each made of a non-volatile transistor are arranged in a matrix, and a read boosting means for reading the contents of the memory array. In reading the data into the data processing device, the first signal output in response to the rising of the boosting means for reading after the rise of the power supply voltage and the stable ensuring state of the boosted output outputted after a predetermined time from the rise of the power supply voltage Showing the second
A read adaptive signal indicating readability is generated by the signal and the content of the memory array can be read to the data processing device, and the predetermined time from the rise of the power supply voltage depends on the level of the power supply voltage. The data reading method is characterized in that the adjustment is performed by adjusting.