JP2003133478A - BGA type semiconductor device - Google Patents
BGA type semiconductor deviceInfo
- Publication number
- JP2003133478A JP2003133478A JP2001324684A JP2001324684A JP2003133478A JP 2003133478 A JP2003133478 A JP 2003133478A JP 2001324684 A JP2001324684 A JP 2001324684A JP 2001324684 A JP2001324684 A JP 2001324684A JP 2003133478 A JP2003133478 A JP 2003133478A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- adhesive
- film
- semiconductor device
- adhesive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 239000002313 adhesive film Substances 0.000 claims abstract description 42
- 229910000679 solder Inorganic materials 0.000 claims abstract description 16
- 229920006332 epoxy adhesive Polymers 0.000 claims abstract description 5
- 238000004080 punching Methods 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 8
- 239000012790 adhesive layer Substances 0.000 abstract description 7
- -1 polytetrafluoroethylene Polymers 0.000 abstract description 3
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 abstract description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 206010040844 Skin exfoliation Diseases 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 229920001646 UPILEX Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Abstract
(57)【要約】
【課題】 はんだリフロー時に絶縁フィルムの絶縁層と
接着用フィルムとの界面で剥離を生じなくし、実装信頼
性の向上したＢＧＡ半導体装置を得る。
【解決手段】 絶縁フィルム５に半導体素子８を接着す
る接着用フィルム４０は厚さ５０μｍの多孔質のポリテ
トラフルオロエチレンを支持体７とし、その両面に厚さ
２０から３０μｍのエポキシ系の接着剤６，６を配する
三層構造とした。そのため、接着用フィルム４０に応力
緩衝機構を持たすことができるとともに、支持体７は多
孔質であるので、はんだリフロー時接着層に含まれる揮
発成分を解放することができ、熱膨張等によって絶縁フ
ィルム５と接着用フィルムとの界面に剥離を生じること
を防止することができる。
(57) [Problem] To provide a BGA semiconductor device in which peeling does not occur at an interface between an insulating layer of an insulating film and an adhesive film during solder reflow and mounting reliability is improved. SOLUTION: An adhesive film 40 for bonding a semiconductor element 8 to an insulating film 5 is made of a porous polytetrafluoroethylene having a thickness of 50 μm as a support 7, and an epoxy adhesive having a thickness of 20 to 30 μm on both surfaces thereof. It has a three-layer structure in which 6 and 6 are arranged. Therefore, the adhesive film 40 can have a stress buffering mechanism, and since the support 7 is porous, volatile components contained in the adhesive layer can be released at the time of solder reflow, and the insulating film can be thermally expanded or the like. 5 can be prevented from being peeled off at the interface between the film 5 and the adhesive film.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＢＧＡ（Ｂａｌｌ
Ｇｒｉｄ Ａｒｒａｙ）型の半導体装置に関する。TECHNICAL FIELD The present invention relates to a BGA (Ball).
The present invention relates to a grid array type semiconductor device.
【０００２】[0002]
【従来の技術】最近、パッケージの小型化・高密度実装
化の要求に対応すべく、ＢＧＡ型半導体装置が開発され
ている。図３に示すようなＢＧＡ型半導体装置、特にマ
イクロＢＧＡ型半導体装置においては、リード１４と半
導体素子８とを接続する場合、コア２１の両面に接着層
２２、２２を設けたエラストマ（接着用フィルム）２０
を介して接続するため、接着用フィルム２０の厚さがそ
のまま接続（ボンディング）作業時においてリードの段
差となることから、Ｓ字状などに湾曲させたリード１４
を使用していた。また、マイクロＢＧＡ型半導体装置の
多くは、図４に示すように配線を備えた絶縁フィルム３
１と半導体素子３３とは、接着層のみを有する接着用フ
ィルム３２により接続されていた。2. Description of the Related Art Recently, a BGA type semiconductor device has been developed in order to meet the demand for miniaturization and high density packaging of packages. In the BGA type semiconductor device as shown in FIG. 3, particularly in the micro BGA type semiconductor device, when the lead 14 and the semiconductor element 8 are connected, an elastomer (adhesive film 22) provided with adhesive layers 22 and 22 on both surfaces of the core 21 is used. ) 20
Since the thickness of the adhesive film 20 remains as it is during the connection (bonding) work, the lead 14 curved in an S shape is connected.
Was using. In addition, many of the micro BGA type semiconductor devices have an insulating film 3 provided with wiring as shown in FIG.
1 and the semiconductor element 33 were connected by the adhesive film 32 having only the adhesive layer.
【０００３】[0003]
【発明が解決しようとする課題】しかし、ＢＧＡ型半導
体装置、特にマイクロＢＧＡ型半導体装置において、リ
ード１４と半導体素子８とを接続する場合、接着用フィ
ルム２０が存在するため、接着用フィルムの厚さがその
まま接続（ボンディング）作業時においてリードの段差
となることから、通常のＴＡＢテープのリードボンディ
ングの場合（絶縁フィルム４１に接続されたリード４２
と半導体素子４３とは、両者を圧着すれば接続できる。
図５参照）と比較して、ボンディングツールによるリー
ドの取扱い、ボンディングツールの先端を特殊な形状と
しなければならないこと及び操作のしやすさなどの点
で、ボンディング作業が難しかった。また、リード１４
をＳ字状などにうまく湾曲させてやらないと、接着用フ
ィルム２０の動きに追随できず、使用時にリード１４が
断線するおそれがあった。However, in the BGA type semiconductor device, particularly in the micro BGA type semiconductor device, when the lead 14 and the semiconductor element 8 are connected to each other, the adhesive film 20 exists, so that the thickness of the adhesive film is large. Since it becomes a step of the lead during the connection (bonding) work as it is, in the case of the lead bonding of the normal TAB tape (the lead 42 connected to the insulating film 41).
The semiconductor element 43 and the semiconductor element 43 can be connected to each other by pressure bonding.
5)), the bonding work was difficult because of the handling of the leads by the bonding tool, the tip of the bonding tool having to have a special shape, and the ease of operation. Also, the lead 14
If it is not properly curved into an S shape, the movement of the adhesive film 20 cannot be followed, and the lead 14 may be broken during use.
【０００４】さらに、図４に示すように、配線を備えた
絶縁フィルム３１と半導体素子３３とを、接着層のみを
有する接着用フィルム３２により接着すると、はんだリ
フロー時に加熱するため、絶縁フィルムと半導体素子の
熱膨張係数の相違や接着層に含まれる揮発成分の膨張等
により絶縁フィルム３１の絶縁層と接着用フィルム３２
との界面で剥離を生じるおそれがあった。Further, as shown in FIG. 4, when the insulating film 31 provided with wiring and the semiconductor element 33 are adhered by the adhesive film 32 having only an adhesive layer, the insulating film 31 and the semiconductor are heated because they are heated during solder reflow. The insulating layer of the insulating film 31 and the adhesive film 32 are different due to the difference in thermal expansion coefficient of the elements and the expansion of volatile components contained in the adhesive layer.
There was a risk of peeling at the interface with.
【０００５】[0005]
【課題を解決するための手段】半導体素子に接着用フィ
ルムを介して接着する絶縁フィルムと、接着用フィルム
と接していない絶縁フィルムの面上に位置し、ランド部
およびボンディング部とを有する配線と、ボンディング
部と半導体素子のパッドとをモールドする封止樹脂と、
ランド部に搭載されるはんだボールとからなり、接着用
フィルムと絶縁フィルムとは各々その中央部に打ち抜き
孔を有し、かつ、その打ち抜き孔は互いに重なるように
位置し、ボンディング部は打ち抜きの周囲に位置するＢ
ＧＡ型半導体装置において、前記ボンディング部と前記
半導体素子のパッドとは、ボンディングワイヤーにより
電気的に接続されていることを特徴とするＢＧＡ型半導
体装置を提供する。An insulating film adhered to a semiconductor element via an adhesive film, and a wiring having a land portion and a bonding portion located on the surface of the insulating film not in contact with the adhesive film. A sealing resin for molding the bonding portion and the pad of the semiconductor element,
It consists of solder balls to be mounted on the land, the adhesive film and the insulating film each have a punching hole in the center, and the punching holes are positioned so as to overlap each other, and the bonding portion is around the punching. Located in B
In a GA type semiconductor device, the BGA type semiconductor device is characterized in that the bonding portion and the pad of the semiconductor element are electrically connected by a bonding wire.
【０００６】また、上記の欠点を解消するために、前記
半導体装置に用いられる接着用フィルムは、多孔質の支
持体を有し、支持体の両面にエポキシ系の接着剤を配す
る三層構造とし、さら接着用フィルムは、はんだリフロ
ー温度領域での絶縁フィルムの絶縁層と接着用フィルム
との界面の接着強度が１００ｇｆ以上を有することを特
徴とするＢＧＡ型半導体装置を提供する。In order to solve the above drawbacks, the adhesive film used in the semiconductor device has a porous support and has a three-layer structure in which an epoxy adhesive is provided on both sides of the support. Further, the adhesive film has a bonding strength of 100 gf or more at the interface between the insulating film of the insulating film and the adhesive film in the solder reflow temperature region, to provide a BGA type semiconductor device.
【０００７】[0007]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を説明する。図１は本発明のＢＧＡ半導体装置
の概念図であり、図２は本発明に用いられる接着用テー
プの概念図である。この半導体装置は、以下の構成であ
る。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram of a BGA semiconductor device of the present invention, and FIG. 2 is a conceptual diagram of an adhesive tape used in the present invention. This semiconductor device has the following configuration.
【０００８】薄膜配線を備えた変形容易な絶縁フィルム
５は、７５μｍ又は１２５μｍの厚さのポリイミドフィ
ルム（ユーピレックスＳ：宇部興産製）で形成する。そ
の中央部に半導体素子８との接続用の打ち抜き孔５１を
形成する。この絶縁フィルム５の片面には１８μｍ厚の
電解銅箔を加熱圧着し、銅箔上に感光性レジストを塗布
後、ベークし、回路パターンを露光現像してエッチング
マスクを形成する。次いで、塩化鉄中で銅をエッチング
し、レジストを剥離させ、ボンディング部５２およびラ
ンド部４を含む銅箔回路パターンを形成する。ボンディ
ング部５２は絶縁フィルムに備えられた配線と半導体素
子の中央部にあるパッド８１との接続に用いるものであ
り、打ち抜き孔５１の周囲に設けられている。The easily deformable insulating film 5 having thin film wiring is formed of a polyimide film (Upilex S: Ube Industries, Ltd.) having a thickness of 75 μm or 125 μm. A punching hole 51 for connection with the semiconductor element 8 is formed in the center thereof. An electrolytic copper foil having a thickness of 18 μm is thermocompression-bonded to one surface of the insulating film 5, a photosensitive resist is applied on the copper foil, followed by baking, and the circuit pattern is exposed and developed to form an etching mask. Next, copper is etched in iron chloride, the resist is peeled off, and a copper foil circuit pattern including the bonding portion 52 and the land portion 4 is formed. The bonding portion 52 is used to connect the wiring provided on the insulating film and the pad 81 in the central portion of the semiconductor element, and is provided around the punched hole 51.
【０００９】絶縁フィルム５の他の面に厚さ５０μｍの
多孔質のポリテトラフルオロエチレンを支持体７とし、
その両面に厚さ２０から３０μｍのエポキシ系の接着剤
６，６を塗布した接着用フィルム４０により半導体素子
８を接着する。On the other surface of the insulating film 5, porous polytetrafluoroethylene having a thickness of 50 μm is used as a support 7,
The semiconductor element 8 is adhered by the adhesive film 40 having epoxy adhesives 6, 6 having a thickness of 20 to 30 μm applied on both surfaces thereof.
【００１０】半導体素子８の中央部にあるパッド８１と
絶縁フィルム５の中央部に位置する打ち抜き孔５１の周
囲に設けられたパッド５２とをボンディングワイヤー９
により接続することで、前記銅箔回路パターンと半導体
素子８とが電気的に接続される。また、前記銅箔回路パ
ターン４とマザーボード１とは、はんだボール２により
電気的に接続される。なお、半導体素子８の周辺、ボン
ディングワイヤー９の周辺は封止樹脂１０により封止さ
れる。ここに封止樹脂とは、たとえばエポキシ樹脂等が
使用される。なお、３は、絶縁皮膜であり、たとえば感
光性のレジスト材等が使用される。The pad 81 in the center of the semiconductor element 8 and the pad 52 provided around the punched hole 51 located in the center of the insulating film 5 are connected to the bonding wire 9
The connection is performed so that the copper foil circuit pattern and the semiconductor element 8 are electrically connected. The copper foil circuit pattern 4 and the mother board 1 are electrically connected by the solder balls 2. The periphery of the semiconductor element 8 and the periphery of the bonding wire 9 are sealed with the sealing resin 10. Here, as the sealing resin, for example, epoxy resin or the like is used. In addition, 3 is an insulating film, for example, a photosensitive resist material or the like is used.
【００１１】はんだボール２を銅箔回路パターン４と電
気的に接続するには、２００〜２５０℃でリフローはん
だ付けが行われる。To electrically connect the solder ball 2 to the copper foil circuit pattern 4, reflow soldering is performed at 200 to 250 ° C.
【００１２】ボンディングワイヤー９は、ボンディング
技術として完成されたものであり、ボンディングの信頼
性が向上する。さらに、接着フィルム４０の動きに容易
に追随し、使用時に断線するおそれが少ない。The bonding wire 9 has been completed as a bonding technique, and the reliability of bonding is improved. Furthermore, the movement of the adhesive film 40 is easily followed, and there is little risk of disconnection during use.
【００１３】接着用フィルム４０は多孔質の支持体７の
両面にエポキシ系の接着剤６、６を配する三層構造とし
たことにより、接着用フィルム４０には絶縁フィルム５
と半導体素子８の応力緩衝機構を持たすことができ、は
んだリフロー時の絶縁フィルムの絶縁層と接着用フィル
ムとの界面で剥離が生じることを防止することができ
る。また、接着用フィルム４０は多孔質の支持体７を有
しているので、はんだリフロー時接着層に含まれる揮発
成分を解放することができ、熱伸縮等によって絶縁フィ
ルムの絶縁層と接着用フィルムとの界面に剥離を生じる
ことを防止することができる。The adhesive film 40 has a three-layer structure in which epoxy adhesives 6, 6 are provided on both surfaces of the porous support 7 so that the adhesive film 40 has an insulating film 5
With this, a stress buffering mechanism for the semiconductor element 8 can be provided, and peeling can be prevented from occurring at the interface between the insulating film of the insulating film and the adhesive film during solder reflow. Further, since the adhesive film 40 has the porous support body 7, it is possible to release volatile components contained in the adhesive layer during solder reflow, and the insulating film of the insulating film and the adhesive film can be released by thermal expansion or contraction. It is possible to prevent peeling from occurring at the interface with.
【００１４】さらに接着用フィルム４０は、はんだリフ
ロー温度領域（２００〜２５０℃）での絶縁フィルムの
絶縁層と接着用フィルムとの界面の接着強度が１００ｇ
ｆ以上を有することとした。このように構成することに
より、絶縁フィルム５と半導体素子８を強固に接着する
ことができ、はんだリフロー時の絶縁フィルムの絶縁層
と接着用フィルムとの界面で剥離が生じることを防止す
ることができる。Further, the adhesive film 40 has an adhesive strength of 100 g at the interface between the insulating film of the insulating film and the adhesive film in the solder reflow temperature range (200 to 250 ° C.).
It is decided to have f or more. With this configuration, the insulating film 5 and the semiconductor element 8 can be firmly bonded together, and peeling can be prevented from occurring at the interface between the insulating film of the insulating film and the adhesive film during solder reflow. it can.
【００１５】[0015]
【発明の効果】以上説明したように、本発明の半導体装
置によると、接着用フィルムの厚さのためにリードをＳ
字状に形成する必要がなく、ボンディング技術として確
立したボンディングワイヤーを用いることができるの
で、ボンディングの信頼性が向上する。また、接着用フ
ィルムは多孔質の支持体を有しているので、はんだリフ
ロー時接着層に含まれる揮発成分を解放することがで
き、熱伸縮等によって絶縁フィルムの絶縁層と接着用フ
ィルムとの界面に剥離を生じることを防止することがで
きる。さらに接着用フィルムは、はんだリフロー領域で
の絶縁フィルムの絶縁層と接着用フィルムとの界面の接
着強度が１００ｇｆ以上を有するため、絶縁フィルムと
半導体素子を強固に接着することができ、はんだリフロ
ー時の絶縁フィルムの絶縁層と接着用フィルムとの界面
で熱伸縮による剥離が生じることを防止することができ
る。As described above, according to the semiconductor device of the present invention, the leads are separated by S due to the thickness of the adhesive film.
Since it is not necessary to form in a letter shape and a bonding wire established as a bonding technique can be used, the reliability of bonding is improved. Further, since the adhesive film has a porous support, it is possible to release the volatile components contained in the adhesive layer during solder reflow, and the thermal expansion of the insulating film between the insulating layer and the adhesive film It is possible to prevent peeling at the interface. Furthermore, since the adhesive film has an adhesive strength of 100 gf or more at the interface between the insulating layer of the insulating film and the adhesive film in the solder reflow area, the insulating film and the semiconductor element can be firmly adhered to each other. It is possible to prevent peeling due to thermal expansion and contraction at the interface between the insulating layer of the insulating film and the adhesive film.
【図１】 本発明のＢＧＡ半導体装置の概念図である。FIG. 1 is a conceptual diagram of a BGA semiconductor device of the present invention.
【図２】 本発明に用いられる接着用テープの概念図で
ある。FIG. 2 is a conceptual diagram of an adhesive tape used in the present invention.
【図３】 従来の半導体装置の概念図である。FIG. 3 is a conceptual diagram of a conventional semiconductor device.
【図４】 従来の絶縁フィルムと半導体素子との接合
を示す概念図である。FIG. 4 is a conceptual diagram showing joining of a conventional insulating film and a semiconductor element.
【図５】 ＴＡＢテープのリードボンディングの概念図
である。FIG. 5 is a conceptual diagram of lead bonding of a TAB tape.
１ マザーボード ２ はんだボール ３ 絶縁皮膜 ４ ランド部 ５ 絶縁フィルム ６ 接着剤 ７ 支持体 ８ 半導体素子 ９ ボンディングワイヤー 1０ 封止樹脂 １４ リード ２０ 接着用フィルム ４０ 接着用フィルム 1 Motherboard 2 Solder balls 3 Insulation film 4 land section 5 insulating film 6 adhesive 7 Support 8 Semiconductor elements 9 Bonding wire 10 sealing resin 14 reed 20 Adhesive film 40 Adhesive film
───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉本 洋 茨城県日立市日高町５丁目１番１号 日立 電線株式会社総合技術研究所内 (72)発明者 鈴木 幸雄 茨城県日立市日高町５丁目１番１号 日立 電線株式会社総合技術研究所内 (72)発明者 萩谷 重男 茨城県日立市日高町５丁目１番１号 日立 電線株式会社総合技術研究所内 (72)発明者 高萩 茂治 茨城県日立市日高町５丁目１番１号 日立 電線株式会社総合技術研究所内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Hiroshi Sugimoto Hitachi, 1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture Electric Cable Co., Ltd. (72) Inventor Yukio Suzuki Hitachi, 1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture Electric Cable Co., Ltd. (72) Inventor Shigeo Hagiya Hitachi, 1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture Electric Cable Co., Ltd. (72) Inventor Shigeharu Takahagi Hitachi, 1-1 Hidaka-cho, Hitachi City, Ibaraki Prefecture Electric Cable Co., Ltd.
Claims (3)
着する絶縁フィルムと、接着用フィルムと接していない
絶縁フィルムの面上に位置し、ランド部およびボンディ
ング部とを有する配線と、ボンディング部と半導体素子
のパッドとをモールドする封止樹脂と、ランド部に搭載
されるはんだボールとからなり、接着用フィルムと絶縁
フィルムとは各々その中央部に打ち抜き孔を有し、か
つ、その打ち抜き孔は互いに重なるように位置し、ボン
ディング部は打ち抜きの周囲に位置するＢＧＡ型半導体
装置において、 前記ボンディング部と前記半導体素子のパッドとは、ボ
ンディングワイヤーにより電気的に接続されていること
を特徴とするＢＧＡ型半導体装置。1. An insulating film which is adhered to a semiconductor element via an adhesive film, a wiring which is located on the surface of the insulating film which is not in contact with the adhesive film, and has a land portion and a bonding portion, and a bonding portion. It consists of a sealing resin that molds the pad of the semiconductor element and a solder ball that is mounted on the land, and the adhesive film and the insulating film each have a punched hole in the center thereof, and the punched hole is In a BGA type semiconductor device, which is positioned so as to overlap with each other, and a bonding portion is positioned around the punching, the bonding portion and the pad of the semiconductor element are electrically connected by a bonding wire. Type semiconductor device.
て、前記接着用フィルムは多孔質の支持体を有し、支持
体の両面にエポキシ系の接着剤を配する三層構造である
ことを特徴とするＢＧＡ型半導体装置。2. The BGA type semiconductor device according to claim 1, wherein the adhesive film has a porous support, and has a three-layer structure in which an epoxy adhesive is disposed on both surfaces of the support. BGA type semiconductor device.
て、前記接着用フィルムは、はんだリフロー温度領域で
の絶縁フィルムの絶縁層と接着用フィルムとの界面の接
着強度が１００ｇｆ以上を有することを特徴とするＢＧ
Ａ型半導体装置。3. The BGA type semiconductor device according to claim 1, wherein the adhesive film has an adhesive strength of 100 gf or more at an interface between the insulating film of the insulating film and the adhesive film in a solder reflow temperature region. BG
A type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001324684A JP2003133478A (en) | 2001-10-23 | 2001-10-23 | BGA type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001324684A JP2003133478A (en) | 2001-10-23 | 2001-10-23 | BGA type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003133478A true JP2003133478A (en) | 2003-05-09 |
Family
ID=19141368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001324684A Pending JP2003133478A (en) | 2001-10-23 | 2001-10-23 | BGA type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003133478A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592709B2 (en) | 2005-10-27 | 2009-09-22 | Samsung Electronics Co., Ltd. | Board on chip package and method of manufacturing the same |
-
2001
- 2001-10-23 JP JP2001324684A patent/JP2003133478A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592709B2 (en) | 2005-10-27 | 2009-09-22 | Samsung Electronics Co., Ltd. | Board on chip package and method of manufacturing the same |
| US7923296B2 (en) | 2005-10-27 | 2011-04-12 | Samsung Electronics Co., Ltd. | Board on chip package and method of manufacturing the same |
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