JP2003243521A - Capacity element and semiconductor integrated circuit using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacity element of superior area efficiency in which there is no bias dependence in a capacity value, without an additional process for capacity. <P>SOLUTION: A first terminal 30 is connected to a p-type polysilicon 21 of a first pMOS gate capacitor 43, a p-type diffusion layer 15 and an n-type diffusion layer 14 of a second pMOS gate capacitor 44, an n-type polysilicon 20 of a first storage capacitor 40 and an n-type diffusion layer 14 of a second storage capacitor 41. A second terminal 31 is connected to a p-type diffusion layer 15 and an n-type diffusion layer 14 of the first pMOS gate capacitor 43, a p-type polysilicon 21 of the second pMOS gate capacitor 44, an n-type diffusion layer 14 of the first storage capacitor 40 and an n-type polysilicon 20 of the second storage capacitor 41. The first pMOS gate capacitor 43 and the second pMOS gate capacitor 44, and the first storage capacitor 40 and the second storage capacitor 41 have the same layouts. By appropriately adjusting the area ratio of the former and the latter, the bias dependence of the capacity value is made extremely small. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a capacitive element,
In particular, the present invention relates to a capacitive element that is suitable for use in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Necessity of Capacitance Element Independent of Bias: First, the necessity of a capacitance element independent of bias will be described. There are many and many integrated circuits that require a capacitance element whose capacitance value is constant independent of a bias voltage applied across the capacitance element. For example, a differential circuit, a switched capacitor circuit, and an operational amplifier circuit. In particular, a circuit having a differential configuration is not easily affected by noise, and thus has been widely used in recent years.

[Requirement for Capacitance Element]: In addition to the bias dependence of the capacitance value, the capacitance element for an integrated circuit needs to satisfy the following two requirements.

(1) No additional process for capacitance formation is required other than the CMOS standard process.

(2) The capacitance value per unit area is large.

With respect to the above (1), as will be described later, a bias-independent capacitance can be realized by adding a capacitance forming step. However, the addition of this step increases the manufacturing cost. This additional step is necessary if there is even one integrated circuit that requires a bias-independent capacitance on a semiconductor chip. Therefore, the additional process is frequently required, which is one of the factors that increase the manufacturing cost of the LSI. Therefore, CMOS
There is a strong demand for a capacitive element that can be formed only by a standard process and that does not depend on bias.

With respect to the above (2), if the capacitance value per unit area is small, the chip area increases due to an increase in the area occupied by the capacitive element, and the manufacturing cost increases. Therefore, a capacitive element having a large capacitance value per unit area is required.

A conventional capacitive element will be described. 14
FIG. 4 is a diagram schematically showing a cross-sectional structure of metal-insulating film-metal capacitor (hereinafter, referred to as “MIM capacitor”). Referring to FIG. 14, the insulating film 1 is formed between the upper electrode 10 and the lower electrode 11.
A capacitor is formed by inserting 2. As the electrode material of the upper electrode 10 and the lower electrode 11, aluminum, copper, titanium nitride, polysilicon to which impurities are added, or the like is used. The insulating film 12 has a silicon oxide film,
A silicon nitride film, a tantalum oxide film or the like is used.

In manufacturing this MIM capacitor, either one or both of the upper electrode 10 and the lower electrode 11
An additional process for forming the insulating film 12 is required separately.

The MIM capacitance is excellent in that the capacitance value does not depend on the bias, but the capacitance value per unit area is small. The design rule is about 1.0 fF / μm ^{2 in} the 0.13 μm CMOS process.

FIG. 15 is a diagram schematically showing a cross-sectional structure of polysilicon-insulating film-diffusion capacitance (hereinafter, also referred to as "poly-diffusion capacitance"). Referring to FIG. 15, a capacitance is formed by inserting a silicon oxide film 19 between the n-type diffusion layer 14 in the p-type silicon substrate 18 and the doped polysilicon 13. In the current CMOS standard process, an n-type diffusion layer is formed after polysilicon processing. For example, normally, after forming a pattern of gate polysilicon, an LDD region (extension region) is formed by ion implantation, a gate sidewall spacer is formed, and then a source.
The drain diffusion layer is formed, and the n-type diffusion layer is formed after processing the polysilicon. Therefore, in order to form this capacitance, an additional step for separately forming the n-type diffusion layer 14 of FIG. 15 is required.

In the capacitive element having the structure shown in FIG. 15, the n-type diffusion layer 14 immediately below the polysilicon 13 is always
Since it is in the storage state, there is almost no bias dependence of the capacitance value.

Then, as the silicon oxide film 19, MO
Since it uses the same gate oxide film as the S transistor,
The oxide film is thin and the capacitance value per unit area is large. 0.
In the 13 μm CMOS process, it is about 9.6 fF / μm ² .

FIG. 16 is a diagram schematically showing a sectional structure of a pMOS gate capacitor. Referring to FIG. 16, in a p-type silicon substrate 18, a p-type diffusion layer 15 and an n-type diffusion layer 14 are formed in an n-well 17, and a polysilicon 21 doped with a p-type impurity via a silicon oxide film 19. ("P
Type polysilicon "). Since the capacitive element having this structure is the structure itself of a normal pMOS transistor, no additional step is required for manufacturing the capacitive element.

The p-type polysilicon 21 is connected to the first terminal 30.
Then, the p-type diffusion layer 15 and the n-type diffusion layer 14 are connected to the second terminal 31.
I am trying.

FIG. 17 shows a power supply voltage of 1.5 V and 0.13 μm.
pMOS gate capacitance in the mCMOS process (see FIG.
6) shows the capacitance-bias voltage characteristic. As the bias voltage of the first terminal 30 with respect to the second terminal 31 is changed from positive to negative, the n-well region 17 immediately below the p-type polysilicon 21 is changed from the accumulation state (accumulation mode) to the depletion state (depletion mode). Inversion mode (inversion mod
e). As shown in FIG. 17, the capacitance value changes about four times due to the bias voltage, which is a problem.

FIG. 18 shows another structure of the capacitive element, n
It is a figure which shows typically the cross-section of the type | mold storage capacitor (it is abbreviated also as "storage capacitor"). In the p-type silicon substrate 18, the n-type diffusion layer 14 is formed in the n-well 17, and the n-type impurity-added polysilicon 20 (referred to as “n-type polysilicon”) is formed through the silicon oxide film 19. .

Since this n-type storage capacitor has a structure in which the p-well of a normal nMOS transistor is replaced with an n-well for a pMOS transistor, no additional step is required.

The n-type polysilicon 20 is connected to the first terminal 30.
In addition, the n-type diffusion layer 14 is used as the second terminal 31.

FIG. 19 shows a 1.5V, 0.13 μm CMO.
It is a figure which shows the capacity | capacitance-bias voltage characteristic of the storage capacity | capacitance in S process. First terminal 3 with respect to second terminal 31
As the bias voltage of 0 is changed from positive to negative, the n-well region 17 directly under the n-type polysilicon 20 changes from the accumulation state to the depletion state, and the capacitance value decreases. Therefore, the capacitance value is quadrupled by the bias voltage. It varies and is a problem.

[0021]

As described above, in the conventional capacitive element, in order to realize the capacitive element in which the bias value of the capacitance value is small, an additional process for forming the capacitance is added to the CMOS standard process. There is a problem that it will be necessary.

Therefore, the problem to be solved by the present invention is to provide an element capable of producing a capacitive element having a small capacitance value bias dependency without requiring an additional step for forming a capacitance,
And to provide a semiconductor integrated circuit.

[0023]

A capacitance element according to one aspect of the present invention which provides means for solving the above-mentioned problems is desired by connecting a plurality of capacitance elements having a bias value of capacitance value. To realize the characteristics of. In the capacitive element according to the present invention, bias dependency of the capacitance value is eliminated. In the capacitive element according to the present invention,
It is symmetrical with respect to both terminals of the capacitive element.

In the capacitive element according to the present invention, two diffusion layers of the first conductivity type and one diffusion layer of the first conductivity type are spaced apart from each other on the surface of the well of the second conductivity type provided in the semiconductor substrate of the first conductivity type. Two
A diffusion layer of a conductivity type, a gate electrode is provided on the substrate surface between the two diffusion layers of the first conductivity type via an insulating film, and the gate electrode is connected to one terminal; The diffusion layer of the first conductivity type and the diffusion layer of the second conductivity type are
Two capacitors configured to be commonly connected to one terminal (referred to as “first and second capacitors”) are provided, and they are mutually formed on the surface of the second conductivity type well provided in the first conductivity type semiconductor substrate. Two diffusion layers of the second conductivity type are provided separately from each other, a gate electrode is provided on the substrate surface between the two diffusion layers of the second conductivity type with an insulating film interposed, and the gate electrode is one terminal. And two capacitors of the second conductivity type are commonly connected to the other one terminal (“third,”
A fourth capacitance ”), the first capacitance of the gate electrode, the second capacitance of the two first conductivity type diffusion layers and the second conductivity type diffusion layer, and the third capacitance of the third conductivity type diffusion layer. The gate electrode of the capacitor and the two diffusion layers of the second conductivity type of the fourth capacitor are connected to each other by a wiring to form a first terminal of the capacitor, and the two electrodes of the first capacitor are connected. A diffusion layer of a first conductivity type and a diffusion layer of the second conductivity type; the gate electrode of the second capacitance; the two diffusion layers of the second conductivity type of the third capacitance; The gate electrode having the capacitance of 1 is connected to each other by a wiring to form a second terminal of the capacitance element.

That is, in the present invention, the first terminal is the first
Of p-type polysilicon with pMOS gate capacitance of
A p-type diffusion layer and an n-type diffusion layer having a MOS gate capacitance;
Is connected to the n-type polysilicon of the n-type storage capacitor and the n-type diffusion layer of the second n-type storage capacitor, and the second terminal is connected to the p-type diffusion layer and the n-type of the first pMOS gate capacitance. A diffusion layer and a p-type polysilicon of a second pMOS gate capacitance,
It is connected to the n-type diffusion layer of the first n-type storage capacitor and the n-type polysilicon of the second n-type storage capacitor. In the capacitive element according to the present invention, the first pMOS gate capacitance and the second pMOS gate capacitance
The same pMOS gate capacitance has the same layout, and similarly, the first n-type storage capacitance and the second n-type storage capacitance have the same layout. Further, in the capacitive element according to the present invention, the ratio of the area of the pMOS gate capacitance to the area of the n-type storage capacitance is set to a predetermined value to eliminate the bias dependence of the capacitance value.

A semiconductor integrated circuit according to another aspect of the present invention, which provides means for solving the above problems, includes the above-described capacitive element according to the present invention. A semiconductor integrated circuit according to another aspect of the present invention may have a configuration in which the above-described capacitive element according to the present invention is provided in a phase locked loop (PLL). A semiconductor integrated circuit according to another aspect of the present invention may have a configuration including the above-described capacitance element according to the present invention as a decoupling capacitance. A semiconductor integrated circuit according to another aspect of the present invention may have a configuration in which the above-described capacitive element according to the present invention is included in a circuit having a differential configuration. A semiconductor integrated circuit according to another aspect of the present invention may have a configuration in which the above-described capacitive element according to the present invention is included in a switched capacitor circuit. A semiconductor integrated circuit according to another aspect of the present invention may have a configuration in which the above-described capacitive element according to the present invention is included in an operational amplifier circuit.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. In the present invention, the principle of realizing a capacitive element whose capacitance value has a small bias dependency will be described. First, the first n
Attention is paid to the combined capacitance of the second storage capacitance (see FIG. 18) and the terminal connection of the first n-type storage capacitance inverted. FIG. 20 shows the capacitance-bias voltage characteristic of the n-type storage capacitor. In FIG. 18, in the n-well region 17 just below the polysilicon 20, the bias voltage changes between the accumulation state and the depletion state at the boundary of the flat-band voltage VFB1. The capacitance value at the flat band voltage is the flat band capacitance CFB. Maximum capacity C in accumulated state
It becomes max and becomes the minimum capacity Cmin in the depleted state. The capacitance value at 0V bias voltage is defined as C0.

VFB1 in formula (1), CFB in formula (2), Cma
Equation (3) represents x, and Equation (4) represents Cmin.

[0029]

[0030]

[0031]

[0032]

Where Eg is the band gap, q is the elementary charge, ΨB is the difference between the Fermi level and the intrinsic level, tox is the silicon oxide film thickness, LD is the Debye length, εox is the dielectric constant of the silicon oxide film, and εSi is the silicon. , WD represents the width of the depletion layer.

When VFB1 is applied to the gate electrode, the energy band on the semiconductor surface becomes flat, and the gate capacitance (equation (2)) at this time is the Cox defined by the silicon oxide film thickness tox and the Debye length in the semiconductor. The LD capacity is connected in series.

In the equation (1), the influences of the fixed charges of the silicon oxide film and the interface order are neglected. From formula (1), VFB1
Is always negative. In addition, from Expression (2) to Expression (4), C
When the device parameter of the MOS process is substituted, the relationship of the formula (5) is established for the capacitance CFB in VFB1 which is a negative value.

[0036]

Therefore, with respect to C0, the relationship of equation (6) holds.

[0038]

This is the first n-type storage capacitor and the first n-type storage capacitor.
This means that the combined capacitance of the second storage capacitors obtained by inverting the terminals of the mold storage capacitors is always the maximum at the bias voltage of 0V.

FIG. 21 shows the first n-type storage capacitor 40 and the second n-type storage capacitor 40.
3 shows the bias voltage dependence of each of the n-type storage capacitors 41 and the combined capacitor 42 in FIG. The combined capacitance becomes maximum at a bias voltage of 0 V, and the capacitance value decreases as the absolute value of the bias voltage increases.

Next, the first pMOS gate capacitance (see FIG. 16)
(See) and the combined capacitance of the second pMOS gate capacitance obtained by inverting the terminal connection of the first pMOS gate capacitance. FIG. 22 shows the capacitance-bias voltage characteristic of the pMOS gate capacitance. In FIG. 16, the n-well region 17 immediately below the polysilicon 19 changes between the inversion state and the depletion state at the threshold voltage Vt, and changes between the depletion state and the accumulation state at the flat band voltage VFB2. . The capacity is minimum in the depleted state. The capacitance value at 0V bias voltage is defined as C0. VFB2 is shown in equation (7).

[0042]

From equation (7), VFB2 is always a positive value.
On the other hand, the threshold voltage Vt is a negative value as long as it is in the enhancement mode. Therefore, since C0 is almost the minimum value of the capacitance, the first pMOS gate capacitance and the first pMO
This means that the combined capacitance of the second pMOS gate capacitances obtained by inverting the terminals of the S gate capacitances is always the minimum at the bias voltage of 0V.

FIG. 23 shows the first pMOS gate capacitance 43.
(See FIG. 16), and the bias voltage dependence of the first pMOS gate capacitance 43, the second pMOS gate capacitance 44 with the terminal connection inverted, and the combined capacitance 42. When the bias voltage is 0 V, the combined capacitance becomes the minimum, and the capacitance value increases as the absolute value of the bias voltage increases.

As described above, the capacitance-bias voltage characteristic (see FIG. 21) of the combined capacitance of the first n-type storage capacitance and the second storage capacitance obtained by inverting the terminals of the first n-type storage capacitance, and the first
By combining the pMOS gate capacitance of the above and the capacitance-bias voltage characteristic of the combined capacitance of the second pMOS gate capacitance obtained by inverting the terminal of the first pMOS gate capacitance (see FIG. 23) at an appropriate ratio. As shown in FIG. 4, it is possible to realize a capacitive element in which the capacitance value has a small bias dependency. The capacitive element according to the embodiment of the present invention includes the first and second pMOS gate capacitors (43, 44) and the first and second pMOS gate capacitors.
Of n-type storage capacitors (40, 41) and first and second terminals (30, 31), the first terminal (30) being the first
P-type polysilicon of pMOS gate capacitance (43) of
The p-type diffusion layer of the second pMOS gate capacitance (44) and n
The second terminal (31) is connected to the n-type diffusion layer, the n-type polysilicon of the first n-type storage capacitor (40), and the n-type diffusion layer of the second n-type storage capacitor (41). , A p-type diffusion layer and an n-type diffusion layer of the first pMOS gate capacitance (43), and a second
P-type polysilicon of pMOS gate capacitance (44),
The n-type diffusion layer of the first n-type storage capacitor (40) and the second n-type diffusion layer
It is connected to the n-type polysilicon of the type storage capacitor (41).

[0046]

EXAMPLES Examples of the present invention will be described with reference to the drawings in order to describe the above-described embodiments of the present invention in more detail. Power supply voltage 1.5V, 0.13μm CMO
A capacitive element was prototyped using the S process technology. Hereinafter, a description will be given according to this specific example.

[First Embodiment] FIG. 1 is a diagram schematically showing a configuration of a first embodiment of the present invention. Referring to FIG. 1, the capacitive element according to the first embodiment includes a p-type silicon substrate 18 and two pMOS gate capacitors shown in FIG.
Two n-type storage capacitors (abbreviated as “storage capacitors”) shown in FIG. 18 are formed. In this example. No additional step for forming the capacitance is required.

The first terminal 30 is connected to the p-type polysilicon 21 of the first pMOS gate capacitance 43, the p-type diffusion layer 15 and the n-type diffusion layer 14 of the second pMOS gate capacitance 44,
The n-type polysilicon 20 of the first storage capacitor 40 and the n-type diffusion layer 14 of the second storage capacitor 41 are connected. The second terminal 31 is connected to the p-type diffusion layer 1 of the first pMOS gate capacitance 43.
5 and the n-type diffusion layer 14, and the second pMOS gate capacitance 4
4 p-type polysilicon 21 and the first storage capacitor 40 n
The type diffusion layer 14 and the n-type polysilicon 20 of the second storage capacitor 41 are connected.

FIG. 2 is a diagram schematically showing a layout of a semiconductor device having a capacitive element according to an embodiment of the present invention. Referring to FIG. 2, the first and second pMOS gate capacitors 43 and 44 and the first and second storage capacitors 40 and 41 are arranged in a grid pattern. First pMOS gate capacitance 4
3 is the first n-well 1 provided on the p-type silicon substrate
7 _first surface, spaced apart from one another, are arranged along the one direction, the first diffusion layer 14 of n-type, the second p-type,
The third diffusion layer 15 is provided, and the first polysilicon 21 to which p-type impurities are added is provided on the substrate surface between the second and third diffusion layers 15 via an insulating film. Regions 50 _1, a gate region (area having a second, third diffusion layer 15 on both sides =
(Gate length x gate width) is shown. The second p next to it
The MOS gate capacitor 44 is arranged on the surface of the _second n-well 172 so as to be separated from each other and along one direction, and has an n-type fourth diffusion layer 14 and a p-type fifth diffusion layer 14. A sixth diffusion layer 15 is provided, and a second polysilicon 21 added with a p-type impurity is provided on the substrate surface between the fifth and sixth diffusion layers 15 via an insulating film. Region 50 _2, 5 on both sides, indicates a gate region having a sixth diffusion layer 15 (area = gate length × gate width). The first storage capacity 40 is
On the surface of the first n-type well 17 ₁ are provided n-type seventh and eighth diffusion layers 14 which are separated from each other, and an insulating film is provided on the substrate surface between the seventh and eighth diffusion layers. The third polysilicon 20 added with an n-type impurity is provided. Area 50 ₃
Indicates a gate region (area = gate length × gate width) having the seventh and eighth diffusion layers 14 on both sides. The second storage capacitor 41 includes n-type ninth and tenth diffusion layers 14 spaced apart from each other on the surface of the _second n-well 172, and the substrate surface between the ninth and tenth diffusion layers. The fourth polysilicon 20 to which n-type impurities are added via an insulating film is provided on the top. Area 50 _4, 9 on both sides, the diffusion layer 1 of the 10
4 shows a gate region having 4 (area = gate length × gate width).

The first pMOS gate capacitance 43 and the second pMOS gate capacitance 43
The MOS gate capacitors 44 have the same size layout configuration and are arranged adjacent to each other in one direction. The first storage capacitor 40 and the second storage capacitor 41 have the same size layout configuration and are arranged adjacent to each other along the one direction. Furthermore, the first pM
The OS gate capacitance 43 and the first storage capacitance 40 are arranged adjacent to each other along the direction orthogonal to the one direction. Then, the second pMOS gate capacitance 44 and the second storage capacitance 41 are arranged adjacent to each other along the direction orthogonal to the one direction. In the first pMOS gate capacitance 43 and the first storage capacitance 40, the gate region 5
0 ₁ and the second, third diffusion layer 15 on both sides thereof, the gate region 50 ₃ and the seventh on both sides, the diffusion layer 14 of the eighth, respectively, aligned along a direction orthogonal to the one direction Are arranged. In a second pMOS gate capacitance 44 a second storage capacitor 41, the gate region 50 ₂ and the fourth on both sides, a fifth diffusion layer 15, the both sides of the gate region 50 ₄ 9, 10 diffusion of The layers 14 are arranged in alignment along a direction orthogonal to the one direction.
The polysilicon 21 of the first pMOS gate capacitance 43,
The fourth, fifth, and sixth diffusion layers of the second pMOS gate capacitance 44, the polysilicon 20 of the first storage capacitance 40, and the ninth and tenth diffusion layers of the second storage capacitance 41 are They are connected to each other by the first wiring 51 ₁ on the wiring layer, and the second p
The polysilicon 21 of the MOS gate capacitor 44 and the first p
First, second and third diffusion layers of the MOS gate capacitance 43,
Polysilicon 20 of the second storage capacitor 41, the seventh of the first storage capacitor 40, and the diffusion layer of the first 8 are connected to each other by the second wiring 51 ₂ on the wiring layer. First wiring 51 ₁
Has four comb-teeth-shaped wirings extending from outside the regions of the first and second pMOS gate capacitors 43 and 44 into the region of the capacitive element. are connected by the diffusion layers 14 and 15 and the contact 52, the second wiring 51 ₂ which is disposed to face the first wiring 51 _1, the capacitor element from the area outside the first and second storage capacitor 40 and 41 It has four comb-teeth-shaped wires extending in the region, and they are connected to the corresponding diffusion layers 14 and 15, the gate polysilicon 20 and the contacts 52, respectively. First wiring 51 ₁ and ₂ the second wiring 51 is used as the two terminals of the capacitor. Note that the first pM
The polysilicon 21 of the OS gate capacitance 43 and the polysilicon 20 of the first storage capacitance 40 have contacts 52, respectively.
The polysilicon 21 of the second pMOS gate capacitor 44 and the polysilicon 20 of the second storage capacitor 41 are connected to each other via a contact 52.

The first pMOS gate capacitance 43 and the second pMOS gate capacitance 44 have the same layout in order to make the bias dependence characteristic of the capacitance value symmetrical with respect to the positive / negative of the bias between the two terminals of the capacitance. Similarly, the first storage capacitor 40 and the second storage capacitor 41 have the same layout.

The first and second pMOS gate capacitors 43, 4
The area of the gate region 50 of the first and second storage capacitors 4
When the area of the gate regions 50 of 0 and 41 is set to about 0.15 times, the bias dependence of the capacitance value is minimized, which is preferable. Since this ratio is uniquely determined for various CMOS processes to be used, the ratio may be determined in advance as a rule, and the designer may design the capacitive element of the present invention according to this rule.

In order to improve the frequency characteristics, the n-type polysilicon 20 and the p-type polysilicon 21 may be laid out so that the length and width of the n-type polysilicon 20 and the p-type polysilicon 21 are short. By reducing the area of the gate region, the gate capacitance value and the resistance value of the channel portion are reduced, and the frequency characteristic is improved.

The bias dependence of the capacitance value of the capacitance element according to the first embodiment will be described. FIG. 3 is a diagram showing a capacitance-bias voltage characteristic (actually measured value) of the capacitance element according to the first embodiment of the present invention. Bias dependence of capacitance value is small,
The amount of change in capacity is ± 3%. The capacitance per unit gate area is 6.3 fF / μm ^2, which is 34% smaller than the polysilicon-diffusion capacitance of 9.6 fF / μm ^2.
It is much larger than the capacity of 1.0 fF / μm ² .

Next, an equivalent circuit of the capacitive element according to the first embodiment of the present invention will be described. FIG. 5 is a diagram showing an equivalent circuit of the capacitive element (FIG. 1) according to one embodiment of the present invention. The gate capacitance 60 between the first terminal 30 and the second terminal 31 is an intrinsic component as a capacitive element, and the first terminal 3
0, or n well-p between the second terminal 31 and ground
The substrate capacitance 61 is a parasitic component.

As described above, by performing the layout symmetrically, the n well-p substrate capacitance 61 of the first terminal 30 is formed.
And the n well-p substrate capacitance 61 of the second terminal 31 is equal to each other. The n-well-p substrate capacitance 61 is the gate capacitance 6
It is as small as 1.7% of 0, which is excellent.

On the other hand, in the MIM capacitance shown in FIG. 14 and the polysilicon-diffusion capacitance shown in FIG. 15, the capacitance of the parasitic component is as large as 10% to 20% of the capacitance of the intrinsic component.

According to the first embodiment of the present invention, a capacitance element having a small bias dependence of capacitance value of ± 3% and a medium capacitance per unit area (6.3 fF / μm ² ) is used for capacitance formation. It has become possible to fabricate without requiring additional steps.

The advantage of the first embodiment of the present invention over the conventional MIM capacitance and poly-diffusion capacitance is that no additional process is required.

In contrast to the conventional pMOS gate capacitance and storage, the first embodiment of the present invention has an advantage that the bias dependency of the capacitance value is small.

[Second Embodiment] FIG. 6 is a diagram for explaining a second embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of a phase locked loop (hereinafter referred to as “PLL”). The input 70 and the output 71 are input to the phase comparator 72, and the phase comparator 72 outputs the control voltage 77. The control voltage 77 is input to the voltage controlled oscillator 74 via the loop filter 73. The loop filter 73 has a resistor 7
5 and a capacitor 76.

Conventionally, the storage capacitor shown in FIG. 18 was used as the capacitive element 76. However, in the storage capacitor, as shown in FIG. 19, when the control voltage 77 becomes 0.5 V or less, the capacitance value decreases. When the capacitance value of the loop filter 73 is changed by the control voltage 77, the transfer function of the PLL is changed and the jitter is increased.
Since the power supply voltage of the LSI is decreasing year by year, the control voltage is 77
The problem has become even more apparent.

Therefore, the PL according to the second embodiment of the present invention
In L, the capacitive element described in the first embodiment is used as the capacitive element 76 of the loop filter 73. That is, the capacitive element 76 of the loop filter 73 is composed of the capacitive elements shown in FIG. 1 and FIG.
The capacitance value of 6 does not depend on the terminal voltage. That is, the control voltage 77 does not change the capacitance value of the loop filter 73,
The characteristics of the PLL can be improved.

[Third Embodiment] FIG. 7 is a diagram for explaining a third embodiment of the present invention. A decoupling capacitor 82 is inserted between the power supply line 80 and the ground line 81 in order to reduce noise on the power supply line 80 and the ground line 81 due to the switching current of the circuit.

Conventionally, as the decoupling capacitance 82, the storage capacitance shown in FIG. 16, the nMOS gate capacitance, and the pMOS gate capacitance shown in FIG. 18 have been used.

However, even with the storage capacitor having the smallest bias dependence, the capacitance value decreases when the voltage between the power supply line 80 and the ground line 81 becomes 0.5 V or less as shown in FIG. Therefore, as the noise of the power supply line 80 and the ground line 81 increases, the voltage between the power supply line 80 and the ground line 81 decreases and the capacitance value also decreases. Therefore, the noise reduction effect of the decoupling capacitance 82 decreases. Occurs. Moreover, since the power supply voltage of the LSI is decreasing year by year, it is considered that this problem will become apparent in the future.

Therefore, in the third embodiment of the present invention, the capacitive element described in the first embodiment is used as the decoupling capacitor 82. With such a configuration, the decoupling capacitance value does not depend on the noise amount or the power supply voltage, and the noise on the power supply line 80 and the ground line 81 can be effectively reduced.

[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIGS. Figure 8
FIG. 9 is a diagram showing a configuration of a conventional PLL circuit having a differential configuration as a comparative example. Input 70 and output 71 are phase comparators 72
And the first comparator 72 outputs the first control voltage 78 and the second control voltage 79. First control voltage 78
And the second control voltage 79 is a differential signal. The first control voltage 78 and the second control voltage 79 are input to the voltage controlled oscillator 74 via the loop filter 73. In general, PL
The capacitance value of the loop filter 73 used in L is several hundred pF
And occupies most of the area of the PLL. In the conventional circuit, as the capacitive element 76 of the loop filter 73, as shown in FIG.
A storage capacity of 8 is used. But for storage capacity,
As shown in FIG. 19, since the capacitance value greatly changes depending on whether the bias voltage is positive or negative, the capacitance cannot be inserted between the first control voltage 78 and the second control voltage 79, and the first control voltage 78 cannot be inserted.
One resistor 75 and one capacitor 76 are used for each of the control voltage 78 and the ground voltage and between the second control voltage 79 and the ground voltage.

Therefore, the single structure P shown in FIG. 6 is used.
There is a problem that the area of the capacitor 76 is doubled and the area of the PLL is almost doubled in the differential PLL as compared with the LL.

FIG. 9 is a diagram showing the configuration of a PLL circuit using the capacitive element according to the present invention for the loop filter 73.
Since the capacitance element 76 according to the present invention has a small bias dependence of the capacitance value, the first control voltage 78 and the second control voltage 79 are provided.
It can be inserted between and.

The first control voltage 78 and the second control voltage 79
Is a differential signal, the required capacitance value may be half the capacitance value of the loop filter of the single configuration (single end configuration) PLL of FIG. The total sum of the capacitance values is shown in FIG.
1/4 times that of the conventional differential configuration PLL.

The capacitive element according to the first embodiment is shown in FIG.
34% capacity value per unit area compared to 8 storage capacity
Considering the smallness, the present invention makes it possible to reduce the area of the capacitance of the loop filter to 38% of the conventional one.

[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described. FIG. 10 is a diagram showing the configuration of the fifth embodiment of the present invention, and shows the circuit configuration of an integrator using a switched capacitor. Referring to FIG. 10, the integrator includes one operational amplifier 90, four switches 91, 92, 93 and 94 and two capacitors 95 and 9.
6 and 6. In the sampling mode, the first switch 91 and the third switch 93 are closed, the second switch 92 and the fourth switch 94 are opened, and the input 70 is sampled in the first capacitor 95. The second capacity 96 holds the previous value.

In the integration mode, when the first switch 91 and the third switch 93 are opened and the second switch 92 and the fourth switch 94 are closed, the charge of the first capacitor 95 becomes the second charge.
Is added to the capacitor 96 and the integration result is output.

Attention is now paid to the first capacitor 95. First
In the capacitance 95 of the first capacitance 95, the grounded terminal is reversed in the sampling mode and the integration mode.
The bias voltage applied to is continuously changing from a positive value to a negative value.

Therefore, in the prior art, the first capacitor 95 is replaced by the one shown in FIG.
The MIM capacity shown in 4 was used.

In this embodiment, the capacitance element according to the first embodiment (see FIGS. 1 and 2) is used as the first capacitance 95, so that an additional step for forming the capacitance is unnecessary and the capacitance area is reduced. Can be reduced to 16% of the conventional level.

[Sixth Embodiment] Next, a sixth embodiment of the present invention will be described. FIG. 11 is a diagram for explaining the sixth embodiment of the present invention, and the configuration of the operational amplifier is shown in a block diagram. Referring to FIG. 11, this operational amplifier includes a differential amplifier 97 for inputting a differential input signal, an amplification stage 98, and a buffer 99. In the operational amplifier,
In order to prevent oscillation, a phase compensating capacitor 76 of several 100 fF to several pF is used.

As shown in FIG. 11, this phase compensation capacitor 7
6 is inserted between the input and output of the amplification stage 78. The bias voltage applied to the phase compensation capacitor 76 continuously changes from a positive value to a negative value.

Conventionally, the MIM capacitor shown in FIG. 14 is used as the phase compensation capacitor 76. In this embodiment, by using the capacitance element according to the first embodiment as the phase compensation capacitance 76, an additional step for forming a capacitance is unnecessary, and the capacitance area can be reduced to 16% of the conventional one. It was

As described above, the capacitive element according to the present invention is applied.
Although one circuit has been described as an example, it goes without saying that the present invention can be applied to other circuits (analog-digital converter, digital-analog converter, etc.), sample-and-hold circuits, charge pumps, and the like. That is, it is suitable for use in an application example in which the voltage between terminals changes with time and the capacitance value is constant without depending on the voltage between terminals. The capacitive elements shown in FIGS. 1 and 2 may be registered in the library as basic capacitor cells.

[Seventh Embodiment] FIG. 12 shows a seventh embodiment of the present invention.
FIG. 6 is a diagram for explaining an example of FIG. It is configured by connecting two identical capacitive elements 76 in series. 24 is the same as FIG.
It is a figure which shows the bias dependence of the capacitance value of the 2nd capacitive element simple substance. The capacitance value changes due to the bias only in the range of -1V to 1V. However, when a capacitive element that changes in the range of −2 V to 2 V is required, this capacitive element alone cannot satisfy the requirement.

Therefore, as shown in FIG. 12, two capacitors are connected in series. FIG. 13 shows an example of the bias dependence of the capacitance value of the capacitance element configured by connecting the two capacitance elements 76 shown in FIG. 12 in series. Although the absolute value of the capacitance is halved as compared with FIG. 24, it has succeeded in realizing a capacitive element that changes in the range of −2V to 2V.

Although the present invention has been described with reference to each of the above embodiments, the present invention is not limited to the configuration of the above embodiments, and within the scope of the invention of each claim of the claims. Needless to say, it includes various variations and modifications that can be made by those skilled in the art.

[0085]

As described above, according to the capacitive element and the semiconductor integrated circuit of the present invention, a capacitive element having a small bias dependency of the capacitance value can be realized without requiring an additional step for forming a capacitance. There is an effect that it is possible.

According to the capacitive element and the semiconductor integrated circuit of the present invention, since the capacitance value per unit area is large,
Excellent area efficiency. As described above, according to the example in which the present invention is implemented, the area of the capacitance can be reduced to about 16% as compared with the conventional MIM capacitance.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a cross section of a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing bias dependence of a capacitance value according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a bias dependency of a capacitance value of a combined capacitance.

FIG. 5 is a diagram showing an equivalent circuit of the first exemplary embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a third exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a circuit configuration of a conventional PLL having a differential configuration.

FIG. 9 is a diagram showing a circuit configuration of a fourth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing a circuit configuration of a fifth exemplary embodiment of the present invention.

FIG. 11 is a diagram showing a circuit configuration of a sixth exemplary embodiment of the present invention.

FIG. 12 is a diagram showing a circuit configuration of a seventh exemplary embodiment of the present invention.

FIG. 13 is a diagram showing the bias dependence of the capacitance value according to the seventh embodiment of the present invention.

FIG. 14 is a diagram schematically showing a cross section of a conventional MIM capacitor.

FIG. 15 is a diagram schematically showing a cross section of a conventional poly-diffusion capacitor.

FIG. 16 is a diagram schematically showing a cross section of a conventional pMOS gate capacitor.

FIG. 17 is a diagram showing the bias dependence of the capacitance value of a conventional pMOS gate capacitance.

FIG. 18 is a diagram schematically showing a cross section of a conventional storage capacitor.

FIG. 19 is a diagram showing a bias dependence of a capacitance value of a conventional storage capacitor.

FIG. 20 is a diagram showing the bias dependence of the capacitance value of the storage capacitance.

FIG. 21 is a diagram showing bias dependence of a capacitance value of a combined capacitance of storage capacitors.

FIG. 22 is a diagram showing the bias dependence of the capacitance value of the pMOS gate capacitance.

FIG. 23 is a diagram showing bias dependence of a capacitance value of a combined capacitance of pMOS gate capacitances.

FIG. 24 is a diagram showing bias dependence of a capacitance value of a conventional capacitive element.

[Explanation of symbols]

10 Upper electrode 11 Lower electrode 12 Insulating film 13 Polysilicon doped with impurities 14 n-type diffusion layer 15 p-type diffusion layer 17 n-well 18 p-type silicon substrate 19 Silicon oxide film 20 n-type polysilicon 21 p-type polysilicon 30 First terminal 31 Second terminal 40 First storage capacity 41 Second storage capacity 42 synthetic capacity 43 First pMOS gate capacitance 44 Second pMOS gate capacitance 50 gate area 51 wiring 52 contacts 60 gate capacity 61 n-well-p substrate capacitance 70 inputs 71 outputs 72 Phase comparator 73 Loop filter 74 Voltage controlled oscillator 75 resistance 76 capacity 77 Control voltage 78 First control voltage 79 Second control voltage 80 power line 81 Ground wire 82 decoupling capacity 90 operational amplifier 91 First switch 92 Second switch 93 Third switch 94 Fourth switch 95 First capacity 96 Second capacity 97 Differential amplifier 98 amplification stage 99 buffer

Claims (19)

[Claims] 1. A surface of a well of the second conductivity type provided in a semiconductor substrate of the first conductivity type and two diffusion layers of the first conductivity type and one diffusion layer of the second conductivity type which are spaced apart from each other. A gate electrode is provided on the surface of the substrate between the two diffusion layers of the first conductivity type via an insulating film, the gate electrode is connected to one terminal, and the diffusion of the two first conductivity type is provided. A first layer and a second diffusion layer of the second conductivity type that are commonly connected to another terminal to form two capacitors (referred to as “first and second capacitors”); On the surface of the second conductivity type well provided on the conductivity type semiconductor substrate, two diffusion layers of the second conductivity type are provided apart from each other on the surface of the substrate between the two diffusion layers of the second conductivity type. A gate electrode via an insulating film, the gate electrode is connected to one terminal, and the two second conductivity type diffusion layers are provided. And two capacitors (referred to as “third and fourth capacitors”) that are configured by commonly connecting to the other one terminal, the gate electrode of the first capacitor, and the second capacitor. The two diffusion layers of the first conductivity type and the one diffusion layer of the second conductivity type, the gate electrode of the third capacitance, and the diffusion of the two second conductivity type of the fourth capacitance. A first terminal of the capacitive element connected to each other with a wiring, and the two first diffusion layers of the first conductivity type and the one diffusion layer of the second conductivity type; The gate electrode of the second capacitance, the two diffusion layers of the second conductivity type of the third capacitance, and the gate electrode of the fourth capacitance are connected to each other by wiring to form a second capacitance element. The terminal of
A capacitive element characterized by the above. 2. The gate area of the first capacitor and the third capacitor
The ratio of the area of the gate of the capacitance and the ratio of the area of the gate of the second capacitance and the area of the gate of the fourth capacitance are set to a predetermined value set in advance. The capacitive element according to claim 1. 3. The gate electrode having the first capacitance and the gate electrode having the second capacitance are made of polysilicon doped with an impurity of a first conductivity type, and the gate electrode having the third capacitance. The capacitive element according to claim 1, wherein the gate electrode of the fourth capacitor is made of polysilicon doped with an impurity of the second conductivity type. 4. A first and a second pMOS gate capacitor, a first and a second n-type storage capacitor, a first and a second terminal, and the first terminal, P of the first pMOS gate capacitance
Type polysilicon and p of the second pMOS gate capacitance
A second diffusion layer, an n-type diffusion layer, an n-type diffusion layer of the second n-type storage capacitance, and an n-type diffusion layer of the second n-type storage capacitance. Is p of the first pMOS gate capacitance.
Type diffusion layer and n-type diffusion layer, p-type polysilicon of the second pMOS gate capacitance, n-type diffusion layer of the first n-type storage capacitance, and n-type polysilicon of the second n-type storage capacitance. A capacitive element characterized by being connected to silicon. 5. The first pMOS gate capacitance and the second pMOS gate capacitance.
5. The layout of the p-MOS gate capacitor is the same as the layout, and the layout of the first n-type storage capacitor and the second n-type storage capacitor is the same. The described capacitive element. 6. The capacitance element according to claim 4, wherein the ratio of the area of the pMOS gate capacitance to the area of the polysilicon gate of the n-type storage capacitance is set to a predetermined value. 7. A capacitive element comprising at least two capacitive elements having a bias voltage dependency of a capacitance value connected in series to reduce the bias voltage dependency. 8. A semiconductor integrated circuit comprising the capacitive element according to claim 1. Description: 9. A semiconductor integrated circuit, comprising a phase-locked loop having the capacitive element according to claim 1 as a capacitance forming a loop filter. 10. A semiconductor integrated circuit comprising the capacitor according to claim 1 as a decoupling capacitor. 11. A semiconductor integrated circuit comprising a differential type circuit having the capacitive element according to claim 1 between a pair of differential signal lines. 12. A semiconductor integrated circuit comprising the capacitive element according to claim 1 as a capacitance of a switched capacitor circuit. 13. A semiconductor integrated circuit comprising an operational amplifier circuit having the capacitance element according to claim 1 as a phase compensation capacitance. 14. A second substrate provided on a first conductivity type semiconductor substrate.
A first diffusion layer of a second conductivity type and a second diffusion layer of a first conductivity type, which are spaced apart from each other and arranged along one direction, on the surface of the first well of the conductivity type. A first capacitor having a diffusion layer and a first gate electrode on the substrate surface between the second and third diffusion layers with an insulating film interposed between the first capacitance and the first capacitance; A second diffusion layer of the second conductivity type, which is spaced apart from each other on the surface of the second well of the second conductivity type and is arranged along one direction;
Conductive type fifth and sixth diffusion layers, and the fifth and sixth diffusion layers.
A second capacitor having a second gate electrode on the surface of the substrate between the diffusion layers via an insulating film; and a surface of a second well of the second conductivity type provided in the first conductivity type semiconductor substrate. A second conductive type seventh and eighth diffusion layers spaced apart from each other, and a second gate electrode provided on the substrate surface between the seventh and eighth diffusion layers via an insulating film. And a third capacitor and a second conductive type ninth and tenth diffusion layers spaced apart from each other on the surface of the second conductive type fourth well provided in the first conductive type semiconductor substrate. A fourth capacitor having a fourth gate electrode on the surface of the substrate between the ninth and tenth diffusion layers with an insulating film interposed therebetween, the first capacitor and the second capacitor. The third capacitors and the fourth capacitor have the same size layout configuration and are arranged adjacent to each other along the one direction. The capacitors have the same size layout configuration and are arranged adjacent to each other along the one direction, and the first capacitor and the third capacitor are arranged in a direction orthogonal to the one direction. And the second capacitor and the fourth capacitor are arranged adjacent to each other along a direction orthogonal to the one direction, and the first gate electrode And the fourth, fifth, and sixth diffusion layers, the third gate electrode, and the ninth and tenth diffusion layers are connected to each other by wiring to form a first terminal of the capacitive element. And the second gate electrode, the first, second, and third diffusion layers, the fourth gate electrode, and the seventh and eighth diffusion layers are connected to each other by wiring. A capacitive element, which is a second terminal of the capacitive element. 15. A gate region of the first capacitance and the second and third diffusion layers on both sides thereof, and a gate region of the third capacitance and the seventh and eighth diffusion layers on both sides thereof. Are arranged in line along a direction orthogonal to the one direction, and the gate region of the second capacitor and the fifth and fifth regions on both sides thereof are disposed.
The sixth diffusion layer and the gate region of the fourth capacitor and the ninth and tenth diffusion layers on both sides thereof are arranged in alignment along a direction orthogonal to the one direction. 15. The capacitive element according to claim 14, wherein 16. A first wiring part connected to the first gate electrode, which is connected to the third gate electrode, and the fourth wiring part.
Second wiring portion connected to the diffusion layer of No. 5, a third wiring portion connected to each of the fifth diffusion layer and the ninth diffusion layer, the sixth diffusion layer and the tenth diffusion layer. Fourth wiring portions connected to the diffusion layer and the fourth wiring portions are arranged in this order, and each wiring portion protrudes like a comb from a fifth wiring portion commonly connected to each wiring portion. A first wiring; a first wiring portion connected to the first diffusion layer;
A second wiring portion connected to each of the diffusion layer and the second diffusion layer, a third wiring portion connected to each of the eighth diffusion layer and the third diffusion layer, and Fourth wiring portions connected to the fourth gate electrode connected to the second gate electrode are arranged in this order from the one side, and each wiring portion is common to each wiring portion. 5th connecting
Second wirings protruding from the wiring portion in a comb shape, the first wirings and the second wirings are arranged to face each other, and the first wirings of the first wirings are arranged. The wiring portion is disposed between the second and third wiring portions of the second wiring, and the fourth wiring portion of the second wiring is the third and fourth wirings of the first wiring. It is arrange | positioned between parts, 14 or 15 characterized by the above-mentioned.
The capacitive element according to. 17. The capacitor according to claim 14, wherein a plurality of wells of the first to fourth wells are the same well. 18. The gate electrode having the first capacitance and the gate electrode having the second capacitance are made of polysilicon doped with an impurity of a first conductivity type, and the gate electrode having the third capacitance is used. 18. The gate electrode of the fourth capacitor is made of polysilicon doped with an impurity of the second conductivity type.
The capacitive element according to any one of 1. 19. A semiconductor device comprising the capacitive element according to claim 14.