JP2003273130A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

[PROBLEMS] To provide a compound semiconductor semiconductor device having good operation characteristics. SOLUTION: A high resistance layer 2, a channel layer 3 made of Si-doped GaAs, and an undoped GaAs are formed on a substrate 1.
And a contact layer 5 of Si-doped GaAs is formed. At the center of the mesa, the contact layer 5 is removed by etching, and the high-resistance layer 4 is exposed. A gate electrode 8 is formed on the exposed high-resistance layer 4 to have a recess structure. From the top of the contact layer 5 to the side of the mesa,
A source electrode layer 6 and a drain electrode layer 7 are formed. The passivation layers 9a and 9b cover the region of the contact layer 5 where the source electrode layer 6 and the drain electrode layer 7 are not formed and the high resistance layer 2. Since the passivation layers 9a and 9b are made of a silicon oxynitride film, the strain applied to the device can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Field effect transistors, such as FETs and HEMTs, formed on a compound semiconductor substrate made of GaAs, InP, etc., are characterized in that they can operate at ultrahigh speeds and high frequencies. For this reason, vigorous research and development has been carried out, and metal-
Semiconductor field effect transistor (MESFET), metal-
Insulator-semiconductor transistors (MISFETs) and the like have been reported.

FIG. 12A is a sectional view showing a conventional field effect transistor (MESFET) structure. In the conventional MESFET, the high resistance layer 1 is formed on the substrate 101.
02, a channel layer 103, a high resistance layer 104, and a contact layer 105 are formed.

In the mesa portion, the central portion of the contact layer 105 is removed by etching, and a gate electrode layer 108 having a recess structure is formed on the exposed high resistance layer 104. A source electrode layer 106 and a drain electrode layer 107 are formed over the contact layer 105 and the side surface of the mesa portion. A region of the contact layer 105 where the source electrode layer 106 and the drain electrode layer 107 are not formed and the high resistance layer 102 are covered with a passivation layer 109 made of a silicon oxide film.

FIG. 12B is a sectional view showing the structure of a conventional field effect transistor (MISFET). In the conventional MISFET, a semiconductor layer 112 made of n-GaAs is formed on a semi-insulating substrate 111 made of GaAs to which Fe is added, and an upper part of the semiconductor layer 112 is a source layer made of n ⁺ -GaAs. Drain region 113
Has become. A gate electrode 115 is formed on the channel of the semiconductor layer 112 with a gate insulating film 114 made of a silicon oxide film interposed therebetween, and a source / drain electrode 116 is formed on the source / drain region 113 of the semiconductor layer 112. There is.

[0006]

[Problems to be Solved by the Invention] However, GaA
FE formed on a compound semiconductor substrate such as s or InP
In field effect transistors such as T and HEMT,
There is a problem that defects or dislocations at the device interface occur due to the strain applied to the device surface by the passivation layer or the gate insulating film. Therefore, it is difficult to maintain a desired breakdown voltage when the distance between the gate and the channel is reduced.

Further, since a compound semiconductor is generally a polar compound, when elastic stress acts on its surface, polarization is induced inside the semiconductor crystal. Such a phenomenon is the piezoelectric effect. In MESFETs, HEMTs, etc., the piezoelectric stress is generated due to the elastic stress from the passivation layer or the gate insulating film, which causes variations in the threshold voltage and the saturation current.

The present invention realizes a low interface state density by reducing the strain applied to the device surface by the passivation layer or the gate insulating film, and improves the device characteristics such as the gate breakdown voltage by reducing the piezoelectric effect. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof.

[0009]

The semiconductor device of the present invention comprises:
A semiconductor substrate, a compound semiconductor layer formed on the semiconductor substrate and having an active region, and an insulating film formed in a region above the active region in the compound semiconductor layer and containing silicon, oxygen and nitrogen. It is characterized by including.

This makes it possible to reduce the strain applied to the device surface by the insulating film. Therefore, the device characteristics such as the gate breakdown voltage can be improved, and high functionality and downsizing can be achieved. In addition, since it is possible to suppress the occurrence of the piezo effect, it is possible to suppress fluctuations in the threshold voltage, the saturation current, and the like.

The insulating film may be a silicon oxynitride film.

The insulating film may be a multilayer film in which at least one silicon oxide film and at least one silicon nitride film are laminated.

A gate electrode, which is in Schottky contact with the active region, is further provided on the active region, and the insulating film is provided on a side of the gate electrode.
The effects of the present invention can be obtained in high-speed / high-frequency devices.

A gate electrode facing the active region may be formed on the insulating film with the insulating film interposed therebetween.

The compound semiconductor layer is composed of GaAs, In
P, ZnSe, InGaAs, InAlAs, InGa
AsN, InGaAsP, InGaPN, GaN, Al
It is preferably any one of GaN and InGaN.

The upper surface of the compound semiconductor layer is {110}
One of the {111} plane and {100} plane
By this, the strain amount generated in the device can be greatly reduced.

The semiconductor device manufacturing method of the present invention comprises a step (a) of forming a compound semiconductor layer on a semiconductor substrate, a step (b) of cleaning the surface of the compound semiconductor layer, and the compound semiconductor layer. A step (c) of forming an insulating film containing silicon, oxygen and nitrogen above the inner active region.

As a result, it is possible to obtain a semiconductor device in which the insulating film exerts a small strain on the device surface. Therefore, the element characteristics such as the gate breakdown voltage can be improved, and the semiconductor device can be made highly functional and miniaturized.
Also, since it is possible to suppress the occurrence of the piezo effect,
It is possible to obtain a semiconductor device in which variations in threshold voltage, saturation current, etc. are suppressed.

In the step (c), a silicon oxynitride film may be formed as the insulating film.

In the step (c), at least one silicon oxide film and at least one silicon nitride film are alternately used as the insulating film.
You may form the multilayer film laminated | stacked layer by layer.

After the step (b), there is further provided a step of forming a gate electrode in Schottky contact with the active region of the compound semiconductor layer, so that a semiconductor for high speed / high frequency in which strain or the like is suppressed is suppressed. The device can be obtained.

After the step (c), there may be further provided a step of forming a gate electrode on the insulating film.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In this embodiment, a GaAs MESFET (Metal Semiconductor Fis) having a passivation film made of a silicon oxynitride film is provided.
eld Effect Transistor) will be described as an example. Figure 1,
FIG. 2 is a plan view and a sectional view showing the structure of the semiconductor device of the first embodiment. FIG. 2 shows a cross section taken along the line II-II in FIG. The dimensions in FIGS. 1 and 2 do not necessarily match the actual dimensions.

As shown in FIG. 2, in the FET of this embodiment, a thickness of about 3 is formed on the substrate 1 which is semi-insulating GaAs.
A high resistance layer 2 made of undoped GaAs of 00 nm and a channel layer 3 made of Si-doped GaAs having a thickness of about 15 nm.
And a mesa portion composed of a high resistance layer 4 of undoped GaAs having a thickness of about 60 nm and a contact layer 5 of Si-doped GaAs having a thickness of 10 nm. Here, in the channel layer 3 and the contact layer 5, the doping density of Si is about 2 × 10 ¹⁸ cm ⁻³ .

At the central portion of the mesa portion, the contact layer 5 is removed by etching, and the upper surface of the high resistance layer 4 is exposed.
A gate electrode layer 8 having a recess structure and a gate width of about 150 μm and a gate length of about 0.5 μm is formed on the exposed high resistance layer 4.
Are formed. The gate electrode layer 8 is made of Al, Ti or the like, and forms good Schottky contact with the high resistance layer 4.

A source electrode layer 6 and a drain electrode layer 7 are formed over the contact layer 5 and the side surfaces of the mesa portion. Source electrode layer 6 and drain electrode layer 7
Are made of AuGe alloy or the like and form good ohmic contact with the contact layer 5.

A region of the contact layer 5 where the source electrode layer 6 and the drain electrode layer 7 are not formed and the upper portion of the high resistance layer 2 are covered with passivation layers 9a and 9b. Here, the passivation layers 9a and 9b
Is a silicon oxynitride (SiON) with a thickness of about 100 nm.
Consists of.

The semiconductor device manufacturing method of this embodiment will be described below with reference to FIGS. 3 (a) to 3 (c) and 4 (a) to 4 (c).
Will be described with reference to. 3 (a) to 3 (c) and FIG.
(A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. The dimensions in 3 (a) to (c) and FIGS. 4 (a) to 4 (c) do not always match the actual dimensions.

First, in the step shown in FIG. 3A, an undoped GaAs layer 2a having a thickness of about 300 nm and a thickness of about 300 nm are formed on the (100) plane of the substrate 1 made of semi-insulating GaAs by the epitaxial growth technique. About 15 nm thick Si-doped GaAs layer 3a and about 60 nm thick undoped GaA
s layer 4a and Si-doped GaAs layer 5 having a thickness of about 10 nm
a and.

Here, as the epitaxial growth technique, MBE (Molecular Beam Epitaxy) method, CBE (Ch
emical beam epitaxy method, OMVPE (Organic Metal
VaporPhase Epitaxy method, MOCVD (Metal Organic)
Chemial Vapor Deposition) method, chloride VPE (C
The hloride Vapor Phase Epitaxy method is suitable.

Next, in the step shown in FIG. 3B, the Si-doped GaAs layer 5 is formed based on the photolithography technique.
A resist 11 is deposited on a and patterned.
Then, wet etching is performed using an H ₂ SO ₄ —H ₂ O ₂ —H ₂ O based etching solution or the like to form a mesa composed of the high resistance layer 2, the channel layer 3, the high resistance layer 4 and the contact layer 5. To form a part.

Next, in the step shown in FIG. 3C, the substrate after removing the resist 11 has a vacuum degree of 1.33 × 10 ^−4.
It is introduced into an ECR plasma CVD apparatus of about Pa. After the introduction, the substrate temperature is set to about 300 ° C., and the substrate is left for about 10 minutes until the temperature stabilizes. Then microwave output 200
SiH ₄ gas at a flow rate of 10 ml / min and a flow rate of 2 at W
O ₂ gas at 0 ml / min and N ₂ gas at a flow rate of 20 ml / min are introduced to form a silicon oxynitride (SiON) film having a thickness of about 100 nm on the substrate.

Then, a resist 1 is formed on the silicon oxynitride film.
2 is deposited and patterned. Then, reactive ion etching is performed using CF ₄ gas to remove the portion of the silicon oxynitride film where the source / drain electrode layer is to be formed, whereby the upper part of the contact layer 5 and the high resistance layer 2 are formed. On top, passivation layers 9a and 9b made of a silicon oxynitride film are formed. Here, as the epitaxial growth technique, a plasma CVD method or the like may be used instead of the ECR plasma CVD method.

Next, in the step shown in FIG. 4A, the resist 12 remaining on the passivation layers 9a and 9b is removed. Then, an ohmic electrode such as AuGe is vapor-deposited and alloyed by using a metal vapor deposition method and a lift-off method, so that the source electrode layer 6 and the drain electrode layer are formed over the contact layer 5 and the side surface of the mesa portion. Form 7. Here, a vacuum vapor deposition method, a sputtering method, or the like is suitable as the metal vapor deposition method.

Next, in the step shown in FIG. 4B, a resist 13 is deposited on the substrate and patterned by the photolithography technique. Then, the high-resistance layer 4 is formed by removing the passivation layer 9a and the contact layer 5 in the central portion of the mesa based on the wet etching method.
Expose. Here, the passivation layer 9a is CF
Removed by reactive ion etching using ₄ gases,
The contact layer 5 is removed by using an H ₂ SO ₄ —H ₂ O ₂ —H ₂ O based etching solution or the like.

Next, in the step shown in FIG. 4C, a metal such as Al or Ti is vapor-deposited on the high resistance layer 4 exposed in the central portion of the mesa portion based on the lift-off method and the metal vapor deposition method. Then, the gate electrode layer 8 is formed. As shown in FIG. 1, the gate electrode layer 8 is formed so as to extend from the side surface of the step portion 10 of the mesa portion to the passivation layer 9b. Here, as the metal vapor deposition method, a vacuum vapor deposition method or a sputtering method, which has directivity for attachment of the gate metal, is suitable. Through the above steps, the semiconductor device of this embodiment is formed.

FIG. 5 is a graph showing the relationship between the amount of strain received by the device and the material of the passivation layer when the (110) plane of the substrate 1 is the main surface. As the passivation layer, the conventional silicon oxide film and silicon nitride film and the silicon oxynitride film (SiO 2) of the present embodiment are used.
N) was used. The strain amount when the silicon oxide film was used as the passivation layer was set to 1, and the strain amounts when the silicon nitride film and the silicon oxynitride film were standardized. The amount of strain given to each device by each passivation layer was measured by Raman spectroscopy.

As shown in FIG. 5, when the passivation layer is a silicon oxynitride film (SiON), the amount of strain received by the device is smaller than when the passivation layer is an oxide film or a nitride film.

That is, in this embodiment, the passivation layer is formed of a silicon oxynitride film, so that the strain applied to the device surface by the passivation layer is reduced as compared with the case of the conventional silicon oxide film or silicon nitride film. You can Thereby, generation of defects and dislocations at the device interface can be suppressed, and a low interface state density can be realized. As a result, the generation of leak current can be significantly suppressed. Therefore, the device characteristics such as the gate breakdown voltage are improved, and higher functionality can be achieved. Further, it becomes possible to reduce the distance between the gate and the channel while maintaining a desired gate breakdown voltage.

Since compound semiconductors such as GaAs and InP are generally polar compounds, when elastic stress acts on the surface of the compound semiconductor, polarization is induced inside the semiconductor crystal and a piezoelectric effect occurs. Conventionally, fluctuations in threshold voltage, saturation current, etc. due to the piezoelectric effect have been problems, but in the present embodiment, the strain applied to the device surface by the passivation layer or the gate insulating film can be reduced as described above, so The effect can be suppressed, and fluctuations in threshold voltage, saturation current, etc. can be suppressed.

The present invention is not limited to the above embodiment, and various modifications can be made.

In order to obtain the effects of this embodiment, the substrate 1
When the {110} plane of is used as the main plane, the strain can be particularly reduced, but another plane may be selected. For example, as shown in FIG. 6, the strain can be reduced even when the {111} plane of the substrate is selected. In addition, the substrate {10
The 0} plane may be selected.

In this embodiment, an ME using a GaAs substrate
Although the SFET has been described, in the present invention, the compound semiconductors InP, ZnSe, InGaAs, InAlA are used.
s, InGaAsN, InGaAsP, InGaPN,
Similar effects can be obtained also in MESFET, MOSFET, or HEMT using GaN, AlGaN, InGaN, or a polar material as a substrate material.

(Second Embodiment) In the present embodiment, Ga
As MESFET (Metal Semiconductor Field Effe
ct Transistor) as an example. 7 and 8 show
5A and 5B are a plan view and a cross-sectional view showing the structure of the semiconductor device of the second embodiment. FIG. 8 shows a cross section taken along the line VIII-VIII of FIG. 7. In addition, each dimension in FIG. 7 and FIG.
It does not always match the actual size.

As shown in FIG. 7, in the FET of this embodiment, a high-resistance layer 22 made of undoped GaAs having a thickness of about 300 nm is formed on a substrate 21 made of semi-insulating GaAs.
A channel layer 23 made of Si-doped GaAs having a thickness of about 15 nm, a high resistance layer 24 made of undoped GaAs having a thickness of about 60 nm, and a Si-doped GaAs having a thickness of 10 nm.
And a contact layer 25, which is a metal layer, are formed. Here, the channel layer 23 and the contact layer 25
Then, the doping density of Si is about 2 × 10 ¹⁸ cm −3.

In the central portion of the mesa portion, the contact layer 25 is removed by etching, and the upper surface of the high resistance layer 24 is exposed. A gate electrode layer 28 having a recess structure and a gate width of about 150 μm and a gate length of about 0.5 μm is formed on the exposed high resistance layer 24. The gate electrode layer 28 is A
1 and Ti, and forms good Schottky contact with the high resistance layer 24.

A source electrode layer 26 and a drain electrode layer 27 are formed over the contact layer 25 and the side surface of the mesa portion.
Are formed. The source electrode layer 26 and the drain electrode layer 27 are made of AuGe alloy or the like, and the contact layer 2
5 and good ohmic contact are formed.

Source electrode layer 2 on the contact layer 25
6 and the region where the drain electrode layer 27 is not formed, and the top of the high resistance layer 22 are the passivation layer 29.
It is covered with a and 29b. Here, the passivation layers 29a and 29b are formed of a multilayer film in which a silicon oxide film having a thickness of 10 nm and a silicon nitride film having a thickness of 10 nm are alternately laminated.

The manufacturing method of the semiconductor device of this embodiment will be described below with reference to FIGS. 9 (a) to 9 (c) and 10 (a).
This will be described with reference to (c). 9 (a) to (c),
10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device of the second embodiment. 9 (a) to (c),
The dimensions in FIGS. 10A to 10C do not always match the actual dimensions.

First, in the step shown in FIG. 9A, an undoped GaAs layer 22a having a thickness of about 300 nm and a thickness of about 300 nm are formed on the (100) plane of the substrate 21 made of semi-insulating GaAs, based on the epitaxial growth technique. About 15 nm thick Si-doped GaAs layer 23a, about 60 nm thick undoped GaAs layer 24a, and about 10 nm thick Si-doped Ga layer.
The As layer 25a is formed.

Here, as the epitaxial growth technique, MBE (Molecular Beam Epitaxy) method, CBE (Ch
emical beam epitaxy method, OMVPE (Organic Metal
vaporPhase Epitaxy method, MOCVD (Metal Organic)
Chemial Vapor Deposition) method, chloride VPE (C
The hloride Vapor Phase Epitaxy method is suitable.

Next, in the step shown in FIG. 9B, the Si-doped GaAs layer 2 is formed based on the photolithography technique.
A resist 31 is deposited on 5a and patterned. Then, wet etching is performed using an H ₂ SO ₄ —H ₂ O ₂ —H ₂ O based etching solution or the like,
A mesa portion including the high resistance layer 22, the channel layer 23, the high resistance layer 24, and the contact layer 25 is formed.

Next, in the step shown in FIG. 9C, the substrate after removing the resist 31 has a vacuum degree of 1.33 × 10 ^−4.
It is introduced into an ECR plasma CVD apparatus of about Pa. After the introduction, the substrate temperature is set to about 300 ° C., and the substrate is left for about 10 minutes until the temperature stabilizes. Then microwave output 200
Supply of SiH ₄ gas at a flow rate of 10 ml / min and O ₂ gas at a flow rate of 20 ml / min at W and a flow rate of 10 ml / min.
min SiH ₄ gas and flow rate 20 ml / min N
By alternately supplying ₂ gases, a thickness of 1 on the substrate
A 0 nm silicon oxide film and a 10 nm thick silicon nitride film are formed for 10 cycles. As a result, a multilayer film of a silicon oxide film / silicon nitride film having a thickness of about 100 nm is formed. Here, the film thickness and the period of the silicon oxide film and the silicon nitride film forming the multilayer film are not limited to 10 nm and 10 periods.

Subsequently, a resist 32 is deposited on the multi-layer film of silicon oxide film / silicon nitride film and patterned. Then, reactive ion etching is performed using CF ₄ gas to remove the portion of the multilayer film where the source / drain electrode layer is to be formed.
Of the silicon oxide film /
Passivation layer 29, which is a multilayer film of a silicon nitride film
a and 29b are formed. Here, as the epitaxial growth technique, plasma CV other than ECR plasma CVD is used.
Method D or the like may be used.

Next, in the step shown in FIG. 10A, the resist 32 remaining on the passivation layers 29a and 29b is removed. Then, an ohmic electrode such as AuGe is vapor-deposited and alloyed by using a metal vapor deposition method and a lift-off method, so that the source electrode layer 26 and the drain electrode layer are formed over the contact layer 25 and the side surface of the mesa portion. 27 is formed. Here, a vacuum vapor deposition method, a sputtering method, or the like is suitable as the metal vapor deposition method.

Next, in the step shown in FIG. 10B, the resist 33 is formed on the substrate based on the photolithography technique.
Is deposited and patterning is performed. Subsequently, the high resistance layer 34 is exposed by removing the passivation layer 29a and the contact layer 35 in the central portion of the mesa portion based on the wet etching method. Here, the passivation layer 2
9a is removed by reactive ion etching using CF ₄ gas, and the contact layer 25 is H ₂ SO ₄ —H ₂ O ₂ —H.
₂ Remove using an O ₂ -based etching solution.

Next, in the step shown in FIG. 10C, a metal such as Al or Ti is vapor-deposited on the high resistance layer 24 exposed at the central portion of the mesa portion based on the lift-off method and the metal vapor deposition method. Then, the gate electrode layer 28 is formed. Gate electrode layer 2
As shown in FIG. 7, the layer 8 is formed so as to extend from the side surface of the step portion 30 of the mesa portion onto the passivation layer 29b. Here, as the metal vapor deposition method, a vacuum vapor deposition method or a sputtering method, which has directivity for attachment of the gate metal, is suitable. Through the above steps, the semiconductor device of this embodiment is formed.

In this embodiment, when a silicon oxide film / silicon nitride film multilayer film, a silicon oxide film or a silicon nitride film is used as the passivation layer,
The strain applied to the device surface by each passivation layer was measured by laser Raman spectroscopy. As a result, when the passivation layer is a multi-layer film of silicon oxide film / silicon nitride film, the amount of strain received by the device is smaller than that in the case of a silicon oxide film or a silicon nitride film.

That is, in this embodiment, the strain applied to the device surface by the passivation layer can be reduced as compared with the case of the conventional silicon oxide film or silicon nitride film. Thereby, generation of defects and dislocations at the device interface can be suppressed, and a low interface state density can be realized. As a result, the generation of leak current can be significantly suppressed. Therefore, element characteristics such as breakdown voltage are improved, and high functionality can be achieved. Further, it is possible to reduce the distance between the gate and the channel while maintaining a desired breakdown voltage.

In general, since compound semiconductors such as GaAs and InP are polar compounds, when elastic stress acts on the surface of the compound semiconductor, polarization is induced inside the semiconductor crystal and a piezoelectric effect occurs. Conventionally, fluctuations in threshold voltage, saturation current, etc. due to the piezoelectric effect have been problems, but in the present embodiment, the strain applied to the device surface by the passivation layer or the gate insulating film is reduced to suppress the piezoelectric effect. Therefore, it is possible to suppress variations in threshold voltage, saturation current, and the like.

The present invention is not limited to the above embodiment, but various modifications can be made.

In order to obtain the effects of this embodiment, the substrate 1
It is desirable to use the {110} plane of
Other planes such as the 1} plane or the {100} plane may be selected.

In this embodiment, an ME using a GaAs substrate
Although the SFET has been described, in the present invention, the compound semiconductors InP, ZnSe, InGaAs, InAlA are used.
s, InGaAsN, InGaAsP, InGaPN,
ME whose substrate is GaN, AlGaN, InGaN, etc.
Also in SFET, MOSFET or HEMT,
The same effect can be obtained.

(Third Embodiment) In this embodiment, M of a compound semiconductor using a silicon oxynitride film as a gate insulating film is used.
The ISFET will be described.

FIG. 11A shows a structure of the semiconductor device of the third embodiment in which the source / drain regions are formed by ion implantation, and FIG. 11B shows the source / drain region.
It shows a structure in which the drain layer is formed by in-situ doping. The dimensions in FIGS. 11A and 11B do not always match the actual dimensions.

In the structure shown in FIG. 11A, n- is formed on the semi-insulating substrate 41 made of Fe-doped GaAs.
A semiconductor layer 42 made of GaAs is formed, and an upper portion of the semiconductor layer 42 is a source / drain region 43 made of n ⁺ -GaAs. A gate electrode 45 is formed on the channel of the semiconductor layer 42 with a gate insulating film 44 made of a silicon oxynitride film interposed therebetween, and a source / drain electrode 46 is formed on the source / drain region 43 of the semiconductor layer 42. There is.

In the structure shown in FIG. 11B, n− is formed on the semi-insulating substrate 51 made of GaAs to which Fe is added.
The semiconductor layer 52 made of GaAs is formed, and the semiconductor layer 52
A source / drain layer 53 made of n ⁺ -GaAs and a gate insulating film 54 made of a silicon oxynitride film are formed thereon. A gate electrode 55 is formed on the gate insulating film 54, and a source / drain electrode 56 is formed on the source / drain layer 53.

Here, a method of manufacturing the gate insulating film of this embodiment will be described. ECR plasma CVD with a degree of vacuum of about 1.33 × 10 ⁻⁴ Pa for the substrate that has been subjected to the previous process
Install it in the device. After the introduction, the substrate temperature is set to about 300 ° C., and the substrate is left for about 10 minutes until the temperature stabilizes. After that, Ar gas is introduced at a flow rate of 10 ml / min, and the semiconductor surface is plasma-cleaned by argon plasma for about 5 minutes. Then, SiH at a flow rate of 10 ml / min
₄ gases, O ₂ gas with a flow rate of 20 ml / min, and a flow rate of 2
A gate insulating film made of a silicon oxynitride (SiON) film having a thickness of about 10 nm is formed on the substrate by introducing 0 ml / min of N ₂ gas.

In this embodiment, MI using a GaAs substrate
Although the SFET has been described, in the present invention, the compound semiconductors InP, ZnSe, InGaAs, InAlA are used.
s, InGaAsN, InGaAsP, InGaPN,
ME using GaN, AlGaN, InGaN, etc. as a substrate
Similar effects can be obtained in SFET and HEMT.

Instead of argon plasma cleaning, O ₂ gas was introduced at a flow rate of 20 ml / min, and 5
Oxygen plasma treatment may be performed for about a minute. In the oxygen plasma treatment, a natural oxide film is formed on the substrate surface,
It is suitable for forming a silicon oxynitride film.

(Fourth Embodiment) In this embodiment, a compound semiconductor MISFET in which a multilayer film of a silicon oxide film / a silicon nitride film is used as a gate insulating film will be described.

The semiconductor device of this embodiment is shown in FIG.
In the structure shown in (a) and (b), the gate insulating film 4
4, 54 has a structure composed of a multilayer film of a silicon oxide film / silicon nitride film.

The method of manufacturing the gate insulating film of this embodiment will be described below. ECR plasma CVD with a degree of vacuum of about 1.33 × 10 ⁻⁴ Pa for the substrate that has been subjected to the previous process
Install it in the device. After the introduction, the substrate temperature is set to about 300 ° C., and the substrate is left for about 10 minutes until the temperature stabilizes. After that, Ar gas is introduced at a flow rate of 10 ml / min, and the semiconductor surface is plasma-cleaned by argon plasma for about 5 minutes. After that, SiH at a flow rate of 20 ml / min
₄ gas and O ₂ gas at a flow rate of 30 ml / min are introduced to form a silicon oxide thin film having a thickness of about 10 nm. Then, with SiH ₄ gas at a flow rate of 20 ml / min,
A N ₂ gas at a flow rate of 20 ml / min was introduced to obtain a thickness of 10
A silicon nitride thin film of about nm is formed. This process is repeated alternately to form a silicon oxide film / silicon nitride film multilayer film, and then the substrate is slowly cooled and taken out from the plasma CVD apparatus.

In this embodiment, the same effect can be obtained even if the order of forming the silicon oxide film and the silicon nitride film is exchanged.

In this embodiment, MI using a GaAs substrate
Although the SFET has been described, in the present invention, the compound semiconductors InP, ZnSe, InGaAs, InAlA are used.
s, InGaAsN, InGaAsP, InGaPN,
ME using GaN, AlGaN, InGaN, etc. as a substrate
Similar effects can be obtained in SFET and HEMT.

Instead of argon plasma cleaning, O ₂ gas was introduced at a flow rate of 20 ml / min, and 5
Oxygen plasma treatment may be performed for about a minute. In the oxygen plasma treatment, a natural oxide film is formed on the substrate surface,
It is suitable for forming a multilayer thin film of oxide film / nitride film. When the silicon nitride film is formed after the oxygen plasma treatment, the same effect as when the multi-layer thin film of silicon oxide film / silicon nitride film is used as the gate insulating film layer can be obtained.

[0077]

According to the present invention, since the strain applied to the device surface by the passivation layer or the gate insulating film can be reduced, the piezoelectric effect can be suppressed, and fluctuations in threshold voltage, saturation current, etc. can be suppressed. A suppressed field-effect transistor can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device of the first embodiment.

4A to 4C are cross-sectional views showing a manufacturing process of the semiconductor device of the first embodiment.

FIG. 5 is a graph showing the relationship between the amount of strain received by the device and the material of the passivation layer when the (110) plane of the substrate is the main surface.

FIG. 6 is a graph showing the relationship between the amount of strain received by the device and the material of the passivation layer when the (111) plane of the substrate is the main surface.

FIG. 7 is a plan view showing a structure of a semiconductor device according to a second embodiment.

FIG. 8 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment.

9A to 9C are cross-sectional views showing a manufacturing process of the semiconductor device of the second embodiment.

10A to 10C are cross-sectional views showing a manufacturing process of the semiconductor device of the second embodiment.

11A and 11B are cross-sectional views showing the structure of the semiconductor device according to the third and fourth embodiments.

12A and 12B are cross-sectional views showing the structure of a conventional semiconductor device.

[Explanation of symbols]

1 substrate 2 High resistance layer 3 channel layers 4 High resistance layer 5 Contact layer 6 Source electrode layer 7 Drain electrode layer 8 gate electrode 9a passivation layer 9b passivation layer 10 Step 11 Resist 12 Resist 13 Resist 21 board 22 High resistance layer 23 channel layer 24 High resistance layer 25 Contact layer 26 Source electrode layer 27 Drain electrode layer 28 Gate electrode layer 29a passivation layer 29b passivation layer 30 step 31 Resist 32 resist 33 Resist 41 substrate 42 semiconductor layer 43 Source / drain region 44 Gate insulating film 45 gate electrode 46 Source / drain electrodes 51 substrate 52 semiconductor layer 53 Source / drain layer 54 Gate insulating film 55 Gate electrode 56 Source / drain electrodes

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masahiro Deguchi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Shigeo Yoshii             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Asami Yoshi Suzuki             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5F102 FA01 GB01 GC01 GD01 GD10                       GJ05 GK05 GL05 GM05 GM07                       GN05 GQ01 GR01 GR04 GR15                       GT03 GV06 GV07 GV08 HC01                       HC11 HC15 HC24                 5F140 AA01 BA06 BA07 BA08 BA09                       BA10 BB06 BD01 BD09 BD10                       BE02 BE10

Claims (12)

[Claims] 1. A semiconductor substrate, a compound semiconductor layer formed on the semiconductor substrate and having an active region, and silicon, oxygen and nitrogen formed in a region located above the active region in the compound semiconductor layer. An insulating film including: a semiconductor device. 2. The semiconductor device according to claim 1, wherein the insulating film is a silicon oxynitride film. 3. The semiconductor device according to claim 1, wherein the insulating film includes a silicon oxide film and a silicon nitride film.
A semiconductor device comprising a multi-layer film in which at least one layer is laminated. 4. The semiconductor device according to claim 1, further comprising a gate electrode on the active region, the gate electrode being in Schottky contact with the active region, wherein the insulating film is the gate. A semiconductor device, which is provided on a side of an electrode. 5. The semiconductor device according to claim 1, wherein a gate electrode facing the active region is formed on the insulating film with the insulating film interposed therebetween. A semiconductor device characterized by the above. 6. The semiconductor device according to claim 1, wherein the compound semiconductor layer is GaAs, InP, ZnSe,
InGaAs, InAlAs, InGaAsN, InG
aAsP, InGaPN, GaN, AlGaN, InG
A semiconductor device, wherein the semiconductor device is any one of aN. 7. The semiconductor device according to claim 1, wherein an upper surface of the compound semiconductor layer has a {110} plane and a {11} plane.
A semiconductor device having one of a 1} plane and a {100} plane. 8. A step (a) of forming a compound semiconductor layer on a semiconductor substrate, a step (b) of cleaning the surface of the compound semiconductor layer, and a step (a) above an active region in the compound semiconductor layer. silicon,
A step (c) of forming an insulating film containing oxygen and nitrogen, the method for manufacturing a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the step (c), a silicon oxynitride film is formed as the insulating film. 10. The method of manufacturing a semiconductor device according to claim 8, wherein in the step (c), at least one silicon oxide film and at least one silicon nitride film are alternately laminated as the insulating film. A method for manufacturing a semiconductor device, which comprises forming a film. 11. The method for manufacturing a semiconductor device according to claim 8, wherein a gate which is in Schottky contact with the active region of the compound semiconductor layer after the step (b). A method of manufacturing a semiconductor device, further comprising a step of forming an electrode. 12. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a gate electrode on the insulating film after the step (c). A method of manufacturing a semiconductor device, comprising: