JP2003204058A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a decrease in capacitance value and an increase in leak current in a semiconductor device having a metal oxide film as a gate insulating film and doped polysilicon or doped polysilicon germanium as a gate electrode. Further, it prevents the exudation of the dopant from the electrode. SOLUTION: After depositing a hafnium oxide film 105, depositing tantalum metal 106, depositing doped silicon 108, and performing activation heat treatment. As a result,
Since the composite film 110 of tantalum silicide and tantalum oxide film is formed at the interface between the silicon substrate and the hafnium oxide film 105, the formation of the silicon oxide film that lowers the dielectric constant can be suppressed. With this composite film, the crystal grains of polysilicon do not penetrate the gate insulating film, so that the leakage current does not increase and there is no diffusion of the dopant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a method of manufacturing a MOSFET and a MOS capacitor having a high dielectric gate insulating film.

[0002]

2. Description of the Related Art In recent years, both high speed operation and low power consumption operation have been required for the characteristics of logic devices. In order to realize high speed operation, it is necessary to increase the gate capacitance of the MOSFET and increase the drive current. In the conventional gate oxide film structure using a silicon oxide film or a silicon oxynitride film, if the thickness of the insulating film is reduced to 1.5 nm or less in order to increase the gate capacitance, the leak current flowing through the capacitor increases. Therefore, even if high-speed operation can be realized, it is difficult to reduce power consumption, and further, the original operation of the capacitor for accumulating charges becomes difficult.

Therefore, as a material of the gate insulating film of the MOSFET, a high dielectric constant metal oxide film, for example, aluminum, which has a higher relative dielectric constant than a silicon oxide film (relative dielectric constant: 3.9) is used. Oxide film (same: 9), zirconium oxide film (same: 20), hafnium oxide film (same: 2)
0), tantalum oxide film (25: the same), titanium oxide film (40: the same), etc. have been attempted (for example, Journal of Applied Physics vol. 89 5243 (2001).
See). Since the relative permittivity of these metal oxide films is larger than that of the silicon oxide film, the charge storage amount is large. For this reason, even if the capacitance value is the same, the actual physical film thickness can be set to be thick, and an increase in the leak current of the capacitor can be suppressed.

On the other hand, aluminum having a low resistivity has been used for a long time as a gate electrode material of MOSFET. However, since aluminum has a unique work function, the threshold voltage cannot be set individually for both the p-type MOSFET and the n-type MOSFET. Therefore, the channel structure of the transistor becomes a buried type, and it is difficult to increase the carrier mobility. Therefore, at present, silicon doped with impurities (doped silicon) is used as the gate electrode material instead of aluminum. As the dopant material (impurity for doping the silicon gate electrode),
The gate electrode of the n-type MOSFET is phosphorus (P), p-type M
Boron (B) or the like is used for the gate electrode of the OSFET, the work function of the doped silicon electrode can be controlled by selecting the dopant material, and the threshold value can be changed for each of p-type and n-type.

Therefore, the conventional MOSFET structure is
A combination of a silicon oxide film for the gate insulating film and doped silicon for the gate electrode is used.

[0006]

However, when the gate insulating film material is simply replaced with a high dielectric constant metal oxide film while using doped silicon as the electrode material, the high dielectric constant metal oxide film contains Oxygen atoms and silicon atoms in the doped silicon film diffuse with each other to form a silicon oxide film at the interface. When the silicon oxide film is formed at the interface, the relative permittivity of the silicon oxide film is lower than that of the high-dielectric-constant metal oxide film, so that the total capacitance value is significantly reduced. The advantage of using the melting point metal oxide film is lost.

The problem to be solved by the present invention is to suppress the mutual diffusion of oxygen atoms in the high dielectric constant metal oxide film and silicon atoms in the doped silicon film, which results in high speed operation and low power consumption operation. It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that are compatible with each other.

[0008]

A semiconductor device according to the present invention includes a first metal oxide film, a second metal oxide film, and a metal silicide contained in the second metal oxide film on a substrate. , A laminated structure in which an electrode containing silicon (doped silicon electrode) is in direct contact.

More specifically, a MOSFET having a high dielectric constant metal oxide film as a gate insulating film is characterized in that a metal is sandwiched at the interface between the gate insulating film and the doped silicon or doped silicon germanium electrode.

According to the semiconductor device of the present invention, the metal silicide contained in the second metal oxide film is prevented from diffusing silicon atoms between the first metal oxide film and the electrode containing silicon. Therefore, the formation of the silicon oxide film is suppressed. Further, since the second metal oxide film formed at the interface between the first metal oxide film and the silicide has a higher relative dielectric constant than the silicon oxide film, the capacitance value is high even if the second metal oxide film is formed. It never drops.

Further, even if the grains of the doped silicon electrode are formed during the activation heat treatment, since the metal silicide contained in the second metal oxide film exists, the electrode containing silicon and the first metal oxide film are Since the grain boundary does not penetrate during this period, the penetrated grains are not introduced into the high dielectric constant metal oxide film gate insulating film. Further, a high-dielectric-constant metal oxide film does not form a through-grain boundary in the gate insulating film, and a metal, high-dielectric-constant metal oxide film, or metal silicide exists on the gate insulating film. The dopant inside does not diffuse into the gate insulating film,
The threshold of does not change.

A method of manufacturing a semiconductor device according to the present invention has a structure in which a metal capable of forming a high dielectric film is sandwiched, and a step of forming a high dielectric constant metal oxide film gate insulating film; Rate metal oxide film a step of depositing a metal capable of forming a high dielectric film on the gate insulating film, a step of depositing a doped silicon electrode on the metal, and a heat treatment of the doped silicon electrode to electrically And a step of activating.

According to the present invention, since the metal capable of forming the high dielectric constant film is sandwiched between the high dielectric constant metal oxide film gate insulating film and the doped silicon electrode, the high dielectric constant metal oxide film is formed. Even when oxygen and silicon of the doped silicon film interdiffuse, due to the presence of the metal, oxygen reacts with the metal to form a metal oxide film, and silicon reacts with the metal to form a silicide. Therefore, the formation of the silicon oxide film is suppressed, and the capacitance value can be prevented from decreasing.

Further, even if the grain of the doped silicon electrode is formed during the activation heat treatment, the grain boundary does not penetrate due to the presence of the metal at the interface, so the penetrated grain is introduced into the high dielectric constant metal oxide film gate insulating film. It will not be done. Further, a through-grain boundary is not formed in the high dielectric constant metal oxide film gate insulating film,
Further, since the metal, the high dielectric constant metal oxide film, and the metal silicide are present on the gate insulating film, the dopant in the doped silicon electrode is not diffused into the gate insulating film and the threshold value of the MOSFET does not change.

A method of manufacturing a semiconductor device according to the present invention has a structure in which a metal capable of forming a high dielectric constant film is sandwiched between a high dielectric constant metal oxide film gate oxide film and a doped silicon electrode. Forming a high dielectric constant metal oxide gate insulating film, depositing a metal capable of forming a high dielectric constant film on the high dielectric constant metal oxide gate insulating film, and doping silicon on the metal It is characterized by including a step of depositing an electrode and a step of heat-treating the doped silicon electrode to electrically activate it.

A method of manufacturing a semiconductor device according to the present invention comprises a step of etching and cleaning a semiconductor substrate, a step of nitriding the semiconductor substrate to form a silicon nitride film, and a high dielectric constant on the high dielectric metal. A step of depositing a high-k metal oxide film, a step of heat-treating the high-k metal oxide film in a gas containing no oxygen, a step of depositing a high-dielectric metal film on the high-k metal oxide film, The method comprises the steps of depositing doped silicon on the high-dielectric metal and activating heat treatment of the doped silicon to form doped polysilicon. Another method of manufacturing a semiconductor device according to the present invention is a step of etching and cleaning a semiconductor substrate, a step of nitriding the semiconductor substrate to form a silicon nitride film, and a step of forming a silicon nitride film on the high dielectric metal. Depositing a dielectric constant metal oxide film, heat treating the high dielectric constant metal oxide film in a gas containing no oxygen, depositing a high dielectric metal on the high dielectric constant metal oxide film, The method comprises the steps of depositing doped silicon germanium on the high dielectric metal and activating heat treatment of the doped silicon germanium to form doped polysilicon germanium.

The nitriding of the semiconductor substrate in these cases is characterized by being formed by heat treatment in an ammonia atmosphere or heat treatment in an ammonia plasma atmosphere.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

First, as shown in FIG. 1A, a silicon substrate 101 is mounted on an STI (Shallow Trench).
Element isolation insulating film 102 is formed by a known element isolation method such as isolation, and is separated into an active region and an inactive region. A natural oxide film 103 is formed on the surface of the active region after the element isolation insulating film 102 is formed.

Next, as shown in FIG. 1B, the natural oxide film 103 is removed by etching with diluted hydrofluoric acid (HF: H2O = 1: 200), followed by washing with pure water and nitrogen blowing. The active area is exposed by drying. As a drying method, pure water may be replaced with isopropyl alcohol and then dried in a reduced pressure atmosphere.

Next, as shown in FIG. 1C, rapid thermal processing is performed in an ammonia atmosphere to nitride the surface of the silicon substrate 101 and form a silicon nitride film 104. The film thickness of the silicon nitride film 104 is about 1 nm or less. The conditions of the rapid thermal treatment are, for example, a temperature of 600 ° C. and a time of 30
Second, the pressure is 1 × 10 ⁵ Pa or less. Although rapid thermal processing is performed in this embodiment, a furnace may be used. The reason why the pressure is reduced to 1 × 10 ⁵ Pa or less is to prevent oxygen from being mixed into the silicon nitride film due to mixing of oxygen during the heat treatment. If oxygen is mixed, the relative dielectric constant of the silicon nitride film is reduced. Is significantly reduced and the total capacitance value of the capacitors is reduced.

The role of the silicon nitride film 104 is to suppress the reaction between the silicon substrate 101 and the film deposited on the silicon substrate 101, and to suppress the formation of hafnium silicide or silicon oxide film at the interface.

Next, as shown in FIG. 1D, a hafnium oxide film 105 is deposited by a chemical vapor deposition method (CVD method). The film thickness is 3 nm or more and 10 nm or less. The deposition conditions for the hafnium oxide film 105 are a deposition temperature of 400 ° C., a pressure of 30 Pa, and the source gas is a mixed gas of tetradiethylaminohafnium and oxygen (oxidizing gas). By using nitrogen as a carrier gas, the hafnium oxide film 10 is formed.
5 is deposited. Tetradiethylamino hafnium flow rate is 0.1 ml / min (standard state), carrier nitrogen flow rate is 500 ml / min (standard state), oxygen flow rate is 500 m.
1 / min (standard state).

The hafnium oxide film is deposited by CV
The method is not limited to the D method, and a sputtering method, an electron beam evaporation method, a molecular beam epitaxy method, or the like may be used. An example of the sputtering conditions that can be realized when depositing the hafnium oxide film 105 by the sputtering method is that metal hafnium is used as the sputtering target, the chamber pressure is 0.4 kPa, the sputtering power is 100 W, and the argon flow rate is about 20 ml / min (standard state). You can go in.

Next, the hafnium oxide film 105 is subjected to rapid thermal processing in a nitrogen atmosphere to remove impurities such as water contained in the CVD-deposited hafnium oxide film 105 by heating. The heat treatment conditions are a temperature of 400 ° C. or higher and a time of 30 seconds or longer. Since the desorption temperature of impurities is 400 ° C or higher,
The heat treatment requires a temperature of 400 ° C. or higher. In this embodiment, rapid thermal processing is used, but a furnace may be used.

Next, as shown in FIG. 2E, tantalum 106 is deposited by the sputtering method. The film thickness of the tantalum 106 may be 1 nm or less.

The deposition condition of tantalum 106 is that metal tantalum is used as the sputtering target, the chamber pressure is 0.4 kPa or more, the sputtering power is 50 W or less, and the argon flow rate is 20 ml / min (standard state).

The reason why the chamber pressure is 0.4 kPa or more and the sputtering power is 50 W or less is to reduce plasma damage to the high dielectric constant metal oxide film generated during sputtering.

Next, as shown in FIG. 2F, non-doped silicon 107 is deposited by the CVD method. Film thickness is 2
It is about 00 nm. The deposition conditions for the non-doped silicon 107 are a deposition temperature of 620 ° C. and silane gas as a source gas. The deposition temperature is preferably 600 ° C. or higher. The reason is that when the structure of the non-doped silicon 107 is in the amorphous phase, large grains are formed during the activation heat treatment, and the penetrating grain boundary is introduced into the gate insulating film. Therefore, when the non-doped silicon 107 is deposited, a crystalline phase containing microcrystals is preferable rather than a completely amorphous phase, and can be formed at a deposition temperature of 600 ° C. or higher.

Next, as shown in FIG. 2G, phosphorus or boron is ion-implanted into the non-doped silicon 107 to form the doped silicon 108. The ion implantation conditions are as follows: monovalent phosphorus at a dose of 10 keV and a dose of 8 × 10 ¹⁵ cm ^-2 , and boron implantation at 5 keV and a dose of 5 × 10 ¹⁵ cm ^-2. To do.

Next, as shown in FIG. 3H, a rapid thermal oxidation process is performed to activate the dopant of the doped silicon 108, and the activated doped polysilicon 10 is activated.
8a is formed. The heat treatment condition is 900 in a nitrogen atmosphere.
C, 30 seconds. Although the rapid thermal processing is used, a furnace may be used. When the furnace is used, the heat treatment conditions are 750 ° C. and about 30 minutes. At this time, the hafnium oxide film 105 and the doped polysilicon 108a are simultaneously formed.
The tantalum metal 106 at the interface of is transformed into a composite film 110 of tantalum silicide and tantalum oxide film. The composite film has more tantalum silicide as it is closer to the substrate side, and the composition is closer to that of the tantalum oxide film as it is closer to the hafnium oxide film.

As described above, according to the present invention, the conventional structure in which the doped silicon electrode and the high-dielectric-constant metal oxide film are in direct contact with each other is not preferable. Therefore, the oxygen atoms in the high-dielectric-constant metal oxide film and the doped silicon film are Metals such as tantalum are sandwiched in order to prevent mutual diffusion with the silicon atoms inside. The grain boundary generated in the doped polysilicon 108a due to the change of the tantalum metal into the composite film 110 of tantalum silicide and tantalum oxide film is not introduced into the hafnium oxide film 105, and therefore boron and phosphorus diffuse. Nor.

Next, as shown in FIG. 3I, a resist film is formed in the gate electrode region by a known method, and then a dry etching process is performed to form a gate capacitor structure.

Finally, as shown in FIG. 3 (j), a low-concentration impurity diffusion layer is formed, a sidewall 111 is formed,
High-concentration impurity diffusion layer to be source / drain (not shown)
A MIS type transistor having a high dielectric constant gate insulating film as a gate electrode is completed according to a normal manufacturing process of a MIS type transistor such as forming a.

Thus, the silicon substrate 101, the hafnium oxide film 105 as the gate insulating film, the activated polysilicon 108a as the upper electrode, the tantalum silicide and the tantalum oxide film at the interface between the gate insulating film and the gate electrode. A gate capacitor including the composite film 110 is configured. Although the hafnium oxide film is used as the gate insulating film in the embodiment, it may be a zirconium oxide film, a tantalum oxide film, or a titanium oxide film. Although tantalum was mentioned as the metal material, hafnium, zirconium,
Titanium or aluminum may be used.

The doped silicon film requires activation heat treatment at 900 ° C. or higher in order to electrically activate the dopant in the film. Generally, the doped silicon film immediately after deposition is composed of an amorphous phase or a microcrystalline phase, but it is changed to polycrystalline polysilicon having large grains by high temperature activation heat treatment. At this time, the crystal grains formed in the doped silicon film penetrate the underlying metal oxide film to form a grain boundary which is continuous in the high dielectric constant metal oxide film. Since the grain boundary formed in the insulating film acts as a current leakage path, the leakage current increases and the capacitor cannot operate.However, according to the present invention, even if the heat treatment for activating the doped silicon is performed, the metal remains on the interface. By providing the layer, an increase in leak current can be suppressed.

As the dopant of the doped silicon film, the n-type impurity is doped with phosphorus and the p-type impurity is doped with boron. Boron has a smaller atomic radius than phosphorus, and is very easy to diffuse in the film. Generally, the thickness of the metal oxide film gate insulating film is set to be thicker than that of the silicon oxide film, but if the grain boundary penetrates in the metal oxide film, the diffusion of boron through the grains is remarkable. Therefore, the boron reaching the silicon substrate fluctuates the threshold value of the MOSFET, but since the grain boundary does not penetrate into the metal oxide film, it is extremely effective in suppressing the diffusion of boron through the grain. Is big.

[0038]

As is apparent from the above description, in the semiconductor device of the present invention, the tantalum metal is deposited on the hafnium oxide film and then the doped silicon electrode is formed. Even if the above is performed, the hafnium oxide film and the doped silicon film do not react with each other to form a silicon oxide film, and the dielectric constant does not decrease. Even if the doped silicon film is crystallized into a doped polysilicon film, the grain boundary does not penetrate the hafnium oxide film and the leak current does not increase. Furthermore, since the grain boundary does not penetrate, boron diffuses and reaches the silicon substrate.
It does not change the threshold of the SFET.

In the semiconductor device according to the present invention, although the high dielectric constant metal oxide film is used as the gate insulating film, the silicon oxide film is not formed at the interface with the gate electrode such as doped silicon. It has good leak characteristics and can be used for next-generation logic devices that can achieve both high-speed operation and low-power consumption operation.

According to the method of manufacturing the semiconductor device of the present invention, it is possible to suppress the formation of the silicon oxide film which causes the capacitance value to decrease at the upper interface of the insulating film.
As a result, it is possible to prevent the crystal grains from penetrating the metal oxide film gate insulating film during the activation heat treatment of the doped silicon film, and further to significantly suppress the diffusion of boron.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a process sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the invention.

[Explanation of symbols]

101 Silicon substrate 102 element isolation insulating film 103 Natural oxide film 104 Silicon nitride film 105 hafnium oxide film 106 tantalum metal 107 non-doped silicon 108 doped silicon 108a Activated doped polysilicon 110 Composite film of tantalum silicide and tantalum oxide film 111 sidewall

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Claims (8)

[Claims] 1. A semiconductor device comprising a MOSFET having a high dielectric constant metal oxide film as a gate insulating film, wherein a metal is sandwiched at an interface between the gate insulating film and doped silicon or a doped silicon germanium electrode. 2. A step of etching and cleaning a semiconductor substrate, a step of nitriding the semiconductor substrate to form a silicon nitride film, and a step of depositing a high dielectric constant metal oxide film on the high dielectric metal. A heat treatment of the high dielectric constant metal oxide film in a gas containing no oxygen, a step of depositing a high dielectric constant metal on the high dielectric constant metal oxide film, and a doped silicon on the high dielectric constant metal. And a step of forming a doped polysilicon by activating heat treatment of the doped silicon to form doped polysilicon. 3. A step of etching and cleaning a semiconductor substrate, a step of nitriding the semiconductor substrate to form a silicon nitride film, and a step of depositing a high dielectric constant metal oxide film on the high dielectric metal. A heat treatment of the high dielectric constant metal oxide film in a gas containing no oxygen, a step of depositing a high dielectric constant metal on the high dielectric constant metal oxide film, and a doped silicon on the high dielectric constant metal. A method of manufacturing a semiconductor device, comprising: a step of depositing germanium; and a step of activating heat treatment of the doped silicon germanium to form doped polysilicon germanium. 4. A method of manufacturing a semiconductor device, wherein the nitriding of the semiconductor substrate according to claim 2 or 3 is performed by heat treatment in an ammonia atmosphere or heat treatment in an ammonia plasma atmosphere. 5. A method of manufacturing a semiconductor device, wherein the high dielectric metal according to claim 2 or 3 contains any one of hafnium, zirconium, tantalum, titanium, and aluminum. 6. The semiconductor device according to claim 2, wherein the high dielectric constant metal oxide film is an oxide film containing any one of hafnium, zirconium, tantalum, titanium, and aluminum. . 7. A method of manufacturing a semiconductor device, wherein the oxygen-free gas according to claim 2 or 3 contains any one of nitrogen, argon and hydrogen. 8. A method of manufacturing a semiconductor device, wherein the doped silicon film and the doped polysilicon film according to claim 2 or 3 are formed by using either ion implantation or diffusion.