JP2003209260A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in a gate electrode forming step of a GOLD structure TFT. <P>SOLUTION: The method for manufacturing the semiconductor comprises the steps of forming an island-shaped semiconductor film on an insulation board, forming a gate insulation film made of an oxide film on the semiconductor film, forming a first layer gate electrode film made of a nitride tantalum or a tantalum on the gate insulation film, forming a second layer gate electrode film made of a tungsten, a compound containing the tungsten as a main component or a tungsten nitride on the first gate electrode film, and forming a mask on the second layer gate electrode film. Thus, since a size of the second layer gate electrode film in a channel direction can be formed to become shorter than that of the first layer gate electrode film in the channel direction by a dry etching treatment of one step, the manufacturing steps of the GOLD structure TFT can be reduced. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a GOLD (Gate-Overlapped-LD).
Thin film transistor (Thin-Film-Transisto)
r: hereinafter abbreviated as TFT) and its manufacturing method.
In this specification, a semiconductor device means a GOLD structure T
This refers to all semiconductor devices including a circuit including semiconductor elements including FT, and includes semiconductor display devices such as active matrix liquid crystal display devices or organic EL (abbreviation of Electro-luminescence) display devices in its category.

[0002]

2. Description of the Related Art TF is formed on a transparent insulating substrate such as a glass substrate.
In a semiconductor display device such as an active matrix type liquid crystal display device or an organic EL display device configured by T, a polycrystalline silicon TFT having a high field effect mobility
Is attracting attention. In the case of a polycrystalline silicon film applied to a polycrystalline silicon TFT, the field effect mobility of electrons and holes is larger than that of a conventional amorphous silicon film, and not only in the pixel transistor but also in the peripheral circuit of the driver circuit. It has an advantage that integration can be realized. For this reason, each company is developing an active matrix type semiconductor display device including a circuit made of polycrystalline silicon TFTs.

While the polycrystalline silicon TFT has a high field effect mobility, when it is continuously driven, the field effect mobility and the on-current (current flowing in the on-state) are lowered and the off-current (the off-state is turned off). Deterioration phenomena such as an increase in the current sometimes flowing) may be observed, which is a reliability problem. This deterioration phenomenon is called a hot carrier phenomenon, and is known to be a work of hot carriers generated by a high electric field near the drain.

This hot carrier phenomenon is caused by a MOS (Metal-Oxide-Semiconducto) first fabricated on a semiconductor substrate.
(abbreviation of r) A phenomenon discovered in a transistor, and it has been clarified that it is caused by a high electric field near the drain. As a hot carrier countermeasure, various basic studies have been conducted so far, and MO with a design rule of 1.5 μm or less has been performed.
For S-transistors, LDD (Lightly-Doped-Dr)
The ain abbreviation) structure is adopted. In the LDD structure, an n-type or p-type low-concentration impurity region (n-region or p-region) is formed at the drain end using the sidewall of the gate side wall made of an insulating film, and the impurity concentration of the drain junction is increased. By providing the slope, the electric field concentration near the drain is relaxed. Here, the n-type low-concentration impurity region and the high-concentration impurity region are referred to as an n− region and an n + region, respectively, and p
P-type low concentration impurity regions and high concentration impurity regions
They are called −region and p + region.

However, in the LDD structure, the drain breakdown voltage is considerably improved as compared with the single drain structure.
Since the resistance of the low-concentration impurity region (n-region or p-region) is large, the drain current is reduced. In addition, since there is a high electric field region directly under the sidewall, impact ionization is maximized there, and hot electrons are injected into the sidewall, so that the low-concentration impurity region (n-region or p-region) is depleted, Further, the deterioration mode peculiar to the LDD in which the resistance increases further poses a problem. As the channel length shrinks, the above problems have become apparent,
In a MOS transistor of 0.5 μm or less, as a structure for overcoming such a problem, a low-concentration impurity region (n-region or p-region) is overlapped with the end portion of the gate electrode.
A GOLD structure for forming a film has been developed and is being applied to mass production.

Against this background, even in a polycrystalline silicon TFT manufactured on a transparent insulating substrate such as a glass substrate, an LDD structure is provided for the purpose of relaxing a high electric field in the vicinity of the drain like a MOS transistor. And the GOLD structure is being developed. The LDD structure means that an n-type or p-type low-concentration impurity region (n-region or p-region) functioning as an electric field relaxation region is formed in a semiconductor layer made of a polycrystalline silicon film corresponding to the outside of a gate electrode. Further, a high-concentration impurity region (n + region or p + region) of the same conductivity type, which functions as a source region and a drain region, is further formed outside thereof. The LDD structure has an advantage that an off current is small and a defect that a hot carrier suppressing effect by electric field relaxation near the drain is small. One GO
In the case of the LD structure, a low concentration impurity region (n-region or p
The region (-) is formed so as to overlap with the end of the gate electrode, and has the advantage that the effect of suppressing hot carriers is greater and the disadvantage that the off current is greater than in the LDD structure.

As described above, the LDD structure and the GOLD structure have advantages and disadvantages. Therefore, in an actual semiconductor display device, from the viewpoint of improving the quality of the semiconductor display device, the low off-current characteristic and the GOLD of the LDD structure are provided. A combination of circuit configurations that makes use of the high hot carrier resistance of the structure is being studied.
Specifically, in the case of the pixel TFT in the pixel region, a gate structure that focuses on reducing the off current value is preferable to high reliability against hot carriers, and an LDD structure having low off current characteristics is preferable. . On the other hand, in the case of a peripheral circuit including a driving circuit, a gate structure that emphasizes high reliability against hot carriers rather than low off-current characteristics is preferable, and a GOLD structure having high hot carrier resistance is preferable. Therefore, in a recent semiconductor display device including a circuit composed of a polycrystalline silicon TFT, the pixel T in the pixel region is
FT is formed by LDD structure TFT, and the peripheral circuit is GOLD.
Structure TFT tends to be formed.

Incidentally, n-channel type polycrystalline silicon GOL
As a known example of the D structure TFT, Non-Patent Document 1 discloses the structure and basic characteristics of an n-channel type GOLD structure TFT. GOLD structure TF studied here
In the structure of T, the gate electrode and the sidewall for LDD are formed of polycrystalline silicon, and the n-type low-concentration impurity region (n) which functions as an electric field relaxation region is formed in the active layer (formed of polycrystalline silicon) immediately below the sidewall for LDD. -Region), and a high concentration impurity region (n + region) of the same conductivity type that functions as a source region and a drain region is further formed on the outside thereof. Its basic characteristics are that a large drain current is obtained along with the relaxation of the drain electric field as compared with a normal LDD structure TFT, and the drain avalanche hot carrier (Drain-Avalanche-Hot-Carr) is obtained.
The characteristic is that the effect of suppressing ier) is large.

As another known example of a GOLD structure TFT, Japanese Patent Application Laid-Open Publication No. 2004-242242 discloses that "a gate electrode has a two-layer structure in which widths are different from each other, and an upper layer width is smaller than a lower layer width. A thin film transistor having an LDD structure and a "two-layer structure having different widths from each other, an upper layer having a width smaller than that of a lower layer is formed, and then the gate electrode is used as a mask to implant ions into a region serving as a source or a drain. A method of manufacturing a thin film transistor having an LDD structure, which is characterized in that the injection is performed ". In the patent publication, "If the accelerating voltage and the ion implantation amount at the time of ion implantation are appropriately selected, at the time of ion implantation, a region without a gate electrode is an n + region (or p + region), and a gate electrode has only one layer. The region is an n-region (or p-region), and the region having both gate electrodes is an intrinsic (non-implanted) region at the same time. "
Since the n-region (or p-region), which is the electric field relaxation region, overlaps the end of the gate electrode, the invention related to the GOLD structure TFT is disclosed.

In Patent Document 2, a gate electrode is formed in a two-layer laminated structure, and a GOLD structure TFT is manufactured by a dry etching process including a number of process steps of taper etching and anisotropic etching. Is disclosed.

In Patent Document 3, a film made of the material forming the gate electrode is formed, a mask is formed on the film made of the material forming the gate electrode, and a film made of the material forming the gate electrode is formed. By side etching,
An invention is disclosed in which a gate electrode having a width smaller than that of the mask is formed and impurities are introduced into the semiconductor film to form an LDD region.

[0012]

[Non-Patent Document 1] Mutuko Hatano, Hajime Akimoto and T
akesi Sakai, IEDM97 TECHNICAL DIGEST, p523-526,1997

[Patent Document 1] JP-A-7-202210

[Patent Document 2] Japanese Patent Laid-Open No. 2001-281704

[Patent Document 3] JP-A-7-226518

[0013]

The GOLD structure TFT excellent in hot carrier resistance is also under development at our company, and the structure of a typical GOLD structure TFT will be described below with reference to FIG. Figure 3-A is Lo
FIG. 3B is a cross-sectional view of a GOLD structure TFT having only a v region, and FIG. 3B shows a GOL having both a Lov region and a Loff region.
It is sectional drawing of D structure TFT. In this specification, the electric field relaxation region that overlaps with the gate electrode is referred to as a Lov region, and the electric field relaxation region that does not overlap with the gate electrode is referred to as a Loff region.

GOLD structure TF having only Lov region
The structure of T is that the substrate 301 is formed on the transparent insulating substrate 301.
From the side closer to the island-shaped semiconductor layer 302 and the gate insulating film 303
And a gate electrode 304 are stacked, and the source region 3 is formed on the island-shaped semiconductor layer 302 outside the gate electrode 304.
GOLD and the drain region 306 are formed.
In the structure TFT, the gate electrode 304 is composed of a first layer gate electrode 304a and a second layer gate electrode 304b, and the first layer gate electrode 304a has a longer dimension in the channel direction than the second layer gate electrode 304b. Formed,
The island-shaped semiconductor layer 3 corresponding to the exposed region of the first-layer gate electrode 304a from the second-layer gate electrode 304b.
02, a Lov region 307 which is an electric field relaxation region is formed, and the source region 305 and the drain region 3 are formed in the island-shaped semiconductor layer 302 corresponding to the outside of the gate electrode 304.
06 is formed (FIG. 3-A)
reference).

In the GOLD structure TFT having the above structure,
The Lov region 307 is an electric field relaxation region formed so as to overlap the end of the first-layer gate electrode 304a, and is an n-type or p-type low-concentration impurity region (n-region or p-type).
-Region). The Lov area 307 is
The drain region 306 has a concentration gradient such that the impurity concentration gradually increases as it approaches the source region 305 or the drain region 306, which is an n-type or p-type high-concentration impurity region (n + region or p + region). It has the feature of more effectively alleviating the electric field concentration in the depletion layer near. Such a concentration gradient of the Lov region 307 accelerates the n-type or p-type impurity element by an electric field, and the first-layer gate electrode 304a and the gate insulating film 303 corresponding to the exposed region from the second-layer gate electrode 304b. And a method of injecting into the island-shaped semiconductor layer 302 through a laminated film of
Made in. The concentration gradient is generated by injecting an impurity into the island-shaped semiconductor layer 302 by the through doping method when the first-layer gate electrode 304a, which is the upper layer film of the island-shaped semiconductor layer 302, is formed.
This is because the gate insulating film 303 (irrelevant because the film thickness does not change) is thinned toward the end. In the present specification, a doping method of injecting an impurity into a target material layer by passing a certain material layer located above the target material layer is referred to as a "through doping method" for convenience.

The structure of the GOLD structure TFT having both the Lov region and the Loff region is the transparent insulating substrate 40.
1, the island-shaped semiconductor layer 402 from the side closer to the substrate 401.
In a GOLD structure TFT in which a gate insulating film 403 and a gate electrode 404 are laminated, and a source region 405 and a drain region 406 are formed in the island-shaped semiconductor layer 402 outside the gate electrode 404. The gate electrode 404 includes a first-layer gate electrode 404a and a second-layer gate electrode 404b, and the first-layer gate electrode 404.
a is formed to be longer in the channel direction than the second-layer gate electrode 404b, and is formed on the island-shaped semiconductor layer 402 corresponding to an exposed region of the first-layer gate electrode 404a from the second-layer gate electrode 404b. Lov region 407, which is a field relaxation region, is formed in the island-shaped semiconductor layer 402 corresponding to the outer side of the gate electrode 404 from the side closer to the gate electrode 404, which is a second field relaxation region Lo.
ff region 408, source region 405, and drain region 4
06 are formed adjacent to each other (see FIG. 3-B).

In the GOLD structure TFT having the above structure,
The Lov region 407 is a first electric field relaxation region formed so as to overlap an end portion of the first layer gate electrode 404a, and is an n-type or p-type low-concentration impurity region (n− region or p− region). -Region). The Lov region 407 has a concentration gradient such that the impurity concentration gradually increases as it approaches the Loff region 408. Further, the Loff region 408 is the first layer gate electrode 404a.
The second electric field relaxation region formed so as not to overlap with the n-type or p-type low concentration impurity region (n−
Region or p-region). The Loff region 408 has a concentration gradient such that the impurity concentration gradually increases as it approaches the source region 405 or the drain region 406 which is an n-type or p-type high-concentration impurity region (n + region or p + region). ing. The Lov area 407
When the impurity is implanted into the island-shaped semiconductor layer 402 by the through doping method, the first layer gate electrode 404a (gate insulating film 403 is
This is due to the fact that the film thickness (irrelevant because there is no change in film thickness in that region) becomes thinner as it approaches the edge. Similarly, the concentration gradient of the Loff region 408 depends on the island-shaped semiconductor layer 4
This is because the thickness of the gate insulating film 403, which is the upper layer film of 02, becomes thinner with increasing distance from the gate electrode 404.

By the way, the GO shown in FIGS.
The gate electrodes 304 and 404 of the LD structure TFT are the first layer gate electrodes 304a and 404a and the second layer gate electrode 30.
4b and 404b, the first layer gate electrode 304
The a and 404a are formed to be longer in the channel direction than the second-layer gate electrodes 304b and 404b. And
The portions of the first-layer gate electrodes 304a and 404a corresponding to the exposed regions from the second-layer gate electrodes 304b and 404b have a thin taper shape, and the thickness gradually decreases toward the ends. . For processing the gate electrodes 304 and 404 having such a structure, a dry etching method using a high density plasma capable of independently controlling the plasma density and the bias voltage applied to the substrate is suitable. Specific dry etching methods include microwave and inductively-coupled-plasma (hereinafter referred to as ICP).
(Abbreviated) is known, but in our company, ICP type dry etching equipment is adopted. The reason is that in the case of the ICP dry etching apparatus, it is easy to control the plasma and there is an advantage that it is possible to easily cope with an increase in the area of the processed substrate.

When the gate electrodes 304 and 404 are processed by using the ICP dry etching apparatus, it is necessary to perform a dry etching process including a number of process steps in which taper etching and anisotropic etching are combined. Here, in one processing step, it is assumed that the etching process is performed without changing the etching condition under a constant etching condition. The etching conditions mentioned here indicate the chamber pressure, the ICP power density, the bias power density, and the flow rate ratio of each gas forming the etching gas.

For example, GOLD having only Lov region
In the dry etching process of the gate electrode 304 of the structured TFT (see FIG. 3-A), the dry etching process consisting of three steps is performed, so that the etching gas needs to be switched twice. Switching the etching gas requires a time until the pressure in the etching chamber is stabilized at the time of switching, which causes a problem that the throughput of the dry etching process is reduced. In addition, since etching gas is required to flow until the pressure in the etching chamber is stabilized, there is a problem that the process cost is increased due to an increase in the consumption of etching gas. In addition to these problems, complication of the dry etching process leads to an increase in process defects and troubles, and also involves a problem of reduction in yield of semiconductor devices.

The above problem is not limited to the manufacturing process of the GOLD structure TFT, but is similarly recognized in the manufacturing process of the LDD structure TFT. Because GO
This is because the gate electrodes of both the LD structure TFT and the LDD structure TFT are processed in the same dry etching process.

An object of the present invention is to solve the above problems of the prior art. In other words, it is an object of the present invention to provide a semiconductor device manufactured by applying a dry etching method with a small number of processing steps for processing a gate electrode and a manufacturing method thereof. In this specification, a semiconductor device generally means a semiconductor device including a semiconductor element including a GOLD structure TFT, and a semiconductor display device such as an active matrix liquid crystal display device or an organic EL display device is included in the category. Included in.

[0023]

[Means for Solving the Problems] [Study on Reduction of Number of Processing Steps in Dry Etching Process] (Structure of ICP Dry Etching Device) An ICP dry etching device used in this study will be described below. The ICP dry etching apparatus employs a method of applying high-frequency power to a plurality of spiral coil portions via an impedance matching device to generate plasma as a means for performing plasma processing with high accuracy. Here, the length of each coil part is 1/4 of the high frequency wavelength.
In addition, a high-frequency power is separately applied to the lower electrode holding the object to be processed, and a bias voltage is applied. The details of the ICP plasma etching apparatus are disclosed in Japanese Patent Application Laid-Open No. 9-293600.

FIG. 4 shows a schematic view of the ICP dry etching apparatus. An antenna coil 502 is arranged on a quartz plate 501 placed above the reaction space, and is connected to a first high frequency power supply 504 via a matching box 503. The first high frequency power source 504 is 6 to 60 MH
z, typically 13.56 MHz high frequency power supply.
In addition, the lower electrode 5 that holds the substrate 505 to be processed
A second high frequency power source 508 is connected to 06 via a matching box 507. This second high frequency power source 508 is 100 KHz-60 MHz, for example 6-29 MHz.
Supply high frequency power. When high frequency power is applied to the antenna coil 502, a high frequency current J flows in the antenna coil 502 in the θ direction, a magnetic field B (equation 1) is generated in the Z direction, and induction is performed in the θ direction according to Faraday's law of electromagnetic induction. An electric field E (Formula 2) is generated (see FIG. 4-A).

[0025]

[Equation 1]

[Equation 2]

Electrons are accelerated in the θ direction by the induced electric field E and collide with gas molecules, so that plasma is generated. Since the direction of the induced electric field E is the θ direction, the probability that charged particles collide with the inner wall of the reaction chamber or the substrate 505 and lose energy is small. Further, since the magnetic field B hardly reaches below the antenna coil 502, a high density plasma region spreading in a flat plate shape is generated. Then, the lower electrode 506
The plasma density and the bias voltage applied to the substrate 505 can be controlled independently by adjusting the high-frequency power applied to the substrate. It is also possible to change the frequency of the applied high frequency power according to the material to be etched.

In order to generate high density plasma by the ICP method, it is necessary to flow the high frequency current J flowing through the antenna coil with low loss, and it is required to reduce its inductance. In this respect, the method of dividing the antenna coil is effective. FIG. 4-B is a schematic diagram showing such a configuration, in which a plurality of spiral coil parts 510 are arranged on a quartz plate 509 and are connected to a first high frequency power supply 512 via a matching box 511. ing. At this time, if the length of each coil is set to an integral multiple of 1/4 of the high frequency wavelength, a standing wave occurs in the coil, and the peak value of the generated voltage can be increased (Fig. 4-B). reference).

The ICP dry etching apparatus having the above-mentioned structure is used to perform the dry etching step which is the step of processing the gate electrode of the GOLD structure TFT. However, the number of processing steps of the dry etching step is large. Has become. Therefore, we considered reducing the number of processing steps.

(Structure of Substrate and Etching Gas) First, the structure of the substrate used in this study will be described. The substrate used here has a film thickness of 2 on a square glass substrate (square having a side of 12.5 cm) such as a Corning 1737 substrate.
This is a substrate having a structure in which a silicon oxide film having a thickness of 00 nm, a TaN film having a thickness of 30 nm, and a W film having a thickness of 370 nm are stacked in this order from the side closer to the substrate. Briefly, a W film (370 nm thick)
/ TaN film (30 nm thickness) / Silicon oxide film (200 n
m thickness) / glass substrate is used. In the substrate having the structure, a W film (370 nm thick) / Ta laminated on a silicon oxide film having a film thickness of 200 nm
A metal laminated film having a two-layer structure composed of an N film (30 nm thick) is the substance to be etched. For the examination of the etching rate of each film, a W film (370 nm thickness), a TaN film (30 nm thickness) or a silicon oxide film (200 nm) was formed on a glass substrate.
(nm thickness) is used for the substrate on which a single layer film of 100 nm thick is deposited.

Using a substrate having such a structure, a film thickness of 1.
W film (370 nm
Thickness) / TaN film (thickness of 30 nm), the metal laminated film is dry-etched. Conventionally, the dry-etching process is composed of a number of processing steps of taper etching and anisotropic etching. In the taper etching process step, CF ₄ , Cl ₂ and O _{2 are used.}
Was used, and a mixed gas of SF ₆ , Cl ₂ and O ₂ was used in the anisotropic etching process step. In this study, the etching gas used is SF ₆
The reduction of the number of processing steps was examined by limiting to a mixed gas of Cl, Cl ₂ and O ₂ . In the mixed gas type etching gas, the reason why the F type gas is unified from CF ₄ to SF ₆ is that the W film (370 nm
This is because it can be expected that the etching rate of (thickness) is increased and the selection ratio with respect to the silicon oxide film (thickness of 200 nm) is improved accordingly.

In the following description, SF ₆ is used as the F-based gas for the above-mentioned reason, but the present invention is not limited to this. SF ₆ is the most preferred and other F based gases (eg CF ₄ etc.) can also be used. Also, a Cl-based gas may be used instead of Cl ₂ .

Further, in the present specification, as the metal laminated film, only the laminated structure of the combination of the W film and the TaN film is explained, but the present invention is not limited to this. The combination of W and TaN is the most preferable, and instead of W, a metal compound containing W as a main component or WN
Ta can be used instead of (tungsten nitride) and TaN.

(Experiment 1) A W film and TaN film were formed by using the above ICP dry etching apparatus, substrate and etching gas.
The ICP power dependence of each etching rate of the film and the silicon oxide film was evaluated. Etching conditions other than ICP power are:
The etching gas flow rates of SF ₆ and Cl ₂ are 4 respectively.
At 0 sccm and 20 sccm (in this case, the O ₂ gas flow rate is 0 sccc
m), and a chamber pressure of 1.3 Pa and a bias power of 2
It is 0 W (bias power density: 0.128 W / cm ² ). Under these conditions, ICP power is 500 W (ICP power
Power density: 1.019W / cm ² ) and 700W (ICP
Power density: 1.427W / cm ² ) and 900W (ICP
The power density was 1.834 W / cm ² ) and the experiment was performed. The bias power is the power applied to the substrate 505 by the second high frequency power supply 508, and the bias power density is the bias power that is applied to the substrate 505 (1 side is 12.
It is the value divided by the area of a 5 cm square). Further, the ICP power is the power applied to the plurality of spiral coil parts 510 by the first high-frequency power supply 512, and the ICP power density is the area of the plurality of spiral coil parts 510 (ICP power density). It is a value divided by a circular area having a diameter of 25 cm) (see FIG. 4).

The results of this experiment are shown in FIG. As can be seen from FIG. 5A, as the ICP power increases, the TaN film and the silicon oxide film show almost no increase in etching rate.
It was confirmed that the etching rate was increased in the case of the W film. Based on the result of this etching rate, the TaN of the W film is
FIG. 5B shows the result of evaluation of the selection ratio with respect to the film and the silicon oxide film. As can be seen from FIG. 5B, an increase in the ICP power is observed to improve the selection ratio of the W film to the TaN film and the selection ratio of the W film to the silicon oxide film. From the results of this experiment, it was found that it is preferable to increase the ICP power as much as possible in terms of the etching rate and the selection ratio of the W film, but the maximum value of the ICP power of the dry etching apparatus is 1 kW. When it is used in the vicinity of 1 kW, there is a concern that the load on the dry etching apparatus will be increased. Therefore, the results of this experiment were weighed against the load on the dry etching apparatus, and it was determined that an ICP power of about 700 W was suitable.

(Experiment 2) Next, S which is an etching gas is used.
With the gas flow rate ratio of F ₆ and Cl ₂ fixed at SF ₆ : Cl ₂ = 2: 1 and the total gas flow rate fixed at 60 sccm, the addition amount of oxygen (O ₂ ) gas was changed from 0 to 60%. , W film and TaN
The oxygen addition amount dependency of each etching rate of the film and the silicon oxide film was evaluated. The etching conditions other than the gas flow rate were a chamber pressure of 1.3 Pa and a bias power of 10 W (bias power density: 0.064 W / cm ² ). And I
CP power is 500W (ICP power density: 1.019W /
cm ² ), the amount of oxygen added is 0, 20, 40, 6
The etching rate was evaluated by changing it to 0%. At the same time, the ICP power is 700 W (ICP power density: 1.42
7 W / cm ² ) and the amount of oxygen added was 40%. For reference, details of the dry etching conditions in this experiment are shown in Table 1.

[Table 1]

The results of this experiment are shown in FIG. As can be seen from FIG. 6-A, when the ICP power is 500 W, the oxygen addition amount is 4
It was confirmed that the etching rate of the W film was maximum when the content was 0%. On the other hand, it was recognized that the etching rate of the TaN film tends to decrease as the amount of oxygen added increases. No particular tendency was observed in the etching rate of the silicon oxide film, except that the amount of oxygen added decreased at 0%. Based on the result of this etching rate, the TaN of the W film is
The results of evaluation of the selection ratio for the film and the silicon oxide film are shown in FIG. 6-B. As can be seen from FIG. 6-B, the T of the W film is
It was observed that the selection ratio with respect to the aN film tends to increase as the amount of oxygen added increases. On the contrary, the selection ratio of the W film to the silicon oxide film tended to decrease.
From the result of FIG. 5 above, it is preferable that the ICP power is about 700 W, and from the result of this experiment (FIG. 6), the oxygen addition amount of 40% is considered to be optimal.
In the case of 0%, the etching rate and the selection ratio were evaluated in the same manner, and the results are shown in the right ends of FIGS. 6-A and 6-B.
From the results, etching gas SF ₆ , Cl ₂ and O
The gas flow rates of ₂ are 24 sccm, 12 sccm and 24 sccm (corresponding to the oxygen addition amount of 40%), and the chamber pressure is 1.3P.
a, ICP power of 700 W, bias power of 10 W, and the etching rate of the W film is 227 nm and Ta.
An N film etching rate of 32 nm and a silicon oxide film etching rate of 34 nm were obtained, and a W film to TaN film selectivity of 7.1 and a W film to silicon oxide film of 6.8 could be obtained.

(Experiment 3) The dry etching conditions were set to the conditions shown in Table 2 below, and using a resist pattern having a film thickness of 1.5 μm as a mask, W film (370 nm thickness) / silicon oxide film (200 nm thickness) / glass substrate A substrate with a structure consisting of
A substrate having a structure of W film (370 nm thickness) / TaN film (30 nm thickness) / silicon oxide film (200 nm thickness) / glass substrate was dry-etched.

[Table 2]

FIG. 7-A shows the case where the substrate having the structure of W film (370 nm thickness) / silicon oxide film (200 nm thickness) / glass substrate is dry-etched, and over-etching is performed for about 20 seconds from the etching end point of the W film. It is a SEM photograph at the time of performing. As can be seen from FIG. 7A, it is recognized that the W film is subjected to side etching of about 0.2 to 0.3 μm in the state where the silicon oxide film which is the base film of the W film is exposed. In addition, FIG. 7-B shows a W film (370 n
m thickness) / TaN film (30 nm thickness) / silicon oxide film (2
12 is a SEM photograph when a substrate having a structure of (00 nm thickness) / glass substrate is dry-etched and over-etched for about 30 seconds from the etching end point of the W film. As can be seen from FIG. 7-B, side etching of the W film is not observed when the TaN film, which is the underlying film of the W film, is exposed. From this, it is understood that the side etching of the W film has a causal relationship with the exposure of the silicon oxide film during overetching. If the silicon oxide film is exposed during overetching, it is considered that oxygen is released from the silicon oxide film.
It is considered to be the direct cause of the side etching of the film. Based on this point, W film (370 nm thickness) / TaN film (30 n
(m thickness) / silicon oxide film (200 nm thickness) / glass substrate is dry-etched to form TaN.
As a result of performing over-etching for a predetermined time from the etching end point of the film, as shown in the SEM photograph of FIG.
With the silicon oxide film that is the base film of the N film exposed,
It was possible to obtain an etching shape in which the W film had side etching of about 0.2 to 0.3 μm. Furthermore, TaN
The film thickness of the corresponding TaN film in the exposed region from the W film of the film is
It was also confirmed that the film gradually became thinner toward the edge.

(Construction of Process Step Reduction Process) FIG.
In the SEM photograph of -C, the metal laminated pattern composed of the W film / TaN film in which the W film has side etching is GO.
It is considered that it can be applied as a gate electrode of an LD structure TFT (including an LDD structure TFT). Because, GOLD structure TFT (including LDD structure TFT) developed by our company.
Of the first layer gate electrode (TaN film) has a channel direction dimension of the second layer gate electrode (W film). ) Which is larger than the dimension in the channel direction and corresponds to the exposed region of the first layer gate electrode from the second layer gate electrode.
This is because the film thickness of the layer gate electrode is gradually thinned toward the end portion, and is substantially the same as the shape of the metal laminated pattern of FIG. 7C. Therefore, GO
It is considered possible to form the gate electrode of the LD structure TFT (including the LDD structure TFT) by the dry etching condition of the 1 step process shown in Table 2 by the dry etching condition of the 1 step process. The cross-sectional view of the substrate shown is shown in FIG. Here, the dry etching in the one-step process means that the etching process is performed once without changing the etching condition under a constant etching condition, and the etching condition here means the chamber pressure, the ICP power density, The bias power density and the flow rate ratio of each gas constituting the etching gas are shown. The dry etching conditions for the one-step process shown in Table 2 are preferable values and are not limited to these values.

The substrate cross-sectional view of FIG. 1-A shows the first half of the dry etching process of the one-step process, in which the second layer gate electrode 105 made of the W film and the first layer gate electrode 106 made of the TaN film are resist. It shows how anisotropic etching is performed using the pattern 104 as a mask. At this time, the resist pattern 104 slightly recedes from the initial resist pattern end portion by etching, the gate insulating film 103 which is the underlying silicon oxide film is exposed, and the thinning progresses in the region outside the initial resist pattern end portion. I'm out. The gate insulating film 103 corresponding to the region inside the initial resist pattern end portion is the resist pattern 10
Since the end portion of No. 4 recedes due to etching, the end portion of No. 4 is formed in a taper shape, and becomes thinner as it goes away from the end portion of the first layer gate electrode 106. The substrate cross-sectional view of FIG. 1-B shows the latter half of the dry etching process, in which the film reduction of the silicon oxide film which is the underlying gate insulating film 109 further progresses, and the silicon oxide film from the silicon oxide film is further removed. Side etching of the W film, which is the second-layer gate electrode 107, is progressing due to the effect of released oxygen. At this time, the second
The first layer gate electrode 108 corresponding to the exposed region from the layer gate electrode 107 is etched into a taper shape, and the thickness of the first layer gate electrode 108 is further reduced toward the end. Further, the gate insulating film 109 corresponding to the region inside from the edge portion of the initial resist pattern is generally thinned while maintaining the same tapered shape as in the first half step of the dry etching step.

Although a silicon oxide film is used here as the gate insulating film, this is the most preferable and is not limited to this. As described above, it is considered that the silicon oxide film is exposed at the time of overetching and the oxygen released from the silicon oxide film causes the side etching of the W film. If so, it is considered that the same effect can be obtained.

Further, based on the knowledge of the dry etching conditions of the above one-step treatment, when the oxygen addition amount is increased, side etching of the W film which is the second layer gate electrode is performed without exposing the underlying silicon oxide film. It is expected that it can be promoted. Therefore, add oxygen from 24sccm to 30sc
Dry etching treatment was performed for a predetermined time under the dry etching conditions increased to cm. The cross-sectional view of the substrate in FIG. 2-A shows the cross-section of the substrate after the dry etching process, in which the W film that is the second-layer gate electrode 205a is isotropically etched while the underlying TaN film 206 remains. I was able to. At this time, as the edge of the resist pattern 204a recedes from the initial edge of the resist pattern by etching, the underlying TaN film 206 is etched in a taper shape in the region inside the initial edge of the resist pattern, and As the distance from the end of the two-layer gate electrode (W film) 205a increases, the film thickness decreases, and the remaining film thickness becomes constant in the region outside the initial end of the resist pattern. Next, in FIG. 2-B, since the underlying TaN film 206 is anisotropically etched, the gas flow rate of Cl ₂ as an etching gas is 60 s.
ccm, chamber pressure 1.0Pa, ICP power 350W
(ICP power density: 0.713 W / cm ² ), bias power 20 W (bias power density: 0.128 W / c
It is a substrate cross-sectional view after the dry etching process for a predetermined time by dry etching conditions of m ^2). At this time, T
The first-layer gate electrode 207 formed by anisotropic etching of the aN film 206 is formed into a second-layer gate electrode (W film) 205 by a combination of taper etching and anisotropic etching.
The film is gradually thinned away from the end of b, and is sharply cut off at the end of the first-layer gate electrode 207. Further, the gate insulating film 208 made of the underlying silicon oxide film is etched in a tapered shape in the region inside from the initial end portion of the resist pattern, and becomes thinner as it is separated from the end portion of the first-layer gate electrode 207. The initial residual thickness of the resist pattern is constant in the outer region.

From the above results, the dry etching conditions for the two-step processing are set to the GOLD structure TFT (LDD structure TF).
It is considered that the method can be applied to the dry etching step of the gate electrode (including T). Details of the dry etching conditions for the two-step process are shown in Table 3. Where 2
The dry etching in the step process is the first step process, in which the dry etching process is performed without changing the etching condition under a certain constant etching condition (first etching condition), and the second step process is performed. This shows that dry etching is performed without changing the etching conditions under the constant etching conditions (second etching conditions) different from those in the step. The dry etching conditions for the two-step treatment shown in Table 3 are preferable values, and the present invention is not limited to these values.

[Table 3]

Summarizing the above results, the W film (370 n
m thickness) / TaN film (30 nm thickness) / silicon oxide film (2
(00 nm thickness) / glass substrate is used for the one-step dry etching condition (see Table 2) or 2
By performing the dry etching process under the dry etching conditions of the step process (see Table 3), the GOLD structure TF is obtained.
It is possible to process the gate electrode of T (including the LDD structure TFT). Therefore, by performing the dry etching treatment under the dry etching condition of the one-step process or the dry etching condition of the two-step process, the problems of the conventional technique in the process of processing the gate electrode of the GOLD structure TFT (including the LDD structure TFT) are solved. I think we can solve it.

[Semiconductor Device and Manufacturing Method Thereof] GOLD
Described is the structure of the invention relating to a semiconductor device and a manufacturing method thereof in the case where a dry etching process including a one-step process or a two-step process is applied to a dry etching process of a gate electrode of a structure TFT (including a TFT with an LDD structure). To do.

(Structure of Invention Concerning Semiconductor Device) The structure of the present invention related to a semiconductor device has a plurality of TFTs including a GOLD structure TFT formed on one main surface of a transparent insulating substrate.
The GOLD structure TFT has a semiconductor layer, a gate insulating film, and a gate electrode stacked from the side closer to the transparent insulating substrate, and the gate electrode is a first-layer gate electrode. The second-layer gate electrode has a shorter dimension in the channel direction than the first-layer gate electrode, and the first-layer gate electrode corresponding to the exposed region from the second-layer gate electrode is gradually thinned toward the end. A first conductivity type first impurity region is formed in the semiconductor layer corresponding to an exposed region of the first layer gate electrode from the second layer gate electrode. In a semiconductor device in which a second impurity region having the same conductivity type as the first impurity region is formed in the semiconductor layer corresponding to the outside of the electrode, one step treatment is performed to form the gate electrode. Alternatively, a dry etching process of a two-step process is applied, the second layer gate electrode is formed by isotropic etching of the dry etching process, and the first layer gate corresponding to an exposed region from the second layer gate electrode. The electrode is characterized by being formed by taper etching in the dry etching process.

In the structure of the above invention, the transparent insulating substrate may be any transparent substrate having an insulating property.
For example, a glass substrate or a quartz substrate may be used. The semiconductor layer is an island-shaped semiconductor layer that functions as an active layer of a TFT, and is formed of a polycrystalline silicon film having semiconductor characteristics or a crystalline silicon film formed by using a catalytic element. . The thickness range of the polycrystalline silicon film or the crystalline silicon film is 20 to 200 nm, preferably 30 to
About 70 nm is preferable. Incidentally, in this specification,
A polycrystalline silicon film that is crystallized using a catalytic element is called a crystalline silicon film in order to distinguish it from a normal polycrystalline silicon film. Here, the reason why it is referred to as crystalline instead of being polycrystalline is that, compared with a normal polycrystalline silicon film, the crystal grains are oriented in substantially the same direction and have high field effect mobility. Therefore, it is intended to be distinguished from a normal polycrystalline silicon film.

Further, in the above-mentioned structure of the present invention, the gate insulating film is formed of a silicon oxide film or a silicon oxynitride film, and at a certain distance from the end of the gate electrode, the end of the gate electrode is formed. It becomes a taper shape that becomes thinner as it moves away from the part. The thickness of the gate insulating film when deposited is 30 to 200 nm, preferably 8
About 0 to 130 nm is suitable. 80 to 1 as film thickness
The reason why the thickness of about 30 nm is preferable is to prevent the electrical characteristics of the TFT from being affected by the stress from the upper gate electrode (W film / TaN film stacked gate electrode).
This is because a film thickness of nm or more is required.

In the structure of the above invention, the gate electrode has a film thickness of 5 to 50 nm, preferably 20 to 40 nm.
The first-layer gate electrode made of a TaN film having a thickness of about 200 to 600 nm, preferably 300 to 500 nm,
More preferably, the second layer gate electrode is formed of a W film having a thickness of about 350 to 500 nm. The first layer corresponding to the exposed region from the second-layer gate electrode
The layer gate electrode is formed in a taper shape which is gradually thinned toward the end. The film thickness range of the TaN film is determined by the balance between the controllability of the film thickness in the tapered region during dry etching and the injection characteristics when the impurity element is injected through the TaN film by the through doping method. It Further, the film thickness range of the W film is determined in consideration of the prevention of the channeling phenomenon of the W film when implanting the impurity element and the electric resistance of the W film. The channeling phenomenon is a phenomenon in which a part of implanted ions penetrates into the lower semiconductor layer without colliding with W atoms, and it is known that a film thickness of at least 340 nm or more is necessary to prevent the channeling phenomenon. Has been.

Further, in the structure of the above invention, the first
The impurity region is a low-concentration impurity region (n-region, p-region) having n-type or p-type conductivity, and functions as an electric field relaxation region for relaxing an electric field in the horizontal direction of the channel. The second impurity region is a high-concentration impurity region (n + region, p +) of the same conductivity type as the first impurity region.
Region), which functions as a source region or a drain region. The first impurity region has a concentration gradient, and the impurity concentration gradually increases as the distance from the end of the second layer gate electrode increases. Also, the second
The impurity region has a concentration gradient in a certain region from the end of the first layer gate electrode, and the impurity concentration gradually increases as the distance from the end of the first layer gate electrode increases. .

According to the invention configured as described above, GO
Since the gate electrode of the semiconductor device composed of a plurality of TFTs including the LD structure TFT can be processed by the dry etching process of the one-step process or the two-step process, the problem of the prior art in the dry etching process, that is, It is possible to solve problems such as a decrease in the throughput of the dry etching process, an increase in the process cost due to an increase in the consumption of etching gas, and a decrease in the yield of semiconductor devices due to the complexity of the dry etching process.

(Structure of Invention for Manufacturing Method of Semiconductor Device) The structure of the present invention for manufacturing method of a semiconductor device has a first step of forming a semiconductor layer on one main surface of a transparent insulating substrate, and the semiconductor layer. A second step of depositing a gate insulating film so as to cover the gate insulating film, a third step of depositing a first-layer gate electrode film on the gate insulating film, and a second layer on the first-layer gate electrode film. A fourth step of depositing a gate electrode film, a fifth step of forming a resist pattern for forming a gate electrode, and the first layer gate electrode film and the second layer gate electrode film using the resist pattern as a mask. Dry-etching the laminated film including the first layer gate electrode and the first layer
A sixth step of forming a gate electrode comprising a second layer gate electrode having a dimension shorter in the channel direction than the layer gate electrode;
A seventh step of removing the resist pattern, and a first conductivity type impurity element are implanted into the semiconductor layer corresponding to an exposed region of the first layer gate electrode from the second layer gate electrode. Forming a second impurity region in the semiconductor layer corresponding to the outer side of the first-layer gate electrode at the same time, and forming a second impurity region in the semiconductor layer. An electrode is formed by a dry etching process of a one-step process or a two-step process, and the second-layer gate electrode is formed by isotropic etching of the dry-etching process, which corresponds to an exposed region from the second-layer gate electrode. The first layer gate electrode is formed by taper etching in the dry etching process.

In the structure of the above invention, the transparent insulating substrate may be any transparent substrate having an insulating property.
For example, a glass substrate or a quartz substrate may be used. The semiconductor layer is an island-shaped semiconductor layer that functions as an active layer of a TFT and has a film thickness of 20 to 20 having semiconductor characteristics.
It is formed of a polycrystalline silicon film or a crystalline silicon film (a silicon semiconductor film which is crystallized by using a catalytic element) having a thickness of 0 nm, preferably about 30 to 70 nm. As the gate insulating film, either a silicon oxide film or a silicon oxynitride film may be applied, and a film thickness range of 30 to 200 nm, preferably about 80 to 130 nm is suitable. Further, a TaN film having a film thickness of 5 to 50 nm, preferably about 20 to 40 nm is applied as the first layer gate electrode film, and a film thickness of 200 to 600 nm, preferably 300 to 500 nm, as the second layer gate electrode film.
More preferably, a W film of about 350 to 500 nm is applied.

Further, in the above invention, the first
A metal laminated film composed of a layer gate electrode film and the second layer gate electrode film is processed by a dry etching process of a one-step process or a two-step process using the resist pattern as a mask to form the gate electrode. . At this time, since the second layer gate electrode is formed by isotropic dry etching, the dimension of the second layer gate electrode in the channel direction is shorter than that of the first layer gate electrode. Also, the second
The first layer gate electrode corresponding to the exposed region from the layer gate electrode is formed by taper etching into a tapered shape in which the film is gradually thinned toward the end. Further, for the dry etching step, a dry etching method using high-density plasma capable of independently controlling the plasma density and the bias voltage applied to the substrate to be processed is suitable, and for example, an ICP dry etching apparatus is suitable.

The specific dry etching conditions of the ICP dry etching apparatus are based on the dry etching conditions shown in Tables 2 to 3 above. The dry etching conditions in Tables 2 to 3 are rectangular with sides of 12.5 cm. It corresponds to the substrate. Actual large-sized rectangular substrate, for example 1m on a side
In the case of a large-sized substrate, it is considered that the gas flow rate of the etching gas becomes completely different as the inner volume of the etching chamber increases. Therefore, in order to make the dry etching conditions versatile, it is necessary to specify the gas flow rate instead of the gas flow rate. Further, even in the same type of ICP dry etching apparatus, if the apparatus is different, each parameter of the dry etching conditions may slightly change. Furthermore, it is necessary to define the dry etching conditions in consideration of the process margin of the dry etching process. From these points, it is necessary to introduce a numerical range into each parameter of the dry etching conditions, and Tables 4 to 5 show the dry etching conditions in which the numerical range is introduced into each parameter. Here, Table 4 shows the dry etching conditions corresponding to the one-step processing, and Table 5 shows the dry etching conditions corresponding to the two-step processing. Table 4, Table 5
The etching process may be performed with a predetermined value within the numerical range shown in. In Tables 4 and 5, the parameters are defined by the gas flow rate ratio, the ICP power density, and the bias power density in order to avoid the influence of the substrate size of the substrate to be processed.

[Table 4]

[Table 5]

In the structure of the above invention, as the one conductivity type impurity element, an n-type impurity typified by a P element may be implanted, or a p-type impurity typified by a B element may be implanted. May be injected. By implanting such an impurity element, the first impurity region is formed by a through doping method in the semiconductor layer corresponding to the exposed region of the first layer gate electrode from the second layer gate electrode, and the first layer is formed. The second impurity region is simultaneously formed in the semiconductor layer corresponding to the outside of the gate electrode by a through doping method. At this time, since the impurity regions are simultaneously formed by the through doping method, the first
And the impurity concentration of the second impurity region is
It depends on the acceleration voltage and the dose amount at the time of implanting the impurity element, as well as the type and film thickness of the upper layer film of each impurity region. For example, in the first impurity region, the gate insulating film and the first-layer gate electrode made of a TaN film are present as an upper layer film, and since the upper layer film has a large ion blocking ability, an n-type or p-type is formed. A low-concentration impurity region (n-region, p-region) having a conductivity type is formed. In this case, since the first-layer gate electrode made of the TaN film, which is a part of the upper-layer film, is formed in a tapered shape by taper etching, the second impurity is formed in the first impurity region.
A concentration gradient is formed in which the impurity concentration gradually increases as it approaches the impurity region. On the other hand, in the second impurity region, since only the gate insulating film is present as the upper layer film, and the ion blocking ability of the upper layer film is not so large, it is possible to obtain a high conductivity type having n-type or p-type conductivity. A concentration impurity region (n + region, p + region) is formed. Also in this case, since the tapered region exists in a specific region of the gate insulating film that is the upper layer film, the second impurity region has a constant region from the end of the first layer gate electrode. A concentration gradient is formed in. The first impurity region has a function as an electric field relaxing region for relaxing an electric field in the horizontal direction of the channel, and the second impurity region is formed so as to have a function as a source region or a drain region. ing.

According to the invention configured as described above, GO
Since the gate electrode of the semiconductor device composed of a plurality of TFTs including the LD structure TFT can be processed by the dry etching process of the one-step process or the two-step process, the problem of the prior art in the dry etching process, that is, It is possible to solve problems such as a decrease in the throughput of the dry etching process, an increase in the process cost due to an increase in the consumption of etching gas, and a decrease in the yield of semiconductor devices due to the complexity of the dry etching process.

By the way, the structure of the present invention is similar to the technique disclosed in Japanese Patent Application Laid-Open No. 7-202210 described as a known example, but it should be noted that the structure of the invention is different in the following basic parts. I'll do it. JP-A-7-202210
In the disclosed technique of the publication, an example of wet etching or a combination of anodic oxidation and wet etching is described in the step of forming the second layer gate electrode having a channel dimension shorter than that of the first layer gate electrode. In this case, in the step of forming the second-layer gate electrode, the first-layer gate electrode corresponding to the exposed region from the second-layer gate electrode is hardly reduced in film thickness. It is expected to be formed, and the rectangular first-layer gate electrode is shown in the sectional views showing the manufacturing process. On the other hand, in the structure of the present invention, the first-layer gate electrode corresponding to the exposed region from the second-layer gate electrode is formed by taper etching into a tapered shape in which the film is gradually thinned toward the end. It is characterized by being done. Therefore, when the impurity element is implanted by the through doping method, a concentration gradient is formed in the first impurity region which is the electric field relaxation region. Since the concentration gradient promotes the electric field relaxation effect of the first impurity region and is extremely effective in preventing the hot carrier phenomenon, it is considered that the matters specifying the invention are essentially different between the present invention and the known example.

[0059]

FIG. 8 shows an embodiment of the present invention.
It will be specifically described with reference to FIGS. 8 to 9 and FIG.
1 to 12 are process cross-sectional views showing the manufacturing process of the present embodiment,
FIG. 10 is a conceptual diagram showing the distribution of the impurity concentration in the semiconductor layer.

[Embodiment 1] In this embodiment, an LDD structure TFT and a GO are provided on a glass substrate which is a transparent insulating substrate.
A manufacturing process of a semiconductor display device having an LD structure TFT will be described with reference to FIGS. As a concrete circuit configuration, the pixel TFT is configured with an LDD structure excellent in low off-current characteristics, and the n-channel type or p-channel type driving circuit is configured with a GOLD structure excellent in high hot carrier resistance.

First, a glass substrate 601 which is a rectangular transparent insulating substrate having a side length of 12.5 cm is formed by a plasma CVD method or a low pressure CVD method into an amorphous film having a film thickness of 20 to 200 nm, preferably 30 to 70 nm. Deposit a silicon film. In this embodiment, an amorphous silicon film having a film thickness of 53 nm is deposited. Then, heat treatment is performed to obtain a film thickness of 5
A 0 nm polycrystalline silicon film is formed. At this time, as a heat treatment method for the amorphous silicon film, a furnace furnace is used.
Heat treatment at 00 ℃ -24 hours or laser power 2
Laser crystallization at 00 mJ / cm ² or more, or a combination of heat treatment in a furnace and laser crystallization may be mentioned. Although a polycrystalline silicon film is applied in the present embodiment, a crystalline silicon film that is thermally crystallized by adding a catalytic element that promotes crystallization may be applied. In addition, after forming the polycrystalline silicon film or the crystalline silicon film, a channel doping process for controlling the threshold voltage of the TFT may be performed in some cases. The channel doping step is performed by a method of implanting a low-dose p-type impurity (specifically, B element) into the entire surface of the substrate in order to make the n-channel TFT an enhancement type (see FIG. 8-A).

Next, the island-shaped semiconductor layer 602 having a predetermined pattern shape and a predetermined dimension is patterned by the usual photolithography process and dry etching process. After patterning, the gate insulating film 603a having a film thickness of 30 to 200 n is formed so as to cover the semiconductor layer 602.
m, preferably a silicon oxide film or a silicon oxynitride film having a thickness of 80 to 130 nm is subjected to plasma CVD or low pressure CV.
Deposit by the D method. In this embodiment, the film thickness is 100 nm
The gate insulating film 603a made of the silicon oxide film is deposited by the plasma CVD method. The gate insulating film 603
It is known that the film thickness of a needs to be 80 nm or more in order to avoid stress from the upper gate electrode (W film / TaN film laminated gate electrode). Considering this point (See FIG. 8-A).

Next, a first-layer gate electrode film 604a made of a TaN film having a film thickness of 5 to 50 nm, preferably 20 to 40 nm is deposited by the sputtering method. In this embodiment, the first-layer gate electrode film 604a made of a TaN film having a film thickness of 30 nm is deposited. Then, the film thickness of 200 to 60
A second layer gate electrode film 605a made of a W film having a thickness of 0 nm, preferably 300 to 500 nm, and more preferably 350 to 500 nm is deposited by a sputtering method. In this embodiment, the second layer gate electrode film 605a made of a W film having a film thickness of 370 nm is deposited. Incidentally, the film thickness of the TaN film takes into consideration both the controllability of the remaining film thickness in the taper-shaped region during dry etching and the injection characteristics when the impurity element is injected through the TaN film by the through doping method. Decided. Further, the film thickness of the W film is 34 in order to prevent the channeling phenomenon of the W film when the impurity element is implanted.
It is known that a film thickness of 0 nm or more is required, and it was determined in consideration of this point. After depositing the metal laminated film having a two-layer structure in this manner, a general photolithography process is performed to form a resist pattern 60 for forming a gate electrode.
6a is formed (see FIG. 8-A).

Next, using the resist pattern 606a as a mask, a metal laminated film composed of a first layer gate electrode film 604a made of a TaN film having a film thickness of 30 nm and a second layer gate electrode film 605a made of a W film having a film thickness of 370 nm. Is dry-etched. At this time, a gate electrode composed of the first layer gate electrode 604b and the second layer gate electrode 605b is formed by applying a dry etching process of a one-step process or a two-step process. In the dry etching process, since the second layer gate electrode 605b is formed by isotropic etching, the second layer gate electrode 605b is formed.
Has a shorter dimension in the channel direction than the first-layer gate electrode 604b. Further, the first layer gate electrode 604b corresponding to the exposed region from the second layer gate electrode 605b is formed by the taper etching in the dry etching process, and thus is formed in a taper shape which is gradually thinned toward the end. Has been done. In addition, the gate insulating film 603
b is reduced in film thickness during dry etching, the etching progresses in a taper shape in a certain region from the end of the first layer gate electrode 604b, and the film thickness decreases as the distance from the first layer gate electrode 604b increases, and The remaining film thickness is constant outside of. The resist pattern 6 after development
No. 06a has the shape of the resist pattern 606b due to film loss during dry etching (see FIG. 8-B).

By the way, for the above dry etching process, a dry etching method using high density plasma capable of independently controlling the plasma density and the bias voltage applied to the substrate to be processed is suitable. It is adopted. The specific dry etching conditions of the ICP dry etching apparatus are different between the one-step processing and the two-step processing.
In the case of step processing, dry etching conditions shown in Table 2,
In the case of the two-step process, the dry etching conditions shown in Table 3 are applied. That is, in the case of the one-step dry etching process, the gas flow rates of SF ₆ , Cl _2, and O ₂ , which are etching gases, are 24 sccm, 12 sccm, and 24 sccm, respectively.
(Oxygen addition corresponds to 40%), chamber pressure 1.3
Pa, ICP power 700 W (ICP power density: 1.42
Processing is performed under the etching conditions of 7 W / cm ² ) and bias power of 10 W (bias power density: 0.064 W / cm ² ). On the other hand, in the case of the two-step dry etching process, the gas flow rates of etching gases SF ₆ , Cl ₂ and O ₂ are 24 sccm, 12 sccm and 30 sccm, respectively, the chamber pressure is 1.3 Pa, the ICP power is 700 W (ICP power density : 1.427 W / cm ² ) and a bias power of 10 W (bias power density: 0.064 W / cm ² ), the first step is performed, and then the flow rate of Cl ₂ as an etching gas is increased. At 60 sccm, chamber pressure 1.0 Pa, ICP power 350 W (ICP power density: 0.713 W / cm ² ), bias power 20 W
The second step treatment is performed under the dry etching condition of (bias power density: 0.128 W / cm ² ) (see Tables 2 to 3).

Next, the resist pattern 606b, which is a mask for dry etching, is removed by ashing treatment and cleaning with an organic solvent. Then, an ion doping apparatus is used to implant a low-dose n-type impurity of P element, which is the first doping process, using the first-layer gate electrode 604b as a mask. By the first doping process, a low-concentration impurity region (n−− region) 607 of an n-type impurity is formed in the semiconductor layer 602 corresponding to a region outside the first-layer gate electrode 604b. At this time, in forming the low-concentration impurity region (n−− region) 607, the implantation is performed through the gate insulating film 603b which is the upper layer film by a so-called through doping method. As the doping conditions, phosphine ion source (PH ₃₎ using the dilution 3-20% concentration of phosphine (PH ₃₎ / hydrogen (H _2), accelerating voltage 30
~ 90kV dose 6x10 ¹² ~ 1.5x10 ¹⁴ ions
/ Cm ² is considered, but in the present embodiment, phosphine (P
H ₃₎ dilution ratio of 5% strength phosphine (PH ₃₎ / hydrogen (H
₂ ), an accelerating voltage of 50 kV, and a doping condition of a dose of 3 × 10 ¹³ ions / cm ² (see FIG. 8C).

Next, resist patterns 608 and 609, which are masks for doping impurities, are formed by ordinary photolithography. The resist patterns 608 and 609 are the pixel TFT 7 of the LDD structure.
01 and the formation region of the p-channel drive circuit 703 having the GOLD structure, and is not formed in the production region of the n-channel drive circuit 702 having the GOLD structure. At this time, LDD
In the manufacturing region of the pixel TFT 701 having the structure, the end portion of the resist pattern 608 is the first inside the semiconductor layer 602.
Lo so as to be located outside by a predetermined distance from the layer gate electrode 604b, that is, Lo from the end of the first layer gate electrode 604b.
It is formed so as to be located outside by the ff region (details will be described in a later step). In addition, in the manufacturing region of the p-channel drive circuit 703 having the GOLD structure, the resist pattern 609 is formed so that the end portion thereof is located outside the semiconductor layer 602, that is, so as to completely cover the semiconductor layer 602. (See FIG. 8-D).

Next, using an ion doping apparatus, the second
N of high dose amount consisting of P element which is the doping process of
Type impurities. At this time, the pixel TFT of the LDD structure
In the manufacturing region of 701, the second doping process is performed.
By reason, the half corresponding to the outside of the resist pattern 608 is
The conductor layer 602 has a high-concentration impurity region (n + region) of n-type impurities.
Area 610 is formed. The semiconductor layer 602 has already been formed.
A low concentration impurity region (n--region) 607 of an n-type impurity
Is formed, but a high concentration impurity region (n + region) 6
With the formation of 10, the low-concentration impurity region (n−− region)
Region 607 is a high concentration impurity region (n + region) 610.
Resulting low-concentration impurity region (n--region)
611. Formed in this way
The high-concentration impurity region (n + region) 610 is an LDD structure
Has a function as a source region or a drain region of
The concentration impurity region (n--region) 611 is L of the LDD structure.
off region (electric field that does not overlap with the gate electrode)
Functioning as an electric field relaxation region).
Will be done. On the other hand, a GOLD structure n-channel type drive
In the manufacturing region of the dynamic circuit 702, the first layer gate electrode
The semiconductor layer 602 corresponding to the outside of 604b already has n
A low concentration impurity region (n--region) 607 of the type impurity is formed.
Although it is formed, a high concentration impurity region of n-type impurities is formed on it.
Region (n + region) 612 is formed, and at the same time, the first layer gate
Exposed area of the electrode 604b from the second-layer gate electrode 605b
The semiconductor layer 602 corresponding to the region has a low concentration of n-type impurities.
A pure region (n-region) 613 is formed. In this way
The high concentration impurity region (n + region) 612 formed by
Function as source or drain region of OLD structure
And the low-concentration impurity region (n− region) 613 is a GOL.
D region Lov region (overlap with the gate electrode
Electric field relaxation region)
It will have a function. In addition, as a doping condition
Phosphine (PH₃) Dilution rate 3-20%
Concentration of phosphine (PH₃) / Hydrogen (H₂) And add
High-speed voltage 30-90 kV and dose 6 × 10¹⁴~ 1.5x
10¹⁶ions / cm ²However, in the present embodiment,
Fin (PH₃) Phosphine (PH₃)
/ Hydrogen (H₂), Acceleration voltage 65 kV, dose amount 3 × 10
¹⁵ions / cm ²(Fig. 8-
See D).

The high concentration impurity region (n + region) 61 described above.
0, 612 and the low concentration impurity region (n-region) 613,
It is formed by a so-called through-doping method of injecting through an upper layer film. The through-doping method is a doping method in which impurities are injected into the target material layer through the upper layer film, and is characterized in that the impurity concentration of the target material layer can be changed depending on the film quality and film thickness of the upper layer film. Therefore, although the impurities are implanted under the same doping condition, the high-concentration impurity regions (n + regions) 610 and 612 are formed in the region where the upper layer film is composed of the gate insulating film 603b having a small ion blocking ability. , The upper layer film is a first layer gate electrode (TaN
Film) 604b and a gate insulating film 603b in a region formed of a stacked film, a low concentration impurity region (n− region) 613.
Can be formed at the same time. Further, the first-layer gate electrode (TaN film) 604b, which is the upper layer film of the low-concentration impurity region (n− region) 613, and the gate insulating film 603.
In the laminated film with b, the first layer gate electrode (TaN
Since the film) 604b is formed in a tapered shape by taper etching, the low concentration impurity region (n-region) 6
13, a concentration gradient is formed in which the impurity concentration gradually increases as it approaches the high-concentration impurity region (n + region) 612. Similarly, in the gate insulating film 603b, which is the upper layer film of the high-concentration impurity region (n + region) 612, the taper in which the film thickness is gradually thinned from the end of the first-layer gate electrode 604b in a certain region Since it is formed in a shape, a concentration gradient of impurity concentration is formed (see FIG. 8-D).

The generation state of such a concentration gradient of the impurity concentration will be described in more detail with reference to FIG. Figure 10
Is a partially enlarged view (FIG. 10-A) of a process cross-sectional view (corresponding to D-2 in the drawing) of the GOLD structure n-channel drive circuit 702 shown in FIG. 8-D and the impurity concentration in the semiconductor layer. FIG. 10B is a conceptual diagram showing the distribution of FIG. As can be seen from FIG. 10, the second layer of the first-layer gate electrode (TaN film) 604b is formed.
A region corresponding to the exposed region from the layer gate electrode (W film) 605b is formed in a taper shape with a taper angle θ _{1 which} is thinned toward the end by taper etching. Therefore, when the n-type impurity is implanted by the through-doping method, in the low-concentration impurity region (n-region) 613 of the n-type impurity which is directly below the first-layer gate electrode 604b, A concentration gradient is formed in which the impurity concentration gradually increases toward the end. In the high-concentration impurity region (n + region) 612 of the n-type impurity covered only with the gate insulating film 603b, the film thickness is gradually reduced from the end of the first-layer gate electrode 604b to a certain region. Since it is formed in a taper shape with a taper angle θ ₂ that changes, a concentration gradient of the impurity concentration is formed in the region. In this case, it is known that the reason why the tapered shape is formed in a certain region from the end of the first-layer gate electrode 604b is due to the receding phenomenon of the resist pattern that is the mask for dry etching. . The presence of such a concentration gradient is extremely effective in alleviating the electric field in the horizontal direction of the channel and extremely advantageous in preventing the generation of hot carriers, as compared with the conventional GOLD structure TFT in which there is no concentration gradient.

Next, the resist patterns 608 and 609 which are the masks for the second doping process are removed by ashing process and organic solvent cleaning. After that, a resist pattern 614 which is a mask for doping impurities is formed by a normal photolithography process. At this time, the resist pattern 614 is GOLD.
The p-channel drive circuit 703 having the structure is formed so as to open a manufacturing region (see FIG. 9A).

Next, using an ion doping apparatus, a third
Which is a doping process of P and has a high dose of B element.
A type impurity is injected by the through doping method. By the third doping process, in the formation region of the p-channel drive circuit 703 having the GOLD structure, the first-layer gate electrode 60 is formed.
A high-concentration impurity region (p + region) 615 of p-type impurity is formed in the semiconductor layer 602 corresponding to the outside of 4b. In addition, the second layer gate electrode 60 of the first layer gate electrode 604b
A low-concentration p-type impurity region (p− region) 616 is simultaneously formed in the semiconductor layer 602 corresponding to the exposed region from 5b. The high-concentration impurity region (p + region) 615 thus formed has a function as a source region or a drain region of the GOLD structure, and is a low-concentration impurity region (p + region).
−region 616 has a function as an electric field relaxation region which is a Lov region (which means an electric field relaxation region overlapping the gate electrode) of the GOLD structure (FIG. 9).
-See A).

By the way, in the high-concentration impurity region (p + region) 615 of the p-type impurity, the low-concentration impurity region (n−− region) 607 of the n-type impurity is previously formed. Since a p-type impurity having a concentration higher than the concentration is implanted, a high-concentration impurity region (p + region) 615 having a p-type conductivity type is formed as a whole. Incidentally, a high concentration impurity region (p + region) 615 of p-type impurities and a low concentration impurity region (p
Similar to the case of the n-type impurity region, the −region 616 is simultaneously formed by the through doping method by utilizing the difference in film quality and film thickness of the upper layer film. The doping conditions at this time are as follows: Diborane (B ₂ H ₆ ) dilution ratio of 3 to
20% concentration of diborane (B ₂ H ₆ ) / hydrogen (H ₂ ) is used, and the acceleration voltage is 60 to 100 kV and the dose is 4 × 10 ¹⁵ to
1 × 10 ¹⁷ ions / cm ² is considered, but in the present embodiment, diborane (B ₂ H ₆ ) having a dilution ratio of 5% is used.
₂ H ₆ ) / hydrogen (H ₂ ), acceleration voltage 80 kV, dose 2
The implantation is performed under the doping condition of × 10 ¹⁶ ions / cm ² (see FIG. 9-A).

Finally, the resist pattern 614 which is the mask for the third doping process is removed by ashing process and organic solvent cleaning (see FIG. 9-B).

As described above, the pixel TFT having the LDD structure
It is possible to fabricate a semiconductor display device having 701 and n-channel or p-channel drive circuits 702 and 703 having a GOLD structure. In the gate electrode forming process of the semiconductor display device, a dry etching process of a one-step process or a two-step process by an ICP dry etching device is applied. It is possible to solve problems such as a decrease in process throughput, an increase in process cost due to an increase in etching gas consumption, and a decrease in semiconductor device yield due to a complicated dry etching process.

[Embodiment 2] In this embodiment, a manufacturing process different from that of Embodiment 1 is performed for a semiconductor display device having an LDD structure TFT and a GOLD structure TFT by referring to FIGS.
It is described based on 2. The specific circuit configuration in this case is the same as that of the first embodiment. 11-A, B
Since the manufacturing process of is basically the same as that of the first embodiment (FIGS. 8A and 8B), the manufacturing process will be briefly described.

First, a polycrystalline silicon film having a film thickness of 50 nm is formed on a glass substrate 801 which is a rectangular transparent insulating substrate having a side of 12.5 cm (a crystalline silicon film formed by using a catalytic element may be used). Is formed into an island-shaped semiconductor layer 802, and a film thickness of 100 n is formed so as to cover the semiconductor layer 802.
A gate insulating film 803a made of a silicon oxide film (or a silicon oxynitride film) of m is deposited. After that, the film thickness 5
The first layer gate electrode film 804a made of a TaN film having a thickness of 50 nm, preferably 20 to 40 nm, and the thickness of 200 to 60
A second layer gate electrode film 805a made of a W film having a thickness of 0 nm, preferably 300 to 500 nm, and more preferably 350 to 500 nm is deposited by a sputtering method. In this embodiment, a first layer gate electrode film 804a made of a TaN film having a film thickness of 30 nm and a second layer gate electrode film 805a made of a W film having a film thickness of 370 nm are deposited. After that, by performing a normal photolithography process,
A resist pattern 806a for forming a gate electrode is formed (see FIG. 11-A).

Next, using the resist pattern 806a as a mask, a metal laminated film composed of the first-layer gate electrode film 804a and the second-layer gate electrode film 805a is subjected to a one-step treatment or two-step treatment.
The dry etching process is performed in the step dry etching process. In the dry etching process, the second
Since the layer gate electrode 805b is formed by isotropic etching, the dimension of the second layer gate electrode 805b in the channel direction is shorter than that of the first layer gate electrode 804b. In addition, the first layer gate electrode 804b corresponding to the exposed region from the second layer gate electrode 805b is formed by the taper etching in the dry etching process, and thus is formed in a taper shape that is gradually thinned toward the end. Has been done. In addition, the gate insulating film 803b is tapered in a certain region from the end portion of the first-layer gate electrode 804b due to film loss during dry etching, and the film thickness is reduced as the distance from the first-layer gate electrode 804b is increased. The remaining film thickness is constant outside the constant area. The reason why the tapered shape is formed in the certain region is that the resist pattern recedes during dry etching (from the resist pattern 806a to the resist pattern 8).
It is considered that this is due to the retreat to 06b) (see FIG. 11-B).

By the way, for the above dry etching process, a dry etching method using high density plasma capable of independently controlling the plasma density and the bias voltage applied to the substrate to be processed is suitable. It is adopted. The specific dry etching conditions of the ICP dry etching apparatus are different between the one-step processing and the two-step processing.
In the case of step processing, dry etching conditions shown in Table 2,
In the case of the two-step process, the dry etching conditions shown in Table 3 are applied. That is, in the case of the one-step dry etching process, the gas flow rates of SF ₆ , Cl _2, and O ₂ , which are etching gases, are 24 sccm, 12 sccm, and 24 sccm, respectively.
(Oxygen addition corresponds to 40%), chamber pressure 1.3
Pa, ICP power 700 W (ICP power density: 1.42
Processing is performed under the etching conditions of 7 W / cm ² ) and bias power of 10 W (bias power density: 0.064 W / cm ² ). On the other hand, in the case of the two-step dry etching process, the gas flow rates of etching gases SF ₆ , Cl ₂ and O ₂ are 24 sccm, 12 sccm and 30 sccm, respectively, the chamber pressure is 1.3 Pa, the ICP power is 700 W (ICP power density : 1.427 W / cm ² ) and a bias power of 10 W (bias power density: 0.064 W / cm ² ), the first step is performed, and then the flow rate of Cl ₂ as an etching gas is increased. At 60 sccm, chamber pressure 1.0 Pa, ICP power 350 W (ICP power density: 0.713 W / cm ² ), bias power 20 W
The second step treatment is performed under the dry etching condition of (bias power density: 0.128 W / cm ² ) (see Tables 2 to 3).

Next, using an ion doping apparatus, the first
N of high dose amount consisting of P element which is the doping process of
Type impurities. According to the first doping process
Outside the resist pattern 806b, that is, the first layer gate.
Of the semiconductor layer 802 corresponding to the outside of the gate electrode 804b.
High-concentration impurity region (n + region) 807 of
It is formed by the dope method. As the doping conditions at this time
The phosphine (PH₃) Dilution rate 3 to 20
% Concentration of phosphine (PH₃) / Hydrogen (H₂),
Accelerating voltage of 60 to 100 kV and dose of 2 × 10¹⁴~ 5x
10¹⁵ions / cm²However, in the present embodiment,
Fin (PH₃) Phosphine (PH₃)
/ Hydrogen (H₂), Acceleration voltage 80 kV, dose 1 × 10
¹⁵ions / cm ²Is implanted under the doping conditions of
-C).

Next, the resist pattern 806b serving as a mask for the dry etching process and the first doping process is removed by ashing process and organic solvent cleaning.
Then, an ion doping apparatus is used to implant a low-dose n-type impurity of P element, which is the second doping process, using the second-layer gate electrode 805b as a mask. By the second doping process, the first-layer gate electrode 804b
In the semiconductor layer 802 corresponding to the exposed region from the second-layer gate electrode 805b of the n-type impurity.
-Region) 809 is formed by the through doping method. Also,
The semiconductor layer 8 corresponding to the outside of the first-layer gate electrode 804b
In 02, a high-concentration impurity region (n + region) 807 of n-type impurities has already been formed. By implanting a low-dose amount of n-type impurity into the region, the concentration of the n-type impurity is further increased. Increased high concentration impurity region (n + region) 808
Is formed. As the doping conditions, phosphine ion source (PH ₃₎ using the dilution 3-20% concentration of phosphine (PH ₃₎ / hydrogen (H _2), accelerating voltage 60
Dose amount 3 × 10 ^{13 to} 7.5 × 10 ¹⁴ ions at 100 kV
/ Cm ² is considered, but in the present embodiment, phosphine (P
H ₃₎ dilution ratio of 5% strength phosphine (PH ₃₎ / hydrogen (H
₂ ), acceleration voltage 90 kV, dose 1.5 × 10 ¹⁴ ions
It is implanted under the doping condition of / cm ² (see FIG. 11-D).

Through the steps up to here, in the manufacturing region of the n-channel drive circuit 902 having the GOLD structure, a high concentration impurity region (n + region) 808 of n-type impurities having a function as a source region or a drain region is formed. And that the formation of the low-concentration impurity region (n-region) 809 of the n-type impurity having the function of the electric field relaxation region, which is the Lov region (the electric field relaxation region overlapping the gate electrode), is completed. Become.

Next, a resist pattern 810 serving as a mask for the dry etching process is formed by a normal photolithography process. At this time, the resist pattern 810 is formed so as to open the manufacturing region of the pixel TFT 901 having the LDD structure. Then, in the opening region, the first layer gate electrode 804b made of the TaN film is removed by dry etching using the second layer gate electrode 805b made of the W film as a mask. An ICP dry etching apparatus is applied to the dry etching process.
Dry etching conditions that reduce the film loss of the W film are applied. As a specific dry etching condition, it is possible to perform processing under the same condition as the second step of the dry etching condition shown in Table 3. That is, the gas flow rate of Cl ₂ as an etching gas is 60 sccm, the chamber pressure is 1.0 Pa, the ICP power is 350 W (ICP power density:
0.713 W / cm ² ) and a bias power of 20 W (bias power density: 0.128 W / cm ² ) are dry-etched for a predetermined time (see FIG. 12-A, Table 3).

Through the steps up to here, the pixel TF of the LDD structure is formed.
In the formation region of T901, a high-concentration impurity region (n + region) 808 of an n-type impurity that functions as a source region or a drain region and a Loff region (an electric field relaxation region that does not overlap with a gate electrode) are formed. That is, the formation of the low-concentration impurity region (n− region) 809 of the n-type impurity having a function as the electric field relaxation region is completed.

Next, the resist pattern 810 serving as the mask for the dry etching process is removed by ashing process and organic solvent cleaning. After that, a dry etching process is performed for a predetermined time by using a normal RIE type dry etching apparatus, so that the exposed region of the gate insulating film 803b made of a silicon oxide film is entirely etched back (that is, thinned by etching). By the etch-back process, the shape of the gate insulating film 812 is etched back in the region where the pixel TFT 901 having the LDD structure is formed.
In the formation region of the n-channel drive circuit 902 or the p-channel drive circuit 903 having the D structure, the gate insulating film 813 is etched back. The etch-back process is for improving the implantation efficiency when implanting a high dose amount of B element in the subsequent p-type impurity doping process step. As specific dry etching conditions, the gas flow rate of CHF ₃ as an etching gas is 35 sccm,
A dry etching process is performed for a predetermined time under a dry etching condition of a chamber pressure of 7.3 Pa and an RF power of 800 W (RF power density: 1.28 W / cm ² ). In addition, since the etch back process is performed by the time etching method instead of the end point detecting method, it is necessary to monitor and control the etching rate. Since the dry etching apparatus used in the etch back process is a batch process of four substrates to be processed (square substrate having a side of 12.5 cm), the RF power density is the same as the RF power (800 W). It is calculated by dividing by the area (4 × 12.5 × 12.5 cm ² ) of four treated substrates (see FIG. 12-B).

Next, a resist pattern 814 serving as a mask for impurity doping processing is formed by ordinary photolithography processing. At this time, the resist pattern 814 is formed so as to open the formation region of the p-channel drive circuit 903 having the GOLD structure. After that, using an ion doping apparatus, p-type impurities composed of B element are implanted by the through doping method by the third doping process. In the third doping process, the doping process is performed twice. At this time, a low acceleration and high dose doping process and a high acceleration and low dose doping process are performed. The reason why the doping process is performed in two steps is that the ion blocking ability of the upper layer film between the formation region of the high-concentration impurity region and the formation region of the low-concentration impurity region is caused by the etching back treatment of the gate insulating film 803b. This is because the difference is further increased, and it is difficult to simultaneously form the high concentration impurity region (p + region) and the low concentration impurity region (p− region) by one doping process. By such low acceleration and high dose doping processing, in the manufacturing region of the p-channel drive circuit 903,
The semiconductor layer 8 corresponding to the outside of the first-layer gate electrode 804b
02, a p-type impurity high-concentration impurity region (p + region) 8
15 is formed. In addition, the second acceleration of the first-layer gate electrode 804b is performed by the high-acceleration and low-dose doping process.
A low-concentration impurity region (p − region) 816 of p-type impurity is formed in the semiconductor layer 802 corresponding to the exposed region from the layer gate electrode 805b. The high-concentration impurity region (p + region) 815 has a function as a source region or a drain region of the GOLD structure, and the low-concentration impurity region (p− region) 816 is a Lov region (gate electrode and gate electrode) of the GOLD structure. (Overlapping electric field relaxation region)
Is formed so as to have a function as an electric field relaxation region (see FIG. 12-C).

By the way, a high-concentration impurity region of p-type impurities
(P + region) 815 and low concentration impurity region (p− region) 8
16 is a high-concentration impurity region (n + region) of n-type impurities.
Region 808 and low-concentration impurity region (n-region) 809, respectively.
However, the n-type impurity concentration in each impurity region is
P-type impurities are implanted more than twice as much, so that p-type as a whole
-Concentration impurity region (p + region) 815 having the conductivity type of
And a low-concentration impurity region (p-region) 816 are formed.
There is. In addition, the doping conditions of low acceleration and high dose
Then, diborane (B₂H₆) Dilution rate 3 to 20
% Concentration of diborane (B₂H₆) / Hydrogen (H₂),
Dose amount 4 × 10 at accelerating voltage 20-50 kV¹⁴~ 1 x 1
0¹⁶ions / cm²However, in this embodiment,
(B₂H ₆) Diborane (B₂H₆)/water
Elementary (H₂), Acceleration voltage 30 kV, dose 2 × 10¹⁵ion
s / cm²Is implanted under the doping conditions of. Also high acceleration
And a low dose doping condition is an ion source
Is the same, and the dose amount is 1.8 at an acceleration voltage of 60 to 100 kV.
× 10¹⁴~ 4.5 x 10¹⁵ions / cm²Can be considered
In the embodiment, diborane (B₂H₆) Divora with 5% dilution
(B₂H₆) / Hydrogen (H₂), Acceleration voltage 80kV, do
Amount 9 × 10¹⁴ions / cm²Under the doping conditions of
(See FIG. 12-C).

Finally, the resist pattern 814 which is the mask for the third doping process is removed by ashing process and organic solvent cleaning (see FIG. 12-D).

As described above, the pixel TFT having the LDD structure
It is possible to manufacture a semiconductor display device having 901 and n-channel or p-channel drive circuits 902 and 903 having a GOLD structure. In the gate electrode forming process of the semiconductor display device, a dry etching process of a one-step process or a two-step process by an ICP dry etching device is applied. It is possible to solve problems such as a decrease in process throughput, an increase in process cost due to an increase in etching gas consumption, and a decrease in semiconductor device yield due to a complicated dry etching process.

[0090]

EXAMPLES Example 1 In this example, a method for manufacturing an active matrix type liquid crystal display device using the present invention will be specifically described with reference to FIGS. In this example, basically, the same manufacturing method as that of the first embodiment is adopted, but the semiconductor layer which is the active layer of the TFT is not formed by a usual polycrystalline silicon film but is formed by utilizing a catalytic element. It should be noted that a crystalline silicon film to be converted is applied.

First, the plasma C is formed on the glass substrate 1001.
By the VD method, a first layer silicon oxynitride film 1002a and a second layer silicon oxynitride film 1002b having different composition ratios are deposited with a thickness of 50 nm and 100 nm, respectively, to form a base film 1002. The glass substrate 10 used here
Examples of 01 include quartz glass, barium borosilicate glass, aluminoborosilicate glass, and the like. Then, a film thickness of 20 to 20 is formed on the base film 1002 (1002a and 1002b) by a plasma CVD method or a low pressure CVD method.
An amorphous silicon film 1003a having a thickness of 0 nm, preferably 30 to 70 nm is deposited. In this embodiment, the film thickness is 53n
m amorphous silicon film 1003a is deposited by the plasma CVD method. At this time, an extremely thin natural oxide film (not shown) is formed on the surface of the amorphous silicon film 1003a due to the influence of oxygen in the air mixed in the processing atmosphere.
Although the amorphous silicon film 1003a is deposited by the plasma CVD method in this embodiment, it may be deposited by the low pressure CVD method (see FIG. 13-A).

When depositing the amorphous silicon film 1003a, carbon, oxygen and nitrogen existing in the air may be mixed. It is empirically known that the mixing of these impurity gases causes deterioration of the characteristics of the finally obtained TFT, and it is considered that the mixing of the impurity gas acts as a factor for inhibiting crystallization. Therefore, the mixing of the impurity gas should be thoroughly eliminated. Specifically, in the case of carbon and nitrogen, both are 5E17 atom.
It is preferable to control to s / cm ³ or less, and to 1E18 atoms / cm ³ or less in the case of oxygen (see FIG. 13-A).

Next, the substrate is washed with dilute hydrofluoric acid for a predetermined time to remove the natural oxide film (not shown) formed on the surface of the amorphous silicon film 1003a. Then, the surface of the amorphous silicon film 1003a is light-oxidized by performing ozone water treatment for a predetermined time. A clean ultra-thin silicon oxide film (not shown) is formed on the surface of the amorphous silicon film 1003a by the light oxidation process. Further, the ultrathin silicon oxide film (not shown) may be formed by a treatment with hydrogen peroxide solution. It should be noted that the ultrathin silicon oxide film (not shown) is formed by uniformly depositing the Ni element when a Ni element aqueous solution, which is a solution containing the catalyst element (hereinafter abbreviated as the catalyst element solution), is added by the spin addition method. Therefore, the amorphous silicon film 1003a is formed for the purpose of improving wettability (see FIG. 13-A).

Next, a catalyst element solution consisting of an Ni element aqueous solution having a crystallization promoting effect is added to the entire surface of the amorphous silicon film 1003a (strictly speaking, an extremely thin silicon oxide film) by a spin addition method. . In this example, nickel acetate, which is a Ni compound, was dissolved in pure water to obtain 10 by weight conversion.
A Ni elemental solution adjusted to a concentration of ppm is used as an Ni elemental solution, and a Ni-containing layer (not shown) is uniformly attached to the entire surface of the amorphous silicon film 1003a (strictly, an extremely thin silicon oxide film). (See Figure 13-A).

Next, in order to control the amount of hydrogen contained in the amorphous silicon film 1003a to be 5 atom% or less, dehydrogenation treatment of the hydrogen contained in the amorphous silicon film 1003a is performed. The dehydrogenation treatment is performed by heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere using a furnace. After that, heat treatment is performed in a furnace at 550 ° C. for 4 hours to promote crystallization of the amorphous silicon film 1003a and form a crystalline silicon film 1003b with a thickness of 50 nm. Subsequently, the obtained crystalline silicon film 1003
In order to further improve the crystallinity of b, pulse oscillation type KrF
Crystallization is performed by irradiation with an excimer laser (wavelength 248 nm). In the present specification, the catalytic element Ni is used.
A polycrystalline silicon film that is crystallized by using an element is called a crystalline silicon film in order to distinguish it from a normal polycrystalline silicon film. Here, the reason why it is referred to as crystalline instead of being polycrystalline is that the crystal grains are oriented in substantially the same direction as compared with a normal polycrystalline silicon film and that it has high field effect mobility. Therefore, it is intended to be distinguished from the polycrystalline silicon film (see FIG. 13-A).

Next, pre-channel dope cleaning is performed for a predetermined time by cleaning with dilute hydrofluoric acid and cleaning with ozone water to form an extremely thin silicon oxide film (not shown) on the surface of the crystalline silicon film 1003b. The ultra-thin silicon oxide film (not shown) forms a crystalline silicon film 1003b by hydrogen ions (generated from a mixed gas of diborane (B ₂ H ₆ ) as an ion source) and hydrogen during channel doping treatment. This is to prevent etching. After that, n-channel type T
In order to control the threshold voltages of the FT and p-channel TFTs, an ion doping apparatus is used to perform a first doping process, that is, a channel doping process. The channel doping process is performed by implanting a low-dose p-type impurity (specifically, B element) into the entire surface of the substrate. As the doping conditions at this time, diborane (B ₂ H ₆ ) with a concentration of 0.01 to 1% diborane (B ₂ H ₆ ) / hydrogen (H ₂ ) was used as an ion source, and an acceleration voltage was 5 to 30 kV. And dose amount 8
× 10 ^{13 to} 2 × 10 ¹⁵ ions / cm ² are considered, and in this embodiment, the B concentration in the crystalline silicon film 1003b is 1 × 10.
^{Since it is} about ¹⁷ atoms / cm ³ , diborane (B ₂ H ₆ ) is diluted at a concentration of 0.1% diborane (B ₂ H ₆ ) / hydrogen (H ₂ ), acceleration voltage is 15 kV, and dose is 4 × 10 ¹⁴ ions. Element B is implanted under the doping condition of / cm ² (see FIG. 13-B).

Next, the crystalline silicon film 1003b is formed by the usual photolithography process and dry etching process.
Is patterned to form island-shaped semiconductor layers 1004 to 1008 having a predetermined pattern shape and dimensions. still,
The semiconductor layers 1004 to 1008 will be TFTs in a later step.
For forming a source region or a drain region and a channel region. (See Figure 13-B).

Next, the gate insulating film 1009 having a film thickness of 30 to 30 is formed so as to cover the semiconductor layers 1004 to 1008.
A silicon oxide film or a silicon oxynitride film having a film thickness of 200 nm, preferably 80 to 130 nm is deposited by a plasma CVD method or a low pressure CVD method. In this embodiment, the film thickness is 10
Gate insulating film 1009 made of 0 nm silicon oxide film
Are deposited by the plasma CVD method. The thickness of the gate insulating film 1009 is 80 nm in order to avoid stress from the upper gate electrode (W film / TaN film stacked gate electrode).
It is known that the above film thickness is necessary, and it was determined in consideration of this point (see FIG. 14-A).

Next, in order to deposit the metal laminated film for the gate electrode, the first layer gate electrode film 1010 and the second layer gate electrode film 1011 are successively deposited by the sputtering method. The first layer gate electrode film 1010 has a film thickness of 5 to 50 nm,
A TaN film having a film thickness of 20 to 40 nm is preferably considered, but in this embodiment, a TaN film having a film thickness of 30 nm is deposited. Further, the film thickness of the second-layer gate electrode film 1011 is 2
00-600 nm, preferably 300-500 n film thickness
m, and more preferably, a W film having a film thickness of 350 to 500 nm can be considered, but in this embodiment, a W film having a film thickness of 370 nm is deposited. Incidentally, the film thickness of the TaN film takes into consideration both the controllability of the remaining film thickness in the taper-shaped region during dry etching and the injection characteristics when the impurity element is injected through the TaN film by the through doping method. Decided. Also,
It is known that the film thickness of the W film needs to be 340 nm or more in order to prevent the channeling phenomenon of the W film at the time of implanting an impurity element. -See A).

Next, by carrying out an ordinary photolithography process, resist patterns 1012a to 1017a having predetermined dimensions are formed on the above metal laminated film. The resist patterns 1012a to 1017a are for forming the gate electrode, the storage capacitor electrode, the source wiring, etc. (see FIG. 14-B).

Next, resist patterns 1012a-1010 are formed.
Using 17a as a mask, the metal laminated film including the first layer gate electrode film 1010 made of a TaN film having a film thickness of 30 nm and the second layer gate electrode film 1011 made of a W film having a film thickness of 370 nm is dry-etched. At this time, a dry etching process of a one-step process or a two-step process is applied to the dry etching process. Then, the first layer gate electrodes 1012d to 1015d and the second layer gate electrode 1
012c to 1015c of a predetermined size are formed, and at the same time, the first layer storage capacitor electrode 1016d and the second layer are formed.
A storage capacitor electrode having a predetermined size including a layer storage capacitor electrode 1016c, a first layer source wiring electrode 1017d and a second layer
A source wiring electrode having a predetermined size including the layer source wiring electrode 1017c is formed. In the dry etching step, the second layer electrodes 1012c to 1017c (collective name of electrodes including the second layer gate electrodes 1012c to 1015c, the second layer storage capacitor electrode 1016c, and the second layer source wiring electrode 1017c) are equal to each other. Since the second layer electrodes 1012c to 1017c are formed by the anisotropic etching, the first layer electrodes 1012d to 1017d (the first layer gate electrode 1012d
-1015d, a first layer storage capacitor electrode 1016d, and a first layer source wiring electrode 1017d) (generally referred to as an electrode), and the dimension in the channel direction is shorter. Further, since the first layer electrodes 1012d to 1017d corresponding to the exposed regions from the second layer electrodes 1012c to 1017c are formed by the taper etching in the dry etching process,
The taper shape is gradually thinned toward the end. Further, the gate insulating film 1018 is reduced in film thickness during dry etching, so that the first layer electrodes 1012d to 1012d-1.
Etching progresses in a taper shape in a certain region from the end of 017d, and the film thickness decreases as the distance from the first layer electrodes 1012d to 1017d increases, and the remaining film thickness becomes constant outside the certain region. The resist patterns 1012a to 1017a after development have the shapes of the resist patterns 1012b to 1017b due to film loss during dry etching (see FIG. 15-A).

By the way, for the above-mentioned dry etching process, a dry etching method using high density plasma capable of independently controlling the plasma density and the bias voltage applied to the substrate to be processed is suitable. It is adopted. The specific dry etching conditions of the ICP dry etching apparatus are different between the one-step processing and the two-step processing.
In the case of step processing, dry etching conditions shown in Table 2,
In the case of the two-step process, the dry etching conditions shown in Table 3 are applied. That is, in the case of the one-step dry etching process, the gas flow rates of SF ₆ , Cl _2, and O ₂ , which are etching gases, are 24 sccm, 12 sccm, and 24 sccm, respectively.
(Oxygen addition corresponds to 40%), chamber pressure 1.3
Pa, ICP power 700 W (ICP power density: 1.42
Processing is performed under the etching conditions of 7 W / cm ² ) and bias power of 10 W (bias power density: 0.064 W / cm ² ). On the other hand, in the case of the two-step dry etching process, the gas flow rates of etching gases SF ₆ , Cl ₂ and O ₂ are 24 sccm, 12 sccm and 30 sccm, respectively, the chamber pressure is 1.3 Pa, the ICP power is 700 W (ICP power density : 1.427 W / cm ² ) and a bias power of 10 W (bias power density: 0.064 W / cm ² ), the first step is performed, and then the flow rate of Cl ₂ as an etching gas is increased. At 60 sccm, chamber pressure 1.0 Pa, ICP power 350 W (ICP power density: 0.713 W / cm ² ), bias power 20 W
The second step treatment is performed under the dry etching condition of (bias power density: 0.128 W / cm ² ) (see Tables 2 to 3).

Next, the resist patterns 1012b to 1017b, which are masks for dry etching, are removed by ashing treatment and cleaning with an organic solvent. Then, using an ion doping apparatus, the first layer electrodes 1012d to 101
Using 6d as a mask, a low-dose n-type impurity of P element, which is the second doping process, is implanted. By the second doping process, the first layer electrodes 1012d to 1016 are formed.
The semiconductor layers 1004 to 1008 corresponding to the region outside d.
A low-concentration impurity region (n--region) 101 of n-type impurity
9-1023 are formed. At this time, in forming the low-concentration impurity regions (n−− regions) 1019 to 1023,
Gate insulating film 1 which is an upper layer film by a so-called through doping method
Injection via 018. In addition, as a doping condition, a phosphine (PH ₃ ) dilution ratio of 3 to 20 is applied to the ion source.
% Concentration of phosphine (PH ₃ ) / hydrogen (H ₂ ) is used,
Accelerating voltage of 30 to 90 kV and dose of 6 × 10 ^{12 to} 1.5
Although x10 ¹⁴ ions / cm ² may be considered, in the present embodiment, the phosphine (PH ₃ ) dilution ratio of 5% is used.
H ₃ ) / hydrogen (H ₂ ), acceleration voltage 50 kV, dose 3 × 1
Implantation is performed under the doping condition of 0 ¹³ ions / cm ² (Fig. 1
5-B).

Next, resist patterns 1024 to 1025, which are masks for doping impurities, are formed by a normal photolithography process. The resist patterns 1024 to 1025 are formed on the p-channel TFT 1102 and the L-type TFT 1102 which are the drive circuit 1106 having the GOLD structure.
Is formed in a manufacturing region of the pixel TFT 1104 having a DD structure,
An n-channel type T which is a driving circuit 1106 having a GOLD structure
It is not formed in the manufacturing region of the FTs 1101 and 1103 and the storage capacitor 1105. At this time, in the production region of the p-channel TFT 1102 having the GOLD structure, the end portion of the resist pattern 1024 is formed so as to be located outside the semiconductor layer 1005, that is, so as to completely cover the semiconductor layer 1005. It In addition, the pixel TFT 110 of the LDD structure
In the fabrication region of No. 4, the end portion of the resist pattern 1025 is inside the semiconductor layer 1007 and the first layer gate electrode 10 is formed.
It is formed so that it is located outside by a predetermined distance from 15d, that is, it is located outside from the end of the first layer gate electrode 1015d by the Loff region (details will be described in a later step) (FIG. 16). -See A).

Next, using an ion doping apparatus, the third
N of high dose amount consisting of P element which is the doping process of
Type impurities. At this time, the n-channel TFTs 1101 and 1103, which are the drive circuit 1106 having the GOLD structure, are formed.
In the manufacturing region of the first layer gate electrode 1012d,
Semiconductor layers 1004, 100 corresponding to the outside of 1014d
In FIG. 6, n-type impurity low-concentration impurity regions (n−− regions) 1019 and 1021 have already been formed. From above, n-type impurity high-concentration impurity regions (n + regions) 102.
6, 1028 are formed, and at the same time, the first-layer gate electrode 10 is formed.
12d, 1014d second layer gate electrodes 1012c, 1
Semiconductor layer 1004 corresponding to the exposed region from 014c
In 1006, low-concentration impurity regions (n− regions) 1027 and 1029 of n-type impurities are formed. High concentration impurity regions (n + regions) 1026, 10 thus formed
28 has a function as a source region or a drain region of the GOLD structure, and has a low concentration impurity region (n-region) 102.
7, 1029 have a function as an electric field relaxation region which is a Lov region (which means an electric field relaxation region overlapping the gate electrode) of the GOLD structure. Also,
Also in the region where the storage capacitor 1105 is formed, a high concentration impurity region (n + region) 1032 and a low concentration impurity region (n− region) 1033 of n-type impurities are similarly formed. N-type impurity high-concentration impurity region (n + region) formed here
1032 and the low concentration impurity region (n − region) 1033 are
Since the region is not the TFT but the region for forming the storage capacitor 505, the region has a function as one side of the capacitor formation electrode (see FIG. 16-A).

On the other hand, the pixel TFT 1104 of the LDD structure
In the manufacturing region, the third doping process is performed.
A semiconductor corresponding to the outside of the resist pattern 1025
The layer 1007 has a high-concentration impurity region (n + region) of n-type impurities.
Area 1030 is formed. In the semiconductor layer 1007
Is an n-type impurity low-concentration impurity region (n--region).
1022 is formed, the high concentration impurity region (n +
Region) 1030, the low-concentration impurity region is formed.
(N−− region) 1022 is a high concentration impurity region (n + region).
Region) 1030 and the resulting low concentration impurity region
(N−− area) 1031. This
High-concentration impurity region (n + region) 1 formed as
030 is a source region or a drain region of the LDD structure
And a low-concentration impurity region (n−− region) 10
31 is the Loff region of the LDD structure (over the gate electrode
Electric field relaxation which is the electric field relaxation area which is not overlapped)
It will have a function as an area. In addition, doping
As conditions, phosphine (PH₃) Dilution rate
Phosphine of 3 to 20% concentration (PH₃) / Hydrogen (H₂)
Use, accelerating voltage 30 ~ 90kV, dose 6x10¹⁴
~ 1.5 × 10¹⁶ions / cm²However, this embodiment
In the state, phosphine (PH₃) Phosphie with a concentration of 5%
(PH₃) / Hydrogen (H₂), Acceleration voltage 65 kV, dose
Amount 3 × 10¹⁵ions / cm ²Under the doping conditions of
(See FIG. 16-A).

The high concentration impurity region (n + region) 10 described above.
26, 1028, 1030, 1032 and the low-concentration impurity regions (n − regions) 1027, 1029, 1033 are formed by a so-called through doping method in which they are implanted through the upper layer film. The through-doping method is a doping method in which impurities are injected into the target material layer through the upper layer film, and is characterized in that the impurity concentration of the target material layer can be changed depending on the film quality and film thickness of the upper layer film. Therefore, even if the impurities are implanted under the same doping condition, the high-concentration impurity regions (n + regions) 1026, 1028, 1030, 1
032 is formed, and the upper layer film is a first layer electrode (TaN film) 1012d, 1014d, 1016d having a large ion blocking ability.
And low-concentration impurity regions (n-regions) 1027 and 102
It is possible to form 9,1033 at the same time. In addition, low-concentration impurity regions (n− regions) 1027, 1
029, 1033 first layer electrode (TaN
In the laminated film of the films 1012d, 1014d, 1016d and the gate insulating film 1018, the first layer electrode (TaN
Since the films 1012d, 1014d, and 1016d are formed in a tapered shape by taper etching, the low-concentration impurity regions (n− regions) 1027, 1029, and 103 are formed.
High impurity concentration regions (n + regions) 1026 and 102
A concentration gradient is formed in which the impurity concentration gradually increases toward 8, 1032. Similarly, in the gate insulating film 1018, which is the upper layer film of the high-concentration impurity regions (n + regions) 1026, 1028, 1032, the first layer electrode 1
Since the taper shape in which the film thickness is gradually thinned in a certain region from the end portions of 012d, 1014d, and 1016d is formed, a concentration gradient of the impurity concentration is formed (FIG. 1).
6-A).

In the manufacturing region of the n-channel type TFTs 1101 and 1103 which are the drive circuit 1106 having the GOLD structure, the high concentration impurity region (n + region) 102 is formed.
6, 1028 and low-concentration impurity region (n-region) 102
7, 1029 are formed, the semiconductor layers 1004, 100
A channel region of the TFT is defined in a region overlapping with the second-layer gate electrodes 1012c and 1014c in FIG. Similarly, a pixel TFT 1 having an LDD structure
In the manufacturing region of 104, the channel region of the TFT is defined in a region of the semiconductor layer 1007 that overlaps with the first-layer gate electrode 1015d.

Next, the resist patterns 1024 to 1025, which are masks for the third doping process, are removed by ashing process and organic solvent cleaning. Then, resist patterns 1034-1 which are masks for performing impurity doping processing by normal photolithography processing.
036 is formed. At this time, the resist pattern 10
34 to 1036 are formed so as to open the regions where the p-channel TFT 1102 which is the drive circuit 1106 having the GOLD structure and the storage capacitor 1105 are opened (see FIG. 16-B).

Next, using an ion doping apparatus, the fourth
Which is a doping process of P and has a high dose of B element.
A type impurity is injected by the through doping method. By the fourth doping process, in the manufacturing region of the p-channel TFT 1102 which is the drive circuit 1106 having the GOLD structure, the semiconductor layer 1005 corresponding to the outside of the first-layer gate electrode 1013d has a high p-type impurity concentration. Impurity region (p +
A region) 1037 is formed. Further, a low concentration impurity region (p − region) 1038 of p-type impurities is simultaneously formed in the semiconductor layer 1005 corresponding to the exposed region of the first layer gate electrode 1013d from the second layer gate electrode 1013c.
High concentration impurity region (p + region) formed in this way
1037 has a function as a source region or a drain region of the GOLD structure, and is a low concentration impurity region (p-region) 1
038 has a function as an electric field relaxation region which is a Lov region (which means an electric field relaxation region overlapping the gate electrode) of the GOLD structure. On the other hand, also in the production region of the storage capacitor 1105, similarly, a high concentration impurity region (p + region) 1039 and a low concentration impurity region (p− region) 1040 which function as one side of the capacitance forming electrode are formed.
And are formed (see FIG. 16-B).

By the way, a high-concentration impurity region (p +) of p-type impurities in the manufacturing region of the p-channel TFT 1102 is formed.
In the region 1037, a low concentration impurity region (n--region) 1020 of n-type impurities has already been formed, but since p-type impurities having a concentration higher than that of the n-type impurity are implanted, the p-type impurity region is formed as a whole. High-concentration impurity region having conductivity type (p + region)
1037 will be formed. In addition, the storage capacity 11
Also in the production region of No. 05, the high concentration impurity region (n + region) 1032 of the n-type impurity and the low concentration impurity region (n
-Region) 1033 is formed, but since a p-type impurity having a concentration higher than that of the n-type impurity is implanted, a high-concentration impurity region (p + region) 103 having a p-type conductivity type as a whole is formed.
9 and a low-concentration impurity region (p − region) 1040 are formed. The high-concentration p-type impurity regions (p + regions) 1037 and 1039 and the low-concentration impurity regions (p-regions) 1038 and 1040 are similar to the n-type impurity regions in the upper layer film quality and film thickness. Are formed at the same time by the through doping method by utilizing the difference. As the doping conditions in this, using diborane (B ₂ H ₆₎ dilution 3-20% concentration of diborane (B ₂ H ₆₎ / hydrogen (H ₂₎ to the ion source, the acceleration voltage 60~100kV Therefore, a dose amount of 4 × 10 ¹⁵ to 1 × 10 ¹⁷ ions / cm ² can be considered.
In the present embodiment, diborane (B ₂ H ₆ ), a dilution ratio of 5%, diborane (B ₂ H ₆ ) / hydrogen (H ₂ ), an acceleration voltage of 80 kV,
The implantation is performed under the doping conditions of a dose amount of 2 × 10 ¹⁶ ions / cm ² (see FIG. 16-B).

Next, after removing the resist patterns 1034 to 1036, which are the masks for the fourth doping process, by ashing and cleaning with an organic solvent, a film thickness of 150 nm is obtained.
First interlayer insulating film 1041 made of a silicon oxynitride film
Are deposited by the plasma CVD method. After that, the n-type impurities (P
In order to thermally activate the element) or the p-type impurity (B element), heat treatment is performed in a furnace at 600 ° C. for 12 hours. The heat treatment is performed for thermal activation treatment of n-type or p-type impurities, and the purpose is to getter the catalytic element (Ni element) existing in the channel region located directly under the gate electrode by the impurities. Also doubles. Note that the thermal activation treatment may be performed before the deposition of the first interlayer insulating film 1041, but if the heat resistance of the wiring material such as the gate electrode is weak, it is performed after the deposition of the first interlayer insulating film 1041. Is preferred. After the heat treatment, the semiconductor layers 1004 to
To terminate the dangling bond of 1008, 410
A hydrogenation treatment at -1 hour is performed in a nitrogen atmosphere containing 3% hydrogen (see FIG. 17-A).

Next, a second interlayer insulating film 1042 made of an acrylic resin film having a film thickness of 1.6 μm is formed on the first interlayer insulating film 1041. The acrylic resin film is formed by applying the acrylic resin film by a spin coating method and then performing heat treatment in an oven bake oven. After that, a predetermined photolithography process and a dry etching process are performed so as to penetrate the second interlayer insulating film 1042 and the first interlayer insulating film 1041 and further the gate insulating film 1018 made of a silicon oxide film as a lower layer film. A contact hole 1043 having a size is formed. The contact hole 1043 is formed in a high concentration impurity region (n
+ Regions) 1026, 1028, 1030 and high-concentration impurity regions (p + regions) 1037, 1039 of p-type impurities,
Further, the source wiring electrode 10 that functions as a source wiring
17 cd (composed of the first layer source wiring electrode 1017 d and the second layer source wiring electrode 1017 c) (see FIG. 17-B).

Next, conductive metal wirings 1044 to 1049 are formed so as to be electrically connected to the high concentration impurity regions (n + regions) 1026 and 1028 and the high concentration impurity regions (p + regions) 1037 of the drive circuit 1106. To form. In addition, the connection electrodes 1050, 1052 to 105 of the pixel region 1107
3 and the gate wiring 1051 are formed of the same conductive material.
In this embodiment, the metal wirings 1044 to 1049, the connection electrodes 1050, 1052 to 1053, and the gate wiring 1051.
As a constituent material of, a Ti film with a film thickness of 50 nm and a film thickness of 500 nm
The laminated film of Al-Ti alloy film is applied. And
The connection electrode 1050 is a high-concentration impurity region (n + region) 1
030 and the second layer source wiring electrode 1017c functioning as a source wiring are electrically connected to each other. The connection electrode 1052 is formed so as to be electrically connected to the high-concentration impurity region (n + region) 1030 of the pixel TFT 1104, and the connection electrode 1053 is the storage capacitor 110.
5 is formed so as to be electrically connected to the high concentration impurity region (p + region) 1039 of FIG. In addition, the gate wiring 105
1 is a plurality of second layer gate electrodes 1 of the pixel TFT 1104
015c is formed to be electrically connected (Fig. 1
8-A).

Next, an ITO (Indi
um-Ti-Oxide) film or other transparent conductive film is deposited,
The pixel electrode 1054 is formed by photolithography and wet etching. Pixel electrode 1054
Is electrically connected to a high-concentration impurity region (n + region) 1030 functioning as a source region or a drain region of the pixel TFT 1104 via the connection electrode 1052, and further via the connection electrode 1053, the storage capacitor 1105.
Is also electrically connected to the high-concentration impurity region (p + region) 1039 (see FIG. 18-B).

Through the above steps, the n-channel or p-channel TFTs 1101 to 1103 of the GOLD structure and the L-channel TFTs
An active matrix liquid crystal display device including the pixel TFT 1104 having a DD structure can be manufactured.
In the process of forming the gate electrode, the storage capacitor electrode, and the source wiring electrode of the active matrix type liquid crystal display device, a dry etching process of a one-step process or a two-step process by an ICP dry etching device is applied. Problems of the prior art in the etching process, namely, a decrease in the throughput of the dry etching process, an increase in the process cost due to an increase in the consumption of etching gas, and a decrease in the yield of semiconductor devices due to the complexity of the dry etching process, etc. It is possible to solve the problem.

The method for manufacturing an active matrix type liquid crystal display device including a semiconductor element including a GOLD structure TFT has been specifically described above, but the present invention can be variously modified without departing from the scope of the invention.
It is needless to say that the method is applicable to a method for manufacturing an active matrix type organic EL display device including a semiconductor element including a D structure TFT.

[Embodiment 2] In this embodiment, an electronic device incorporating a semiconductor display device manufactured by applying a dry etching method with a small number of processing steps to the processing of a gate electrode of a semiconductor element including a GOLD structure TFT. A specific example will be described. As the semiconductor display device, there are an active matrix liquid crystal display device, an EL display device, and the like, which are applied to the display section of various electronic devices. Here, specific examples of electronic devices in which the semiconductor display device is applied to the display unit will be described with reference to FIGS.

The electronic equipment in which the semiconductor display device is applied to the display unit includes a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggle type display), a game machine and a car navigation system. Examples include personal computers and personal digital assistants (mobile computers, mobile phones, electronic books, etc.).

FIG. 19-A shows a personal computer including a main body 1201, a video input section 1202, a display device 1203 and a keyboard 1204. The semiconductor display device of the present invention can be applied to the display device 1203 and other circuits.

FIG. 19-B shows a video camera, which is a main body 1.
301, display device 1302, voice input unit 1303, operation switch 1304, battery 1305, and image receiving unit 130.
6 and 6. The semiconductor display device of the present invention can be applied to the display device 1302 and other circuits.

FIG. 19-C shows a mobile computer (mobile computer), which has a main body 1401 and a camera unit 1.
The image forming unit 402 includes an image receiving unit 1403, an operation switch 1404, and a display device 1405. The semiconductor display device of the present invention can be applied to the display device 1405 and other circuits.

FIG. 19-D shows a goggle type display, which includes a main body 1501, a display device 1502 and an arm portion 150.
3 and 3. The semiconductor display device of the present invention can be applied to the display device 1502 and other circuits.

FIG. 19-E shows a player used for a recording medium (hereinafter, abbreviated as a recording medium) in which a program is recorded, which includes a main body 1601, a display device 1602 and a speaker section 1.
603, a recording medium 1604, and operation switches 1605. In this device, a DVD, a CD, etc. are used as a recording medium, and can be used for listening to music, playing games, or the Internet. The semiconductor display device of the present invention can be applied to the display device 1602 and other circuits.

FIG. 19-F shows a mobile phone, which has a display panel 1701, an operation panel 1702, a connection section 1703, a display section 1704, a voice output section 1705, and operation keys 170.
6, a power switch 1707, a voice input unit 1708, and an antenna 1709. The display panel 1701 and the operation panel 1702 are connected by the connecting portion 1703. The surface of the display panel 1701 on which the display unit 1704 is installed and the operation keys 1706 of the operation panel 1702.
The angle θ with respect to the surface on which is installed can be arbitrarily changed at the connecting portion 1703. The display unit 170
4 and other circuits, the semiconductor display device of the present invention can be applied (see FIG. 19).

FIG. 20-A shows a front type projector, which includes a light source optical system and a display device 1801 and a screen 1.
And 802. The semiconductor display device of the present invention can be applied to the display device 1801 and other circuits.

FIG. 20-B shows a rear type projector, which is composed of a main body 1901, a light source optical system and a display device 1902, mirrors 1903 to 1904, and a screen 1905. The semiconductor display device of the present invention can be applied to the display device 1902 and other circuits.

20C shows an example of the structure of the light source optical system and display device 1801 shown in FIG. 20-A and the light source optical system and display device 1902 shown in FIG. 20-B. It is a figure. Light source optical system and display device 1801,
Reference numeral 1902 denotes a light source optical system 2001 and mirrors 2002, 2
004 to 2006, a dichroic mirror 2003, an optical system 2007, a display device 2008, a retardation plate 2009, and a projection optical system 2010. Projection optical system 201
0 is composed of a plurality of optical lenses including a projection lens. This configuration is called a three-plate type because it uses three display devices 2008. Further, in the optical path indicated by the arrow in the figure, an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like may be appropriately disposed.

FIG. 20-D is a diagram showing an example of the structure of the light source optical system 2001 in FIG. 20-C. In this embodiment, the light source optical system 2001 is the reflector 201.
1, a light source 2012, lens arrays 2013 to 2014, a polarization conversion element 2015, and a condenser lens 2016. It is needless to say that the light source optical system 2001 shown in the figure is merely an example and is not limited to the configuration. For example, a film having an optical lens and a polarization function, a film for adjusting a phase difference, an IR film, or the like may be appropriately attached to the light source optical system 2001 (see FIG. 20).

FIG. 21-A shows an example of a single plate type. The light source optical system and the display device shown in the figure are the light source optical system 2101, the display device 2102, and the projection optical system 2103.
And a retardation plate 2104. Projection optical system 210
Reference numeral 3 is composed of a plurality of optical lenses including a projection lens. The light source optical system and display device shown in FIG.
20. A light source optical system and display device 180 in FIGS.
1, 1902 can be applied. Also, the light source optical system 2101
May use the light source optical system shown in FIG.
A color filter (not shown) is attached to the display device 2102 to colorize the display image.

The light source optical system and display device shown in FIG. 21-B is an application example of FIG. 21-A. Instead of attaching a color filter, the RGB rotary color filter disc 2 is used.
The display image is colorized by applying 105. The light source optical system and the display device shown in FIG.
-B light source optical system and display devices 1801 and 190
Applicable to 2.

The light source optical system and the display device shown in FIG. 21-C are called a color filterless single plate type. In this method, the microlens array 2 is added to the display device 2116.
115 attached, dichroic mirror (green) 2112
A display image is colorized by applying a dichroic mirror (red) 2113 and a dichroic mirror (blue) 2114. The projection optical system 2117 is composed of a plurality of optical lenses including a projection lens. The light source optical system and the display device shown in the figure can be applied to the light source optical system and the display devices 1801 and 1902 in FIGS. 20-A and 20-B. Further, as the light source optical system 2111, an optical system using a coupling lens and a collimator lens may be applied in addition to the light source (see FIG. 21).

As described above, the present invention has a very wide range of application and can be applied to various electronic devices incorporating a semiconductor display device such as an active matrix type liquid crystal display device and an EL display device.

[0134]

The effects of the present invention are listed below.

The first effect of the present invention is that it is effective in improving the throughput of the dry etching process.

The second effect of the present invention is that it is effective in reducing the consumption of etching gas.

The third effect of the present invention is that it is effective for improving the yield of semiconductor devices by reducing defects and troubles associated with the simplification of the dry etching process.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a dry etching process of a one-step process.

FIG. 2 is a substrate cross-sectional view showing a dry etching process of a two-step process.

FIG. 3 is an example of a cross-sectional view showing a GOLD structure TFT developed by our company.

FIG. 4 is a schematic view of an ICP dry etching apparatus.

FIG. 5 is a diagram showing ICP power dependence of etching rate and selectivity.

FIG. 6 is a diagram showing the oxygen addition amount dependency of an etching rate and a selection ratio.

FIG. 7 is an SEM photograph after dry etching.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor display device having an LDD structure TFT and a GOLD structure TFT.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor display device having an LDD structure TFT and a GOLD structure TFT.

FIG. 10 is a partially enlarged view of a process cross-sectional view of a GOLD structure TFT and a conceptual diagram showing distribution of impurity concentration in a semiconductor layer.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor display device having an LDD structure TFT and a GOLD structure TFT.

FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor display device having an LDD structure TFT and a GOLD structure TFT.

FIG. 13 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 14 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 15 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 16 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 17 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 18 is a cross-sectional view showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 19 is a schematic view showing an example of an electronic device incorporating a semiconductor display device.

FIG. 20 is a schematic view showing an example of an electronic device incorporating a semiconductor display device.

FIG. 21 is a schematic diagram showing an example of an electronic device incorporating a semiconductor display device.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/49 H01L 21/302 104C 301S F term (reference) 4M104 AA09 BB17 BB18 BB32 DD65 FF06 FF13 GG09 5F004 BA20 CA02 CA03 DA04 DA18 DA26 DB08 DB10 DB12 EB02 5F110 AA14 AA16 AA28 BB02 BB04 CC02 DD02 DD03 DD15 DD17 EE01 EE04 EE14 EE23 EE44 FF02 FF04 FF30 FF32. NN27 NN35 NN36 NN73 NN78 PP01 PP03 PP04 PP10 PP13 PP29 PP34 PP35 QQ04 QQ11 QQ24 QQ28

Claims (7)

[Claims] 1. A first layer gate made of tantalum nitride or tantalum, wherein an island-shaped semiconductor film is formed on an insulating substrate, a gate insulating film made of an oxide film is formed on the semiconductor film, and tantalum nitride or tantalum is formed on the gate insulating film. An electrode film is formed, a second layer gate electrode film made of tungsten, a compound containing tungsten as a main component, or tungsten nitride is formed on the first layer gate electrode film, and a mask is formed on the second layer gate electrode film. And using a constant flow rate etching gas containing a fluorine-based gas, a chlorine-based gas, and oxygen, the chamber pressure, the ICP power density, the bias power density, the fluorine-based gas, the chlorine-based gas, and the oxygen. The gate insulating film is exposed by performing the etching process without changing the flow rate ratio of the second gate electrode film, and the dimension of the second-layer gate electrode film in the channel direction is The method for manufacturing a semiconductor device, characterized in that to be shorter than the channel dimensions of the layer gate electrode film. 2. An island-shaped semiconductor film is formed on an insulating substrate, a gate insulating film made of an oxide film is formed on the semiconductor film, and a first-layer gate electrode film made of tantalum nitride is formed on the gate insulating film. And forming a second tungsten layer on the first-layer gate electrode film.
A layer gate electrode film is formed, a mask is formed on the second layer gate electrode film, and a chamber pressure, an ICP power density, The gate insulating film is exposed by etching without changing the bias power density and the flow ratio of the fluorine-based gas, the chlorine-based gas, and the oxygen, and the channel direction of the second-layer gate electrode film is exposed. Is smaller than the dimension of the first-layer gate electrode film in the channel direction. 3. An island-shaped semiconductor film is formed on an insulating substrate, a gate insulating film made of an oxide film is formed on the semiconductor film, and a first-layer gate electrode film made of tantalum nitride is formed on the gate insulating film. And forming a second tungsten layer on the first-layer gate electrode film.
A layer gate electrode film is formed, a mask is formed on the second layer gate electrode film, and a chamber pressure, an ICP power density, The gate insulating film is exposed by etching without changing the bias power density and the flow ratio of the fluorine-based gas, the chlorine-based gas, and the oxygen, and the channel direction of the second-layer gate electrode film is exposed. Is smaller than the dimension of the first-layer gate electrode film in the channel direction, wherein a dry etching apparatus of ICP method is used in the etching process. The chamber pressure is 1.0 to 1.6 Pa, the ICP power density is 1.02 to 2.04 W / cm ² , and the bias power density is 0. A method for manufacturing a semiconductor device, which has a predetermined value within the range of 03 to 0.19 W / cm ² . 4. The method for manufacturing a semiconductor device according to claim 1, wherein the fluorine-based gas is SF ₆ and the chlorine-based gas is Cl ₂ . 5. The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film is a silicon oxide film. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the first-layer gate electrode film is formed to have a film thickness of 5 to 50 nm. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the second-layer gate electrode film is formed to have a film thickness of 200 to 600 nm.