JP2003234436A - Matrix board and resin molding method - Google Patents
Matrix board and resin molding methodInfo
- Publication number
- JP2003234436A JP2003234436A JP2002033616A JP2002033616A JP2003234436A JP 2003234436 A JP2003234436 A JP 2003234436A JP 2002033616 A JP2002033616 A JP 2002033616A JP 2002033616 A JP2002033616 A JP 2002033616A JP 2003234436 A JP2003234436 A JP 2003234436A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resin
- molding
- matrix
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 title claims abstract description 78
- 229920005989 resin Polymers 0.000 title claims abstract description 78
- 238000000465 moulding Methods 0.000 title claims abstract description 66
- 239000011159 matrix material Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims description 89
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004743 Polypropylene Substances 0.000 description 1
- 229920001328 Polyvinylidene chloride Polymers 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000005033 polyvinylidene chloride Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する利用分野】本発明は、基板の一方の面に
半導体チップがマトリクス状に搭載され、他方の面に端
子接続部が形成されたマトリクス基板及び該マトリクス
基板を用いた樹脂モールド方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix substrate in which semiconductor chips are mounted in a matrix on one surface of the substrate and terminal connecting portions are formed on the other surface, and a resin molding method using the matrix substrate. .
【0002】[0002]
【従来の技術】半導体パッケージの一例として、BOC
(Board・On・Chip)タイプのパッケージを
樹脂モールドする場合、生産性を向上や成形品質を一定
にするため、基板(樹脂基板など)の一方の面に半導体
チップがマトリクス状に搭載され、他方の面に端子接続
部が形成される被成形品をモールド金型に搬入してクラ
ンプし、半導体チップが搭載された一方の面を一括して
樹脂モールドしている。樹脂モールド後、ダイシング装
置により、成形品を半導体チップ毎に個片になるように
ダイシングされて半導体装置が製造されている。2. Description of the Related Art A BOC is an example of a semiconductor package.
When resin-molding a (Board / On / Chip) type package, semiconductor chips are mounted in a matrix on one surface of a substrate (resin substrate or the like) and the other is formed in order to improve productivity and keep molding quality constant. The molded product having the terminal connection portion formed on its surface is carried into a molding die and clamped, and one surface on which the semiconductor chip is mounted is collectively resin-molded. After the resin molding, a semiconductor device is manufactured by dicing a molded product into individual pieces for each semiconductor chip by a dicing device.
【0003】図3はBOCタイプの半導体パッケージを
例示したものである。被成形品である樹脂基板51の一
方の面には半導体チップ52がマトリクス状に搭載され
ている。各半導体チップ52の中央部に設けられたスリ
ット孔53より他方の面に向けてワイヤボンディングさ
れて、半導体チップ52の電極部と端子接続面とがボン
ディングワイヤ54により電気的に接続されている。樹
脂基板51の他方の面には接続パッドが形成されてお
り、樹脂モールド後にはんだボールなどの接続端子55
が接続される。FIG. 3 illustrates a BOC type semiconductor package. Semiconductor chips 52 are mounted in a matrix on one surface of a resin substrate 51 which is a molded product. Wire bonding is performed from the slit hole 53 provided in the central portion of each semiconductor chip 52 to the other surface, and the electrode portion of the semiconductor chip 52 and the terminal connection surface are electrically connected by the bonding wire 54. Connection pads are formed on the other surface of the resin substrate 51, and connection terminals 55 such as solder balls are formed after resin molding.
Are connected.
【0004】樹脂基板51は、図4に示すように、例え
ば下型56にキャビティ凹部57が形成されたモールド
金型に搬入されてクランプされ、モールド樹脂58がキ
ャビティ凹部57に充填されて樹脂モールドされる。樹
脂基板51の一方の面に搭載された複数の半導体チップ
52は一括して樹脂モールドされ、各半導体チップ52
と樹脂基板51とのスリット孔53を通じた配線部へも
モールド樹脂58が充填される。この場合、モールド樹
脂58は図3に示すように下型側のキャビティ凹部57
より上型59側のキャビティ凹部60へ、スリット孔5
3と半導体チップ52との間に形成された隙間53aよ
り充填されるようになっている。樹脂モールド後、成形
品(樹脂基板51)は、半導体チップ52毎にダイシン
グされて個片に切断されて半導体装置が製造される。図
3及び図4において、Cがダイサーカットラインを示
す。As shown in FIG. 4, the resin substrate 51 is carried in and clamped in, for example, a molding die in which a cavity recess 57 is formed in a lower die 56, and a mold resin 58 is filled in the cavity recess 57 to mold the resin. To be done. A plurality of semiconductor chips 52 mounted on one surface of the resin substrate 51 are collectively resin-molded, and each semiconductor chip 52 is
The molding resin 58 is also filled in the wiring portion through the slit hole 53 between the resin substrate 51 and the resin substrate 51. In this case, the molding resin 58 is used as shown in FIG.
To the cavity recess 60 on the upper die 59 side, the slit hole 5
3 and the semiconductor chip 52 are filled through a gap 53a formed between them. After resin molding, the molded product (resin substrate 51) is diced for each semiconductor chip 52 and cut into individual pieces to manufacture a semiconductor device. 3 and 4, C indicates a dicer cut line.
【0005】[0005]
【発明が解決しようとする課題】樹脂基板51の樹脂モ
ールドエリアは、半導体チップ52が搭載された一方の
面(下型56のキャビティ凹部57側)は十分な樹脂路
を確保できるが、他方の面(上型59のキャビティ凹部
60側)は、樹脂路が狭く、厚さも薄く、しかも一方の
面側より他方の面側へ充填されるため、充填時差により
モールド樹脂55が途中で硬化し易く流れ性が低下し易
い。また、スリット孔53にはボンディングワイヤ54
が林立しており、硬化促進したモールド樹脂55の進入
によりワイヤー流れも生じ易い。特に、下型56側のキ
ャビティ凹部57から上型59側のキャビティ凹部60
へモールド樹脂58が流れる樹脂路は隙間53aに絞ら
れているため、マトリクス状に配置された半導体チップ
52によっては、ワイヤー流れが生じたり、モールド樹
脂58の未充填な部分が発生するおそれがあった。In the resin mold area of the resin substrate 51, one surface on which the semiconductor chip 52 is mounted (the cavity recess 57 side of the lower mold 56) can secure a sufficient resin path, but The surface (the cavity concave portion 60 side of the upper mold 59) has a narrow resin path and a small thickness, and moreover, one surface side is filled with the other surface side, so that the molding resin 55 is easily hardened midway due to the filling time difference. Flowability tends to deteriorate. In addition, the bonding wire 54 is provided in the slit hole 53.
However, the wire flow easily occurs due to the penetration of the mold resin 55, which has been accelerated in curing. Particularly, from the cavity recess 57 on the lower mold 56 side to the cavity recess 60 on the upper mold 59 side.
Since the resin path through which the mold resin 58 flows is narrowed to the gap 53a, depending on the semiconductor chips 52 arranged in a matrix, there is a possibility that wire flow may occur or an unfilled portion of the mold resin 58 may occur. It was
【0006】本発明の目的は、上記従来技術の課題を解
決し、基板の一方の面にマトリクス状に搭載され、半導
体チップがスリット孔を通じて他方の面と配線接続され
た基板両面へのモールド樹脂の流れ性を向上させたマト
リクス基板及び該マトリクス基板の成形品質を向上させ
た樹脂モールド方法を提供することにある。The object of the present invention is to solve the above-mentioned problems of the prior art, and to mount a semiconductor chip on one surface of the substrate in a matrix form and to connect the semiconductor chip to the other surface through a slit hole. It is an object of the present invention to provide a matrix substrate in which the flowability of the matrix substrate is improved and a resin molding method in which the molding quality of the matrix substrate is improved.
【0007】[0007]
【課題を解決するための手段】上記課題を解決するた
め、本発明は次の構成を備える。即ち、基板の一方の面
に半導体チップがマトリクス状に搭載され、他方の面に
端子接続部が形成されたマトリクス基板において、半導
体チップが搭載された基板のチップ搭載エリアに交差し
て該半導体チップと基板とが配線接続されるスリット孔
が設けられ、樹脂モールド後に切断除去される基板の不
要部分に貫通孔が設けられていることを特徴とする。ま
た、スリット孔はチップ搭載エリアより外方へ延出して
形成され、半導体チップとの間に隙間が形成されている
ことを特徴とする。また、貫通孔は、上型及び下型に形
成されたキャビティ凹部どうしを連通するように形成さ
れていることを特徴とする。In order to solve the above problems, the present invention has the following constitution. That is, in a matrix substrate in which semiconductor chips are mounted in a matrix on one surface of the substrate and terminal connection portions are formed on the other surface, the semiconductor chips are crossed with the chip mounting area of the substrate on which the semiconductor chips are mounted. Is provided with a slit hole for wiring connection with the substrate, and a through hole is provided in an unnecessary portion of the substrate that is cut and removed after resin molding. Further, the slit hole is formed so as to extend outward from the chip mounting area, and a gap is formed between the slit hole and the semiconductor chip. Further, the through hole is formed so as to communicate the cavity recesses formed in the upper mold and the lower mold.
【0008】また、基板の一方の面に半導体チップがマ
トリクス状に搭載され、他方の面に端子接続部が形成さ
れたマトリクス基板をモールド金型へ搬入してクランプ
し、半導体チップが収容された一方側のキャビティ凹部
から基板のチップ搭載エリアに交差して形成されたスリ
ット孔及び樹脂モールド後に切断除去される基板の不要
部分に形成された貫通孔を通じて他方側のキャビティ凹
部へモールド樹脂を充填し、半導体チップ及びスリット
孔を通じて形成された配線部を一括して樹脂モールドす
ることを特徴とする。また、基板のスリット孔に対向し
て他方の面に形成されたキャビティ凹部は、マトリクス
基板の切断ラインを跨いで各半導体チップ間を連通して
形成されており、前記各半導体チップに対応して形成さ
れたスリット孔及び貫通孔を通じてモールド樹脂を一括
して充填することを特徴とする。Further, semiconductor chips are mounted in a matrix on one surface of the substrate, and the matrix substrate having terminal connection portions formed on the other surface is carried into a mold and clamped to accommodate the semiconductor chips. The mold resin is filled into the cavity concave portion on the other side through the slit hole formed from the cavity concave portion on the one side and the through hole formed in the unnecessary portion of the substrate that is cut and removed after resin molding. The semiconductor chip and the wiring portion formed through the slit hole are collectively resin-molded. Further, the cavity concave portion formed on the other surface facing the slit hole of the substrate is formed so as to communicate between the respective semiconductor chips across the cutting line of the matrix substrate, and corresponds to the respective semiconductor chips. It is characterized in that the molding resin is collectively filled through the formed slit holes and through holes.
【0009】[0009]
【発明の実施の形態】以下、本発明に係るマトリクス基
板及び樹脂モールド方法の好適な実施の形態について添
付図面と共に詳述する。本実施の形態では、BOCタイ
プの半導体パッケージ用のマトリクス基板及び該マトリ
クス基板を用いた樹脂モールド方法について説明する。
図1はBOCタイプの樹脂基板をモールド金型でクラン
プした状態を示す上視図、図2は図1のモールド金型の
断面説明図である。Preferred embodiments of the matrix substrate and the resin molding method according to the present invention will be described below in detail with reference to the accompanying drawings. In this embodiment, a matrix substrate for a BOC type semiconductor package and a resin molding method using the matrix substrate will be described.
1 is a top view showing a state where a BOC type resin substrate is clamped by a molding die, and FIG. 2 is a cross-sectional explanatory view of the molding die of FIG.
【0010】先ず、マトリクス基板1の概略構成につい
て、図1及び図2を参照して説明する。図2において、
1は被成形品であり、BOCタイプのマトリクス基板
(樹脂基板等)が用いられる。マトリクス基板1は、一
方の面に半導体チップ2がマトリクス状に搭載されてお
り、他方の面に端子接続面が形成されるようになってい
る。マトリクス基板1の一方の面には半導体チップ2が
マトリクス状に搭載されている。First, the schematic structure of the matrix substrate 1 will be described with reference to FIGS. In FIG.
1 is a molded product, and a BOC type matrix substrate (resin substrate or the like) is used. The matrix substrate 1 has semiconductor chips 2 mounted in a matrix on one surface thereof, and has a terminal connection surface formed on the other surface thereof. Semiconductor chips 2 are mounted in a matrix on one surface of the matrix substrate 1.
【0011】3はスリット孔であり、各半導体チップ2
が搭載されたチップ搭載エリアに交差して形成されてい
る。このスリット孔3を通じて半導体チップ2とマトリ
クス基板1とがワイヤボンディングにより配線接続され
ている。スリット孔3はチップ搭載エリアより外方へ延
出して形成されている。また、図1において、マトリク
ス基板1の不要部分4(樹脂モールド後に切断除去され
るダイサーカットラインCに囲まれた部分)には、貫通
孔5が設けられている。この貫通孔5は、上型11及び
下型12のキャビティ凹部14、13に連通するように
形成されている(図2参照)。ダイサーカットラインC
は、樹脂モールド後にマトリクス基板1がダイシング装
置により個片化される切断ラインを示す。Denoted at 3 is a slit hole for each semiconductor chip 2.
Is formed so as to intersect with the chip mounting area on which is mounted. The semiconductor chip 2 and the matrix substrate 1 are connected by wire bonding through the slit holes 3. The slit holes 3 are formed so as to extend outward from the chip mounting area. Further, in FIG. 1, a through hole 5 is provided in an unnecessary portion 4 of the matrix substrate 1 (a portion surrounded by a dicer cut line C that is cut and removed after resin molding). The through hole 5 is formed so as to communicate with the cavity recesses 14 and 13 of the upper mold 11 and the lower mold 12 (see FIG. 2). Dicer cut line C
Shows a cutting line by which the matrix substrate 1 is singulated by a dicing device after resin molding.
【0012】図2において、各半導体チップ2は、その
中央部に交差して設けられたスリット孔3より他方の面
に向けてワイヤボンディングされて、半導体チップ2の
電極部と端子接続面とがボンディングワイヤ7により電
気的に接続されている。マトリクス基板1の他方の面に
は接続パッドが形成されており、樹脂モールド後に破線
で示すはんだボールなどの接続端子8が接続される。
尚、半導体チップ2とマトリクス基板1との配線部であ
るボンディングワイヤ7も樹脂モールドされる。このと
き、モールド樹脂9は、半導体チップ2とマトリクス基
板1との間に形成された隙間3a及びマトリクス基板1
の不要部分4に設けられた貫通孔5を通じて充填される
ようになっている。In FIG. 2, each semiconductor chip 2 is wire-bonded to the other surface through a slit hole 3 provided at the center of the semiconductor chip 2 so that the electrode portion of the semiconductor chip 2 and the terminal connection surface are separated from each other. It is electrically connected by a bonding wire 7. Connection pads are formed on the other surface of the matrix substrate 1, and connection terminals 8 such as solder balls shown by broken lines are connected after the resin molding.
The bonding wire 7, which is a wiring portion between the semiconductor chip 2 and the matrix substrate 1, is also resin-molded. At this time, the molding resin 9 is applied to the matrix substrate 1 and the gaps 3 a formed between the semiconductor chip 2 and the matrix substrate 1.
Is filled through the through hole 5 provided in the unnecessary portion 4.
【0013】次にモールド金型の概略構成について図2
を参照して説明する。10はモールド金型であり、上型
11と下型12とを有する。モールド金型10には、被
成形品1及びモールド樹脂(樹脂タブレットなど)が搬
入され、モールド金型10はこれらをクランプし、半導
体チップ2が搭載された一方の面を一括して樹脂モール
ドする。モールド金型10のうち下型12側には半導体
チップ2を収容するキャビティ凹部13が形成され、上
型11側にはスリット孔3に対応する配線部を収容する
キャビティ凹部14が形成されている。Next, a schematic structure of the molding die is shown in FIG.
Will be described with reference to. Reference numeral 10 denotes a molding die, which has an upper die 11 and a lower die 12. The molding target 1 and the molding resin (resin tablet, etc.) are carried into the molding die 10, and the molding die 10 clamps them and collectively molds one surface on which the semiconductor chip 2 is mounted with the resin. . A cavity recess 13 for housing the semiconductor chip 2 is formed on the lower die 12 side of the molding die 10, and a cavity recess 14 for housing the wiring portion corresponding to the slit hole 3 is formed on the upper die 11 side. .
【0014】下型12にはマトリクス基板1を支持する
サポートピン15が設けられている。サポートピン15
は、下型12の底部嵌め込まれた固定ピン15aであ
り、該サポートピン15の先端側はキャビティ凹部13
に突設されている。サポートピン15は、下型12にマ
トリクス基板1が搭載された状態で、基板面に突き当て
て支持するようになっている。サポートピン15が固定
ピン15aである場合には、樹脂モールド後に切断除去
されるマトリクス基板1の不要部分4(ダイサーカット
ラインCに囲まれたエリア)をサポートするように設け
られている。尚、固定ピンタイプのサポートピン15の
先端側外周面には、外径が先端側に向かって小径となる
テーパー面が形成されていてもよい。このテーパー面に
より、樹脂モールド後に成形品の離型をスムーズに行う
ことができる。The lower die 12 is provided with support pins 15 for supporting the matrix substrate 1. Support pin 15
Is a fixed pin 15a fitted in the bottom of the lower mold 12, and the tip side of the support pin 15 is the cavity recess 13
Is projected on. The support pins 15 are adapted to abut against and support the substrate surface with the matrix substrate 1 mounted on the lower die 12. When the support pin 15 is the fixed pin 15a, it is provided so as to support the unnecessary portion 4 (the area surrounded by the dicer cut line C) of the matrix substrate 1 which is cut and removed after the resin molding. A tapered surface may be formed on the outer peripheral surface of the fixed pin type support pin 15 on the front end side so that the outer diameter becomes smaller toward the front end. With this tapered surface, the molded product can be released smoothly after the resin molding.
【0015】また、サポートピン7が可動ピン15bで
ある場合、上記制約にとらわれずに、半導体チップ2に
干渉しない範囲で設けることが可能である。サポートピ
ン15が可動ピン15bである場合には、キャビティ凹
部13にモールド樹脂9の充填が完了するまで基板に当
接した支持位置からキャビティ凹部13と面一となる退
避位置へ移動する必要がある。When the support pin 7 is the movable pin 15b, the support pin 7 can be provided within the range where it does not interfere with the semiconductor chip 2 without being restricted by the above restrictions. When the support pin 15 is the movable pin 15b, it is necessary to move from the support position in contact with the substrate to the retracted position flush with the cavity recess 13 until the cavity recess 13 is completely filled with the mold resin 9. .
【0016】また、下型12には、図示しないポットが
設けられており、該ポットにはプランジャが上下動可能
に設けられている。ポットには、モールド樹脂(樹脂タ
ブレットなど)が装填され、プランジャによりモールド
樹脂をキャビティ凹部13へ圧送りする。モールド樹脂
9は、図1に示すように、下型12側のキャビティ凹部
13よりスリット孔3の隙間3a及び貫通孔5を通じて
上型11側のキャビティ凹部14へ充填されるようにな
っている。モールド樹脂の注入方向は、キャビティ凹部
14の長手方向となるように金型ゲートを設けるのが望
ましい。図1では、下型12側にゲート、上型11側に
エアーベントを設けるのが好ましい。また、図2のよう
に、キャビティ凹部14は1チップに1箇所でなくとも
よく、キャビティ凹部14どうしはつながっていても良
い。Further, the lower mold 12 is provided with a pot (not shown), and a plunger is provided in the pot so as to be vertically movable. A mold resin (resin tablet or the like) is loaded in the pot, and the mold resin is pressure-fed to the cavity recess 13 by the plunger. As shown in FIG. 1, the mold resin 9 is filled from the cavity recess 13 on the lower mold 12 side into the cavity recess 14 on the upper mold 11 side through the gap 3a of the slit hole 3 and the through hole 5. It is desirable to provide the mold gate so that the injection direction of the mold resin is the longitudinal direction of the cavity recess 14. In FIG. 1, it is preferable to provide a gate on the lower mold 12 side and an air vent on the upper mold 11 side. Further, as shown in FIG. 2, the cavity recesses 14 may not be provided at one location on one chip, and the cavity recesses 14 may be connected to each other.
【0017】尚、図2において、上型11のクランプ面
には、端子接続面保護するためリリースフィルム16を
張設してあっても良い。リリースフィルム16は、モー
ルド金型10の加熱温度に耐えられる耐熱性を有するも
ので、金型面より容易に剥離するものであって、柔軟
性、伸展性を有するフィルム材、例えば、PTFE、E
TFE、PET、FEP、フッ素含浸ガラスクロス、ポ
リプロピレン、ポリ塩化ビニリジン等が好適に用いられ
る。リリースフィルム16は、上型11のパーティング
面に形成された図示しない吸着穴よりエアーを吸引する
ことで、吸着保持される。リリースフィルム16は、リ
ール間に巻回された長尺状のものをモールド金型10へ
連続して供給し巻取りするようになっていても或いは予
め短冊状に切断されたもののいずれを用いても良い。In FIG. 2, a release film 16 may be stretched on the clamp surface of the upper mold 11 to protect the terminal connection surface. The release film 16 has heat resistance to withstand the heating temperature of the molding die 10, is easily peeled off from the die surface, and has flexibility and extensibility, such as PTFE and E.
TFE, PET, FEP, fluorine-impregnated glass cloth, polypropylene, polyvinylidene chloride and the like are preferably used. The release film 16 is suction-held by sucking air from a suction hole (not shown) formed on the parting surface of the upper mold 11. The release film 16 may be either a long one wound between reels, which is continuously supplied to the molding die 10 and wound up, or one which is cut into strips in advance. Is also good.
【0018】ここで樹脂モールド方法について説明する
と、一方の面に半導体チップ2が搭載されたマトリクス
基板(樹脂基板など)1及びモールド樹脂(樹脂タブレ
ットなど)をモールド金型10へ搬入してクランプす
る。そして、モールド金型10へ搬入されたマトリクス
基板1の一方の面をキャビティ凹部13に突設されたサ
ポートピン15により支持して基板の平坦度を保ちつ
つ、プランジャを作動してモールド樹脂9が下型12の
ランナゲート17を通じてキャビティ凹部13へ充填さ
れて半導体チップ2が搭載された一方の面が一括して樹
脂モールドされる。また、下型12側のキャビティ凹部
13よりスリット孔3の隙間3a及び貫通孔5を通じて
上型11側のキャビティ凹部14へ充填される。樹脂モ
ールドされた成形品は、モールド金型10より取出され
た後、ダイシング装置でダイサーカットラインCに沿っ
て半導体チップ2ごとに個片に切断される。Explaining the resin molding method here, the matrix substrate (resin substrate or the like) 1 on which the semiconductor chip 2 is mounted on one surface and the molding resin (resin tablet or the like) are carried into the molding die 10 and clamped. . Then, while the flatness of the substrate is maintained by supporting one surface of the matrix substrate 1 carried into the molding die 10 by the support pins 15 provided in the cavity concave portion 13, the plunger is operated and the molding resin 9 is removed. The cavity recess 13 is filled through the runner gate 17 of the lower die 12 and one surface on which the semiconductor chip 2 is mounted is collectively resin-molded. Further, the cavity recess 13 on the lower die 12 side is filled into the cavity recess 14 on the upper die 11 side through the gap 3 a of the slit hole 3 and the through hole 5. The resin-molded molded product is taken out from the molding die 10 and then cut into individual pieces for each semiconductor chip 2 along the dicer cutting line C by a dicing device.
【0019】尚、マトリクス基板1のスリット孔3に対
向して他方の面(上型11側)に形成されたキャビティ
凹部14は、マトリクス基板1のダイサーカットライン
Cを跨いで各半導体チップ2間を連通して形成されてい
ても良い。この場合には、各半導体チップ2に対応して
形成されたスリット孔3の隙間3a及び貫通孔5を通じ
てモールド樹脂9を一括して充填する。The cavity recess 14 formed on the other surface (on the side of the upper mold 11) of the matrix substrate 1 facing the slit hole 3 is located between the semiconductor chips 2 across the dicer cut line C of the matrix substrate 1. May be formed to communicate with each other. In this case, the mold resin 9 is collectively filled through the gap 3a of the slit hole 3 and the through hole 5 formed corresponding to each semiconductor chip 2.
【0020】上記マトリクス基板1を用いれば、半導体
チップ2が搭載された基板のチップ搭載エリアに交差し
て該半導体チップ2と基板とが配線接続されるスリット
孔3が設けられ、樹脂モールド後に切断除去される基板
の不要部分4に貫通孔5が設けられているので、樹脂モ
ールドする際にスリット孔3の隙間3a及び貫通孔5を
樹脂路として利用できるので、モールド樹脂9の基板両
面への流れ性、特に配線部への樹脂の流れ性を向上させ
ることができる。また、マトリクス基板1をモールド金
型10へ搬入してクランプし、半導体チップ2が収容さ
れた基板の一方側のキャビティ凹部13からスリット孔
3の隙間3a及び貫通孔5を通じて基板の他方側のキャ
ビティ凹部14へモールド樹脂9を充填し、半導体チッ
プ2及び配線部を一括して樹脂モールドするので、モー
ルド樹脂の基板両面への流れ性が良く、特にスリット孔
3に形成された狭い配線部分への充填がスムーズに行え
るので成形品質を向上させることができる。If the matrix substrate 1 is used, a slit hole 3 for connecting the semiconductor chip 2 and the substrate by wiring is provided so as to intersect the chip mounting area of the substrate on which the semiconductor chip 2 is mounted, and cut after resin molding. Since the through hole 5 is provided in the unnecessary portion 4 of the substrate to be removed, the gap 3a of the slit hole 3 and the through hole 5 can be used as a resin path during resin molding, so that the mold resin 9 can be applied to both surfaces of the substrate. It is possible to improve the flowability, particularly the flowability of the resin to the wiring portion. In addition, the matrix substrate 1 is carried into the molding die 10 and clamped, and from the cavity concave portion 13 on one side of the substrate in which the semiconductor chip 2 is accommodated to the cavity 3a of the slit hole 3 and the cavity on the other side of the substrate through the through hole 5. Since the recess 14 is filled with the molding resin 9 and the semiconductor chip 2 and the wiring portion are collectively resin-molded, the flowability of the molding resin to both surfaces of the substrate is good, and particularly to the narrow wiring portion formed in the slit hole 3. Since the filling can be done smoothly, the molding quality can be improved.
【0021】以上、本発明の好適な実施例について種々
述べてきたが、本発明は上述の実施例に限定されるので
はなく、モールド金型10にリリースフィルム16を設
けるか否かは任意であり、半導体チップ2を収容するキ
ャビティ凹部は上型11でも下型12の何れに形成され
ていても良い等、発明の精神を逸脱しない範囲で多くの
改変を施し得るのはもちろんである。Although various preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and whether or not the mold die 10 is provided with the release film 16 is arbitrary. However, the cavity recess for housing the semiconductor chip 2 may be formed in either the upper mold 11 or the lower mold 12, and it is needless to say that many modifications can be made without departing from the spirit of the invention.
【0022】[0022]
【発明の効果】本発明に係るマトリクス基板を用いれ
ば、半導体チップが搭載された基板のチップ搭載エリア
に交差して該半導体チップと基板とが配線接続されるス
リット孔が設けられ、樹脂モールド後に切断除去される
基板の不要部分に貫通孔が設けられているので、樹脂モ
ールドする際にスリット孔の隙間及び貫通孔を樹脂路と
して利用できるので、モールド樹脂の基板両面への流れ
性、特に配線部へのモールド樹脂の流れ性を向上させる
ことができる。また、本発明に係る樹脂モールド方法に
よれば、マトリクス基板をモールド金型へ搬入してクラ
ンプし、半導体チップが収容された基板の一方側のキャ
ビティ凹部からスリット孔の隙間及び貫通孔を通じて基
板の他方側のキャビティ凹部へモールド樹脂を充填し、
半導体チップ及び配線部を一括して樹脂モールドするの
で、モールド樹脂の基板両面への流れ性が良く、特にス
リット孔に形成された狭い配線部分への充填がスムーズ
に行えるので成形品質を向上させることができる。When the matrix substrate according to the present invention is used, a slit hole for wiring the semiconductor chip and the substrate is provided so as to intersect the chip mounting area of the substrate on which the semiconductor chip is mounted. Since the through hole is provided in the unnecessary portion of the substrate to be cut and removed, the gap of the slit hole and the through hole can be used as the resin path during resin molding. The flowability of the mold resin to the part can be improved. Further, according to the resin molding method of the present invention, the matrix substrate is carried into a molding die and clamped, and the cavity of one side of the substrate in which the semiconductor chip is accommodated is recessed from the cavity concave portion and the through hole of the substrate. Fill the cavity recess on the other side with mold resin,
Since the semiconductor chip and the wiring part are collectively resin-molded, the flowability of the molding resin to both sides of the substrate is good, and especially the narrow wiring part formed in the slit hole can be smoothly filled, improving the molding quality. You can
【図1】BOCタイプのマトリクス基板をモールド金型
でクランプした状態を示す上視図である。FIG. 1 is a top view showing a state where a BOC type matrix substrate is clamped by a molding die.
【図2】図1のモールド金型の断面説明図である。FIG. 2 is a cross-sectional explanatory view of the molding die of FIG.
【図3】従来のBOCタイプのマトリクス基板をモール
ド金型でクランプした状態を示す上視図である。FIG. 3 is a top view showing a state where a conventional BOC type matrix substrate is clamped by a molding die.
【図4】図3のモールド金型の断面説明図である。4 is a cross-sectional explanatory view of the molding die of FIG.
1 マトリクス基板 2 半導体チップ 3 スリット孔 3a 隙間 4 不要部分 5 貫通孔 7 ボンディングワイヤ 8 接続端子 9 モールド樹脂 10 モールド金型 11 上型 12 下型 13、14 キャビティ凹部 15 サポートピン 15a 固定ピン 15b 可動ピン 16 リリースフィルム 17 ランナゲート 1 Matrix substrate 2 semiconductor chips 3 slit holes 3a gap 4 unnecessary parts 5 through holes 7 Bonding wire 8 connection terminals 9 Mold resin 10 Mold dies 11 Upper mold 12 Lower mold 13, 14 Cavity recess 15 Support pin 15a Fixed pin 15b movable pin 16 release film 17 Lanna Gate
Claims (5)
マトリクス状に搭載され、他方の面に端子接続部が形成
されたマトリクス基板において、 前記半導体チップが搭載された基板のチップ搭載エリア
に交差して該半導体チップと基板とが配線接続されるス
リット孔が設けられ、樹脂モールド後に切断除去される
基板の不要部分に貫通孔が設けられていることを特徴と
するマトリクス基板。1. A matrix substrate in which a plurality of semiconductor chips are mounted in a matrix on one surface of a substrate and terminal connection portions are formed on the other surface, in a chip mounting area of the substrate on which the semiconductor chips are mounted. A matrix substrate, wherein slit holes are provided so as to intersect with each other to connect the semiconductor chip and the substrate by wiring, and through holes are provided in unnecessary portions of the substrate that are cut and removed after resin molding.
外方へ延出して形成され、半導体チップとの間に隙間が
形成されていることを特徴とする請求項1記載のマトリ
クス基板。2. The matrix substrate according to claim 1, wherein the slit hole is formed to extend outward from a chip mounting area, and a gap is formed between the slit hole and the semiconductor chip.
たキャビティ凹部どうしを連通するように形成されてい
ることを特徴とする請求項1記載のマトリクス基板。3. The matrix substrate according to claim 1, wherein the through hole is formed so as to communicate the cavity recesses formed in the upper mold and the lower mold.
マトリクス状に搭載され、他方の面に端子接続部が形成
されたマトリクス基板をモールド金型へ搬入してクラン
プし、半導体チップが収容された一方側のキャビティ凹
部から基板のチップ搭載エリアに交差して形成されたス
リット孔及び樹脂モールド後に切断除去される基板の不
要部分に形成された貫通孔を通じて他方側のキャビティ
凹部へモールド樹脂を充填し、半導体チップ及びスリッ
ト孔を通じて形成された配線部を一括して樹脂モールド
することを特徴とする樹脂モールド方法。4. A matrix substrate having a plurality of semiconductor chips mounted in a matrix on one surface of a substrate and having terminal connection portions formed on the other surface thereof is carried into a molding die and clamped to accommodate the semiconductor chips. Mold resin is injected into the cavity recess on the other side through slit holes formed from the cavity recess on the one side that intersects the chip mounting area of the substrate and through holes formed in unnecessary parts of the substrate that are cut and removed after resin molding. A resin molding method, comprising: filling and resin-molding a wiring portion formed through a semiconductor chip and a slit hole in a lump.
面に形成されたキャビティ凹部は、マトリクス基板の切
断ラインを跨いで各半導体チップ間を連通して形成され
ており、前記各半導体チップに対応して形成されたスリ
ット孔及び貫通孔を通じてモールド樹脂を一括して充填
することを特徴とする請求項4記載の樹脂モールド方
法。5. A cavity recess formed on the other surface of the substrate facing the slit hole of the substrate is formed so as to communicate between the semiconductor chips across the cutting line of the matrix substrate. The resin molding method according to claim 4, wherein the molding resin is collectively filled through the slit hole and the through hole formed corresponding to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002033616A JP3820374B2 (en) | 2002-02-12 | 2002-02-12 | Matrix substrate and resin molding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002033616A JP3820374B2 (en) | 2002-02-12 | 2002-02-12 | Matrix substrate and resin molding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003234436A true JP2003234436A (en) | 2003-08-22 |
| JP3820374B2 JP3820374B2 (en) | 2006-09-13 |
Family
ID=27776355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002033616A Expired - Fee Related JP3820374B2 (en) | 2002-02-12 | 2002-02-12 | Matrix substrate and resin molding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3820374B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443041B2 (en) | 2001-01-15 | 2008-10-28 | United Test & Assembly Center Limited | Packaging of a microchip device |
| US7504715B2 (en) | 2002-06-19 | 2009-03-17 | United Test & Assembly Center Limited | Packaging of a microchip device |
| US7812265B2 (en) | 2007-05-23 | 2010-10-12 | Samsung Electronics Co., Ltd. | Semiconductor package, printed circuit board, and electronic device |
| JP2012084908A (en) * | 2011-12-15 | 2012-04-26 | United Test And Assembly Center (S) Pte Ltd | Packaging method for microchip device |
-
2002
- 2002-02-12 JP JP2002033616A patent/JP3820374B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443041B2 (en) | 2001-01-15 | 2008-10-28 | United Test & Assembly Center Limited | Packaging of a microchip device |
| US7504715B2 (en) | 2002-06-19 | 2009-03-17 | United Test & Assembly Center Limited | Packaging of a microchip device |
| US7812265B2 (en) | 2007-05-23 | 2010-10-12 | Samsung Electronics Co., Ltd. | Semiconductor package, printed circuit board, and electronic device |
| JP2012084908A (en) * | 2011-12-15 | 2012-04-26 | United Test And Assembly Center (S) Pte Ltd | Packaging method for microchip device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3820374B2 (en) | 2006-09-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8497158B2 (en) | Leadframe strip and mold apparatus for an electronic component and method of encapsulating an electronic component | |
| US7247521B2 (en) | Semiconductor assembly encapsulation mold and method for forming same | |
| US7220615B2 (en) | Alternative method used to package multimedia card by transfer molding | |
| JP3194917B2 (en) | Resin sealing method | |
| JP5479247B2 (en) | Manufacturing method of semiconductor device | |
| JP3510554B2 (en) | Resin molding method, mold for molding and wiring substrate | |
| JPH07321139A (en) | Semiconductor device and manufacture thereof | |
| JP2008004570A (en) | Resin-sealed semiconductor device manufacturing method, resin-sealed semiconductor device manufacturing apparatus, and resin-sealed semiconductor device | |
| US7704801B2 (en) | Resin for sealing semiconductor device, resin-sealed semiconductor device and the method of manufacturing the semiconductor device | |
| JP2004134591A (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP2003234436A (en) | Matrix board and resin molding method | |
| JP3139981B2 (en) | Resin sealing method and resin sealing device for chip size package | |
| JP2005085832A (en) | Resin molding apparatus | |
| JP2017087453A (en) | Resin molding die and resin molding method | |
| US20220059369A1 (en) | Method of manufacturing semiconductor devices, and corresponding tool | |
| JP4162720B2 (en) | System and method for encapsulating a semiconductor device | |
| JP4058182B2 (en) | Resin sealing method | |
| JP2000176967A (en) | Resin sealing device | |
| JP2003234365A (en) | Metal mold die and resin-molding method | |
| JP2001217270A (en) | Method and apparatus manufacturing electronic component | |
| JP2002118130A (en) | Resin sealing method for matrix package | |
| JP4035240B2 (en) | Resin sealing method and resin sealing device for chip size package | |
| JP2006103207A (en) | Resin mold device | |
| JP2005081695A (en) | Resin molding mold | |
| JPH05235073A (en) | Method of sealing semiconductor device with resin |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041220 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051213 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051220 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060131 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060613 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060619 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090623 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120623 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120623 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130623 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130623 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130623 Year of fee payment: 7 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |