JP2003345284A - Interface circuit and electronic device provided with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely transfer a start signal STH among cascaded data-side drivers even when an electronic device performs a high-speed operation. <P>SOLUTION: When data-side drivers 40 are cascaded, since a receiver 44 for inputting the start signal of the data-side driver 40 of the first stage is constituted as a CMADS (current mode advanced differential signaling) interface circuit with a transmitter for outputting the start signal of a controller and circuits for bypassing receivers 44 of data-side drivers 40 of the next stage and succeeding stages are constituted as CMOS (complementary metal-oxide semiconductor) interface circuits with buffers 43 of data-side drivers of respective preceding stages by changeover switches 45 which are included in receivers 44 of data-side drivers 40, the delay of the start signal in the cascade connection can be made smaller than that in the CMADS interface circuit and it is possible to read the start signal STH normally at the rising edge of a clock signal CLK in data-side drivers 40 of the side of the succeeding stages. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit and an electronic device including the interface circuit, and more particularly to an interface circuit for cascade connection for sequentially transferring start signals between a plurality of semiconductor integrated circuit devices and the interface circuit thereof. The present invention relates to an electronic device provided.

[0002]

2. Description of the Related Art As a dot matrix type display device,
Liquid crystal display devices are thin, lightweight, and have low power consumption,
The active matrix type color liquid crystal display device, which is used for various devices such as a personal computer and is particularly advantageous for controlling the image quality with high precision, occupies the mainstream.

A liquid crystal display module of a liquid crystal display device of this type has a liquid crystal panel (LCD panel) as shown in FIG.
1, a control circuit (hereinafter, referred to as a controller) 2 including a semiconductor integrated circuit device (hereinafter, referred to as an IC) 2, a plurality of scanning side driving circuits (hereinafter, referred to as scanning side drivers) 3 including an IC, and a data side driving circuit (Hereinafter, referred to as a data side driver) 4. The liquid crystal panel 1 is
Although not shown in detail, a semiconductor substrate on which transparent pixel electrodes and thin film transistors (TFTs) are arranged, and 1
It consists of a counter substrate with two transparent electrodes and a structure in which a liquid crystal is sealed between these two substrates so that a predetermined voltage is applied to each pixel electrode by controlling the TFT having a switching function. , An image is displayed by changing the transmittance of the liquid crystal depending on the potential difference between each pixel electrode and the counter substrate electrode. On the semiconductor substrate, a data line for transmitting a gradation voltage applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) of the TFT are wired.

The controller 2 has an input side connected to a PC (personal computer) 5 and an output side connected to a scanning side driver 3 and a data side driver 4. Scan side driver 3
The output side of the data side driver 4 is connected to the scanning line and the data line of the liquid crystal panel 1, respectively. The chip size of the scanning side driver 3 and the data side driver 4 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 1 is large. In this case, it is necessary to arrange a plurality of them on the outer periphery of the liquid crystal panel 1. For example, in the case of an XGA (1024 × 768 pixel) color display liquid crystal panel, when mounting each driver 3 and 4 in a module, the scanning side driver 3 needs to drive 768 gate lines, and for example, 192 In case of having the driving ability of, the number of four is required, and one side is arranged in a cascade connection on the left outer periphery of the liquid crystal panel 1. The data-side driver 4 requires three data lines for R (red), G (green), and B (blue) in order to display one pixel in color, and therefore 1024 × 3 = 3072 data lines are required. It is necessary to drive, for example, in the case of having a drive capacity of 384 lines, eight are required and they are arranged on one side by cascade connection on the upper outer periphery of the liquid crystal panel 1.

Image data is sent from the PC 5 to the controller 2 of the liquid crystal display module, a clock signal or the like is sent from the controller 2 to the scanning driver 3 in parallel to each scanning driver 3, and a start signal STV for vertical synchronization is sent. Are sent to the scanning-side driver 3 in the first stage, and are sequentially transferred to the scanning-side drivers 3 in the subsequent stages connected in cascade.
Further, a timing signal such as a clock signal or a data signal is sent from the controller 2 to the data side driver 4 in parallel to each data side driver 4, and a start signal STH for horizontal synchronization is sent to the data side driver 4 at the first stage. , And are sequentially transferred to the data-side driver 4 of the next stage and subsequent stages connected in cascade. Then, a pulse-shaped scanning signal is sent from the scanning side driver 3 to each scanning line, and when the scanning signal applied to the scanning line is at a high level, T connected to the scanning line.
All the FTs are turned on, and the gradation voltage sent from the data side driver 4 to the data line at that time is turned on.
Is applied to the pixel electrode via. Then, when the scanning signal becomes low level and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is maintained until the next gray scale voltage is applied to the pixel electrode. Then, by sequentially sending a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.

[0006] The high-speed transfer of image data from the PC5 to the above-mentioned liquid crystal display module, EMI (E lectro M agnet
To reduce ic I nterference) noise, LVDS
(L ow V oltage D ifferential S ignaling) interface is generally adopted as a standard interface. The LVDS interface includes a transmitter that serially converts a parallel signal of image data and outputs the signal as a small-amplitude differential signal, and a receiver that parallel-converts the input signal to restore the original pixel data.
The transmitter is arranged on the PC 5 side, and the receiver is arranged on the liquid crystal display module side. The LVDS receiver is
The one built in the controller 2 is the mainstream.

On the other hand, the IC in the liquid crystal display module
In the signal transfer between the two, conventionally, a binary voltage signal whose amplitude changes between a power supply voltage (“H” level) and a ground (“L” level) (hereinafter referred to as a full-amplitude voltage signal).
Is used as a transmission means. The number of pixels in the liquid crystal panel has increased as the definition of image quality has increased, and from XGA to SXGA (1280 x 102
4 pixels) and UXGA (1600 x 1200 pixels) markets are also expanding, and the clock signal from PC5 is X
In GA, it is about 60MHz at present, but in UXGA, it is 160MHz or more, which is doubled to 320MH.
However, it is necessary to transfer clock signals and data signals at a high speed between the controller 2 and the data side driver 4 in the liquid crystal display module. However, in the conventional CMOS interface, a parallel transmission method must be adopted. There was a problem that the number of wires was increased. Further, there is a problem that a large number of EMI filters are required on the signal wiring in the liquid crystal display module in order to prevent EMI noise.

In order to solve the above problems, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. 1-53598 discloses a high-speed interface circuit technology capable of transmitting a signal with a small voltage amplitude between ICs by utilizing the current difference (differential current signal) between two transmission paths between ICs. disclosed, the high-speed interface circuit, CMADS from NEC Corporation (C urrent M ode
Trademarked as A dvanced D ifferential S ignaling).

An example of the interface circuit disclosed in the above publication will be described below with reference to FIG. The interface circuit of this example is roughly composed of a transmitter 23 which constitutes the IC 21 on the transmission side and a receiver 24 which constitutes the IC 22 on the reception side. The transmitter 23 and the receiver 24 are formed on a printed circuit board. It is connected by paths 25a and 25b.

The transmitter 23 is roughly composed of inverters 26 and 27 and open drain type N-channel MOS transistors 28 and 29. The inverter 26 inverts and outputs the binary input signal V _I , and the inverter 27 inverts and outputs the output signal of the inverter 26. In the MOS transistor 28, the gate is connected to the output terminal of the inverter 26, the source is grounded, the drain is connected to the output terminal 30a of the IC 21, and when the MOS transistor 28 is turned on by the output signal of the inverter 26, the MOS transistor 28 passes through the transmission line 25a. The current supplied from the receiver 24 to the ground. On the other hand, the MOS transistor 29
Has a gate connected to the output terminal of the inverter 27, a source grounded, and a drain connected to the output terminal 30b of the IC 21, and when turned on by the output signal of the inverter 27, the receiver 24 via the transmission line 25b. The current supplied from is sent to the ground.

The receiver 24 is disclosed in Japanese Patent Laid-Open No. 2001-5359.
Although a plurality of embodiments are shown in Japanese Patent Publication No. 8 and a specific example is not shown, when the MOS transistor 28 of the transmitter 23 is turned on, a current of a predetermined value is supplied to the transmission line 25a via the input terminal 36a. It has a first current supply means and a second current supply means for supplying a current of a predetermined value to the transmission line 25b via the input terminal 36b when the MOS transistor 29 is turned on. The current supply means is configured to output a voltage change generated according to the presence or absence of current supply as a binary output signal V _O.

Next, the interface circuit of the above configuration is
The operation will be described with reference to FIG. Figure 10 (a)
~ As shown in (d), input immediately before time T1
Signal V_IIs at "L" level, the MOS transistor
28 is on, and MOS transistor 29 is off
And MO from the first current supply means of the receiver 24.
A current of a predetermined value is sent to the ground via the S transistor 28.
Flowing from the second current supply means of the receiver 24
Is almost grounded via the MOS transistor 29
No current is flowing. Therefore, the output terminal 3 of the IC 21
Voltage Va at 0a, that is, MOS transistor
The drain voltage of the MOS transistor 28 is ON.
There is only a resistance voltage, which is close to 0v, for example, 0.2v
(Hereinafter referred to as "SL" level), output terminal of IC21
The voltage Vb at 30b, that is, the MOS transistor
The drain voltage of the battery 29 is a power supply voltage, for example, 3.3v.
Lower voltage, eg 1.0V (hereinafter referred to as "SH" level
Output signal V _OIs the "L" level.

First, as shown in FIG. 10A, time T
When the input signal V _I rises to "H" level, the output signal of the inverter 26 falls to "L" level.
The OS transistor 28 is turned off, and the first current supply unit of the receiver 24 is connected to the input terminal 36a, the transmission line 25a and the M line.
Almost no current flows to the ground through the OS transistor 28. At this time, the output terminal voltage Va is as shown in FIG.
As shown in (b), the "SL" level shifts to the "SH" level. On the other hand, when the output signal of the inverter 26 falls to the "L" level, the output signal of the inverter 27 rises to the "H" level, the MOS transistor 29 is turned on, and the second current supply means of the receiver 24 supplies the signal. A current of a predetermined value flows to the ground via the input terminal 36b, the transmission line 25b and the MOS transistor 29. At this time, the output terminal voltage Vb is, as shown in FIG.
Transition from "SH" level to "SL" level. As described above, when the differential current signal with the small voltage amplitude flows through the transmission lines 25a and 25b and the output terminal voltages Va and Vb are reversed, the receiver 24 converts the differential current signal into the voltage signal with the full amplitude. The conversion is performed and the output signal V _O is shown in FIG.
As shown in (d), a relatively long time t from time T1
_At time T2 delayed by _d1, it rises to the "H" level.

Next, as shown in FIG. 10A, time T
3 when the input signal V _I falls to "L" level, the output signal of the inverter 26 rises to "H" level.
The OS transistor 28 is turned on, and the first current supply unit of the receiver 24 is connected to the input terminal 36a, the transmission line 25a and the M line.
A current of a predetermined value flows to the ground through the OS transistor 28. At this time, the output terminal voltage Va is as shown in FIG.
As shown in (4), the "SH" level shifts to the "SL" level. On the other hand, the output signal of the inverter 26 is "H".
When rising to the level, the output signal of the inverter 27 is "
Since it falls to the L "level, the MOS transistor 29
Is turned off, and the input terminal 36b, the transmission line 25b, and the MOS transistor 29 are connected from the second current supply means of the receiver 24.
After passing through, almost no current flows to the ground. At this time, the output terminal voltage Vb is, as shown in FIG.
Transition from "SL" level to "SH" level. As described above, when the differential current signal with the small voltage amplitude flows through the transmission lines 25a and 25b and the output terminal voltages Va and Vb are reversed again, the receiver 24 converts the differential current signal into the voltage signal with the full amplitude. Then, as shown in FIG. 10D, the output signal V _O falls to the “L” level at time T4 delayed from the time T3 by the time t _{d1 which} is almost the same as the rising time.

According to this interface circuit, it is possible to transmit a signal with a small voltage amplitude between ICs by utilizing the current difference (differential current signal) between the two transmission paths with a simple circuit configuration. Can be reduced.

Next, the CMADS interface circuit described above is shown in FIG.
From the controller 2 to the data side driver 4 when used to transfer various signals from the data side driver 4 to the data side driver 4
11 and various signal lines from the controller 2 to the data side driver 4 will be described with reference to FIG. Data side driver 4
Are eight along the outer periphery of the liquid crystal panel 1 (A, B,
, H), and various signals are transferred from the controller 2 as follows. The clock signal CLK and the data signal DA are transferred in parallel from the controller 2 to the data side drivers 4 as follows. Transmission and reception is performed via a transmitter 23 provided for the controller 2 to output respective signals and a receiver 24 provided to the data side driver 4 for inputting respective signals.
In addition, the latch signal STB and the polarity signal POL are used for the controller 2 by using the CMOS interface as usual.
Is transferred in parallel to each data side driver 4.

The start signal STH is sent from the controller 2 to the data side driver A of the first stage as follows, and the data side driver B of the next stage and subsequent stages connected in cascade,
It is sequentially transferred to C, ..., H. The timing of the start signal STH from the controller 2 is
Is determined by the controller 2 based on the same clock signal CLK that is transferred in parallel to each data side driver 4. Therefore, the transfer of the start signal STH from the controller 2 to the first-stage data side driver A is performed in order to suppress the timing difference with the clock signal CLK within the allowable time even when the conditions such as the power supply voltage and the ambient temperature change.
The same condition is required that the clock signal CLK is transferred from the controller 2 to the data side drivers 4 in parallel.
Therefore, the transfer of the start signal STH from the controller 2 to the first-stage data side driver A is performed by the clock signal CL.
Similar to K and the data signal DA, it is necessary to use the CMADS interface circuit, and the controller 2 is provided with the transmitter 23 also for outputting the start signal,
The data-side driver 4 is provided with the receiver 24 also for inputting the start signal, and this is performed via the transmitter 23 and the receiver 24. Further, the transfer of the start signal STH to the data-side drivers B, C, ..., H in the subsequent stages connected in cascade is performed via the receiver 24 provided for the start signal input to the data-side driver 4, Therefore, a transmitter 23 for outputting a start signal corresponding to the receiver 24 is provided in the data side driver 4, and the transmitter 23 and the receiver 24 are provided.
Done through.

Next, the operation of the data side driver 4 in the cascade connection will be described with reference to FIG. The start signal STH is input from the controller 2 to the first data-side driver A. Then, the start signal STH, which is the output V _O from the receiver 24 of the data side driver A, becomes "H" level at time t1, and this "H" level is supplied to the start signal reading circuit (not shown) of the data side driver A. , Is read at the rising edge of the pulse a of the clock signal CLK at time t2. The read start signal STH is supplied to a shift register (not shown) of the data side driver A, and is sequentially shifted in cascaded flip-flops of the shift register at the rising edge of the subsequent pulse of the clock signal CLK. Then, the shifted start signal STH becomes "H" level as the input V _I of the transmitter 23 of the data side driver A, slightly behind the rising edge of the pulse b of the clock signal CLK at time t3, and becomes the "H" level at the next stage data side. The data is transferred to the driver B and is output as V _O from the receiver 24 of the data side driver B at time t4 delayed by time t _d1 after the input V _I of the transmitter 23 of the data side driver A becomes “H” level. It becomes H "level. Then, similar to the data side driver A, this "H" level is read at the rising edge of the pulse c of the clock signal CLK at time t5, and the same operation is performed up to the data side driver H at the final stage. When the transfer to the data side driver H is completed, the start signal S
When TH is sent to the data-side driver A, the same operation is started. Although not shown, the shift register arranged between the receiver 24 and the transmitter 23 of each data-side driver 4 receives the start signal STH in the data register arranged in the subsequent stage of the shift register.
During the period from the output from 4 to the supply to the transmitter 23, the signals for reading the data in the data register are sequentially output from the flip-flops connected in cascade in the shift register.

[0019]

By the way, in the above-described cascade connection of the data side driver 4, the transmitter 2 of the data side driver 4 on the upstream side of the cascade connection.
The start signal STH input to 3 is delayed by the time t _d1 from the receiver 24 of the data-side driver 4 in the subsequent stage and output. This delay time t _d1 is the start signal STH.
Is relatively longer than the pulse width of the start signal STH. Therefore, in the data side driver 4 on the latter stage side of the cascade connection, considering the setup time of the start signal STH and the clock signal CLK, the start signal STH is "H" at time t4. There is no margin in the time from the rising of the level to the rising edge of the pulse c of the clock signal CLK, and the “H” level of the start signal STH is set to the clock signal CLK.
There is a possibility that the reading may not be normally performed at the rising edge of, and the transfer of the start signal STH between the data side drivers 4 becomes uncertain. Further, it is desired to further reduce the power consumption generated in the receiver 24 of each data-side driver 4.

Therefore, an object of the present invention is to provide a start signal S between a plurality of cascade-connected semiconductor integrated circuit devices.
An object of the present invention is to provide an interface circuit in which TH transfer is reliably performed with low power consumption, and an electronic device including the interface circuit.

[0021]

An interface circuit according to the present invention is supplied with a differential current signal from a first semiconductor integrated circuit device and sequentially transferred between a plurality of second semiconductor integrated circuit devices connected in cascade. In the period from the transfer of the start signal to the second semiconductor integrated circuit device on the upstream side of the cascade connection to the transfer to the second semiconductor integrated circuit device on the downstream side of the cascade connection, the second semiconductor integrated circuit device on the upstream side is connected. In a cascade connection interface circuit in which data is read into the semiconductor integrated circuit device, the second semiconductor integrated circuit device outputs a binary first voltage signal as a start signal to the second semiconductor integrated circuit device on the subsequent stage side. The buffer and the binary current signal input as the start signal
And a changeover switch for outputting one of the first voltage signal and the second voltage signal from the second semiconductor integrated circuit device on the preceding stage side. In the above interface circuit, when the changeover switch is controlled to output the first voltage signal, the operation of the receiver is controlled to stop.
In the electronic device of the present invention, the start signal supplied from the first semiconductor integrated circuit device and sequentially transferred between the plurality of second semiconductor integrated circuit devices connected in cascade is the second semiconductor on the upstream side of the cascade connection. In an electronic device in which data is read into the second semiconductor integrated circuit device on the front stage side during a period from being transferred to the integrated circuit device to being transferred to the second semiconductor integrated circuit device on the latter stage side of the cascade connection,
The first semiconductor integrated circuit device has a transmission unit that outputs a differential current signal as a start signal, and the second semiconductor integrated circuit device sends a binary signal as a start signal to the second semiconductor integrated circuit device on the subsequent stage side. And a buffer for outputting the first voltage signal of the
And a changeover switch for outputting one of the first voltage signal or the second voltage signal from the second semiconductor integrated circuit device on the preceding stage side. The first semiconductor integrated circuit device of the second semiconductor integrated circuit device is controlled to output the second voltage signal, and the second semiconductor integrated circuit device of the second and subsequent stages is controlled to output the first voltage. It is characterized in that it is controlled to output a signal. In the above electronic device, when the changeover switch is controlled to output the first voltage signal, the operation of the receiver is controlled to stop.
In the above electronic device, the transmitting unit has first and second switching means that are alternately turned on in response to a binary start signal generated in the first semiconductor integrated circuit device, and the receiving unit includes the first and second switching units. 1 is connected to the switching means through the first transmission line, and when the first switching means is turned on,
When a first current supply means for supplying a current of a predetermined value to the first transmission path is connected to the second switching means via the second transmission path and the second switching means is turned on,
A second current supply means for supplying a current of a predetermined value to the second transmission line, and a second change in voltage generated depending on the presence or absence of current supply in the first or second current supply means. It is characterized by outputting as a voltage signal. It is used as a display device, and the first semiconductor integrated circuit device is a control circuit, and the second semiconductor integrated circuit device is a data side driving circuit. The display device is used as a liquid crystal display device.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A feature of the present invention is that a start signal input circuit of a data side driver is CMAD in one IC.
It is possible to switch between the S interface circuit and the CMOS interface circuit. As described above, the transfer of the start signal STH from the controller to the data-side driver in the first stage needs to use the CMADS interface circuit as in the case of the clock signal CLK and the data signal DA. The start signal STH is transferred to the data side driver by the clock signal CLK input to the data side driver.
Since it is output from the previous data driver in synchronism with the above, there is no need to match the timing with the signal output from the controller. Even if a CMOS interface circuit is used, there is no problem.
It is possible to use an OS interface circuit.

An embodiment of the present invention will be described below with reference to FIG.
Will be described with reference to. The same parts as those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted. A liquid crystal display module of a liquid crystal display device includes a liquid crystal panel 1, a controller 2 as a first semiconductor integrated circuit device, a plurality of scanning side drivers 3 and a data side driver 40 as a second semiconductor integrated circuit device. It has.

The data side driver 40 has a start signal S.
The interface circuit has the same interface circuit as the conventional one except the interface circuit for TH, and as the interface circuit for the start signal STH, as shown in FIG. 2, a buffer 43, a receiver 44, and a changeover switch 4 are provided.
5, input terminals 36a and 36b, an output terminal 46, and an interface mode (hereinafter referred to as IFM) selection terminal 47. The buffer 43 is supplied with the binary start signal transferred from the shift register (not shown) inside the data side driver 40 as the input signal V _I , and after buffering, remains as the voltage signal of the full amplitude,
It is output to the output terminal 46 as the first voltage signal. In the receiver 44, the differential current signal converted from the binary start signal by the controller 2 is supplied via the input terminals 36a and 36b, converted into a voltage signal of full amplitude, and output as a second voltage signal. It The change-over switch 45 can be supplied with the first voltage signal from the data-side driver 40 at the preceding stage via the input terminal 36a, and can be supplied with the second voltage signal of the receiver 44, so that the first voltage signal can be supplied. One of the voltage signal and the second voltage signal is selected and output as the output signal V _O. The receiver 44 has a circuit switch similar to that of the receiver 24 shown in FIG.
Has a function of stopping the operation when the first voltage signal is selected. As a result, the power consumption of the receiver 44 whose operation has been stopped can be reduced to zero. The receiver 44 and the changeover switch 45 are controlled by the potential level of the IFM selection terminal 47, and when the level is "H", the changeover switch 45 selects the second voltage signal and the receiver 44 is in the operating state and "L". At the time of the level, the changeover switch 45 selects the first voltage signal and
The receiver 44 is in the operation stopped state.

Regarding the transfer of various signals from the controller 2 of the liquid crystal display module shown in FIG. 1 to the data side driver 40, the controller 2, the data side driver 40, and
Various signal lines from the controller 2 to the data side driver 40 will be described with reference to FIG. Data side driver 40
Are eight (A, B, ..., Along the horizontal side of the liquid crystal panel 1).
H), and various signals are transferred from the controller 2 as follows. The clock signal CLK and the data signal DA are transmitted through the transmitter 23 provided for outputting the respective signals to the controller 2 and the receiver 24 provided for inputting the respective signals to the data side driver 40, as in the conventional case. Sent and received. Further, the latch signal STB and the polarity signal POL are transferred in parallel from the controller 2 to each data side driver 40 by using the CMOS interface as in the conventional case.

The start signal STH is converted as follows.
It is sent from the tracker 2 to the driver A on the first data side,
Data side driver B in the next stage and after connected in a scale,
It is sequentially transferred to C, ..., H. First-stage data side drive
As shown in FIG. 4, Ivar A has input terminals 36a and 3a.
6b is connected to the output terminals 30a and 30b of the controller 2
IFM connected by transmission lines 25a and 25b respectively
The potential level of the selection terminal 47 is set to the “H” level
It This puts the receiver 44 into operation and switches
The switch 45 outputs the second electric power which is the output from the receiver 44.
Output pressure signal V _OCan be output as
The transmitter 23 of the track 2 and the data side
With the receiver 44 of the driver A, the CMADS interface shown in FIG.
Configure the interface circuit. Therefore, the start signal S
TH is the same as the conventional TH
Via the CMADS interface circuit to the driver A
Then sent.

Next, the data driver 40 on the front side and the data driver 40 on the rear side, for example, A and B, are shown in FIG.
As shown in, the output terminal 46 of the data side driver A is connected to the input terminal 36a of the data side driver B by the transmission line 48, and the potential level of the IFM selection terminal 47 of the data side driver B is set to the "L" level. It As a result, the receiver 44 of the data side driver B becomes inoperative and bypassed, and the changeover switch 45 can output the first voltage signal which is the output from the buffer 43 of the data side driver A as the output signal V _O. Yes, data side driver A
Buffer 43 and receiver 4 of data side driver 40B
A CMOS interface circuit is constructed with the bypass of 4. At this time, the receiver 44 of the data side driver B is in the inoperative state, so that the receiver 44 does not consume power. Therefore, the start signal STH is sequentially transferred from the front data driver 40 to the rear data driver 40 via the CMOS interface circuit. In addition, the driver B on the data side of
Since the C, ..., H receivers 44 are in the inoperative state, there is no power consumption in these receivers 44.

Next, the operation of the CMOS interface circuit between the data side driver A and the data side driver B will be described with reference to FIG. 6 (a) to 6 (c)
As shown in, the input signal V _I immediately before time T1
The "L" for a level, the output signal _{V O} from the voltage Va and the change-over switch 45 of the output terminal 46 is at the "L" level. First, as shown in FIG. 6A, when the input signal V _I rises to the “H” level at time T1, the voltage signal of the full amplitude is transmitted to the output terminal 46 via the buffer 43, and the output terminal 46 is transmitted. As shown in FIG. 6 (b), the terminal voltage Va of is at "H" level with a slight delay from time T1. Then, this input signal V _I is further transmitted through the transmission line 48, the input terminal 36 a, and the changeover switch 45 as it is as a voltage signal of full amplitude, and as an output signal V _O ,
As shown in FIG. 6C, the level becomes “H” level at time T2 delayed by time t _d2 from time T1. At this time, it is not necessary to convert the differential current signal in the transmitter 23 and the receiver 24 into a voltage signal of full amplitude as in the conventional technique, and the input signal V _I is switched to the buffer 43 without changing the voltage signal of full amplitude. Output signal V _O via switch 46
Therefore, the delay time t _d2 can be suppressed smaller than the time t _d1 shown in FIG. Next, FIG. 6 (a)
As shown in, when the input signal V _I falls to "L" level at time T3, the buffer 43, the output terminal 46, the transmission line 4
8, the input terminal 36a, and the changeover switch 45, and as an output signal V _O, as shown in FIG.
It falls to "L" level at time T4, which is delayed from time T3 by almost the same time _td2 as at the time of rising.

As described above, when the data-side driver 40 is cascade-connected, the first voltage signal from the buffer 43 of the data-side driver 40 on the upstream side of the cascade connection is output to the output signal V without passing through the receiver 44. _{Since it} is directly transferred as _O , the start signal STH can be output with a delay time t _d2 shorter than the delay time t _d1 of the interface circuit shown in FIG. Also, at this time,
Since the receivers 44 of the data side drivers B, C, ..., H on and after the next stage are in the inoperative state, the power consumption of these receivers 44 can be reduced to zero.

Next, the data side driver 40 described above is used.
Start signal transfer operation in cascade connection
The relationship with the lock signal will be described with reference to FIG. Control
The start signal STH from the roller 2 is the first side data drive
Input to IVA A. Then, the start signal STH is
Output signal V from the receiver 44 of the data side driver A _O
As a result, the level becomes “H” level at time t1, and this “H” level
The start signal (not shown) of the driver A whose level is the data side
The clock signal CLK is supplied to the reading circuit and is supplied at time t2.
Is read at the rising edge of pulse a. Read this
The start signal STH shown in the figure is for the driver A on the data side.
Clock signal CL supplied to shift register not shown
Shift register on rising edge of subsequent pulse of K
The cascaded flip-flops are sequentially shifted
It Then, the shifted start signal STH is
Input V of buffer 43 of driver A_IAs the time
rising edge of pulse b of clock signal CLK at t3
The data of the next stage becomes "H" level slightly after the
Is transferred to the driver B on the data side and received by the driver B on the data side.
Output V from bar 44_OAs the data driver A
Input V of the buffer 43_ITime has passed since the "H" level
t_d2It becomes "H" level at time t4 delayed by only.
Then, like the driver A on the data side, this “H” level is
The rising edge of the pulse c of the clock signal CLK at time t5
It is read at the edge and the same operation is performed at the final stage.
Up to the driver H on the master side. And the driver H on the data side
When the transfer is completed, the start signal STH will
The same operation is started by being sent to the driver A
Be done. Although not shown, each data-side driver 40
Shift register placed between the sheaver 44 and the buffer 43
Is the data register located after the shift register.
The start signal STH is output from the receiver 44 to
Data from the time it is supplied to the buffer 43
Shift register for signal to read data to register
Output from the flip-flops connected in cascade.
It

As described above, when the data side drivers 40 are cascade-connected, the data side drivers 40
, The receiver 44 of the data side driver A of the first stage is configured as a CMADS interface circuit together with the transmitter 23 of the controller 2, and the receiver 44 of the data side drivers B, C, ... Since the bypass circuit is configured as a CMOS interface circuit with the data-side drivers A, B, ..., And G buffers 43 in the preceding stages, the delay of the start signal in the cascade connection can be made smaller than that in the CMADS interface circuit, and the delay circuit in the latter stage of the cascade connection can be The data side driver 40 can normally read the start signal STH at the rising edge of the clock signal CLK. Further, the data side drivers B, C, ...
H is controlled to stop operation when the receiver 44 is set to the potential level of the IFM selection terminal 47 = “L” level, so that the power consumption of these receivers 44 can be reduced to zero, and the liquid crystal display device Power consumption can be reduced.

In the above embodiment, the receiver is C
Although the receiver of the MADS interface circuit has been described as an example, the present invention is not limited to this, and any receiver that can convert a small amplitude differential signal into a voltage signal of full amplitude can be applied.
Further, although the liquid crystal display device has been described as an example, the present invention is not limited to this, and an interface circuit that transfers a start signal by cascade-connecting the data side drive circuits of other display devices to which data is transferred at high speed is also possible. Can be used. Furthermore, without being limited to the display device,
In another electronic device in which data is transferred at high speed, it can also be used as an interface circuit that transfers a start signal by cascade-connecting semiconductor integrated circuit devices.

[0033]

As described above, according to the present invention, when a plurality of semiconductor integrated circuit devices are used and a start signal is transferred between the semiconductor integrated circuit devices by cascade connection, the semiconductor integrated circuit device at the preceding stage of the cascade connection is used. Since the CMOS interface circuit is constituted by the buffer of 1) and the bypass circuit of the receiving section of the subsequent semiconductor integrated circuit device, the delay of the start signal input in the subsequent semiconductor integrated circuit device becomes small, and the start signal can be reliably transferred. It is possible and guaranteed stable operation. Further, since the operation of the receiving unit of the semiconductor integrated circuit device at the latter stage of the cascade connection is controlled to stop, the power consumption of the electronic device can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an interface circuit used for cascade connection of the data side driver shown in FIG.

FIG. 3 is a diagram for explaining the transfer of various signals between the controller and the data side driver shown in FIG.

FIG. 4 is a circuit diagram showing the configuration of an interface circuit between the controller shown in FIG. 3 and the data-side driver A at the first stage.

FIG. 5 is a circuit diagram showing a configuration of an interface circuit between the first-stage and second-stage data side drivers A and B shown in FIG.

6 is a waveform chart for explaining the operation of the interface circuit of FIG.

7 is a waveform diagram of input / output of a start signal in the cascade connection of the data side driver shown in FIG.

FIG. 8 is a circuit diagram showing a circuit of a conventional liquid crystal display device.

FIG. 9 is a circuit diagram showing a configuration of an interface circuit disclosed in Japanese Patent Laid-Open No. 2001-53598.

10 is a waveform diagram for explaining the operation of the interface circuit of FIG.

FIG. 11 is a diagram for explaining the transfer of various signals between the controller and the data side driver shown in FIG.

12 is a waveform diagram of input / output of a start signal in the cascade connection of the data side driver shown in FIG.

[Explanation of symbols]

1 Liquid Crystal Panel 2 Controller (Control Circuit; First Semiconductor Integrated Circuit Device) 23 Transmitter (Transmitting Section) 25a, 25b Transmission Line 40 Data Side Driver (Data Side Driving Circuit; Second Semiconductor Integrated Circuit Device) 43 Buffer 44 Receiver (Receiver) 45 Changeover switch

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G02F 1/133 505 G02F 1/133 505 G09G 3/36 G09G 3/36 H03K 19/0175 H04N 5/66 102Z H04N 5/66 102 H03K 19/00 101Z F term (reference) 2H093 NC11 NC22 NC49 ND34 ND37 ND39 5C006 AF51 AF53 AF61 AF68 AF69 AF71 BB11 BC03 BC11 BC24 BF03 BF16 BF24 FA47 5C058 AA08 BA01 BA26 BA26 5J025BB0 5C058 A0 AA11 BB17 CC14 CC18 CC28 KK01

Claims (7)

[Claims] 1. A start signal supplied from a first semiconductor integrated circuit device as a differential current signal and sequentially transferred between a plurality of second semiconductor integrated circuit devices connected in cascade, is a start signal on the upstream side of the cascade connection. Second semiconductor integrated circuit device is transferred to the second semiconductor integrated circuit device on the latter stage side of the cascade connection in the second semiconductor integrated circuit device on the preceding stage side.
In the cascade connection interface circuit in which data is read into the semiconductor integrated circuit device, the second semiconductor integrated circuit device supplies a binary first voltage as a start signal to the second semiconductor integrated circuit device on the subsequent stage side. A buffer for outputting a signal, a receiver for converting a differential current signal input as a start signal into a binary second voltage signal, and the first voltage signal from the second semiconductor integrated circuit device on the preceding stage side Alternatively, an interface circuit having a changeover switch that outputs one of the second voltage signals. 2. The interface circuit according to claim 1, wherein when the changeover switch is controlled to output the first voltage signal, the operation of the receiver is controlled to stop. 3. A start signal supplied from a first semiconductor integrated circuit device and sequentially transferred between a plurality of second semiconductor integrated circuit devices connected in cascade, is a second semiconductor integrated circuit on the upstream side of the cascade connection. In the electronic device in which data is read into the second semiconductor integrated circuit device on the preceding stage side during a period from being transferred to the device to being transferred to the second semiconductor integrated circuit device on the latter stage side of the cascade connection, The semiconductor integrated circuit device of 1 has a transmitter that outputs a differential current signal as a start signal, and the second semiconductor integrated circuit device outputs to the second semiconductor integrated circuit device of the latter stage as a start signal. A buffer for outputting a first voltage signal having a value, a receiver for converting a differential current signal input as a start signal into a second voltage signal having a binary value, and the second semiconductor device on the preceding stage side. A changeover switch for outputting one of the first voltage signal or the second voltage signal from a circuit device, wherein the changeover switch is the first stage second of the second semiconductor integrated circuit devices. The semiconductor integrated circuit device is controlled to output the second voltage signal, and the second and subsequent semiconductor integrated circuit devices are controlled to output the first voltage signal. And electronic device. 4. The electronic device according to claim 3, wherein when the changeover switch is controlled to output the first voltage signal, the operation of the receiver is controlled to stop. 5. The transmitting section has first and second switching means which are alternately turned on in response to a binary start signal generated in the first semiconductor integrated circuit device, and the receiving section. First current supply means connected to the first switching means via a first transmission path and supplying a current of a predetermined value to the first transmission path when the first switching means is turned on A second current supply which is connected to the second switching means through a second transmission line and supplies a current of a predetermined value to the second transmission line when the second switching means is turned on. And a means for outputting a change in voltage generated in the first or second current supply means depending on the presence or absence of current supply as the second voltage signal. 4. The electronic device according to 4. 6. A display device, wherein the first semiconductor integrated circuit device is a control circuit and the second semiconductor integrated circuit device is a data side driving circuit. Item 6. The electronic device according to item 1. 7. The electronic device according to claim 6, which is used as a liquid crystal display device.