JP2003347404A - Layout method of semiconductor integrated circuit and layout program of semiconductor integrated circuit - Google Patents

Abstract

A layout method and a layout program for a semiconductor integrated circuit capable of arranging and wiring the semiconductor integrated circuit so as to suppress overshoot and undershoot generated by a clock operation. SOLUTION: Flip-flops connected to a clock system are extracted from a netlist 200, and half of the flip-flops designated as cell neighbors are operated with a reverse-phase clock by neighbor designation information 400 based on the result. And replaces the clock driver cell 41 designated as the clock adjacent wiring with the negative-phase clock generation cell 11 and operates with the replaced negative-phase clock when performing placement and wiring based on the netlist reflecting the information. The flip-flops 12 that have not been replaced with the flip-flops 13 that are not replaced are arranged adjacently, and the clock wiring to the two flip-flops is wired adjacently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit layout method and a semiconductor integrated circuit layout program for preventing noise due to the operation of a clock signal.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit such as a cell base, a logic circuit such as an AND (AND) circuit or an OR (OR) circuit, a state holding circuit such as a flip-flop or a latch circuit, a memory circuit and the like are included in an internal area. Multiple
Desired functions have been realized by wiring these circuits according to connection information (net list).

In recent years, with the improvement in the miniaturization technology of semiconductor manufacturing, the scale of the gate mounted on one chip has been increased, and
A high-performance LSI can be realized with one chip. On the other hand, the clock signal of the state holding circuit has become faster and the wiring length has become longer. When the wiring length of the clock signal becomes long, a malfunction due to overshoot and undershoot occurring at a change point of the clock signal becomes a problem.

[0004] Referring to FIG. 4, noise of adjacent wiring due to overshoot and undershoot will be described. In FIG. 4, reference numeral 41 denotes a clock driver cell, 1
2, 14, 43 are flip-flops, 15 is clock 1
Is a wiring connecting the clock driver cell 41 to the flip-flops 12 and 43. Clock 1 and clock 2 are clock signals having different periods, and the period of clock 1 is longer than the period of clock 2.

When the wiring 15 for supplying the clock 1 to the flip-flop 14 and the wiring 42 for supplying the clock 2 to the flip-flops 12 and 43 via the clock driver cell 41 are adjacent to each other, a positive edge of the clock 2 The overshoot and the undershoot at the negative edge appear as noises 44 and 45 during the low level period or the high level period of the clock 1. The noise causes the flip-flop 14 to malfunction. That is, when the flip-flop 14 latches the data at the positive edge of the clock 1, the noise 44 latches the data.

In order to reduce the noise of such a clock signal, an opposite-phase clock of the clock 2 is wired adjacent to a wire 42 connecting the clock driver cell 41 and the flip-flops 12 and 43, and generated on the wire 42. The overshoot and the undershoot may be canceled by the undershoot and the overshoot of the opposite phase clock.

[0007]

However, in the conventional layout program, the designer has to find the clock wiring for which noise needs to be reduced one by one and specify the wiring of the opposite phase clock adjacent to the wiring. Had to be done manually.

In addition, a large number of unnecessary cells are inserted as logic functions to reduce the noise of the clock signal, which causes a problem that the layout area of the semiconductor integrated circuit is increased.

[0009] The present invention has been made in view of the above,
A semiconductor integrated circuit layout method that can automatically arrange and route semiconductor integrated circuits so as to suppress overshoots and undershoots generated by clock operations without inserting cells unnecessary for logic of the semiconductor integrated circuit And a layout program for a semiconductor integrated circuit.

[0010]

In order to achieve the above object, a layout method of a semiconductor integrated circuit according to the present invention is a layout method of a semiconductor integrated circuit for preventing noise due to overshoot and undershoot generated in a clock operation. In, based on the netlist,
A state holding circuit extracting step of extracting a state holding circuit operating with the same clock; A cell replacement step of replacing a clock driver cell that supplies a clock to the state holding circuit with a clock driver cell that outputs an in-phase clock and an opposite-phase clock as an input clock, and a cell replacement step. A netlist changing step of generating a netlist reflecting the changed cell information and connection information in the netlist, and, when performing cell placement based on the generated netlist, the cell adjacent designation state A cell arrangement step of arranging holding circuits adjacent to each other; When performing inter-cell wiring based on the made netlist, said the wiring adjacent to arranged state holding circuit is characterized by having a cell routing step of wiring adjacent.

According to the present invention, a state holding circuit operating with the same clock is extracted based on the netlist, and based on the result, the state holding circuits operating with the same clock are grouped in groups of two and the adjacent cells are set. A clock driver that replaces any one of the designated state holding circuits with a state holding circuit that operates with an inverted phase clock and that outputs a clock driver cell that supplies a clock to the state holding circuit with an input clock and an in-phase clock and an inverted phase clock Replace the cells, change the netlist by reflecting the information, and perform placement and routing based on the changed netlist, and a state holding circuit that operates with the inverted phase clock replaced in the cell replacement step. A state holding circuit that has not been replaced is arranged adjacently, and two clock wirings are arranged adjacently. It is way.

[0012] A layout program for a semiconductor integrated circuit according to the next invention is a program for causing a computer to execute the method described in any one of the above inventions,
The program can be read by a computer, whereby the operation of any one of the above-described inventions can be executed by a computer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor integrated circuit layout method and a layout program according to the present invention will be described below in detail with reference to the accompanying drawings.

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a layout program of the semiconductor integrated circuit of the present embodiment. In FIG. 1, 10
0 is a layout program of the semiconductor integrated circuit, 200 is a netlist of the semiconductor integrated circuit which is cell connection information for realizing a desired function of the semiconductor integrated circuit, and 300 is a state extraction circuit connected to a clock system. A state holding circuit extraction result 400, which is a result of the above, is adjacent designation information for specifying adjacent placement and wiring conditions based on the state holding circuit extraction result 300 in order to remove noise due to overshoot and undershoot.

Layout program 1 for semiconductor integrated circuit
00 extracts the state holding circuit connected to the clock system from the connection information of the netlist 200 and lays out the circuit defined in the netlist 200 based on the neighbor designation information 400.

In the state holding circuit extracting step S110,
The state holding circuit connected to the clock system is extracted from the netlist 200. In the case of FIG. 4, the flip-flop 14 connected to the clock 1 and the flip-flops 12 and 43 connected to the clock 2 via the clock driver cell 41 are extracted. The extraction result is output to the state holding circuit extraction result 300.

When the state holding circuit extraction step S110 is completed and the state holding circuit extraction result 300 is output, the designer creates adjacent designation information 400 based on the state holding circuit extraction result 300. The adjacency designation information 400 includes cell adjacency designation and clock wiring adjacency designation. To specify cell adjacency,
From among the plurality of flip-flops operating at the same edge of the same clock extracted in the state holding circuit extraction step S110, a pair of flip-flops arranged adjacent to each other is designated. In the case of FIG. 4, cell adjacent designation is performed for the flip-flops 12 and 43.

In the clock wiring adjacency specification, the wiring for which the cell adjacency is specified is specified. In the case of FIG. 4, the wiring 42 connecting the clock driver cell 41 and the flip-flops 12 and 43 is specified.

When the adjacency designation information 400 is created, in the cell replacement step S120, one of the flip-flops designated for cell adjacency designation in the adjacency designation information 400 is replaced with a flip-flop that operates on a reverse phase clock.
Specifically, the flip-flop 43 of the flip-flop 12 and the flip-flop 43 designated for cell adjacency designation in the adjacency designation information 400 is replaced with the flip-flop 13 operating at a negative edge as shown in FIG. In addition, the clock driver cell 41 that supplies the clock signal to the flip-flops 12 and 14 is replaced with the opposite-phase clock generation cell 11 that generates two clocks of the input clock and the in-phase clock and the opposite-phase clock.

When the cell replacement step S120 is completed, in a netlist change step S130, a netlist is generated in which the cell information replaced in the cell replacement step S120 and the wiring information of the cell are reflected in the netlist 200. Specifically, the netlist 200
In FIG. 4, the clock driver cell 41 and the flip-flops 12 and 43 are connected by a wiring 42 as shown in FIG. This is a netlist in which the in-phase clock output of the anti-phase clock generation cell 11 and the flip-flop 12 are connected by the wiring 16 and the anti-phase clock output of the anti-phase clock generation cell 11 and the flip-flop 13 are connected by the wiring 17. Change to That is, the netlist designated as the clock neighbor designation in the neighbor designation information 400 is changed.

When the netlist change step S130 is completed, a cell placement step S140 is executed based on the neighbor designation information 400.
The cells defined in the netlist changed in step are placed in the wiring area in the chip. At this time, the adjacent designation information 40
The cell designated by the cell adjacency designation of 0 is arranged adjacently, and the other cells are arranged such that, for example, cells in a net whose timing is restricted by timing constraint information or the like are arranged close to each other. Perform the placement.

When the cell arrangement step S140 is completed,
The cell wiring step S150 performs wiring between cells based on the netlist changed in the netlist changing step S130. At this time, a wiring 16 connecting the antiphase clock generation cell 11 and the flip-flop 12 and a wiring 1 connecting the antiphase clock generation cell 11 and the flip-flop 13
7 are wired adjacently and in parallel, or are wired at the same position on different wiring layers.

FIG. 3 shows the result of laying out the circuit of FIG. 4 using a layout program 100 for a semiconductor integrated circuit. The flip-flop 12 and the flip-flop 43 for which the cell adjacency is specified by the adjacency specification information 400 are:
The flip-flop 43 is replaced with a flip-flop 13 that operates on a negative edge that is a reverse-phase clock, and is arranged adjacent to the flip-flop 12.
The clock driver cell 41 is also a negative-phase clock generation cell 11
The wiring 16 and the wiring 17 are wired in parallel. That is, since the wiring 16 and the wiring 17 are opposite-phase clocks, overshoot and undershoot noises are canceled out, and the wiring 15 and the wiring 15 which are adjacently arranged
There is no influence of noise on.

As described above, in the present embodiment, the cell designation is performed by using the neighbor designation information 400 input based on the state holding circuit extraction result 300 in which all flip-flops connected to the clock system are extracted from the netlist 200. Half of the flip-flops designated adjacent to each other are replaced with flip-flops operating on the opposite-phase clock, and the clock driver cell 41 designated for the clock adjacent wiring is replaced with the opposite-phase clock generation cell 11 to reflect the information. When performing the placement and routing based on the list, the flip-flops 13 operated by the reversed-phase clock replaced in the cell replacement step S120 and the flip-flops 12 not replaced are placed adjacently.
As for wiring, clock wiring to two flip-flops is arranged adjacent to each other. This eliminates the need to insert a large number of unnecessary cells as a logical function to reduce the noise of the clock signal, and eliminates the overshoot and undershoot of the reverse phase clock without increasing the circuit scale. The layout can cancel each other's noise.

Further, the work performed by the designer is only to set the neighbor designation information 400 based on the state holding circuit extraction result 300 in which all flip-flops connected to the clock system are extracted from the netlist 200. ,
Work efficiency during layout can be improved.

[0026]

As described above, according to the layout method of a semiconductor integrated circuit according to the present invention, a state holding circuit operating with the same clock is extracted based on a netlist, and the same clock is extracted based on the result. And a clock driver for supplying a clock to the state holding circuit while replacing any of the state holding circuits designated as cell neighbors with a state holding circuit operating with a negative-phase clock by grouping two state holding circuits each operating with Replace the cell with a clock driver cell that outputs an in-phase clock and an opposite-phase clock to the input clock, change the netlist by reflecting the information, and perform cell placement and routing based on the changed netlist. The state that was not replaced with the state holding circuit that operates with the reversed-phase clock replaced in the replacement step Since the holding circuits are arranged adjacent to each other and the two clock wirings are arranged adjacent to each other, it is not necessary to insert a large number of unnecessary cells as a logical function to reduce noise of a clock signal. Without increasing the scale, a layout can be provided in which the overshoot and the undershoot are canceled by the undershoot and the overshoot of the opposite phase clock.

According to a layout program for a semiconductor integrated circuit according to the next invention, a state holding circuit operating at the same clock is extracted based on a netlist, and two state holding circuits operating at the same clock are extracted based on the result. In each set, one of the state holding circuits designated as cell adjacent is replaced with a state holding circuit that operates with an opposite-phase clock, and a clock driver cell that supplies a clock to the state holding circuit is replaced with an input clock having an in-phase clock and an opposite clock. Replace with a clock driver cell that outputs a phase clock, modify the netlist to reflect that information,
At the time of placement and routing based on the changed netlist, a state holding circuit that operates on the reversed-phase clock replaced in the cell replacement step and a state holding circuit that has not been replaced are placed adjacent to each other, and two clocks are placed. The designer performs the task of setting adjacent designation information based on the state holding circuit extraction result that extracts all flip-flops connected to the clock system from the netlist. , And work efficiency during layout can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout program for a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram for explaining an operation of a cell replacement step shown in FIG. 1;

FIG. 3 is a diagram showing a result of performing a layout using a layout program for a semiconductor integrated circuit of the present invention.

FIG. 4 is a diagram for explaining a conventional technique.

[Explanation of symbols]

11 Negative phase clock generation cell, 12, 13, 14, 43
Flip-flops, 15, 16, 17, 42 wiring,
41 clock driver cell, 44, 45 noise, 1
00 layout program for semiconductor integrated circuit, 200
Netlist, 300 state holding circuit extraction result, 40
0 Neighbor designation information.

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Claims (2)

[Claims] 1. A method of laying out a semiconductor integrated circuit for preventing noise due to overshoot and undershoot generated in a clock operation, wherein a state holding circuit extracting step for extracting a state holding circuit operating with the same clock based on a netlist. A pair of state holding circuits that operate on the same clock are replaced by two, and one of the state holding circuits designated as adjacent to the cell is replaced with a state holding circuit that operates on an opposite-phase clock; Replacing the clock driver cell that supplies the input clock with a clock driver cell that outputs an in-phase clock and an opposite-phase clock to the input clock; and reflecting the cell information and connection information changed in the cell replacement step in the netlist. Generate a netlist A cell list arranging step of arranging the cell-adjacent-designated state holding circuit adjacently when arranging cells based on the generated netlist; and A cell wiring step of wiring adjacently the wiring of the state holding circuit arranged adjacently when performing inter-cell wiring. 2. A layout program for a semiconductor integrated circuit that causes a computer to execute the method according to claim 1.