JP2003318544A - Multilayer wiring board and method of manufacturing the same - Google Patents
Multilayer wiring board and method of manufacturing the sameInfo
- Publication number
- JP2003318544A JP2003318544A JP2002118932A JP2002118932A JP2003318544A JP 2003318544 A JP2003318544 A JP 2003318544A JP 2002118932 A JP2002118932 A JP 2002118932A JP 2002118932 A JP2002118932 A JP 2002118932A JP 2003318544 A JP2003318544 A JP 2003318544A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- wiring board
- multilayer wiring
- current density
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】
【課題】ポリイミド樹脂等の有機絶縁材からなる絶縁層
と銅等の導体材料からなる配線層が交互に積層してなる
多層構造を有する多層配線基板の製造における上下の導
体配線層を接続する微小径ビアホールを穴埋めするめっ
き工程において、短時間で穴埋めが可能となり、かつ、
接続信頼性の高い、フィルドビアめっき方法を提供す
る。
【解決手段】電解めっき工程において、電流密度を少な
くとも2段階に変化させてめっきを行う。なお、電解め
っきの電流密度を、最初の電流密度が一番低く、その後
は徐々に増加させることも含まれる。この多層配線基板
は、半導体素子搭載用インターポーザに用いることがで
きる。
(57) Abstract: Upper and lower conductors in the production of a multilayer wiring board having a multilayer structure in which an insulating layer made of an organic insulating material such as a polyimide resin and a wiring layer made of a conductive material such as copper are alternately laminated. In the plating step of filling the micro-diameter via holes connecting the wiring layers, the filling can be done in a short time, and
Provided is a filled via plating method with high connection reliability. In an electrolytic plating step, plating is performed by changing a current density in at least two stages. In addition, the current density of the electrolytic plating includes the lowest current density at the beginning, and gradually increasing thereafter. This multilayer wiring board can be used for an interposer for mounting a semiconductor element.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ポリイミド等の樹
脂からなる絶縁層と導体配線層が交互に積層してなる多
層構造を有する多層配線基板の製造方法に関し、特に、
半導体素子搭載用インターポーザに用いられ、微小径ビ
アホールをめっきにて形成する多層配線基板及びその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board having a multilayer structure in which insulating layers made of resin such as polyimide and conductor wiring layers are alternately laminated,
The present invention relates to a multilayer wiring board used for a semiconductor element mounting interposer and forming a micro via hole by plating, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】近年、半導体大規模集積回路（ＬＳＩ）
等の半導体素子ではトランジスターの集積度が高まり、
その動作速度はクロック周波数で１ＧＨｚに達するもの
が、また、入出力端子数では１０００を越えるものが出
現するに 至っている。2. Description of the Related Art In recent years, semiconductor large scale integrated circuits (LSI)
In semiconductor devices such as, the degree of integration of transistors has increased,
The operation speed has reached 1 GHz in clock frequency, and more than 1000 in number of input / output terminals has come to appear.
【０００３】半導体素子をプリント配線基板に実装する
ために、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）や
ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）等のイ
ンターポーザが開発され、実用化されている。Interposers such as BGA (Ball Grid Array) and CSP (Chip Size Package) have been developed and put into practical use in order to mount a semiconductor element on a printed wiring board.
【０００４】このような多層配線基板は銅貼基板やセラ
ミック基板上に絶縁樹脂層と導体配線層を交互に積み上
げて形成される。この工法にて作製された多層配線基板
の絶縁層は、ポリイミド等の樹脂を塗布することにより
形成し、薄膜化することができる。また、導体配線層は
めっきで形成でき、微細配線が可能となる。一方、上下
の導体配線層を接続するビアホールはレーザ加工等にて
孔を形成し、内部をめっきで埋めることにより形成でき
る。このため、従来の銅貼り基板を一括積層する多層プ
リント配線基板、あるいは、グリーンシートを積層して
一括焼成するセラミック多層配線基板に比べ、高配線密
度化、薄膜化、小型化を図ることができる。Such a multilayer wiring board is formed by alternately stacking insulating resin layers and conductor wiring layers on a copper-clad board or a ceramic board. The insulating layer of the multilayer wiring board manufactured by this method can be formed by applying a resin such as polyimide to make it a thin film. Further, the conductor wiring layer can be formed by plating, which enables fine wiring. On the other hand, via holes connecting the upper and lower conductor wiring layers can be formed by forming holes by laser processing or the like and filling the inside with plating. Therefore, higher wiring density, thinner film, and smaller size can be achieved as compared with a conventional multilayer printed wiring board in which copper-clad boards are stacked together or a ceramic multilayer wiring board in which green sheets are stacked and fired together. .
【０００５】また、これとは別に、従来の多層プリント
配線基板に銅箔付ポリイミドフィルムを接着剤で貼り合
わせた構成のものも提案されている。この構成において
も、銅箔の薄さから微細配線を形成することが可能とな
り、同じように、高配線密度化、薄膜化、小型化を図る
ことができる。Separately from this, there is also proposed a structure in which a polyimide film with a copper foil is attached to a conventional multilayer printed wiring board with an adhesive. Also in this configuration, fine wiring can be formed from the thinness of the copper foil, and similarly, high wiring density, thinning, and downsizing can be achieved.
【０００６】一方、上下の導体配線層を接続するビアホ
ールは、エキシマーレーザやＹＡＧ第３高調波、第４高
調波を用いたレーザ加工機の導入が盛んになり、微小径
のビアホール形成が容易になってきている。On the other hand, for via holes connecting the upper and lower conductor wiring layers, a laser processing machine using an excimer laser, a YAG third harmonic, or a fourth harmonic becomes popular, and a via hole having a small diameter can be easily formed. It has become to.
【０００７】有機絶縁材からなる絶縁層と導体材料から
なる配線層が交互に積層してなる多層構造を有する多層
配線基板において、上下の導体配線層を接続するビアホ
ールを前記導体材料、有機絶縁材料の順にレーザで形成
して、下部導体配線層表面を露出させた後、ビアホール
下部配線層に堆積した有機絶縁材の残さを除去し、無電
解めっき等で電気めっきのシード層を形成し、それを電
極にして孔内部の側面や底部に一定厚のめっき形成を行
うが高速信号を通すためあるいはビアホール直上へビア
ホールを形成して配線の自由度を上げる目的で孔内部を
めっき金属で埋めてしまう、フィルドビアめっきが盛ん
に行われている。In a multilayer wiring board having a multilayer structure in which an insulating layer made of an organic insulating material and a wiring layer made of a conductive material are alternately laminated, via holes connecting upper and lower conductive wiring layers are formed by the conductive material and the organic insulating material. Laser to expose the surface of the lower conductor wiring layer, the residue of the organic insulating material deposited on the lower wiring layer of the via hole is removed, and a seed layer for electroplating is formed by electroless plating. The inner surface of the hole is filled with plated metal to allow high-speed signals to pass or to form a via hole directly above the via hole to increase the freedom of wiring. , Filled via plating is actively performed.
【０００８】このフィルドビアめっきは、電流波形制御
や添加剤によって選択的に孔内部にめっき金属を析出さ
せる手法をとっているが、小径のビアホールの場合、ビ
ア内部に空隙（ボイド）が発生しないように低電流密度
でのめっきが行われる。したがって低電流密度で長時間
をかけてビアホールを穴埋めめっきしているので、生産
効率が悪いという問題があった。また、テープ状などの
連続めっきが必要な材料では、連続めっきを行うため
に、装置が非常に長くなり、設備コストが膨大となって
しまうという問題があった。This filled via plating employs a method of selectively depositing a plating metal inside the holes by controlling the current waveform and additives, but in the case of a small diameter via hole, voids (voids) are not generated inside the via. Is plated at a low current density. Therefore, since the via holes are filled and plated at a low current density for a long time, there is a problem that the production efficiency is poor. Further, in the case of a material that requires continuous plating, such as a tape, there is a problem that the apparatus becomes very long and the equipment cost becomes huge because the continuous plating is performed.
【０００９】[0009]
【発明が解決しようとする課題】本発明は係る従来技術
の問題点に鑑みてなされたもので、有機絶縁材からなる
絶縁層と導体材料からなる配線層が交互に積層してなる
多層構造を有する多層配線基板の製造における上下の導
体配線層を接続するビアホールを穴埋めするめっき工程
において、短時間で穴埋めが可能となり、かつ接続信頼
性の高いフィルドビアめっき方法を提供することを課題
とする。SUMMARY OF THE INVENTION The present invention has been made in view of the problems of the prior art, and has a multilayer structure in which insulating layers made of an organic insulating material and wiring layers made of a conductive material are alternately laminated. An object of the present invention is to provide a filled via plating method capable of filling holes in a short time in a plating step of filling via holes connecting upper and lower conductor wiring layers in the manufacture of a multilayer wiring board having the above and having high connection reliability.
【００１０】[0010]
【課題を解決するための手段】本発明において上記の課
題を達成するために、請求項１の発明では有機絶縁材料
からなる絶縁層と導体材料からなる配線層を交互に積層
してなる多層構造に上下の配線層を接続するビアホール
を形成し、前記ビアホールを電解めっきにより穴埋めを
する多層配線基板の製造方法において、前記電解めっき
に際し、電流密度を少なくとも2段階に変化させてめっ
きを行うことを特徴とする多層配線基板の製造方法とし
たものである。In order to achieve the above object in the present invention, in the invention of claim 1, a multi-layer structure in which insulating layers made of an organic insulating material and wiring layers made of a conductive material are alternately laminated. Forming a via hole connecting the upper and lower wiring layers to, in the method of manufacturing a multilayer wiring board in which the via hole is filled by electrolytic plating, in the electrolytic plating, changing the current density in at least two stages, it is possible to perform plating. This is a method for manufacturing a characteristic multilayer wiring board.
【００１１】また、請求項２の発明では前記電解めっき
の電流密度は、最初の電流密度が一番低く、その後は徐
々に増加することを特徴とした請求項１記載の多層配線
基板の製造方法としたものである。Further, in the invention of claim 2, the current density of the electroplating is such that the initial current density is the lowest and the current density is gradually increased thereafter. It is what
【００１２】また、請求項3の発明では前記電解めっき
が銅めっきであることを特徴とした請求項1あるいは2に
記載の多層配線基板の製造方法としたものである。The invention of claim 3 provides the method for manufacturing a multilayer wiring board according to claim 1 or 2, wherein the electrolytic plating is copper plating.
【００１３】また、請求項4の発明では前記有機絶縁材
がポリイミドであり、導体材料が銅箔であることを特徴
とした請求項１あるいは2あるいは3のいずれかに記載の
多層配線基板の製造方法としたものである。Further, in the invention of claim 4, the organic insulating material is polyimide, and the conductor material is copper foil, and the production of the multilayer wiring board according to claim 1 or 2 or 3. It is a method.
【００１４】更に、請求項５の発明は前記請求項1ない
し4のいずれかに記載の方法によって形成されたビアホ
ールを有する多層配線基板としたものである。Further, the invention of claim 5 provides a multilayer wiring board having a via hole formed by the method according to any one of claims 1 to 4.
【００１５】[0015]
【発明の実施の形態】本発明の多層配線基板およびその
製造方法は、基本的には、次の通りである。BEST MODE FOR CARRYING OUT THE INVENTION The multilayer wiring board and its manufacturing method of the present invention are basically as follows.
【００１６】有機絶縁材からなる絶縁層と導体材料から
なる配線層が交互に積層してなる多層構造を有する多層
配線基板（図１（ａ））において、上下の導体配線層を
接続するビアホールを形成する（図１（ｂ））。なお基
板については各種基板が使用できるが、薄膜化、高配線
密度化、小型化の観点から、絶縁材料にポリイミド、導
体材料に銅箔を使用した銅箔付きポリイミドフィルムが
より好ましい。In a multilayer wiring board (FIG. 1A) having a multilayer structure in which insulating layers made of an organic insulating material and wiring layers made of a conductive material are alternately laminated, via holes connecting upper and lower conductive wiring layers are formed. Formed (FIG. 1B). Although various substrates can be used as the substrate, a polyimide film with a copper foil using a polyimide as an insulating material and a copper foil as a conductor material is more preferable from the viewpoints of thinning, high wiring density, and miniaturization.
【００１７】ビアホールを形成する方法については、レ
ーザ加工が好ましい。レーザについては炭酸ガスレー
ザ、ＹＡＧ（基本波、第２高調波、第３高調波、第４高
調波）レーザ、エキシマーレーザ等があるが、導体層、
絶縁層共に加工を行う為、両者を同時に加工することの
出来る４００ｎｍ以下の短波長レーザであるＹＡＧ第３
高調波、第４高調波ならびにエキシマーレーザがより好
ましい。As a method of forming a via hole, laser processing is preferable. Regarding the laser, there are carbon dioxide laser, YAG (fundamental wave, second harmonic wave, third harmonic wave, fourth harmonic wave) laser, excimer laser, etc.
Since the insulating layer is processed, YAG No. 3 which is a short wavelength laser of 400 nm or less that can process both of them at the same time
Higher harmonics, fourth harmonics and excimer lasers are more preferred.
【００１８】次に、ビアホールを導体材料、有機絶縁材
料の順にレーザで形成した際に発生する導体材料による
ドロスを物理研磨もしくは化学研磨により除去する（図
１（ｃ））。Next, the dross due to the conductor material generated when the via hole is formed by the laser in the order of the conductor material and the organic insulating material is removed by physical polishing or chemical polishing (FIG. 1C).
【００１９】その後、ビアホール下層に堆積した有機絶
縁材料の残さを過マンガン酸カリウムと水酸化ナトリウ
ムの混合液等の液中に基板を浸漬させ、デスミア処理を
行い（図１（ｄ））、次いで、樹脂面に電解めっきのシ
ード層を形成する為、無電解めっきまたはダイレクトプ
レーティングを行う（図１（ｅ））。After that, the residue of the organic insulating material deposited in the lower layer of the via hole is immersed in a liquid such as a mixed liquid of potassium permanganate and sodium hydroxide to perform desmear treatment (FIG. 1 (d)), and then, In order to form a seed layer for electrolytic plating on the resin surface, electroless plating or direct plating is performed (FIG. 1 (e)).
【００２０】電解めっきは、フィルドビアめっきの時間
短縮をするためにめっき時の電流密度を少なくとも2段
階変化させてめっきを行う。電流密度の設定については
初期の段階は、ボイドの発生を防止するために低電流密
度でめっきを行い（図１（ｆ））、その後フィリングが
進行し、ビアのアスペクト比が初期のアスペクト比より
も小さくなった時点で段階的に電流密度を増加させる
（図１（ｇ））。これにより電解めっきの時間が大幅に
短縮可能である。電解めっき浴については導電性のよい
金属であればよいが、経済性の面から銅めっき浴が好ま
しい。Electrolytic plating is performed by changing the current density during plating by at least two steps in order to shorten the time for filled via plating. Regarding the setting of the current density, at the initial stage, plating is performed at a low current density in order to prevent the occurrence of voids (Fig. 1 (f)), then filling progresses, and the aspect ratio of the via is higher than the initial aspect ratio. When it also becomes smaller, the current density is increased stepwise (FIG. 1 (g)). As a result, the time for electrolytic plating can be significantly shortened. The electrolytic plating bath may be a metal having good conductivity, but a copper plating bath is preferable from the viewpoint of economy.
【００２１】なお、電流密度については、段階的に変化
させても（図２（ａ））、連続的に変化させても構わな
い（図２（ｂ））。The current density may be changed stepwise (FIG. 2A) or continuously (FIG. 2B).
【００２２】このようにして形成した多層配線基板は、
直径２０〜６０μｍのビアホール内部にボイドが発生せ
ず、短時間のめっきで接続信頼性が高い基板を得ること
ができる。The multilayer wiring board thus formed is
A void is not generated inside the via hole having a diameter of 20 to 60 μm, and a substrate having high connection reliability can be obtained by plating for a short time.
【００２３】[0023]
【実施例】以下に、具体的な実施例により本発明を説明
する。尚、本発明は後述する実施例に何ら限定されるも
のではない。EXAMPLES The present invention will be described below with reference to specific examples. The present invention is not limited to the examples described below.
【００２４】＜実施例1＞基板には両面銅箔付ポリイミ
ドテープ(三井化学製 ネオフレックス Cu/PI/Cu=9μm/
30μｍ/9μm)を使用した。この基板にビアホールを加工
する為に、355nmの波長の紫外線レーザを使用し、ビア
ホール加工を行った。加工したビアホール径は30μmで
あった。加工したビアホールを光学顕微鏡にて観察した
ところ、ビアホール開口端部にビア加工によるドロスが
発生していることを確認した。そこでドロス部分を除去
する為に物理研磨を行った。Example 1 A polyimide tape with copper foil on both sides (Neoflex Cu / PI / Cu = 9 μm / manufactured by Mitsui Chemicals) was used as a substrate.
30 μm / 9 μm) was used. In order to process a via hole on this substrate, an ultraviolet laser having a wavelength of 355 nm was used to perform the via hole processing. The processed via hole diameter was 30 μm. When the processed via hole was observed with an optical microscope, it was confirmed that dross was generated at the opening end of the via hole due to the via processing. Therefore, physical polishing was performed to remove the dross portion.
【００２５】その後、ビアホール底部に堆積した樹脂残
さを除去する為に、過マンガン酸カリウムと水酸化ナト
リウムを3対2の割合でイオン交換水に溶解させ、約50℃
に加熱した。この混合液中に基板を浸漬させ、樹脂残さ
を除去した。Thereafter, in order to remove the resin residue deposited on the bottom of the via hole, potassium permanganate and sodium hydroxide were dissolved in ion-exchanged water at a ratio of 3: 2, and the solution was heated to about 50 ° C.
Heated to. The substrate was immersed in this mixed solution to remove the resin residue.
【００２６】次いで、電気めっきのシード層を形成する
為に無電解銅めっき処理を行った。その後硫酸銅めっき
液により電解めっき処理を行った。電解めっき処理はは
じはじめの１０分間を電流密度１Ａ／ｄｍ2で行い、そ
の後２Ａ／ｄｍ2で１０分間めっきの合計２０分間めっ
きを行った。Next, an electroless copper plating process was performed to form a seed layer for electroplating. After that, electrolytic plating treatment was performed with a copper sulfate plating solution. The electroplating treatment was carried out for 10 minutes at the beginning with a current density of 1 A / dm 2 , and then for 10 minutes at 2 A / dm 2 for a total of 20 minutes.
【００２７】その後基板の断面観察を行い、銅の充填不
良をビアホール100個調査したが、不良部分は0個であっ
た。また比較として１Ａ／ｄｍ2で２０分間めっきした
ものと２Ａ／ｄｍ2で２０分間めっきしたものについて
も断面観察を行ったが、１Ａ／ｄｍ2で２０分間めっき
したものについてはフィリングが完全でなく途中の状態
であった。また、２Ａ／ｄｍ2で２０分間めっきを行っ
たものについては、ビア内部にボイドが観測された。After that, the cross section of the substrate was observed, and 100 via holes were inspected for defective copper filling. Although was also cross-sectional observation for those plated with 1A / dm 2 in those plating 20 minutes and 2A / dm 2 as a comparison for 20 minutes, not completely filling for those plated with 1A / dm 2 for 20 minutes It was on the way. Further, voids were observed inside the vias in the case of plating at 2 A / dm 2 for 20 minutes.
【００２８】また信頼性試験として、はんだ耐熱試験、
温度サイクル試験を本発明の製造工程を経た基板につい
て行った。表1にその結果を示す。As a reliability test, a solder heat resistance test,
A temperature cycle test was performed on the substrate that has undergone the manufacturing process of the present invention. Table 1 shows the results.
【００２９】[0029]
【表1】 【table 1】
【００３０】表1に示したように本発明の製造工程を経
た基板についてはいずれの信頼性試験においても異常は
見られなかった。なお表1は分母が検査ビアホール数で
分子が不良ビアホール数である。As shown in Table 1, no abnormality was found in any of the reliability tests of the substrates that had undergone the manufacturing process of the present invention. In Table 1, the denominator is the number of inspection via holes and the numerator is the number of defective via holes.
【００３１】[0031]
【発明の効果】本発明の多層配線基板の製造方法によれ
ば、フィルドビアめっき時のめっき時間を大幅に短縮可
能であり、ビア内にボイド等を発生することなく、層間
の接続信頼性の高いフィルドビアめっきが可能となる。According to the method for manufacturing a multilayer wiring board of the present invention, it is possible to greatly reduce the plating time during filled via plating, and to prevent the occurrence of voids and the like in the vias, and to improve the reliability of connection between layers. Filled via plating is possible.
【００３２】[0032]
【図１】本発明の多層配線基板の製造工程を示す説明
図。FIG. 1 is an explanatory view showing a manufacturing process of a multilayer wiring board of the present invention.
【図2】本発明のフィルドビアめっき工法の電流密度変
化を示す説明図。FIG. 2 is an explanatory diagram showing changes in current density in the filled via plating method of the present invention.
１…導体層 ２…絶縁層 ３…ドロス ４…有機絶縁材料残さ ５…無電解めっき層 ６…電解めっき層 1 ... Conductor layer 2 ... Insulation layer 3 ... Dross 4: Organic insulating material residue 5 ... Electroless plating layer 6 ... Electrolytic plating layer
Claims (5)
らなる配線層を交互に積層してなる多層構造に上下の配
線層を接続するビアホールを形成し、前記ビアホールを
電解めっきにより穴埋めをする多層配線基板の製造方法
において、前記電解めっきに際し、電流密度を少なくと
も2段階に変化させてめっきを行うことを特徴とする多
層配線基板の製造方法。1. A via hole for connecting upper and lower wiring layers is formed in a multi-layer structure in which an insulating layer made of an organic insulating material and a wiring layer made of a conductor material are alternately laminated, and the via hole is filled by electrolytic plating. In the method for manufacturing a multilayer wiring board, in the electrolytic plating, the current density is changed in at least two steps to carry out the plating.
密度が一番低く、その後は徐々に増加することを特徴と
した請求項１記載の多層配線基板の製造方法。2. The method for producing a multilayer wiring board according to claim 1, wherein the current density of the electrolytic plating is lowest at the beginning and gradually increases thereafter.
徴とした請求項1あるいは2に記載の多層配線基板の製造
方法。3. The method for manufacturing a multilayer wiring board according to claim 1, wherein the electrolytic plating is copper plating.
材料が銅箔であることを特徴とした請求項１あるいは2
あるいは3のいずれかに記載の多層配線基板の製造方
法。4. The organic insulating material is polyimide, and the conductor material is copper foil.
Alternatively, the method for manufacturing a multilayer wiring board according to any one of 3).
法によって形成されたビアホールを有する多層配線基
板。5. A multilayer wiring board having a via hole formed by the method according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002118932A JP2003318544A (en) | 2002-04-22 | 2002-04-22 | Multilayer wiring board and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002118932A JP2003318544A (en) | 2002-04-22 | 2002-04-22 | Multilayer wiring board and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003318544A true JP2003318544A (en) | 2003-11-07 |
Family
ID=29535635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002118932A Pending JP2003318544A (en) | 2002-04-22 | 2002-04-22 | Multilayer wiring board and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003318544A (en) |
Cited By (12)
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|---|---|---|---|---|
| JP2007173683A (en) * | 2005-12-26 | 2007-07-05 | Nec Toppan Circuit Solutions Inc | Printed wiring board manufacturing method, printed wiring board and plating / etching / polishing apparatus |
| KR100783467B1 (en) | 2006-02-24 | 2007-12-07 | 삼성전기주식회사 | Printed Circuit Board with Internal Through Hole and Manufacturing Method Thereof |
| JP2008028337A (en) * | 2006-07-25 | 2008-02-07 | Shinko Electric Ind Co Ltd | Method of manufacturing electronic component |
| WO2008153185A1 (en) * | 2007-06-15 | 2008-12-18 | Meltex Inc. | Embedding copper plating method for manufacture of printed wiring board, and printed wiring board obtained by using the embedding copper plating method |
| CN103484908A (en) * | 2013-09-29 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | Electrochemical copper deposition method of TSV |
| US9376758B2 (en) | 2010-12-21 | 2016-06-28 | Ebara Corporation | Electroplating method |
| US9516764B2 (en) | 2013-03-28 | 2016-12-06 | Hitachi Chemical Company, Ltd | Method for manufacturing multilayer wiring substrate |
| US9648759B2 (en) | 2013-10-09 | 2017-05-09 | Hitachi Chemical Company, Ltd. | Multilayer wiring board and method for manufacturing same |
| US10076044B2 (en) | 2013-10-09 | 2018-09-11 | Hitachi Chemical Company, Ltd. | Method for manufacturing multilayer wiring substrate |
| US10165691B2 (en) | 2013-10-09 | 2018-12-25 | Hitachi Chemical Company, Ltd. | Method for manufacturing multilayer wiring substrate |
| CN110769616A (en) * | 2018-07-26 | 2020-02-07 | 健鼎（无锡）电子有限公司 | Method for manufacturing circuit board structure |
| CN112106451A (en) * | 2018-05-11 | 2020-12-18 | 住友电气工业株式会社 | Printed wiring board and method for manufacturing printed wiring board |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173683A (en) * | 2005-12-26 | 2007-07-05 | Nec Toppan Circuit Solutions Inc | Printed wiring board manufacturing method, printed wiring board and plating / etching / polishing apparatus |
| KR100783467B1 (en) | 2006-02-24 | 2007-12-07 | 삼성전기주식회사 | Printed Circuit Board with Internal Through Hole and Manufacturing Method Thereof |
| JP2008028337A (en) * | 2006-07-25 | 2008-02-07 | Shinko Electric Ind Co Ltd | Method of manufacturing electronic component |
| WO2008153185A1 (en) * | 2007-06-15 | 2008-12-18 | Meltex Inc. | Embedding copper plating method for manufacture of printed wiring board, and printed wiring board obtained by using the embedding copper plating method |
| JP2009021581A (en) * | 2007-06-15 | 2009-01-29 | Meltex Inc | Embedded copper plating method for printed wiring board manufacture and printed wiring board obtained by using the embedded copper plating method |
| US9376758B2 (en) | 2010-12-21 | 2016-06-28 | Ebara Corporation | Electroplating method |
| US9516764B2 (en) | 2013-03-28 | 2016-12-06 | Hitachi Chemical Company, Ltd | Method for manufacturing multilayer wiring substrate |
| CN103484908A (en) * | 2013-09-29 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | Electrochemical copper deposition method of TSV |
| US9648759B2 (en) | 2013-10-09 | 2017-05-09 | Hitachi Chemical Company, Ltd. | Multilayer wiring board and method for manufacturing same |
| US10076044B2 (en) | 2013-10-09 | 2018-09-11 | Hitachi Chemical Company, Ltd. | Method for manufacturing multilayer wiring substrate |
| US10165691B2 (en) | 2013-10-09 | 2018-12-25 | Hitachi Chemical Company, Ltd. | Method for manufacturing multilayer wiring substrate |
| CN112106451A (en) * | 2018-05-11 | 2020-12-18 | 住友电气工业株式会社 | Printed wiring board and method for manufacturing printed wiring board |
| CN112106451B (en) * | 2018-05-11 | 2024-05-31 | 住友电气工业株式会社 | Printed wiring board and method for manufacturing the same |
| CN110769616A (en) * | 2018-07-26 | 2020-02-07 | 健鼎（无锡）电子有限公司 | Method for manufacturing circuit board structure |
| CN110769616B (en) * | 2018-07-26 | 2022-08-02 | 健鼎（无锡）电子有限公司 | Method for manufacturing circuit board structure |
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