JP2003332433A - Method for designing full-mounted chip elements on memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing full-mounted chip elements on a memory, which avoids difficulty that a hard macro prevents routing from being sufficiently automated. <P>SOLUTION: The method for designing full-mounted chip elements on a memory comprises dividing an element in the hard macro into ones of transistor level. In the state where two or more high-voltage circuits exist, this method provides multiple bypass circuits as a VSS and a VDD, respectively, which are two power suppliers that can be recognized by software. The many high-voltage circuits are used as ones for routing signals. As a result, automatic routing can be attained in terms of all the elements in the hard macro. For achieving automatic arrangement of all the chips and routing, the basic design in the hard macro is integrated into other portions thereafter. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention [Industrial applications]

The present invention generally relates to a design method for one element, and more particularly to a design method for all mounted chip elements on a memory.

[Prior art]

The commonly used design methods primarily include both bottom-up and top-down approaches. Bottom-up approaches generally design important components in advance, and integrate each component into different modules, and finally connect the modules together to form the product itself. Memory devices, or mixed mode signal integrated circuit devices, generally use a bottom-up design flow because the analog circuits of these circuits are of transistor level design. In the prior art, this design cannot be treated as a logic gate level design, so the device cannot be split for automatic path setting. The top-down design method, on the other hand, first designs the components by considering the product efficiency itself. Besides bottom-up and top-down design methods, it is also possible to integrate bottom-up and top-down design methods and use them to achieve product optimization challenges.

An ordinary memory is mainly composed of a memory cell array portion and a logic portion. Since there are many analog circuits, logic wirings and logic parts in the memory, the bottom-up design method is used for normal memory design. However, although it has been proposed to use a bottom-up design method when designing the logic portion in the memory, the analog circuit portion cannot be designed using the top-down design method. Therefore, designing the logic portion using the top-down design method cannot meet the requirements of full-chip automated design.

1A and 1B are flow charts of a conventional memory design. In the prior art, the memory cell array portion and the logic portion are designed separately. The design of the memory cell array portion includes the steps of basic design 100, hard macro layout 102, full-chip path setting 104, and tape output 106.

FIG. 1B is a flowchart of a conventional logic design. A conventional logic design flow includes the steps of high level hardware description language program 110, synthesis 112, automatic route setup 114, and tape output 116.

FIG. 2 is a flowchart of a conventional memory design. Basic design 2
00, hard macro layout, and function description 202
including. The design of the logic part includes the steps of high level hardware description language program 204 and synthesis 206.
The steps of the memory cell array portion and the steps of the logical portion are then combined and combined with the step 208 of setting up a full chip path by the hard macro and finally the step of tape output 210. Since the whole design is divided into two different parts, the route setting design of the hard macro analog schematic has to use a manual method.

[Problems to be Solved by the Invention]

In the conventional memory design flow, the hard macro in the memory cell array portion including the pulse generator, the capacitor, the resistor, the transistor, and the high-voltage element must be designed in advance, and then the hard macro together with the hard macro. Perform path setting for all chips above. The flexibility of the route setting design is greatly limited by using such a method. Therefore, the whole design cannot be completely automated, which causes a phenomenon that the design time is prolonged and the progress is delayed.

In addition, Avanti Corp. Apollo software developed by or Cad
ence Corp. Current automatic placement and path setting (APR) such as SE software developed by
The tool cannot perform automatic routing in situations where there are two or more high voltage circuits on the same chip, which is common in memory design, such as in conventional flash memory array designs. Therefore, in situations where there are more than one high voltage circuit on the same chip, the path setting must use a semi-automatic method.

Therefore, an object of the present invention is to provide a designing method for all mounted chip elements on a memory in order to avoid the difficulty that the path setting cannot be fully automated by a hard macro.

[Means for Solving the Problems]

In order to achieve the above object, the present invention provides a designing method for all mounted chip elements on a memory. This method divides the devices in the hard macro into devices with transistor levels for automated design. In situations where there is more than one high-voltage circuit, given multiple bypass circuit by automatic placement and path setting tools such as V _SS and V _DD, where V _SS and V _DD are two power supply that can be recognized by the software Is. These power supply circuits can be used as path setting signal circuits, and as a result, the task of performing automatic path setting on all elements in the hard macro can be achieved. In other words, the logic gate level and transistor level portions can be automatically routed by using an automatic placement and routing tool.

A method of designing all mounted chip elements on a memory according to the present invention verilo the basic design in the above hard macro.
After converting to a format such as g (Logic Simulator) or EDIF, it then integrates it into other parts (such as the logical part) other than hard macros. After integration, full chip layout and routing design, and post-full chip layout compositing are processed so that full chip automatic placement and routing can be achieved.

In the present invention, the automatic route setting method uses the cell-based automatic route setting method.
-Type metal oxide semiconductor (NMOS) transistor, P-type metal oxide semiconductor (PMOS) transistor, and NMOS
It applies to high voltage devices such as inverters consisting of transistors and PMOS transistors.

In the present invention, an NMOS transistor,
The size of the PMOS transistor, and the total inverter, is defined as an integer multiple of the standard cell (depending on software it may also be a non-integer multiple of the standard cell), and routing is implemented on these devices. Multiple bypass circuits are also provided as V _SS and V _DD , where V _SS and V _DD are the two power supplies recognizable by software, and their well contacts are used as signal circuits for routing.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 shows a design flow chart for a fully mounted chip element on a memory of a preferred embodiment according to the present invention. In this embodiment, the design flow of all mounted chip elements on the memory is as follows: basic design 300, basic design verilo
g (logic simulator), that is, conversion to EDIF format 302, high-level hardware description language program 304, synthesis 306, integrated full-chip chiplist 30
8, full-chip placement and routing basic design 310, post-full-chip layout synthesis 312, and tape output 314 steps. The design sequence is shown in the drawing.

The hard macro is generally composed of a pulse generator, a capacitor, a resistor, a transistor, and a high voltage element. These devices could not be synthesized in the prior art. However, the present invention uses automatic placement and routing tools to perform automatic routing on logic gate level portions, transistor level portions, and other non-synthesizable circuit portions simultaneously. In other words, the hard macro is divided into a number of devices with transistor levels to implement the automated design of step 300 of this embodiment. The other non-synthesizable circuit parts are designed in the same manner, and the details will be described below.

Cell-based automatic routing is used for routing in situations where there are more than one high voltage circuit on the same chip. This example is based on Avanti Cor
p. Apollo software developed by Cadence Corp. Developed by S
Providing multiple bypass circuits such as V _SS and V _DD (V _SS and V _DD are two power supplies that can be recognized by the software) by using automatic routing software such as E software, and routing By using these two or more high voltage circuits as the signal circuits for use, as a result, it is possible to achieve the task of performing automatic path setting on all the elements in the hard macro. Using more than one high voltage circuit as the path setting signal circuit not only improves the bottleneck that the automatic placement and path setting tool can only recognize two high voltage circuits, but also each Automatic path setting on the device is also performed.
Although the above description uses Apollo software, or SE software as an example, the present invention is not limited to using this software alone.

A method of designing all chip elements on a memory of the present invention verilo the basic design in the above hard macro.
After converting to a format such as g (Logic Simulator) or EDIF, it then integrates it into other parts (such as the logical part) other than hard macros. After integration, full chip layout and routing design and post-full chip layout synthesis are processed, resulting in:
Automatic placement of all chips and path setting can be achieved.

Further, the input capacitance (input C) of the pulse generator, the capacitor, the resistor, the hard macro transistor and the high voltage element, the fan-out load, the maximum capacitance,
And the timing information is recorded in all .lib files.

FIG. 4 is a flowchart showing a multi-power supply type NMOS transistor on an N-type substrate in a fully mounted chip element on a memory according to a preferred embodiment of the present invention. N-type substrate 400 has P-well 402 therein.
In the P well 402 near the surface of the substrate 400, there are source / drain 404 and well contacts 406. N
The mold substrate 400 also has a gate 408 thereon.

The multiple bypass circuits 410, 412 have Av
anti Corp. Developed by Apollo
Software, or Cadence Corp. It is provided within the PR boundary 401 by using an automatic placement and path setting tool (APR tool) such as SE software developed by. Circuits 410, 412
Are connected to voltages such as V _DD and V _SS , respectively, where V _SS and V _DD are two power supplies recognizable by software, and the high voltage circuit is used as a path setting signal circuit 414. Here, the signal circuit 414
Is electrically connected to the well contact 406 via the insertion stub 415 and to the voltage V _DP , so that
The task of performing automatic path setting on all elements in the hard macro can be achieved.

FIG. 5 is a flow chart showing a multi-power supply type (or separate N well) PMOS transistor on an N type substrate in a fully mounted chip element on a memory according to a preferred embodiment of the present invention. N-type substrate 500 is P well 5
02a and deep P well 502b, and P well 5
02a and N well 518 inside deep P well 502b
There is. Here, the N well 518 near the surface of the substrate 500
Source / drain 504 and well contact 5 in
There is 06. The N-type substrate also has a gate 508 thereon.

The multiple bypass circuits 510 and 512 have Av
anti Corp. Developed by Apollo
Software, or Cadence Corp. It is provided within the PR boundary 501 by using an automatic placement and path setting tool (APR tool) such as SE software developed by. Circuits 510 and 512
Are connected to voltages such as V _DD and V _SS , respectively, where V _SS and V _DD are two power supplies recognizable by software and the high voltage circuit is used as path setting signal circuits 514, 516. Here, the signal circuit 514 is electrically connected to the P-well 502a and connected to the voltage V _DP via the insertion stub 515, and the signal circuit 516 is connected to the well contact 50 via the insertion stub 517.
6 electrically and connected to voltage V _B , so that the task of implementing automatic path setting on all elements in the hard macro can be achieved.

FIG. 6 is a flow chart showing an inverter on an N-type substrate in all mounted chip elements on a memory according to a preferred embodiment of the present invention. N-type substrate 600 is P-well 6
02a and deep P well 602b, and P well 6
02a and deep P well 602b inside N well 618
There is. Here, the P well 60 near the surface of the substrate 600
There is a source / drain 604a and a well contact 606a in 2a. P-well 602a also has a gate 608a thereon. In addition, in the N well 618 near the surface of the substrate 600, there are source / drain 604b and well contact 606b. N-well 618 also has a gate 608b thereon.

The multiple bypass circuits 610 and 612 have Av
anti Corp. Developed by Apollo
Software, or Cadence Corp. It is provided within the PR boundary 601 by using an automatic placement and path setting tool (APR tool) such as SE software developed by. Circuits 610 and 612
Are connected to voltages such as V _DD and V _SS , respectively, where V _SS and V _DD are two power supplies recognizable by software, and the high voltage circuit is used as the path setting signal circuits 614, 616. Here, the signal circuit 614 is electrically connected to the P-well 602a via the insertion stub 615 and connected to the voltage V _DP , and the signal circuit 616 is electrically connected to the well contact 606b via the insertion stub 617 and connected to the voltage V _B. As a result, it is possible to achieve the task of performing automatic path setting on all the elements in the hard macro.

FIG. 7 is a flowchart showing a single power supply type NMOS transistor on an N-type substrate in a fully mounted chip device on a memory according to a preferred embodiment of the present invention.
N-type substrate 700 has P-well 702, and the distribution area of P-well 702 is shown in the drawing. Board 700
In the P well 702 near the surface of the NMOS transistor 708.

The multiple bypass circuits 704 and 706 have Av
anti Corp. Developed by Apollo
Software, or Cadence Corp. It is provided within the PR boundary 701 by using an automatic placement and path setting tool (APR tool) such as SE software developed by. Circuits 704 and 706
Is placed at the end of the PR boundary 701 and the circuit 704 has a voltage V
Connected to _SS , circuit 706 is placed on P-well 702 and electrically connected to voltage V _DD . Above V _SS and V
_DD is two power supplies that can be recognized by software.

FIG. 8 is a flow chart showing a single power supply type (or shared N well) PMOS transistor on an N type substrate in a fully mounted chip element on a memory according to a preferred embodiment of the present invention. N-type substrate 800 is P-well 80
2, and the distribution area of P-well 802 is shown in the drawing. The PMOS transistor 808 is provided in the area other than the distribution area of the P well 802 near the surface of the substrate 800.
There is.

The multiple bypass circuits 804 and 806 have Av
anti Corp. Developed by Apollo
Software, or Cadence Corp. It is provided within the PR boundary 801 by using an automatic placement and path setting tool (APR tool) such as SE software developed by. Circuits 804 and 806
Is placed at the end of the PR boundary 801 and the circuit 804 has a voltage V
Connected to _SS , circuit 806 is placed on P-well 802 and electrically connected to voltage V _DD . Above V _SS and V
_DD is two power supplies that can be recognized by software.

The above embodiment is a PMOS as an example for explanation.
Only transistors, NMOS transistors, and inverters on N-type substrates are used, but the invention is not limited to using those of these devices. The present invention is also applicable to the design of devices on P-type substrates.

[0030]

In summary, the method for designing a fully mounted chip device on a memory according to the present invention has at least the following advantages. That is, 1. The method for designing all chip elements on a memory according to the present invention divides a hard macro into a large number of elements having transistor levels for automatic path setting, and as a result, the hard macro cannot independently perform automatic path setting. , Bottleneck is improved. 2. The method of designing all chip elements on the memory according to the present invention, after providing the circuits as V _SS and V _DD , further removes the limitation that the automatic placement and routing tool can recognize only two power supplies. To do this, the high voltage circuit is used as a signal circuit for path setting. 3. The method of designing all chip elements on a memory according to the present invention uses an automatic placement and path setting tool to simultaneously perform automatic path setting on a logic gate level portion, a transistor level portion, and other non-synthesizable circuit portions. As a result, the time for designing the device can be considerably reduced.

Although the present invention has been described with reference to particular embodiments thereof, it is normal in the art that modifications to the described embodiments can be made without departing from the spirit of the invention. Is clear to the parties. The scope of the invention is therefore defined by the appended claims rather than by the above detailed description.

The accompanying drawings are included to provide a thorough understanding of the present invention, and are incorporated in and constitute a part of the present invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawing,

[Brief description of drawings]

FIG. 1A shows a flowchart of a conventional memory design.

FIG. 1B shows a flowchart of a conventional logic design.

FIG. 2 shows a flowchart of a conventional memory design.

FIG. 3 shows a flow chart of a design for a fully mounted chip element on a memory according to a preferred embodiment of the present invention.

FIG. 4 is a flowchart showing a multi-power supply type NMOS transistor on an N-type substrate in a fully mounted chip device on a memory according to a preferred embodiment of the present invention.

FIG. 5 is a flowchart showing a multi-power supply type PMOS transistor on an N-type substrate in a fully mounted chip device on a memory according to a preferred embodiment of the present invention.

FIG. 6 is a flowchart showing an inverter on an N-type substrate in all mounted chip elements on a memory according to a preferred embodiment of the present invention.

FIG. 7 is a single power supply type N on an N type substrate in a fully mounted chip device on a memory according to a preferred embodiment of the present invention.
The MOS transistor is shown in the flowchart.

FIG. 8 is a single power supply type P on an N type substrate in a fully mounted chip element on a memory according to a preferred embodiment of the present invention.
The MOS transistor is shown in the flowchart. .

Continued front page    F-term (reference) 5B025 AD09 AD15 AE00                 5F064 BB21 CC01 CC21 CC22 CC23                       DD02 EE02 EE52 HH01 HH06                       HH08 HH09                 5J056 AA00 BB59 CC03 EE00 HH03                       KK00 KK02

Claims (3)

[Claims] 1. Automatic route setting on logic gate level portions, transistor level portions, and other non-synthesizable circuit portions by providing at least automatic place and route setting software. And to integrate the routing on the logic gate level portion, the transistor level portion, and other non-synthesizable circuit portions to implement the full chip automatic routing problem. Design method for all chip elements on memory. 2. Automatic route setting on logic gate level portions, transistor level portions, and other non-synthesizable circuit portions by at least providing automatic placement and route setting software. And integrating routing on logic gate level portions, transistor level portions, and other non-synthesizable circuit portions to achieve the task of full-chip automatic routing. Design method for all chip elements on analog circuit. 3. An automatic path setting method for a cell body suitable for performing an automatic path setting on an element having a plurality of power supply circuits, wherein automatic placement and path setting software is provided, and V _SS and V _DD are provided. Providing multiple bypass power supply nodes, where V _SS and V _DD are the power supplies that can be recognized by the automatic placement and routing tool, and multiple power supply circuits for automatic routing in the automatic placement and routing software. And assigning it as a signal circuit of.