JP2003514296A - Method of dynamically adjusting operating parameters of a processor according to its environment - Google Patents

Abstract

(57) Abstract When a computer system detects a change in one of a plurality of operating characteristics, the system stops the core clock running on the processor. In response to the detected change, updated frequency control information is provided to the clock control logic, and in response to the change, updated voltage control information is provided to the voltage control circuit. Once the updated information is provided, the system restarts the clock and the processor at a second clock frequency corresponding to the updated frequency control information and at a second voltage corresponding to the updated voltage control information. To work.

Description

Detailed Description of the Invention

[0001]

【Technical field】

The present invention relates to portable computers and their associated performance and thermal issues.

[0002]

[Background technology]

Conventional notebook computers operate at lower performance levels than comparable desktop computers due to power and thermal constraints. When using a battery as a power source, conventional notebook computers can often use battery life-saving techniques to reduce performance levels. In addition, conventional notebook computers have a small and tightly packed system structure that limits the safe dissipation of heat generated by computer operations. Therefore, conventional notebook computers typically use less power than desktop computers, which has a negative impact on performance.

Many power saving techniques have been introduced in an attempt to mitigate the limitations caused by thermal and battery power constraints. The operating frequency (clock frequency) of the processor and its operating voltage determine its power consumption. Since power consumption and therefore heat production are approximately proportional to the operating frequency of the processor, keeping the processor frequency below the desktop performance level is a common way to stay within the power limits of notebook computers. It was

A common power management technique called "throttling" prevents the processor from overheating by temporarily stopping processor operation by stopping the processor clock. Throttling lowers the effective frequency of processor operation and also provides clock control signals (eg, the processor's STPCLK # input).
Is a standard method in the industry for correspondingly reducing processor power consumption and modulating the duty cycle of processor operation. A temperature sensor placed on or near the processor initiates throttling when needed.
Throttling continues to stop or start processor operation according to a predefined duty cycle with a period of a few milliseconds. Reducing the effective speed of the processor reduces power consumption and therefore processor temperature.

Applications such as word processors typically leave the processor idle most of the time. As a result, typical processor power consumption when running word processing applications can be 30-50% lower than maximum. Additional power savings can be achieved by the computer system taking advantage of its idle time to put the processor to sleep temporarily.

For example, in a word processing application, the processor performs a chunk of work shortly after each character is typed, but then the operation stops until the next keystroke. In addition, peripherals may be turned off for additional power savings. For example, a notebook hard drive may be suspended after a period of inactivity until it is next needed. A few minutes, for example
If the system detects another period of inactivity, the display may be turned off. Such techniques are useful in conserving battery power and, in the case of processors, in reducing the amount of heat that must be dissipated. Also often done is
A cooling fan is used to increase the amount of heat removed from the system, lower the processor temperature and prevent system damage.

A typical notebook computer consumes about 15 to 20 watts when power management is active and running on its battery. The power consumption of the processor part is typically 8-12 watts. The remaining power consumption is provided to the display, hard drive, memory subsystem, graphics controller and other peripherals. For a 40 to 50 watt / hour battery pack, the notebook will run for 2.5 to 3.5 hours. In contrast, typical desktop processors, which do not have the power and thermal constraints of the Nodebook processors, consume 20-30 watts.

However, when plugging a notebook computer into an AC line power source, sufficient power is available, auxiliary cooling capacity is available, and more heat can be removed from the processor. This allows the processor to operate at a performance level close to that of a desktop processor. In such an environment, the entire notebook system would remain fully operational even if all power management features were disabled. Notebook total power consumption and losses can increase to about 20 to 30 watts.

Proper monitoring and control of processor operating parameters is important for optimizing notebook performance and battery life. Power management in older personal computer systems was typically accomplished using the exclusive use of system management interrupts (SMI) and / or microcomputers. Current x86 based computer systems leverage industry supported power management strategies. This is Intel, November 19, 1998
, Microsoft and Toshiba, ACPI (Advanced Config
uration and Power Interface Specification) Revision 1.0a. ACPI is an operating system (OS) controlled power management mechanism that uses features built into Windows® 9x and Windows® NT or other compatible operating systems. This is all ACP
It defines a standard interrupt (system control interrupt or SCI) that handles I events.
A system control interrupt is generated by the device notifying the OS about system events.

As part of its power management strategy, ACPI describes sleep and suspend states. The sleep state temporarily halts processor operation, but operation can be restored in a few milliseconds. The notebook goes to sleep when the internal activity monitor indicates that nothing is happening. When a key is typed, the mouse is moved, or data is received via the modem, the processor starts working.

The suspend state may shut down more subsystems (eg, a display or hard drive) and take several seconds to restore operation. The Suspend state either copies the system's current context (enough for the computer to resume processing currently open applications) to memory (suspend to RAM) or to the hard drive. You can copy (suspend to disk) and power down your peripherals.

ACPI defines the standard power states of the system and the power states of individual components. In addition, it defines a standard way of putting systems and devices into different power modes and has features that allow for reporting of events, monitoring and controlling temperature in the system and monitoring of batteries. ACPI power management includes a number of system power states for notebook PC operation. The Gx state indicates the overall operational status of the system. The Cx processor state, Dx device state and Sx sleep state define sleep states such as suspend-to-ram and suspend-to-disk and subsystem status. Four global Gx states are shown in FIG. 1A.

When the computer is operating in the G0 state, the CPU is 4 shown in FIG. 1B.
It may have one computing state. Note that it may not be necessary to support all CPU states on a given platform. For example, C1 and C2 in some systems may provide the same power loss and latency due to restoration of operation. Therefore, the designer need only choose to achieve one of these states. Also, different systems may have different implementations of particular CPU states. Unlike sleep states, where various parts of a computer system may be powered down, all systems remain powered on in the computing state.

When the computer is in the G1 state (sleeping), the system is in one of the four sleep states shown in FIG. 1C. Similar to the Cx state, some sleep states will not behave very differently for a given design. Therefore, it may be appropriate for a particular system not to implement one or more of the states.

As can be seen, the ACPI environment provides a number of mechanisms to deal with thermal and power issues. However, if notebook performance is desired to approach a desktop computer, then it is necessary for the processor to run faster and dissipate more heat. However, notebooks still have to operate in a mobile environment, limited by power and heat constraints. Therefore, it would be desirable if a notebook could easily adapt to its environment and provide an appropriate level of performance in a given operating environment. Although ACPI and current power management techniques provide some level of monitoring and control based on the operating environment of the notebook computer, there are improved power management techniques that respond more effectively to the environment in which the notebook computer is used. Need to provide. Moreover, it would be desirable to dynamically adapt to the requirements of different environments without significantly impacting the user.

[0016]

DISCLOSURE OF THE INVENTION

Therefore, a notebook or similar computing device may have the availability of an external power source (AC adapter, auto-adapter or other external power source), attachment and / or activation of an auxiliary cooling device, and performance during battery operation. Monitor the system environment, such as profiles that may be user definable to select criteria. When changes in any of these factors occur, system level software assigns the appropriate operating parameters or "run state" to the processor of the computing device.

Each run state has different limits on available power and power consumption, but situations can change during notebook use. Ideally, in each run state, the processor makes full use of available power and power consumption caps. To change the run state, the system changes the processor's core clock frequency and core voltage. Since the processor frequency determines the minimum required voltage for operation, the operating frequency and voltage for the processor core are changed at the same time. When the core frequency changes, so does the core voltage.

In one embodiment, a method for controlling power consumption of an integrated circuit in an electronic system is provided. The method includes operating the integrated circuit at a first voltage and a first frequency. When the system detects a change in at least one of the plurality of operating characteristics in the electronic system, in response to detecting the change, the system stops the clock running on at least a substantial portion of the integrated circuit. The updated frequency control information is provided to the clock control logic in response to the detected change, and the updated voltage control information is provided to the voltage control circuit in response to the change. Once the updated information is provided, the system restarts the clock and integrates at the second clock frequency corresponding to the updated frequency control information and at the second voltage corresponding to the updated voltage control information. Operate the circuit.

Another embodiment provides a computer system that includes an integrated circuit having a first logic portion coupled to receive a first clock and a first voltage. The programmable voltage regulator circuit provides a variable voltage level for the first voltage according to a voltage control signal provided to the voltage regulator circuit. The clock control circuit generates the first clock at a frequency determined according to the frequency control signal. The control circuit receives an indication of changes in a plurality of operating characteristics in the computer system. The control circuit responds to a change in one of the operating characteristics by providing an updated voltage control signal and frequency control signal indicating a new voltage value of the first voltage and a new frequency of the first clock. . The new voltage value and the new frequency correspond to the detected change in the operating characteristic.

The present invention may be better understood by those skilled in the art by referring to the accompanying drawings,
Its numerous purposes, features and advantages will also be apparent.

[0021]   The use of the same reference symbols in different drawings indicates similar or identical items.

[0022]

[Modes for Carrying Out the Invention]

A notebook computer or other portable computing device according to one embodiment of the present invention dynamically adapts the operation of the notebook computer and its processor to changes in its environment to provide improved performance and battery life. I will provide a. To determine these changes, the notebook computer applies or removes an external power source (AC adapter, auto-adapter or other external power source), changes in the thermal environment (auxiliary cooling device embedded in the AC adapter, port). User-definable profile changes for battery operation (such as replicators, docking stations, or other wearable devices with cooling capacity in a notebook that can be used due to the availability of an external power source) (eg, , Performance or maximizing battery life) etc.

Upon detecting any change in those or other parameters, the notebook computer changes by inputting the appropriate run mode that sets the operating frequency, operating voltage, power consumption and power consumption capability of the processor. Conforms to. This can be accomplished by generating an interrupt upon detecting a change in the parameter. Interrupts execute system-level software that assigns appropriate operating parameters for various run modes of a computing device.
Preferably, the notebook computer dynamically makes the appropriate changes without the user having to leave the application program or system software.

The various run modes reflect the different environments in which the notebook has to operate. For example, in some environments, such as running on battery power, battery life may be more important than performance. However, performance is probably more important while playing a video clip. Battery life is not an issue when plugged into an AC adapter or auto adapter. Ideally, in each run mode, the processor fully utilizes the available power and power consumption caps.

CPU heat and power management not only involves changing the clock frequency, but also C
It is improved by changing the PU voltage. Each run mode matches the frequency and voltage of the operating parameters of the processor with performance requirements, power consumption limits and dynamic changes of power consumption limits to provide users with improved performance and battery life. Since the processor frequency determines the minimum voltage required for operation, the operating frequency and voltage for the processor core are changed simultaneously. Therefore, reducing the voltage with frequency is a very effective way to reduce the power consumption of the system's processor when the environment is constrained in terms of power or heat, or when power saving is desired. Battery life is
It is improved by minimizing the voltage applied to the CPU to ensure proper operation at the target operating frequency. In effect, this allows a minimum CPU power consumption at a given frequency of operation. The system is thus able to optimize power and frequency within certain limits. Further, thermal management is optimized for a given frequency of CPU operation.

Changing the core clock frequency of a processor has a near linear effect on the power consumed by the processor. Thus, a 20% reduction in clock frequency reduces the power consumed by the processor by 20%. The ratio of the lowest frequency to the highest frequency is typically greater than 2: 1 so the range of variation is quite large. As a result, the power of the processor may change by the same rate. The change in the core voltage of the processor has an almost square law effect. That is, potential power savings is proportional to the square of the rate of voltage reduction. The range of voltage change is generally 50%
Although smaller, if the core voltage of the processor is reduced, the power of the processor will change significantly due to the square effect. It should be noted that high performance processors typically receive multiple voltages, including a voltage for the I / O region and a voltage for the core logic region, and the I / O region is typically used to drive signals out of the chip. The core logic voltage is typically less than that required in the I / O region in order to require a sufficiently high voltage.

Referring to FIG. 2, a state machine is illustrated that implements various run modes to allow the processor to dynamically adapt to its environment. Since it is desirable for a notebook to operate at the performance of a desktop computer, run mode 3 (11) will provide maximum system performance (clock frequency and heat dissipation) when docked, for example, to a docking station that provides auxiliary power and cooling. )give. It requires that the docking station force air through the heat sink of the processor or otherwise conduct heat away from the processor and far away from the processor using, for example, a heat pipe or heat plate. I would like to install a proper cooling system. Heat pipes can also be used to conduct heat into a docking station that uses heat sinks and fans to dissipate the heat.

Once the system is undocked, the system can enter either Run Mode 1 (13) or Run Mode 0 (15). When operating on battery (run mode 0 or 1), the user can choose between power saving and performance. Run mode 1 is a performance mode that maintains processor speed, which may require as high and active cooling as run mode 2. Its high level of performance reduces battery life as a result of increased power consumption due to the processor and the need to move cooling devices such as fans to help dissipate the heat. In the performance / battery operating mode, performance is limited by active cooling limitations.

Alternatively, in Run Mode 0, or Battery Saver Mode, battery life is more important than performance. In maximum battery life mode, or run mode 0, the passive cooling limitation provides an upper performance limit.
The cap may be higher than actual performance because it is desired to extend battery life by keeping the power consumption by the processor below the performance cap. The ability to operate in battery saver mode (run mode 0) without active cooling depends on low power consumption in the stop clock / grant state that shuts down the processor core clock. Otherwise, active cooling must consume power.

Further, at least one operation mode may be provided between the two extremes of the run mode 1 and the run mode 0. The "between two extremes" mode provides active cooling, but has a lower performance goal, so that active cooling may be switched on less frequently. The mode of operation favors lower processor power consumption and less frequent power consumption by cooling fans. An additional battery mode may be provided that has more granularity between the performance emphasized in run mode 1 and the battery life emphasized in run mode 0. In one implementation, the user may specify various battery operating modes through the control panel applet in the same manner as the user selects a time delay before the display or hard drive sleeps.

Run mode 2 (17) provides external power while the notebook computer is undocked (eg, from an AC adapter). Run mode 2 gives maximum performance limited by heat considerations. The performance of run mode 2 may be limited below run mode 1 due to the lack of auxiliary cooling. However, if the notebook has an active cooling device, it can continue to be used in run mode 2 without concern for power consumption. Thereby C
Allows the PU to operate at higher frequencies than Run Mode 1.

Each run mode is intended to provide maximum performance within the constraints of available cooling mechanisms and battery life requirements. FIG. 3A summarizes the various run modes illustrated in FIG. 2 along with total power consumption (TDP). Various environments can prompt or warn the user about operations. For example, a DVD movie playback program can check run mode at the start. ACPI maintains a table showing performance levels. When operating in run mode 0 (battery save mode), it is possible to generate a warning message that playback at full frame rate is not possible unless the user selects one of the other operating modes.

The computer system should only provide a small latency between run modes. The user may be able to tolerate a latency of up to, for example, 1 second, but preferably the latency should be transparent to the user.

FIG. 3B provides a table of exemplary performance parameters for various run modes. For example, in run mode 0, the CPU voltage is 1.6 volts and the CPU frequency is 200 MHz. On the other hand, Run Mode 3 is 2.2 volts and 40
It gives 0 MHz operation.

With reference to FIG. 4, this graph shows a comparison of notebook power reductions that reduce the average operating frequency by the “throttling” described so far. The vertical axis on the left is volts. The vertical axis on the right is watts. Line 41 illustrates the voltage determined as a function of frequency for a typical notebook processor. The middle line 43 shows power as a function of frequency, illustrating the power savings available from lowering frequency. As can be seen, power saving is generally linear. It should be noted that the power savings obtained from lowering the frequency are equivalent to the power savings provided by throttling. Line 45 shows power as a function of both voltage and frequency and illustrates the power savings resulting from lowering both voltage and frequency.
It should be noted that throttling may be used in combination with both voltage and frequency reduction to further reduce the effective speed or power consumption of the processor. In a typical notebook system, additional power savings at 200 MHz equates to a battery life of at least 45 minutes.

The change of run mode is controlled by software-triggered state machine logic, but once triggered, the state machine can perform its operations while the processor is sleeping. The run-mode logic may be incorporated into the power management features of the southbridge integrated circuit, or implemented elsewhere in the computer system by a separate logic device that supplements standard southbridge power management. You may. The software needed to change the run mode can be triggered by SMI or SCI features built into the standard Southbridge. The required software can enhance existing routines to put the processor into sleep or suspend mode and then resume operation.

In one embodiment, as further described herein, the processor modifies its internal bus-multiplier state and maintains or restores the state of its internal registers by chipset control. Or That feature enables multiple frequency operating modes without powering down the system or manually reconfiguring the Bus Frequency (BF) pins, as described further herein.

The sleep and suspend states require that processor activity be halted, and thus system software cannot control all sleep, suspend and recovery operations. To overcome this problem, a state machine is provided in the input / output integrated circuit (known as the South Bridge) to control the final stages of sleep and suspend and resume operations. Many notebook computers use state machines in southbridge integrated circuits to provide general power management features. One such integrated circuit is the 82371AB PCI-TO-ISA / IDE XCELERATO available from Intel Corporation.
R (PIIX4). Power management features included therein reduce power consumption to extend battery life and control heat generation and dissipation to safely operate the processor. Most notebook PCs rely on the Southbridge to provide the hardware for heat and power management, although a separate microcontroller may be used for this task. Southbridge is one of the chipsets that also includes Northbridge. The northbridge provides the memory controller function and the bridge function between the peripheral component interconnect (PCI) bus and the host bus connected to the processor. The Southbridge also interfaces with the PCI bus (which acts as the main input / output bus in the computer system) and interfaces with legacy devices on the ISA bus (or integrated into the Southbridge) and various Interface to other input / output buses and / or functions such as universal serial bus (U
SB)) and providing various power management related functions as well. Southbridge chips from various manufacturers have typically utilized the register, timer and state machine definitions used in the Intel PIIX4 Southbridge. The current Southbridge chip's PIIX4 compatibility is extensible to support the mobile modes of operation described herein.

In the exemplary embodiment illustrated in FIG. 5, voltage regulator 501 is (x86
In a processor environment, commonly referred to as V _CC2 ) core voltage 502
CPU) 503. In the illustrated embodiment, the south bridge 505 is
By supplying the voltage control signal VID [4: 0] to the voltage regulator 501, the voltage level supplied to the CPU 503 is controlled. To control the processor frequency, in one typical implementation, such as that used in AMD-K6® processors, three bus frequency input pins (BF [2: 0]) are used inside the processor. Determine the operating frequency. The south bridge 505 has a BF (
The operating frequency of the CPU 503 is controlled by supplying the bus frequency) signal BF [2: 0]. The bus clock signal 506 is sent from the clock generator 507 to the CPU.
503 and is internally multiplied by the CPU at a ratio determined by the values of the three bus frequency pins. In one implementation, the range of multiplication numbers ranges from 2.5 times the bus clock to 6.0 times the bus clock. Other multiplication numbers are possible depending on the particular system implementation.

FIG. 6 illustrates one implementation of the clock control circuit in the CPU. The frequency divider circuit 61 receives the BF pin, but they are the processor reset signal (CPURST
) Is asserted during the assertion of. The sampled value is provided to a phase locked loop (PLL) clock multiplier / synthesizer circuit for a period sufficient for the PLL to stabilize. The value on the BF pin is latched into divider 61 on the falling edge of the CPURST signal. The reset pulse is long enough to ensure that the clock multiplication circuit is stable. The bus clock 63 is a phase (frequency) detector 64
, The detector provides a control voltage 65 to a voltage controlled oscillator (VCO) 67.
The VCO provides the core logic of the CPU with a clock having a frequency determined by the bus clock frequency multiplied by the value determined by the BF pin. The gating logic 68 is used to allow the CPU to assert the appropriate gating signal 69.
The core clock can be gated off and the core clock stopped.

As faster processors are provided, a larger range of clock multiplier values are provided to fully support battery life mode (run mode 0), ie to ensure that the processor can move slow enough. An additional BF pin would be useful for this.

Referring again to FIG. 5, the south bridge 505 supplies the enable signal 509 to the clock generator 507 to completely disconnect the clock supplied to the CPU 505 and minimize the power consumed by the CPU. Therefore, the south bridge 505 programs the voltage regulator, controls the clock generator, manages the duty cycle for processor throttling via the STPCLK # signal 510 and controls the clock multiplier by controlling the BF pin. To do. In addition, the south bridge 505 manages the transitions between run modes by coordinating the special protocols needed to change the clock multiplier in the processor and change the core voltage. In embodiments where direct operating system (OS) support is not provided to change run modes, the transitions between run modes are preferably as transparent as possible to both the operating system and the user.

One way in which transparency can be achieved is for a system management interrupt (SMI) to be used when detecting docking or AC / battery status changes. The ACPI mechanism does not use that interrupt and is transparent to the operating system. When detecting changes, short latencies for changes up to about 1 second are acceptable, but shorter latencies are desirable. It should be noted that in some embodiments operating system support may be provided, thus reducing transparency.

As shown in FIG. 5, jumper 511 provides the clock multiplier and voltage regulator with a default state upon power-up. The South Bridge receives jumper signals on eight jumper input pins IBF [0: 2] and IV [0: 4].
The number of jumpers and jumper inputs may vary according to the particular design. The setting of the jumper 511 with the resistor 513 is controlled by the voltage regulator control pin Voltage.
Default values are given to both the ID (VID) pin and the processor clock multiplier pin (BF pin). Their default values are provided to Southbridge 505. Upon power up, the South Bridge provides default values for the VID and BF pins to the voltage regulator and CPU, respectively. However, in order to transition between the run modes described herein, the south bridge 505 according to one embodiment of the present invention, as described further herein, uses a voltage rather than a jumper input. The internal register is selected as the source of the output signal supplied to the regulator and the CPU.

In the embodiment illustrated in FIG. 5, three output bits may be used to control the clock frequency and five output bits may be used to control the CPU core voltage regulator. However, other numbers of bits may be used depending on the particular clock frequency strategy and the voltage regulator used. Furthermore, it is not necessary for a particular bit to be dedicated to a voltage or frequency control bit. Thus, if the Southbridge provides 10 inputs for jumpers and 10 outputs for clock and frequency control,
Some applications may require only three frequency control pins and five voltage control pins, while other applications may require four of each or five of each. Moreover, the input bits and outputs are not dedicated to frequency or voltage control bits. Thus, if the voltage regulator has seven control bits available, it may use seven control bits for voltage control and three bits for frequency control. This advantageously provides implementation flexibility without modification to the Southbridge. In some implementations, the processor may provide a default static VID signal, such as that shown at 514, rather than relying on jumper settings.

In order to change both the voltage and the frequency of the processor, it is necessary to stop the processor operation. That is, it is necessary to stop the processor clocks, ie, at least those clocks supplied to storage elements such as registers and latches or other circuit nodes in the time sensing path. Otherwise, unpredictable behavior can occur. In current x86 architectures this is accomplished by first asserting the STPCLK # signal to cause the CPU to stop its internal clock distribution. Upon receiving STPCLK #, the CPU completes the currently active instruction and asserts a "stop grant" indication. Once the "stop grant" is received, the clock can be stopped at clock generator 507 using enable signal 509. Advantageously, the ACPI framework provides a number of suspend and sleep operations. These can be supported and modified in the South Bridge to achieve processor suspend operation in the context required here.

The flow chart of FIG. 7 generally illustrates the operation of controlling voltage and frequency according to one embodiment of the invention. Assume that the processor is operating in the normal operating mode at 70, the voltage regulator 501 receives the appropriate voltage control signal VID [0: 4] and the frequency control circuit receives the appropriate frequency control signal (eg, BF signal). . At 71, the computer system detects changes in operating characteristics such as power supply, thermal environment, or operating parameters selected by the user. In response to detecting the change, the system stops processor operation by stopping its clock at 72 to determine the appropriate new frequency and corresponding voltage setting for the new run mode. The information may be stored in a Southbridge register or other suitable location in the computer system. The updated voltage and frequency control signals are provided at 73 and 74 to the appropriate voltage and frequency control circuitry, and the processor then resumes operation at 75.

The resume action is triggered from one of the last actions of the suspend action. One of the steps of the resume operation contemplated in connection with FIG. 7 is to issue a frequency control signal update instruction (eg, reset (CPURST)) to the processor for the resume operation. The frequency control update or valid signal indicates to the processor that valid data is present on the BF pin to be used for core clock generation. When a CPU reset is used for that purpose, the reset is provided only to the processor and not to those parts of the computer system that do not require reset.

In one implementation, the processor sets the value of the frequency control signal (on the BF pin) when the reset signal is asserted and latches to their value on the falling edge of reset (see FIG. 6). Detect. Alternatively, a signal other than reset may be asserted to indicate to the processor that a new frequency control signal value is present. If the reset signal is used to indicate that a new frequency control (BF) signal is available, the processor loses context upon asserting reset. For example, the value in the processor register may be lost. Therefore, either the processor context must be saved before issuing a reset, or the application cannot resume where it was turned off. Once the reset is complete, the processor context can be restored from any saved location by the processor operating at the new frequency and voltage settings. It is desirable to minimize the latency of resume operations and thus restore the processor context as quickly as possible.

Sleep and suspend states require stopping processor operation.
Therefore, the system software cannot directly control some management operations. To overcome this problem, Southbridge state machines control the system and suspend processor operations and other system devices. Once the system has entered sleep or suspend state, the Southbridge monitors for some possible events that will bring the system back up. When the event occurs, another state machine sequences the system and resumes operation. The same hardware and software used to provide sleep and suspend states can be utilized to switch between run modes.

As mentioned above, the STPCLK # input of the processor (the # symbol indicates that the signal is active low) is often used to temporarily suspend or save power. The processor enters the stop grant state by using the STPCLK # signal. In that state, the core clock is stopped, but some minimal logic, including clock multiplication logic, still works. The Southbridge control register (LVL2) is read to start the sequence used by the current Southbridge chip and place the socket 7 processor in the stop grant state. This asserts STPCLK #, notifying the processor that the processor clock should be stopped. The Southbridge waits for the processor to complete its current operation and issue a Stop Grant indication, thereby indicating that the processor has gated off its core clock. South Bridge (
Assert the ZZ pin (which is an option to suspend the L2 SRAM).
It is enabled by ZZ_EN in the CNTB register in the Southbridge.

Upon detecting a wake-up event, the Southbridge deasserts the ZZ pin (provided this option is enabled) and deasserts STPCLK #. While this control sequence can save considerable power while waiting for an event such as the next keystroke, the processor clock can be configured to change run modes as described herein. It may also be stopped due to a change in the associated core frequency. A variation of this sequence asserts the SLP # signal, leaving the compatible processor portion powered down.

More power can also be saved by stopping the clock supplied to the processor clock multiplication circuit to eliminate that portion of the processor that is still active, as described above. The clock at clock generator 507 may also be stopped as part of the sequence to change the run mode as described herein. To start the sequence on a PIIX4 compatible Southbridge and put the processor in a deep sleep state with the processor clock off,
Software reads the Southbridge control register (LVL3), which results in STPCLK # being asserted. Southbridge waits for a stop grant. The ZZ pin is optionally asserted to suspend the L2 SRAM. It is enabled by ZZ_EN in the CNTB register. Next, SLP # is asserted. SUS_STAT1 # is asserted to Northbridge to put the system memory in auto-refresh mode. CPU_STP (enable 509 in FIG. 5) is asserted to disable the clock synthesizer (clock generator 507) output for the CPU bus clock.

When a wakeup event is detected, the south bridge first makes a CPU_STP.
To enable the CPU synthesizer CPU bus clock output. The Southbridge timer (known in the industry as the "Fast Burn Timer") then counts down to give the CPU PLL time to lock. It should be noted that the value used by the timer is the CLK_L set by the BIOS during the system power-on self-test (POST) sequence.
It is to be loaded from the CK register. Finally, SUS_STAT1 #, S
LP #, ZZ pin (if this option is enabled) and ST
PCLK # is deasserted.

The sleep state machine uses the S in the power management control register of the south bridge.
Setting US_EN (bit 13) and the appropriate value (bit [12: 1
0]) can be loaded to perform the more complex operations required to suspend the system. The value indicates the type of suspend / resume operation desired. Table 1 below details the types of suspend / resume operations available and their associated values in the power management control registers in the Southbridge. The restart latency is different depending on the type of suspend operation. For example, suspend to
Disk restart latencies are typically less than 30 seconds, and suspend to
It is about 1 second for Ram and about 20 ms for Power On Suspend where context is maintained. It is clear that maintaining context reduces restart latency.

[0056]

[Table 1]

As mentioned above, by asserting a reset to notify the processor of changes in the BF signal value and making a change in clock frequency associated with a change in run mode,
Lost processor context. One of the suspend operations to restore the CPU context is the powered on suspend, CPU context non-hold (POSCCL) shown above. Reset may take advantage of that suspend operation when latching the new BF pin value as illustrated in FIG.

Referring to FIG. 8 illustrating the use of POSCCL in one embodiment of the present invention,
Once a new operating environment is detected, ie, a new run mode is desired, the new voltage and frequency settings are loaded into the appropriate registers at 801. The registers may be in the south bridge or in additional logic or in any other suitable location in the computer system. Examples of when in further logic are described below. Once those registers are loaded, 80
At 3, the processor context is saved and the restart operation is set up by specifying the restart address. Saving the processor context may include clearing the processor's internal cache and saving the processor state in DRAM. The jump setup requires setting the startup vector address (real mode) and setting the required flag bytes, so the BIOS immediately branches to a routine restore after CPU reset instead of rebooting the system. To do. The x86 processor always starts execution in the address range F000: FFF0 after reset. In a conventional x86 personal computer system, the BIOS ROM is in that address range. The BIOS checks the flag byte in RAM and
See if S should branch to execute special code (such as restoring processor context or doing a cold boot).

After saving the processor context, the software then, at 805, triggers the Southbridge state machine that suspends the processor by reading the registers in the Southbridge. The last action of the suspend state machine triggers new run mode logic that can be implemented as a state machine. The new run mode logic updates the voltage and frequency control signals provided to the frequency control logic in the voltage regulator and CPU, respectively, with the new voltage and frequency control settings, and then at 809, a wake-up instruction. Give and trigger the resume state machine. It should be noted that the voltage supplied to the core logic is changed while the core clock is off, which reduces the risk of undesired effects of voltage changes. Alternatively or additionally, the core voltage may be changed while the processor is being reset, as further described herein. Although it is not necessary to reset the processor when the core voltage changes, it is desirable to not allow the processor to operate until the core voltage has settled to a new value. The resume state machine issues a reset signal to the processor to provide the new frequency value to the clock multiplication logic. After 813, for example, about 1 ms or less, sufficient time to synchronize the processor's phase-locked loop (PLL), the resume state machine releases reset at 813. Then, at 815, C
The PU begins execution and jumps to the POSCCL resume routine that previously set up the address and restores the CPU context. The processor then points to the POS
Other than by the time the CCL is executed, processing can resume where it was turned off without affecting the application used at the time of the run mode change.

Referring to FIG. 9A, a timing diagram illustrates the operation of the Southbridge for POSCCL suspend and corresponding resume operations. The transition from the on state to the suspend state is shown on the left side of FIG. 9A, and the transition from the suspend state to the on state is shown on the right side of FIG. 9A. Once the processor enters the POSCCL sleep state, RTC alarm, SMBus event, serial port, ring indicator, system soft power button, external SMI (EXTSMI), system lid lift, global standby timer alarm, USB activity, It may be waked up by an event such as IRQ [1,3: 15] or assertion of general purpose input 1 (GPI1). In one embodiment described herein, a general purpose input to the Southbridge is used as a trigger event to wake up the processor. The signals shown in FIG. 9A are described in FIG. 9B. Some of the signals listed in FIG. 9B may be provided as general-purpose outputs (or may not be used in certain notebook PC designs).

Programmable Logic Device Implementations Before describing further details of various southbridge implementations that may be used in the system illustrated in FIG. 5, another approach that provides a short-term solution is described. In that measure, a PIIX4 compatible south bridge is a programmable logic device (PL).
Along with logic devices such as D), provide the required signals to the processor's (BF pin) frequency control input to reprogram the core voltage power supply according to the requirements of various run modes. The programmable logic device may be a programmable array logic (PAL) device or a programmable logic array (PLA) or other suitable logic device.

Referring to FIG. 10, programmable logic device 101 receives a value from jumper 511 and sends 5 out of 8 output bits to CPU core voltage regulator 501.
The three frequency control bits BF [2: 0] are given to the CPU 503. These bits control the processor frequency logic on voltage regulator 501 and CPU 503, respectively. In addition, the south bridge 103 provides some control signals to the programmable logic device 101, as described further herein.
Receive a wake signal from it. The PLD shown in FIG. 10 enables implementation of the run mode transitions described herein without requiring design changes to other system components.

It should be noted that, if desired, the bits provided for voltage and frequency control may be loaded with more bits depending on the need for the voltage regulator and the frequency range of operation desired. By giving control and less bits to voltage control, they can be assigned differently. Indeed, less than all available bits may be used for voltage and / or frequency. For example, a typical processor, such as the AMD-K6 processor, requires only 3 bits for frequency setting. Programmable voltage regulator
Available with 4 or 5 bit control. In many applications, not all ranges of voltage regulators and their precision are required, and some control inputs to the regulator may be tied high or low. Thus, the strategies herein provide flexibility by allowing different numbers of voltage and frequency control signals to be used, based on the needs of the particular system.

Referring to FIG. 11, one implementation of programmable logic device 101 is shown in more detail. In the illustrated implementation, there are 13 inputs and 9 outputs,
The design can be implemented in a standard programmable array logic (PAL) device. The signal generated from the South Bridge is a real time clock (RTC)
It may be clocked by (32 kHz). Therefore, no high speed logic device is required.

Data-in signal 1104 and shift signal 1102 from the south bridge 103
There are eight input flip-flops 1101 connected as a serial shift register that receives The south bridge 103 has one general-purpose output (designated as GPO-X) as a shift signal supplied to the PLD 101, and the PLD 10
Another general purpose output (designated as GPO-Y) as a data-in signal to 1. PLD 101 includes eight output flip-flops 1103 that receive an input signal from selector circuit 1105. The selector circuit selects either one of the input flip-flops or one of the jumper settings (IBF [0: 3] and IV [0: 3]). At the time of power-on reset, the flip-flop outputs the power OK (
PWROK) 1107 is held in reset until asserted. PWR
South Bridge 103 issues a reset to the processor while OK 1107 is asserted.

It should be noted that if a system reset is generated by pressing the reset button or by software or by any other mechanism, the jumper settings represent the default values of the voltage and frequency control signals to the frequency and voltage control signals. It has to be reapplied to the circuit. Therefore, 110
The state of the GPO bit used to drive the data at 4 defaults to a logic 0 if that bit is also used as the select signal for select logic 1105 as shown in the exemplary embodiment shown. Must be. 110
If the data in 4 is 0 for system reset, it ensures that the default value from the jumper setting is properly selected by the select logic 1105. In some implementations, only a few of the bits of the PIIX4-compatible Southbridge have this property (eg GPO [27: 28,30]), so the GPO-X and GPO-Y bits are therefore It is selected from among those bits. The use of one of those bits ensures that the startup jumper settings communicate with the voltage regulator and the BF pin of the processor during the reset of the illustrated implementation. Other implementations will be readily apparent to those skilled in the art. Using the data-in signal 207 as a multiplexer select minimizes the number of GPO pins required. However, an additional GPO signal from the Southbridge can be used to provide the multiplexer select signal.

When the system first boots, the rising edge of the CPURST signal causes
Default or startup voltage and frequency settings are output registers 1103
To the voltage regulator 501 and the CPU 503. Loading the output register immediately sets the voltage regulator to its initial value. The default frequency setting is also output. CPURST causes the processor to load its BF pin input and set the initial bus clock multiplier to generate the CPU core clock.

Once the notebook system detects the need to transition to a new run mode and before executing the suspend / resume sequence to change the processor voltage and bus clock multiplier, the GPO bit on the southbridge is set. It is used to load a new value into the data input register 1101. Referring to FIG. 12, the setup for the transition sequence occurs at 121, at which time shift signal 1102 is used to shift the new voltage and frequency settings on data-in signal line 1104 to input register 1101. Once that set up is complete, a suspend operation is performed, including the steps of saving the processor context and asserting STPCLK # and SLP #, as shown in FIG.

As mentioned above, the GPO bit 1104 used to input data into the shift register also operates the multiplexer 1105. The multiplexer is operated by keeping the bit high during the suspend / resume sequence to provide the output of the shift register to the input of the output register 1103 instead of the jumper. Serial data is written to the logical device that writes to the appropriate GPIO port.

Once the core voltage and frequency are changed in the input register 1101, the south bridge is allowed to perform POSCCL operation. With this, South Bridge
A signal indicating that the suspend operation is completed or is almost completed is supplied. It is an SLP # signal, as shown in FIG. 12, but other signals can be used. The signal indicates the end of the suspend sequence and trigger (TG
#) 1109 is given to PLD 101. In this particular implementation, TG #
Is active low. PLD 101 generates an event that resumes operation, ie wakes up the processor, by logically combining the trigger signal with data input 1107 at gate 1111. It is used as a wake event (active low) to gate SLP # to southbridge input GP11 #. It is detected as a wakeup event, resulting in a standard POSCCL resume operation. As mentioned above, this is useful in setting a new processor frequency multiplier because it repeats the reset of the processor. Therefore, as shown in FIG. 12, the end of the suspend operation results in a wake event. This in turn causes the restart sequence illustrated in FIG. Once the restart sequence is complete, the GPO signal 1107 used as a data input is driven low.

By asserting CPURST during the restart sequence, input register 1101
The value from is loaded into the output register 1103. The value in output register 1103 provides the new frequency multiplier setting and core voltage setting to the processor and voltage regulator, respectively. Therefore, the new voltage setting is provided to the core logic of the processor while CPU reset is asserted. New frequency multiplier ratio BF
The pin settings are sampled by the CPU on the rising edge of CPURST and latched into the processor on the falling edge of CPURST. The POSCCL restart gives time to resynchronize the processor PLL.

The use of PLDs allows unmodified southbridges and processors to be used in notebook systems that can transition between run modes.

If it is desired to keep the run mode transition logic and software as simple as possible, it is recommended that the bus clock frequency does not change between 66 MHz and 100 MHz during the change. Conventionally, the BF setting is in 1 / 2x increments (for example, 2x
, 2.5x, 3x, 3.5x, etc.) it limits the granularity of the stages of the processor clock frequency. Such changes are feasible if greater complexity can be accommodated. Changing the frequency of the bus clock is
Peripheral device interconnect (PCI) and accelerated graphics port (
AGP) affects the divider ratio used to generate the clock. It may be necessary to put the memory to sleep or power it down when changing the clock ratio.

The implementations described herein are National Semiconductors whose output voltage (including any external device) can be controlled by chipset logic.
or) variable voltage regulator supply such as LM4130. The voltage regulator supports at least 4 control bits and the output voltage is 1.45 to 2
． It is desirable to be able to control in a 50 mV (or less) step, covering a minimum range of 2 volts. A wider range may be desirable for some applications. The control pin of the voltage regulator should be configured for default operation at mode 0 (battery saver) voltage level during start-up. The chipset or other suitable logic then regulates the CPU voltage supply for the correct run mode once the system is operating.

South Bridge Implementation To provide an implementation that minimizes the number of components needed to change the run mode as described herein, rather than utilizing an external logic device, a south bridge implementation is provided. The bridge can be modified to provide the logic needed to transition between the various run modes. A high level implementation of such a system is illustrated in FIG.

One approach to the Southbridge implementation is to incorporate the logic contained in the PLD into the Southbridge. However, the various signals needed to interface the south bridge to the PLD can be eliminated, thus simplifying the logic. Furthermore, the use of the data input signal as the multiplexer signal can be eliminated. In fact, the input registers are preferably loaded in parallel rather than serial, thus eliminating the need for shift signals. Once it is determined that a new run mode is needed, the registers in the southbridge are given the proper voltage and frequency settings.

In one implementation, the south bridge uses bits [12:
10] is used to define a new sleep type in the power management control register (see Table 1 above). Those bits are variously referred to as sleep type or suspend type. When the sleep enable bit (or suspend enable) is set to 1 and the sleep type bit is 110, the system causes a notebook run mode transition.

Referring to FIG. 13, run mode control register 130 provides control information necessary for transition to a new run mode. The 2-bit operation mode field 131 has a high performance (00), an AC power supply (01), a battery performance (
A status field that identifies the current run mode as either 10) or battery save mode (11). More run modes require more bits. The 5-bit core voltage field 132 defines the control bit for the new core voltage, and the 4-bit CPU clock frequency control bit 133 is the CPU.
Specifies the core frequency. Clock control in the CPU, as described herein, may be implemented as a frequency multiplier of the bus clock. The reset control bit 134 defines whether the CPU is reset during a run mode transition. In one embodiment, the CPU is reset on a run mode transition when the reset control bit is 1, and not reset when the reset control bit is 0. When resetting the CPU to change the operating core frequency, POSCCL
As described in connection with the sequence, it is necessary to provide a resume operation that saves the processor context before reset and restores the processor context after deasserting the reset signal.

In other embodiments, the processor may have an input signal separate from reset that tells the processor when to latch the clock frequency control bits. In that case, the latch mode CMD bit 135 is asserted. In that implementation, the south bridge indicates to the CPU when to latch new frequency control bits in addition to the frequency control bits (BF [0: 2]).
) 515 (see FIG. 5). When the frequency latch control signal CMD515 is asserted, the BF pin setting is acquired when the CMD515 signal is asserted, and the CM
It may be latched on the falling edge of D515. Other implementations are of course possible to obtain the BF pin setting based on the latch control signal CMD. Latch control signal CMD5
The use of the 15 signal provides the advantage of transitioning to a new run mode without having to provide a reset. This means that no processor context is lost. Therefore, the time spent for transition is POSCCL
Much less than suspend and resume operations.

If the CPU reset signal is not used to indicate a frequency change, once the need to change the run mode is detected, the software loads register 130 with the appropriate value and stops the processor clock. As mentioned above, the STPCLK # signal can be used to stop the clock on the processor. The new voltage and frequency control bits are output by the Southbridge and the frequency control latch signal CMD515 is asserted to indicate that the updated frequency control signal is available. The CPU samples the frequency control bit (BF pin) when asserting the latch control signal CMD515 and latches a new value when deasserting the signal. The hardware in the south bridge maintains the asserted latch control signal CMD515 for a sufficient length of time for the processor PLL to stabilize. Once the processor PLL stabilizes, the southbridge hardware will use STPCLK #
The signal is deasserted and the processor resumes operation unnoticed by the application or user. The transition time is 100 μ, for example.
Less than a second.

If a reset is used to indicate a frequency change, a sequence similar to the POSCCL illustrated in FIG. 9A may be used to avoid requiring changes to the processor. At this time, new control signals for voltage and frequency are provided during the second half of the power on suspend (POS) sequence and the assertion of reset at 91 in FIG. 9A.

The transition sequence from one run mode to another run mode begins when an interrupt (eg, SCI) is generated for an operating mode event. An event is the result of a notebook computer plugging into or out of a docking station, port replicator, or any other device capable of removing large amounts of heat energy from a notebook. Let's do it. Or it could be when AC power is applied or removed or when the battery is low or other event causing a change in operating mode.

Once the system management software detects the event, it programs the operating mode control register 130 with the new core voltage and the new clock frequency control bits. The software then sets the sleep type bit to 110 as well as the sleep enable bit. Special register LV in South Bridge 505
The reading of L3 starts the hardware state machine that performs the POSCCL sequence. Advantageously, the use of operating mode control register 130 may also be used in the Southbridge only implementation and the PLD implementation described above.

As an alternative to starting the modification of the run mode sequence by reading the LVL3 register, such as in a non-ACPI environment, use the write (or read) register 130 as a trigger to start the control logic and run mode. May be implemented. In such a trigger, the change of the run mode is caused by the latch control signal CMD.
Alternatively, it can be used when utilizing either of the reset signals. In such cases, the saving of the processor context, if a reset is utilized, must be completed before writing to the register. When using the latch control signal CMD 515, it may be strobed, for example, for one PCI clock to indicate that the BIF signal is valid after it has been written to register 130.

Referring again to FIG. 5, it should be noted that the Southbridge still sets the default values from jumper settings 511 to CPU 503 and voltage regulator 50.
It is necessary to be sure to give to 1. Referring to FIG. 14, this is a select signal 14 provided from control logic 144 in the same manner as the PLD implementation.
It can be achieved by providing a multiplexer 141 which selects between the control register 130 and the value of the jumper setting 511 according to 2. Control logic 14
4 also accommodates the necessary suspend and resume state machines to implement the suspend and resume sequence illustrated in FIG. 9A, for example. Multiplexer 141
Supplies the value from the jumper setting 511 to the output register 143. This selects the default jumper settings in response to a reset (eg power on reset or other hard or soft reset). Furthermore, the output register 143
Is loaded either after the clock has been stopped and before supplying either the reset or CMD signal to load the new frequency setting, or the falling edge latches the new frequency setting. For example, loaded on the rising edge of CMD reset.

Referring again to FIG. 13, control bit 136 defines whether clock generator 507 is disabled during a run mode transition. STPC from Southbridge
The LK # signal is used to disable the core CPU clock and (POSCC
It is also possible to disable the clock supplied to the CPU with a clock generator 507 (like L). The clock frequency control bits are then updated and the clock is returned to the clock generator 507. It should be noted that the clock generator 507 may be integrated with other system components. South Bridge G
It is desirable to have a clock generator with the PO control bit enabling the output. The clock generator may have multiple PLL cells to support the various clock frequencies desired in any particular design. For example, 100MHz
Or it supports CPU at 66 MHz, serial devices at 24 KHz and 48 KHz, and PCI devices at 33 MHz.

Referring to FIG. 15, a flow chart illustrates the overall operation of a southbridge incorporating hardware that causes a change in run mode. As previously described herein, upon detecting an event that causes a run mode change, such as an additional power supply becoming available, the software sets 1501 the required value in register 130. At 1503, a determination is made as to whether to set the reset control bit 134 in register 130. If set, 1504 needs to save the processor context. This determines the exact sleep type used by Southbridge. If the reset control bit 134 is not used, then the latch command bit 135 is presumed to be set and the step 1504 of saving the processor context may be skipped. Of course, only one bit need be used to indicate whether to use the reset or latch command signal.
If the access register 130 is used as a trigger to initiate a run mode change, it may be necessary to save the context prior to such access. 15
Once the processor context is saved at 04 or if reset is not used, the state machine in the Southbridge will go through the steps that affect the change of run mode.

At 1505, software performs a read of register LVL3, which starts the state machine sequence and changes the run mode. At 1507, the South Bridge asserts STPCLK #. The state machine or other suitable hardware and / or software waits for a stop grant special bus cycle to be received, which is an indication from the processor that the internal core clock has been turned off. It should be noted that the stop grant response can be made without monitoring the CPU bus cycles by simply waiting for a predetermined time which is longer than the maximum time the processor can take to reach the stop grant state. .

In any case, once the stop grant has been responded to or a predetermined time limit has been reached and a stop grant condition is assumed to exist in the processor, the stop clock bit 136 in the control register 130. Is set or not is determined. When the bit is set, at 1513, the clock output from the clock generator 507 to the CPU is the stop clock line (enable 5).
09) is used to turn off. Next, at 1515, the new voltage and frequency control settings are provided to the voltage regulator and the BF pin, respectively. In 1517,
It is determined whether the stop clock bit (enable 509) is asserted. If not asserted, at 1519, the clock generator 507 is enabled to output the clock to the CPU and allow sufficient time for the PLL to stabilize. At 1521, it is determined whether a reset is used to latch the updated frequency control value. If used, at 1523, C
Strobe the PU reset and latch the new frequency control bit. If reset is not used, the CMD signal 515 is strobed by the southbridge, causing the processor to latch the new frequency without reset. At 1527, STP
Deassert the CLK # signal. Thereby, the CPU restarts the supply of the CPU core clock. The processor then resumes execution 1529. It should be noted that
If you lost the context because you used a reset, the context is to be restored at this point. This is accomplished under software control, no longer under hardware (eg state machine) control.

The use of register 130 provides an embodiment in which either use of the reset or latch control signal CMD is selectable, and turning off the clock external to the processor is also provided. In other embodiments, the Southbridge (or other suitable integrated circuit) would not provide the option. In other words, other embodiments may always use reset or always use the latch control command signal. In addition, the run mode change sequence may always turn off the processor's external clock (not only internally) or keep such clock running at all times.

When the notebook PC uses both 66 MHz and 100 MHz bus clock frequencies, the clock generator has a plurality of PLL cells to keep the frequency required by other systems constant. The clock input could be slewed. The clock generator uses the rate of change of the CPU clock frequency as CP.
While keeping within the U jitter criterion, the CPU frequency can be slewed over a desired range to prevent the clock multiplication circuit in the processor from loosening lock.

Heat Management By adjusting the operating frequency and voltage of the processor, power consumption and heat generation and dissipation are optimized according to the environment. Furthermore, the ability to manage heat is required. ACPI has two built-in mechanisms for heat management, one passive,
The other has an active mechanism. Passive features rely on throttled down processors to produce less heat, while active features utilize cooling devices such as fans to remove heat from the processor and system. The preferred thermal sensor measures processor temperature for passive and active mechanisms. The thermal design is based on one or more thermal zones. 3 thermal thresholds for each zone
You can specify up to three.

There are two methods used today for heat monitoring. That is, the whole system monitor policy and the CPU limited monitor. The principle of all board monitors is that all voltages (
For example, CPU core, CPU I / O, 3.3V, 5V 12V, -12V
-5), means for measuring the rotation speed of the fan, the temperature of the CPU and the temperature of the substrate are provided. Devices such as the National LM78 can be used for this system monitoring strategy. National LM75 can be used for the CPU limited monitor method. LM78 is
It has an open collector output used to generate an interrupt when the temperature of the processor exceeds acceptable limits or when the temperature changes by some amount. The system management bus (SMBus) can be used to program excess temperature and temperature hysteresis values within the device. The SM bus is a slow 2-bit serial bus used to communicate with monitoring devices such as thermal sensors, chassis intrusion warning sensors and providing fan speed control. Since the traditional Southbridge has an SMBus interface, system software can talk (setup and control) to and read from (receive data from) such devices. National LM77 devices have a separate output that indicates when excess temperature or temperature is above or below a certain set point, which provides additional reliability. Should ACPI not be able to respond to the setpoint interrupt, an output indicating excessive temperature can shut down the system via hardware.

ACPI maintains a temperature set point that is compared to the processor temperature. When the temperature exceeds the set value, the processor takes action to reduce heat dissipation (passive method) or expel heat from the system (active method). The necessary registers and interfaces are typically housed in the PIIX4 Southbridge. Most new Southbridges are PIIX4 compatible. It helps reduce the effort required to adapt ACPI BIOS and operating system code for different manufacturers' chipsets.

ACPI maintains setpoints for thermal management of the processor. One is a failsafe setting that triggers a shutdown if the processor becomes too hot. The other setpoint is associated with ACPI "active" and "passive" cooling methods. Either or both methods can be incorporated into the knotbook design that incorporates the run modes described herein.

In active cooling mode, ACPI turns the cooling device on and off based on temperature reports generated by sensors placed on the heat sink of the processor or just above the processor. When the temperature sensor detects a temperature change (typically 5 ° C), it reports the new temperature to the ACPI thermal manager. The temperature is ACPI
When the limits given on the table are exceeded, the cooling system is switched on. If the temperature sensor reports that the temperature has dropped below another table value, the cooling device is switched off.

It should be noted that these thresholds are programmable, allowing the software to dynamically adjust the thresholds for optimal results. For example, once the active cooling threshold is crossed, system software may start the system fan at a slow speed to reprogram the active cooling threshold to a higher temperature. If the system temperature continues to rise, it will eventually cross the new active cooling threshold. In response, the speed of the fan can be increased,
The active cooling threshold can be reset to a higher point.

Generally, a cooling device is a small fan placed on or near the heat sink of a processor. By moving the fan, air is circulated from outside the notebook PC case, cooling the processor beyond what is possible with conduction and convection alone. Active cooling systems may be more sophisticated. When docked, an external fan in the port replicator or docking station can circulate more air. Other techniques that can be used are heat pipes,
Includes cooling devices such as large heat dissipation plates or Peltier junction elements that have been used to cool desktop processors.

The mobile system may use different active coolers and temperature setpoints in the ACPI table for each mode of operation (AC / battery and docking / undock). Active devices consume power by themselves, so it is recommended that these devices be used in somewhat limited run mode 0 or battery life mode. Active cooling is a good solution when the system is running on an external power source such as an AC line adapter, a car adapter or an airplane adapter.

In the passive cooling mode, ACPI power management dynamically reduces or increases the “speed” of the processor as needed to keep the operating temperature of the processor at a safe level. Obviously, "throttled" down the processor reduces performance, but even at some reduced speed, today's processors still give enough performance to run applications such as word processing. You can The throttling method used in most notebooks directly supported by ACPI and PIIX4 compatible Southbridges is
The average processor speed is reduced by alternately starting and stopping the processor using the processor's STPCLK # (stop clock) input.

Most throttling implementations use 3-bit granularity. The duty cycle ranges from 12.5% to 100% in 12.5% increments. (Note that 0 is an unacceptable value.) When the temperature rises to the upper limit, throttling begins at the level determined by the ACPI table value until the temperature drops below the lower limit.

The stop and start of the processor is transparent to the user. The reason is that the frequency at which start / stop behavior occurs is faster than humans can perceive it. The PIIX4 compatible chipset uses a real-time clock to drive a 3-bit counter that defines the duty cycle.

Mobile systems operating in extended battery life mode (run mode 0) should use clock throttling to reduce heat generation as needed. Mobile systems must have sufficient passive cooling when operating in Run Mode 0 at room temperature of 25 ° C., where throttling is rarely needed. In an elevated temperature environment, the processor may be throttled down more often.

In order for a notebook PC to achieve desktop performance levels when docked, additional heat may be applied, for example from a docking station (or other solution that provides additional cooling and external power). Need assistance. The additional power consumed by such a solution allows for a higher amount of CPU power, thus allowing the processor to operate at desktop power and performance levels.

Referring to FIG. 16, a docking station solution for a notebook is illustrated. FIG. 16 illustrates a Peltier element 163 in the docking station 162 when the notebook system is docked in the docking station 162.
Probe 16 inserted into the back of the notebook computer 161 using
5 shows an exemplary system for cooling 5. The probe 165 contacts the heat sink of the processor and conducts heat away by conduction. The probe 165 is cooled by the Peltier element 163, which requires a few watts of power available from the AC operating power source of the docking station.

Other options such as heat pipe technology are also available. Heat pipes are typically made from tubes with water or other coolant at low pressure. When one end is heated by the processor, the coolant absorbs heat as it evaporates. The vapor travels to the other end of the pipe where it is cooled by the heat sink.
The vapor condenses when it cools and moves to the starting point by wickback due to the capillary phenomenon. The heat pipe may be made in many different ways and can be connected to a large surface, such as a metal case, to dissipate the heat. Thus, the notebook docking station solution includes a fan, a heat sink and a heat pipe to conduct heat away from the notebook computer when docked to provide the increased performance desired in run mode 3. Can be enabled.

It should be noted that when using heat transfer, no user accessible part should exceed 50 ° C. The area normally touched should not be uncomfortable to the touch. It should also be noted that while the air delivered from the docking station can increase the cooling of the processor, it can also cause annoying and dust problems.

Since the mechanical and electrical design supports the necessary sensing, the notebook computer is designed with an auxiliary power supply and when the computer is docked, currently docked and when it is undocked. It may be possible to detect when auxiliary cooling is available and / or when user-defined operating conditions have changed. In addition, the notebook PC is designed such that when AC power is first applied, when AC power is present, and when AC power is present.
It must detect if power has been removed. The design includes a power and reset button, when the primary battery is present, battery remaining capacity (ie smart battery), battery charge status, whether a secondary battery is present in the option bay, remaining battery capacity and It must support detection of all standard notebook conditions such as battery charge status. that is,
Charge states including fast charge, trickle charge, battery failure (eg short circuit) and no charge must be detected. It must detect when you press the suspend button (or key combination) to suspend or wake the system, when to open or close the cover (for example, the option to suspend and wake, or simply shut down the backlight). I have to.

The system includes at least two settings for the temperature of the processor case and a temperature “alarm”, one for turning on a cooling device such as a fan when the temperature approaches a safe upper limit for operation. , The other, for immediate protection when temperature reaches a critical upper limit) to prevent damage to the processor). When using a fan for auxiliary cooling, provide confirmation that the fan is running (preferably able to detect fan speed)
. The above sensing capabilities are known in the art and are not further described herein.

As described herein, a notebook computer dynamically adapts to its environment, providing improved power and thermal management and optimizing its performance for that environment. To do. It should be noted that the description of the invention provided herein is exemplary and not intended to limit the scope of the invention as set forth in the appended claims. For example, although the invention has been described with respect to a type of mobile computer herein referred to as a notebook (which may also be referred to as a laptop or portable computer), the teachings herein include computing, telephone / Other portable computing devices, such as personal digital assistants (PDAs), which are handheld devices that typically combine fax and networking features, or other small computers and / or communications in which such a run mode may prove useful. It can also be used in devices. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention as set forth in the appended claims.
This can be done based on the description provided herein.

[Brief description of drawings]

FIG. 1A is a diagram of a table showing four global Gx states.

FIG. 1B is a diagram of a table showing four computing states.

FIG. 1C is a diagram of a table showing various sleep states.

FIG. 2 is a diagram of a state machine that implements various run modes to allow a processor to dynamically adapt to its environment.

3A is a diagram summarizing the various run modes illustrated in FIG. 2. FIG.

FIG. 3B is a diagram showing explicit performance parameters for various run modes.

FIG. 4 is a graph illustrating the relationship between voltage, frequency and power.

FIG. 5 is a high level diagram of a computer system incorporating one embodiment of the present invention.

FIG. 6 is a diagram of one implementation example of a clock control circuit in a CPU.

FIG. 7 is a diagram generally illustrating operations for controlling voltage and frequency according to one embodiment of the present invention.

FIG. 8 is a diagram of the use of Power On Suspend CPU State Hold (POSCCL) in one embodiment of the present invention.

FIG. 9A is a timing diagram illustrating a POSCCL suspend and corresponding resume operation.

9B is a table diagram illustrating the signals shown in FIG. 9A.

FIG. 10 is a diagram showing a change of the run mode using a programmable logic device.

11 is a diagram of an implementation example of the logical device of FIG.

FIG. 12 is a timing diagram illustrating the operation of the logic device of FIG.

FIG. 13 is a diagram of a run mode control register used in one South Bridge implementation to change run modes.

FIG. 14 is a high-level block diagram of a southbridge implementation that provides both jumper inputs and register inputs for voltage and frequency control.

FIG. 15 is a diagram of a flow chart for realizing a run mode change in the south bridge integrated circuit.

FIG. 16 is a diagram of an exemplary docking station that may be used in a notebook computer that incorporates various run modes described herein.

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission Date] November 5, 2001 (2001.11.5)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

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Many power saving techniques have been introduced in an attempt to mitigate the limitations caused by thermal and battery power constraints. For example, US-A-5 881 298
Disclosed is a portable computer that saves power by disconnecting from a cooling system when the computer operates from its portable power source, US-A
-5 887 179 describes an apparatus and method for a controller to detect the occurrence of repetitive operations in a system and reduce power consumption by powering down any subsystems not participating in the repetitive operations. .. The operating frequency (clock frequency) of the processor and its operating voltage determine its power consumption. Since power consumption and therefore heat production are approximately proportional to the operating frequency of the processor, keeping the processor frequency below the desktop performance level is a common way to stay within the power limits of notebook computers. It was IBM Technical Disclosure Bulletin Vol. 38, No. 12, December 1995, discloses a method for adjusting clock speed on a particular processor for power management purposes. WO-A-97 / 12329 discloses power control circuits and corresponding techniques for reducing power consumption in electronic devices, where a controller
The voltage and frequency of the electronic device are adjusted to detect if conditions exist, such as high or low temperatures, where it is appropriate to provide the appropriate signals to the clock generation and power supply circuits. The features of this document are disclosed in the preamble of appended claims 1 and 10. JP-A-08 328 698 describes a control system for the two cooling functions of the CPU (reduction of operating speed and rotation of the motor fan). The user can choose between a quiet mode where low power consumption is a priority and a performance mode where high performance is a priority. In the first case, the processor is slowed down and no fan is used, whereas in the latter case, processor speed is maintained and a fan is used for cooling.

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As described herein, a notebook computer dynamically adapts to its environment, providing improved power and thermal management and optimizing its performance for that environment. To do. It should be noted that the description of the invention provided herein is exemplary and not intended to limit the scope of the invention as set forth in the appended claims. For example, although the invention has been described with respect to a type of mobile computer herein referred to as a notebook (which may also be referred to as a laptop or portable computer), the teachings herein include computing, telephone / Other portable computing devices, such as personal digital assistants (PDAs), which are handheld devices that typically combine fax and networking features, or other small computers and / or communications in which such a run mode may prove useful. It can also be used in devices. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims. .

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), JP, KR (72) Inventor Odyon, Kyle             Oh, United States, 78739 Texas             Austin, Redmond Road,             10806 (72) Inventor Mitchell, Charles Weldon             Oh, United States, 78759 Texas             Austin, Skinner Koub, 6501 (72) Inventor Cressi, Quadir Amad             LA, USA, 78681 Texas             Und Rock, Tomcat Dry             Bu, 16708 (72) Inventor Caldwell, Durbin Dual             United States, 94536 California             State, Fremont, Burton Common, 3837 F term (reference) 5B011 DA02 DB03 DC06 EA04 GG10                       HH02 LL08 LL13                 5B079 AA07 BA01 BA12 BA15 BB01                       BC01 DD13

Claims (12)

[Claims] 1. A method of controlling power consumption of an integrated circuit in an electronic system, the method comprising: operating the integrated circuit at a first voltage and a first frequency; and a plurality of operating characteristics in the electronic system. Detecting at least one change; in response to detecting the change; stopping a clock running on at least a substantial portion of the integrated circuit; and in response to the change, updated frequency control information. To the clock control logic and restarting the clock to operate the integrated circuit at a second clock frequency corresponding to the updated frequency control information. 2. Responsive to the change, further comprising providing updated voltage control information to the voltage control circuit, and operating the integrated circuit at a second voltage corresponding to the updated voltage control information. The method of claim 1, comprising. 3. The clock control logic is located on the integrated circuit, at least some of the clock signals are active on the integrated circuit while the clock is stopped on a substantial portion of the integrated circuit, and the clock is The method of claim 2, wherein the method is stopped on a substantial portion of the integrated circuit according to a clock control signal provided to the integrated circuit. 4. The method of claim 2, wherein the frequency control information is provided as clock multiplication information to clock multiplication logic on the integrated circuit. 5. The method according to claim 1, wherein the integrated circuit is a processor and the electronic system is a notebook computer system. 6. The method of claim 1, wherein the operating characteristics include power supply characteristics and a thermal environment. 7. The method according to claim 1, wherein the operating characteristics include user-selected operating parameters. 8. The method of claim 6, wherein the power source feature comprises the presence of an external power source and the thermal environment comprises the availability of auxiliary cooling. 9. The method according to claim 1, further comprising the steps of saving the processor context before stopping the clock and restoring the processor context after restarting the clock. 10. A computer system including an integrated circuit including a first logic portion, the first logic portion coupled to receive a first clock and a first voltage, the voltage regulator circuit further comprising: A programmable voltage regulator circuit for providing a variable voltage level for a first voltage according to a voltage control signal applied to the clock, and a clock control circuit operable to generate a first clock at a frequency determined according to the frequency control signal. A control circuit coupled to receive an indication of a change in at least one of the plurality of operating characteristics in the computer system, wherein the control circuit is responsive to the change in the operating characteristic to generate a new voltage for the first voltage. The voltage control signal and the frequency control signal indicating the voltage value and the new frequency for the first clock are applied to Pressure value and a new frequency corresponds to a change in operating characteristics, the computer system. 11. The operating characteristics include the presence of an external power source and the availability of auxiliary cooling, including user-selected operating parameters for selecting either battery performance mode or battery saving mode for the computer system. 10. The computer system according to item 10. 12. The control circuit is disposed on the second integrated circuit, the second integrated circuit being coupled to provide a clock stop signal to the integrated circuit, the clock stop signal being responsive to changes in operating characteristics. Responsively asserted, the clock stop signal causes the first clock to be stopped on the integrated circuit, the clock stop signal indicating a new voltage and the frequency control signal to the voltage regulator and the frequency control logic, respectively. The computer system of claim 10, wherein the computer system is deasserted after being provided.