JP2004055130A - Semiconductor device - Google Patents

Abstract

A multi-port RAM is provided which enables high-integration read / write from a plurality of ports at the same time in parallel.
A plurality of memory blocks (MB (i, J)) using single-port memory cells, global bit lines (GBLa, GBLaB, GBLb, GBLbB) having a multi-port configuration, and bit lines in the memory blocks are globally defined. Switch means (SW (i, j)) for selectively connecting to the bit lines are provided; the global bit lines and the bit lines are provided in different wiring layers; Enlarge.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor multiport memory, and more particularly to a semiconductor multiport memory excellent in high integration, high speed, low power, and low noise.
[0002]
[Prior art]
Higher performance of microprocessors has been achieved by increasing clock frequency and parallel processing such as superscalar. At the same time, performance is improved by mounting large-capacity registers and cache memories on the processor chip. In current microprocessor, with respect to the register using a multi-port RAM (RAM = R andom A ccess M emory), it is common to parallel processing between a plurality of registers operation.
[0003]
One method for realizing a multi-port RAM is to devise a memory cell. An example of application to a register is discussed in Non-Patent Document 1, for example. In this example, an example of a 6-read, 4-write register file is shown. A word line, a bit line, and a selection MOSFET are provided for each of a plurality of read and write ports so that read / write can be performed independently from the plurality of ports. FIG. 10 shows a memory cell of a two-port RAM according to this technique. The number of word lines WL and bit lines BL is twice as large as that of a normal single-port RAM memory cell. Further, since the number of MOSFETs for connecting the storage node of the memory cell and the bit line is doubled, the area of the memory cell is about twice as large as the area of the single-port memory cell. I will.
[0004]
However, on the other hand, it was common to use a normal single-port RAM for the cache memory. This is because a memory cell of a multi-port RAM becomes larger than an area of a memory cell of a normal single-port RAM, and a relatively large-capacity memory such as a cache memory occupies a large area. . However, in order to further improve the performance of the processor in the future, it will be important to increase the number of ports in the cache memory so that load and store instructions can be processed in parallel.
[0005]
For this reason, a cache memory that operates as a multi-port RAM while physically using a memory cell of a single-port RAM is discussed in Non-Patent Document 2, for example. In this RAM, a memory operation of three cycles is performed during one cycle of the processor so that the RAM substantially functions as a three-port RAM.
[Non-Patent Document 1] Hara, 12 others, "0.5 um BiCMOS Standard Cell Macros Included 0.5W 3ns Register File and 0.6W 5ns 32kB Cache", Digest of Technical Papers, 1992. EE International Solid State Circuits Conference, February 1992, pp. 46-47
[Non-Patent Document 2] Braceras, 6 others, "A 200 MHz Internal / 66 MHz External 64 kB Embedded Virtual Three-Port Cache SRAM", Digest of Technical Papers, 1994 IEE International Solid State Circuits Conference, February 1994, p. 262-263
[0006]
[Problems to be solved by the invention]
However, when a physical multi-port memory cell such as that used for a register is used as a memory cell in the above-described conventional technology, the degree of integration of the cache memory is significantly reduced, and the processor capacity is reduced due to a decrease in cache capacity. However, there is a problem that the performance is degraded from the original purpose. In addition, when the bit line is operated at a low amplitude in order to increase the speed of the read, when the adjacent bit line performing the read is written at the full amplitude, the speed of the read is reduced due to the coupling capacitance between the adjacent bit lines. Or read may cause malfunction.
[0007]
Further, in the prior art in which the RAM is operated at a cycle that is an integral multiple of the microprocessor, it is substantially difficult to increase the speed of the RAM in proportion to the frequency of the processor. In the above-mentioned prior art, the operating frequency of the processor is 66 MHz, and the RAM operates at 200 MHz. Recently, the operating frequency of processors has exceeded 300 MHz, and the RAM operates at twice or three times the operating frequency. It is practically difficult.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-port RAM capable of simultaneously performing read / write operations from a plurality of ports simultaneously and in parallel while maintaining high integration.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, in a multi-port RAM according to the present invention, a memory cell array is divided into a plurality of sub-arrays (banks) so as to divide bit lines into multiples, and wiring different from bit lines in each sub-array is provided. Global bit lines formed by layers were arranged in parallel. Further, the global bit line has a multi-port configuration, and means is provided for selectively connecting a specific bit line to a global bit line corresponding to one of the multiple ports for each sub-array.
[0010]
According to the above configuration, it is possible to independently perform read / write to different sub arrays via global bit lines of a multi-port configuration. In this configuration, the same sub-array cannot be accessed simultaneously. However, if the number of sub-arrays is larger than a certain level, the probability of accessing the same sub-array is reduced, and the performance improvement by using multiple ports becomes dominant. Further, since the memory cell uses a normal single-port memory cell, an increase in area with respect to a normal single-port RAM can be extremely reduced.
[0011]
Furthermore, since the bit line is divided into multiple parts, the parasitic capacitance of the global bit line is reduced, and the high speed and low power consumption are excellent.
[0012]
In addition, since the wiring pitch of the global bit lines can be made smaller than the wiring pitch of the bit lines, the capacitive coupling noise between the bit lines can be reduced. Furthermore, since shield lines can be arranged between the global bit lines corresponding to different ports in the same wiring layer as the global bit lines, the capacitive coupling noise between the bit lines can be reduced to a negligible level.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows an embodiment of the configuration of a multiport RAM according to the present invention. In the figure, MB (i, j) is a memory block, MA (i, j) is a memory array, PC (i, j) is a precharge circuit, SW (i, j) is a bit line selection circuit, MC Is a memory cell, BL and BLB are bit lines, EQ is an equalization signal line, LC is a load control line, PA and PB are port control lines, GBLa and GBLaB are global bit lines for A port, and GBLb and GBLbB are for B port. Global bit line, RC (i) is row control circuit, PCC (i) is precharge control circuit, MX (i) is address multiplexer, XD (i) is X address decoder, PS (i) is port selection Circuit, IOC (j) is an input / output control circuit, IOa (j) is an A port input / output circuit, IOb (j) is a B port input / output circuit, Aa is an address bus for A port, Ab is B Over preparative address bus, Da is data bus A port, Db is data bus for port B, CX is a row control signal, CY is the column control signal.
[0014]
Memory cell array MA (i, j) is composed of 64 word lines decoded by 6 bits of any of addresses a5-a0 or b5-b0, two data line pairs decoded by a6 or b6, and And a plurality of memory cells MC arranged at the intersection of. In this example, as shown in FIG. 2, a general SRAM memory cell including two inverters and two selection MOSFETs is used as a memory cell. A single-port memory cell having a function may be used. The bit lines BL0, BL0B, BL1, BL1B and the global bit lines GBLa0, GBLa0B, GBLb0, GBLb0B are arranged in parallel with each other, but are formed of different wiring layers, and the global bit line is actually a memory cell. Formed on top of
[0015]
The bit line selection circuit SW (i, j) is configured by a switch using MOSFETs Q1 to Q8 so that the bit line of each memory block is connected to either the A port or the B port global bit line. These switches are controlled by port control lines PA0, PB0, PA1, and PB1. For example, when PA0 is Low and other signals are High, Q1 and Q3 are turned on, and BL0 is connected to GBLa0 and BL0B is connected to GBLa0B. When PB0 is Low, BL0 is connected to GBLb0 and BL0B is connected to GBLb0B. As described above, it is possible to select whether to connect the bit line pair BL0 or BL0B to the global bit line of the A port or the B port by setting either of the signals PA0 and PB0 to Low. Similarly, it is possible to select whether to connect the bit line pair BL1 or BL1B to a global bit line of the A port or the B port depending on which signal of PA1 and PB1 is set to Low. In this embodiment, a P-channel MOSFET is used as a switch. However, for example, if a switch is configured by connecting an N-channel and a P-channel MOSFET in parallel, a voltage drop corresponding to the threshold voltage is eliminated. Speed and margin can be improved. Also, it is obvious that an element that substantially operates as a switch may be used without using a MOSFET as in this example.
[0016]
FIG. 3 shows a configuration example of the port selection circuit PS (i). It is composed of two 3-input NAND gates and four 2-input NOR gates. In this example, block selection is performed using three bits a9-a7 or b9-b7. When the block is selected by a combination of the addresses of the A port and the B port, one of the outputs of the NAND gate becomes Low, and the decoder enable signal DEa or DEb is output. For example, when a7B, a8B, and a9B are all High, the decoder enable signal DEa of the port selection circuit PS (0) of the block RC (0) becomes Low. When b7B, b8B, and b9B are all High, the decoder enable signal DEb of the port selection circuit PS (0) becomes Low. Further, by taking the NOR of these signals DEa, DEb and a6, a6B, b6, b6B, the port control lines PA0, PB0, PA1, PB1 can be generated.
[0017]
The decoder enable signal DEa or DEb output in this manner is input to the address multiplexer MX (i). When DEa is Low, addresses a5-a0 are selected and input to the X address decoder XD (i). When DEb is Low, addresses b5-b0 are selected and input to the X address decoder XD (i). When neither of them goes low, the address signal is not transmitted to the decoder because the block is in the non-selected state. Thus, by providing a means for determining in advance whether the divided block is an access from either the A port or the B port, two sets of decoders are provided for each of the A port and the B port. , It can be operated as a multi-port memory.
[0018]
PCC (i) is a circuit for generating a signal for performing equalization of a bit line and control of a MOSFET serving as a load. Here, the control signal CX input to the PCC (i) includes at least a type of Read / Write for each port and a timing signal for equalizing. For example, when writing to the bit lines BL0 and BL0B, the load control signal LC0 is changed from low to high, and Q11 and Q12 are turned off. Thus, even when the bit line is driven from the global bit line with full amplitude, it is possible to prevent unnecessary DC current from flowing through the load. When shifting from the writing to the reading operation, LC0 is set to Low to make Q11 and Q12 conductive, and the equalizing signal EQ0 is set to Low for a certain period to make Q15 conductive so that the potentials of BL0 and BL0B are matched. By making WL (i) High, a signal appears on the bit line at high speed. The above is the operation for BL0 and BL0B, but the same can be done for BL1 and BL1B. Which of the two bit lines is controlled is determined by a combination of Low / High and Read / Write of the address a6 or b6.
[0019]
FIG. 4 shows locations of the memory physically selected by the address Aa of the A port and the address Ab of the B port. In this example, the upper 3 bits select a bank (memory block), the next 1 bit selects a column, and the lower 6 bits select a row (word line). Since input / output of 128 bits is performed for each address, the memory operates as a 1024 WL × 128 Bit × 2 port memory. It is obvious that the number of banks, the number of word lines, the number of columns, the number of input / output bits, and the like are not limited to the values shown here, but can be freely selected to have any memory capacity and word / bit configuration.
[0020]
In the two-port memory having this configuration, the two ports are accessed as independent memories unless the upper three bits of the A-port address and the B-port address match each other, in other words, unless the two banks simultaneously access the same bank. can do. FIG. 5 shows a case where two banks 0 and 1 are accessed from different ports. For port A, a read operation is performed for column address a6 = 0 of bank 0 (a9 = a8 = a7 = 0), and for port B, column address b6 of bank 1 (b9 = b8 = 0, b7 = 1) = 1 for a write operation. A word line corresponding to the lower 6 bits is selected for each block, and each memory cell is connected to the input / output circuit of each port via the bit line and the global bit lines of the A port and the B port. On the other hand, the following two can be considered as control when the upper three bits match. One is that the processor that accesses the cache memory performs control so as not to issue an address for one of the two ports, utilizing the fact that the processor itself can detect in advance. It is. The second is to add a function of detecting that the upper three bits match to the address decoder of the memory, and access only one of the two ports to the memory according to the information. At the same time, a signal is provided to notify the processor that the upper three bits match (the bank has competed), and the processor controls so that the processor can proceed to the next processing corresponding to the signal. The frequency with which the banks compete depends on the number of banks. Generally, if there are eight or more banks, there is almost no contention, and performance substantially equivalent to a two-port memory can be expected.
[0021]
Next, a more detailed operation will be described with reference to the operation timing chart of FIG. In this example, two cycles are shown, and the case where the following operation is performed in each cycle is illustrated.
[0022]
First cycle A port: Block = 0, word line = 0, Read operation B port: Block = 1, word line = 62, Write operation Second cycle A port: Block = 1, word line = 1, Read operation B port Block = 0, word line = 63, and write information At time t0, addresses Aa and Ab, and control information including read / write control for each port are input to the memory. In this example, since a read operation is performed for the A port and a write operation is performed for the B port, data to be written for the B port is taken into the memory from the data bus Db of the B port.
[0023]
For the memory block MB (0,0), since the first cycle is a read operation to the A port, PA0 is set low and the bit line pair BL0, BL0B is connected to the global bit line pair GBLa0, GBLa0B. At the same time, LC0 is set to Low to turn on the load MOSFETs of the bit line pair BL0 and BL0B, and the equalizing signal EQ0 is set to Low for a certain period (t1 to t3) to short-circuit the bit line pair. Thereafter, the word line W0 (0) specified by the address Aa is set to High, and the information of the memory cell is read out to the bit line pair. In this example, High information is stored in the memory cell, and a signal is read such that BL0 becomes High relative to BL0B. In this example, the other bit line pair BL1 and BL1B in the block is pulled up to the High side by setting LC1 to Low. This aims at minimizing the effect of capacitive coupling noise between the bit lines by turning on the load MOSFET so that either BL1 or BL1B is not discharged by the memory cell. However, if the influence of the coupling capacitance is small, the basic operation will not be significantly affected without this. Since the second cycle is a write operation to the B port, PB0 is set to Low, the bit line pair BL0, BL0B is connected to the global bit line pair GBLb0, GBLb0B, and LC0 is set to High, and the bit line pair BL0, BL0, The load MOSFET of BL0B is turned off. Thereafter, the word line W0 (63) specified by the address Ab is set to High, and the information of the bit line is written to the memory cell.
[0024]
The operation for the memory block MB (1, 0) is basically the same as the above operation, and therefore will not be described.
[0025]
As is clear from the above embodiments, according to the present invention, it is possible to realize a substantially two-port memory operation while using a single-port memory cell. Although a similar function can be obtained by arranging a large number of divided memories of the same type, the present invention has an effect that the area can be minimized as follows in view of the configuration of the memory. In the present invention, since the global bit lines are formed in a wiring layer different from the bit lines, it is not necessary to provide an input / output circuit for each bit line. Thus, the memory can be configured with the minimum number of input / output circuits. Further, when a large number of memories of the same type are arranged, the area required for routing the address bus and data bus lines to each memory becomes large.
[0026]
In the memory configuration of the present invention, the same sub-array cannot be accessed simultaneously. However, if the number of sub-arrays is larger than a certain level, the probability of accessing the same sub-array is reduced, and the performance improvement by using multiple ports becomes dominant.
[0027]
Further, according to the present invention, since the bit line is divided into many parts, the parasitic capacitance of the global bit line is reduced, and high speed and low power consumption can be achieved.
[0028]
FIG. 7 is a schematic diagram of the two-port RAM described above. In this example, two global bit line pairs are arranged in a wiring layer different from the two bit line pairs, and each pair corresponds to two ports. As shown in FIG. Two global bit line pairs may be arranged for each line pair, each of which may correspond to two ports. By doing so, the wiring pitch of the global bit line pair can be reduced to の of the wiring pitch of the bit line pair. Therefore, capacitive coupling noise between global bit lines can be reduced. In addition, as shown in FIG. 8, a shield line can be inserted between the global bit lines in the same wiring layer as the global bit lines to further reduce the capacitive coupling noise. Not limited to this example, the pitch of the global bit line pair can be set to an arbitrary integer multiple of the pitch of the bit line pair by devising the switch section and the control method. It can be formed by wiring.
[0029]
As described above, an example in which the present invention is applied to a two-port memory has been described. However, if the configurations of the global bit lines and the switches are devised, a memory having three or more ports can be similarly configured.
[0030]
FIG. 9 shows another embodiment of the configuration of the multi-port RAM according to the present invention. In this example, the memory cell is constituted by a dynamic memory including one MOSFET and one capacitor. In the figure, MC is a memory cell, PC0 and PC1 are precharge circuits, and SA0 and SA1 are sense amplifiers. As described above, even when a dynamic memory is used, considering the procedure of reading a small signal of a memory cell to a bit line, amplifying it with a sense amplifier, and connecting the bit line to a global bit line, As in the examples, the present invention can be applied.
[0031]
As described above, by adopting a configuration in which read / write operations are performed independently on different sub-arrays via global bit lines of a multi-port configuration, it is possible to use a single-port memory cell while substantially using a single-port memory cell. A function corresponding to a multi-port memory can be realized with a minimum area increase with respect to a single-port RAM. Furthermore, since the bit line has a multi-segment configuration, the parasitic capacitance of the global bit line is reduced, and higher speed and lower power consumption can be achieved. In addition, since the wiring pitch of the global bit lines can be made smaller than the wiring pitch of the bit lines, the capacitive coupling noise between the bit lines can be reduced. Furthermore, since shield lines can be arranged between the global bit lines corresponding to different ports in the same wiring layer as the global bit lines, the capacitive coupling noise between the bit lines can be reduced to a negligible level.
[0032]
【The invention's effect】
The multi-port RAM according to the present invention is configured such that a plurality of memory blocks each formed by a single-port memory cell are connected by a global bit line having a multi-port configuration, and a bit line in the memory block is selectively connected to the global bit line. It is another object of the present invention to provide a multi-port RAM which enables read / write operations from a plurality of ports simultaneously and in parallel while maintaining high integration.
[0033]
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a multiport RAM according to the present invention.
FIG. 2 is a circuit diagram showing a configuration example of a memory cell of FIG. 1;
FIG. 3 is a circuit diagram showing a configuration example of a port selection circuit PS (i) of FIG. 1;
FIG. 4 is a diagram showing correspondence between addresses and selected locations of a memory in the embodiment of FIG. 1;
FIG. 5 is a diagram showing access locations from two ports in FIG. 1;
FIG. 6 is an operation timing chart of the embodiment of FIG. 1;
FIG. 7 is a schematic diagram of the two-port RAM of FIG. 1;
FIG. 8 is a schematic diagram of another embodiment of a two-port RAM.
FIG. 9 is a diagram showing an example in which the present invention is applied to a dynamic memory.
FIG. 10 is a circuit diagram showing a configuration example of a memory cell of a conventional two-port RAM.
[Explanation of symbols]
MB (i, j): memory block, MA (i, j): memory array PC (i, j): precharge circuit, SW (i, j): bit line selection circuit MC: memory cell, BL, BLB: Bit line, EQ: Equalize signal line LC: Load control line, PA, PB: Port control lines GBLa, GBLaB: Global bit lines GBLb, GBLbB for A port: Global bit line RC (i) for B port Row control circuit, PCC (i) Precharge control circuit MX (i) Address multiplexer, XD (i) X address decoder PS (i) Port selection circuit, IOC (j) Input / output control circuit IOa (J): A port input / output circuit, IOb (j): B port input / output circuit Aa: Address bus for A port, Ab: address bus for B port Da: A port Use the data bus, Db ... B port for data bus CX ... row system control signal, CY ... column control signal.

Claims (3)

A plurality of first bit line pairs extending in a first direction; a plurality of first word lines extending in a second direction intersecting the first direction; a plurality of first bit line pairs; A first memory cell block including a plurality of first memory cells arranged at the intersection with the first word line;
First and second global bit line pairs extending in the first direction and formed in a wiring layer different from the first bit line pair;
A plurality of first switches for connecting one of the plurality of first bit line pairs and one of the first and second global bit line pairs;
A plurality of second switches for connecting the other of the plurality of first bit line pairs and the other of the first and second global bit line pairs;
A semiconductor device, wherein a wiring pitch between the first global bit line pair and the second global bit line pair is larger than a wiring pitch of the first bit line pair. In claim 1,
A semiconductor device in which a shield line is arranged between the first global bit line pair and the second global bit line pair. In any one of claim 1 or claim 2,
The semiconductor device, wherein the first global bit line pair and the second global bit line pair are formed above the first memory cell.

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