JP2004006449A - Semiconductor integrated circuit device - Google Patents

Abstract

In a NAND-type nonvolatile memory, characteristics of a memory cell transistor and a select gate transistor are deteriorated due to a short channel effect, or a contact plug and a select gate transistor formed in a self-aligned manner with a gate electrode of the select gate transistor. To prevent short circuit of the gate electrode.
In a NAND type nonvolatile memory having a select gate transistor connected to a NAND type memory cell unit, a part of an interface between a source region or a drain region of a select gate transistor and contact plugs is selected. It is formed at a lower position so as to have a step with respect to the interface between the channel region of the gate transistor and the gate insulating film 2.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure of a contact portion on one end side of a select gate transistor in a semiconductor integrated circuit device having a nonvolatile memory cell transistor and an array of select gate transistors. It is used for a semiconductor memory having an array of non-volatile semiconductor storage elements, a memory embedded device, and the like.
[0002]
[Prior art]
FIG. 6A is a plan view showing a configuration of a memory cell array in a conventional NAND type nonvolatile semiconductor memory. FIG. 6B is a cross-sectional view along the line BB in FIG.
[0003]
6A and 6B, a shallow trench-type element isolation region (STI) is selectively formed in a p-type silicon substrate (or a p-type well) 101, and is formed on the element-isolated substrate. A thin gate insulating film (tunnel insulating film) 102 through which a tunnel current can flow is formed on the entire channel region of the (element region).
[0004]
On the tunnel insulating film 102, a charge storage layer 103 separated for each memory cell is formed, on which a control gate 105 is formed via an inter-gate insulating film 104, and a gate cap is formed thereon. By forming the film 106, a stacked gate is formed.
[0005]
On the surface portions on both sides of the surface portion (channel portion) of the p-type semiconductor substrate 101 under the stacked gate, an n-type diffusion layer 107 doped with an impurity of a conductivity type opposite to that of the channel portion is formed, and a source region or a drain region is formed. Area.
[0006]
An insulating film 108 and a contact barrier film 109 are formed so as to cover the stacked gates and between the stacked gates, and an interlayer insulating film 110 is formed thereon.
[0007]
A plurality of transistors having a stacked gate, a channel portion, a source region, and a drain region as described above are arranged in series so that adjacent ones share the n-type diffusion layer 107. Bit line contact plugs 111 or common source line contact plugs 112 are contacted on n-type diffusion layers 107 at both ends of the transistors connected in series via contact holes opened in contact barrier film 109 and insulating film 108. ing. These contact plugs 111 and 112 are made of low-resistance polysilicon (or metal material) which is a conductive material.
[0008]
Here, the transistors at both ends adjacent to the contact plugs 111 and 112 operate as selection gate transistors in which the charge storage layer 103 and the control gate 105 are short-circuited and a gate signal is applied to the charge storage layer 103 as a gate electrode. The plurality of transistors sandwiched between the select gates operate as memory cell transistors.
[0009]
A plurality of memory cell units each including a plurality of memory cell transistors as described above and a plurality of select gate transistors are formed to form a memory cell array. In this case, the common source line contact plug 112 is connected to a common source line 114, and the bit line contact plug 111 is connected to a bit line 113 made of a metal electrode.
[0010]
However, as shown in FIG. 6B, when the bit line contact plug 111 and the common source line contact plug 112 are formed in a self-aligned manner with respect to the gate electrode 103 of the select gate transistor, There is a problem that a short circuit easily occurs between the gate electrode 103 and the bit line contact plug 111 or the common source line contact plug 112.
[0011]
In order to solve this problem, it is effective to optimize the conditions of the anisotropic etching of the gate electrode and process the gate electrode 103 so that the side surface is vertical.
[0012]
A structure that improves the above problem and further improves the reliability of the memory cell is proposed in Japanese Patent Application No. 2001-352020 filed by the present applicant.
[0013]
FIG. 7 shows an example of the structure according to the above proposal.
[0014]
In this structure, as compared with the structure shown in FIG. 6B, when etching the gate electrode, etching is performed sufficiently until the gate insulating film 102 between the gate electrodes and a part of the silicon substrate 101 are dug. Are different in that the position of the silicon substrate between the gate electrodes is lower than that of the channel region.
[0015]
However, in the structure shown in FIG. 7, since the source region and the drain region are deeper in each of the select gate transistor and the memory cell transistor, the transistor characteristics are deteriorated by the short channel effect, and the miniaturization of the select gate transistor and the memory cell transistor is required. There was a problem that it was difficult.
[0016]
[Problems to be solved by the invention]
As described above, in the conventional nonvolatile semiconductor memory, in the array of the nonvolatile memory cell transistor and the select gate transistor, the gate electrode of the select gate transistor and the bit line contact plug or the gate electrode and the common source line contact plug There was a problem that a short circuit was likely to occur between them.
[0017]
Further, the structure in which the position of the silicon substrate between the gate electrodes is lower than the channel region has a problem that transistor characteristics deteriorate due to a short channel effect, and it is difficult to miniaturize the select gate transistor and the memory cell transistor.
[0018]
The present invention has been made to solve the above problems, and the characteristics of the nonvolatile memory cell transistor and the select gate transistor are deteriorated by the short channel effect, or the characteristics of the nonvolatile memory cell transistor and the select gate transistor are self-aligned to the select gate transistor gate electrode. It is an object of the present invention to provide a semiconductor integrated circuit device capable of preventing a short circuit between a formed contact plug and a gate electrode of a select gate transistor.
[0019]
[Means for Solving the Problems]
According to the semiconductor integrated circuit device of the present invention, the second conductivity type is opposite to the first conductivity type and is separated from each other at a surface portion of the first semiconductor region of the first conductivity type formed on the semiconductor substrate. A charge storage layer and a control gate layer are stacked on the first semiconductor region between the second semiconductor regions via a first gate insulating film, and a second semiconductor region is formed on the second semiconductor region. A memory cell unit including at least one memory cell transistor on which a first insulating film is formed; and a second conductive layer separated from a second conductive layer on a surface portion of a first conductive type third semiconductor region formed on the semiconductor substrate. A fourth semiconductor region and a fifth semiconductor region are formed, a first gate electrode is formed on the third semiconductor region via a second gate insulating film, and a second insulating film is formed on the fourth semiconductor region. Formed in the fourth The conductor region includes a selection gate transistor connected to one of the second semiconductor regions of the memory cell unit, a first contact plug formed on a fifth semiconductor region of the selection gate transistor, the memory cell unit and the selection gate transistor. A memory cell array in which a plurality of gate transistors are formed, and a bit line or a source line is electrically connected to the first contact plug; a fourth semiconductor region of the select gate transistor and a second insulating film Is located such that there is no step with respect to the interface between the third semiconductor region and the second gate insulating film, and part of the interface between the fifth semiconductor region of the select gate transistor and the first contact plug is the third contact region. It is characterized by being located low so as to have a first step with respect to the interface between the semiconductor region and the second gate insulating film. That.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
<First embodiment>
FIG. 1A is a plan view showing a part of a memory cell array in the NAND nonvolatile semiconductor memory according to the first embodiment. FIG. 1B is a cross-sectional view taken along the line BB in FIG.
[0022]
1A and 1B, a p-type silicon substrate (or p-type well) 1 has an element isolation region (STI) in which an insulating material (eg, silicon dioxide material) is embedded in a shallow trench. Are selectively formed. A thin gate insulating film (tunnel insulating film) 2 through which a tunnel current can flow is formed on the entire surface of the channel region on the substrate (device region) thus separated from the device.
[0023]
On the tunnel insulating film 2, a charge storage layer 3 separated for each memory cell is formed, on which a control gate 5 is formed via an inter-gate insulating film 4, and a gate cap is formed thereon. By forming the film (for example, a silicon nitride film) 6, a stacked gate is formed.
[0024]
On the surface portions on both sides of the surface portion (channel portion) of the p-type semiconductor substrate 1 under the stacked gate, an n-type diffusion layer 7a or 7b doped with an impurity of a conductivity type opposite to that of the channel portion is formed. Or it is a drain region.
[0025]
An insulating film 8 (for example, a silicon dioxide film formed by thermal oxidation) and a contact barrier film (for example, silicon nitride) 9 are formed so as to cover the stacked gates and between the stacked gates, and an interlayer insulating film (for example, BPSG) is formed thereon. A film 10 is formed.
[0026]
A plurality of transistors having the above-described stacked gate, channel portion, source region and drain region are arranged in series so that adjacent ones share the n-type diffusion layer 7a. Bit line contact plugs 11 or common source line contact plugs 12 are contacted on the n-type diffusion layers 7b at both ends of the transistors connected in series via contact holes opened in the contact barrier film 9 and the insulating film 8. ing. These contact plugs 11 and 12 are made of low-resistance polysilicon (or metal material) which is a conductive material.
[0027]
Here, the transistors at both ends adjacent to the contact plugs 11 and 12 operate as selection gate transistors in which the charge storage layer 3 and the control gate 5 are short-circuited and a gate signal is applied to the charge storage layer 3 as a gate electrode. The plurality of transistors sandwiched between the select gates operate as memory cell transistors.
[0028]
A plurality of memory cell units each including a plurality of memory cell transistors as described above and a plurality of select gate transistors are formed to form a memory cell array. In this case, the common source line contact plug 12 is connected to the common source line 14, and the bit line contact plug 11 is connected to the bit line 13 made of a metal electrode.
[0029]
Next, an example of a method for manufacturing the NAND nonvolatile semiconductor memory of FIG. 1 will be described with reference to FIGS.
[0030]
First, as shown in FIG. 2A, after selectively forming an element isolation region in a p-type silicon substrate (or p-type well) 1, a gate insulating film (tunnel insulating film) is formed over the entire channel region of the element region. 2, and a stacked gate of the charge storage layer 3, the inter-gate insulating film 4, the control gate 5, and the gate cap film 6 is formed thereon. In this case, the charge storage layer 3, the control gate 5, and the gate cap film 6 are processed in a self-aligned manner so that the side ends thereof are aligned.
[0031]
Next, as shown in FIG. 2B, a resist 2r is applied, an opening is formed between the gate electrodes of adjacent (opposing) select gate transistors by lithography, and anisotropic etching is performed. At this time, the side surface of the gate electrode of the select gate transistor becomes vertical by performing sufficient etching until the gate insulating film 2 between the gate electrodes of the select gate transistor and a part of the silicon substrate 1 are removed.
[0032]
Next, as shown in FIG. 2C, after a silicon dioxide film 8 is formed on the surface of the silicon semiconductor substrate 1 between the stacked gate and the gate electrode of the select gate transistor by thermal oxidation, if necessary, a lithography step , Only the memory cell array region is opened, and n-type impurities are doped to form n-type diffusion layers 7a and 7b.
[0033]
Through the above steps, a part of the interface between the n-type diffusion layer 7b and the insulating film 8 between the gate electrodes of the adjacent select gate transistors is a step difference from the interface between the p-type semiconductor substrate 1 and the tunnel insulating film 2 in the channel portion. Obtain a low-lying structure.
[0034]
Here, in order to make the side surface of the gate electrode of the select gate transistor vertical, it is desirable that the depth d1 of the step is larger than the thickness d2 of the tunnel insulating film 2, as shown in FIG. . However, if the step is excessively large, the short channel effect will be greatly deteriorated, and it is necessary to set the depth to such a degree that such an adverse effect does not occur.
[0035]
Further, when the step is formed under the charge storage layer 3 of the stacked gate, the characteristics of the memory cell deteriorate due to the effect of the thickening of the tunnel insulating film 2, so that as shown in FIG. It is desirable that there is a step outside the edge of the charge storage layer 3. That is, it is desirable that the distance l1 from the center of the charge storage layer 3 to the step is larger than the distance l2 from the center of the charge storage layer 3 to the edge.
[0036]
Subsequently, as shown in FIG. 4A, a contact barrier film 9 made of silicon nitride is formed on the entire surface, an interlayer insulating film 10 made of a BPSG film is formed thereon, and flattened by CMP or the like.
[0037]
Next, as shown in FIG. 4B, after a contact hole is opened by a lithography process and an etching process, a contact material made of, for example, low-resistance polysilicon is buried and flattened, and a bit line contact plug 11 and a common source are formed. A line contact plug 12 is formed.
[0038]
Thereafter, by forming an interlayer insulating film, bit lines, and common source lines, a memory cell array region having a structure as shown in FIG. 1B is formed. Note that a metal such as tungsten may be used for the contact material.
[0039]
Thereafter, as shown in FIG. 5, an upper wiring layer and a protective film are formed by a generally known method, thereby completing a memory cell array region and a peripheral circuit region of the NAND nonvolatile memory.
[0040]
According to the NAND-type nonvolatile memory of the present example manufactured as described above, the surface of the n-type diffusion layer 7a on the memory cell unit side of the select gate transistor is positioned with respect to the interface between the channel portion and the tunnel insulating film 2. No step is formed.
[0041]
As a result, as in the structure shown in FIG. 7, the interface between the n-type diffusion layer 107 of the select gate transistor and the insulating film 108 becomes one of the interface between the p-type semiconductor substrate 101 and the insulating film 102 in the channel portion of the select gate transistor. The depth of the n-type diffusion layer 7a becomes shallower than in the case where the portion has a step, the deterioration of the select gate transistor characteristics due to the short channel effect is improved, and the miniaturization of the select gate transistor becomes possible.
[0042]
Further, a part (central part) of the interface between the n-type diffusion layer 7b on the contact plug side of the select gate transistor and the bit line contact plug 11 and a part (central part) of the interface between the n-type diffusion layer 7b and the common source line contact plug 12 Parts) have been removed. As a result, part of the interface between the n-type diffusion layer 7b and the bit line contact plug 11 and part of the interface between the n-type diffusion layer 7b and the common source line contact plug 12 become the p-type semiconductor substrate of the channel portion of the select gate transistor. The height differs with respect to the interface between the insulating film 1 and the insulating film 2 (has a first step). Here, a part of the interface between the n-type diffusion layer 7b and the contact plugs 11 and 12 is lower in position than the interface between the p-type semiconductor substrate 1 and the tunnel insulating film 2 in the channel portion of the select gate transistor.
[0043]
In this case, etching is performed until the insulating film 2 between the gate electrodes of the pair of select gate transistors facing each other on both sides of the bit line contact plug 11 or the common source line contact plug 12 and a part of the silicon substrate 1 are dug. The side surface of the gate electrode 3 of the select gate transistor is vertical.
[0044]
As a result, the insulating film 8 and the contact barrier film 9 can be formed up to the dug portion of the silicon substrate 1, and when the contact plugs 11 and 12 are formed, the contact plug 11 and the gate electrode 3 of the select gate transistor are contacted. Since the insulating film 8 and the contact barrier film 9 remain (are formed) between the plugs 11 and 12, it is possible to prevent an electrical short circuit between the gate electrode 3 and the contact plugs 11 and 12. Has become.
[0045]
For the above-mentioned reason, it is desirable that the first step is larger than the thickness of the gate insulating film 2 and is outside the edge of the stacked gate.
[0046]
Note that the tunnel insulating film 2 of the memory cell transistor and the gate insulating film 2 of the select gate transistor are substantially the same insulating film formed at the same time. be able to.
[0047]
Further, by forming at least one of the bit line contact plug and the common source line contact plug in a self-aligned manner with the gate electrode 3 of the select gate transistor, short-circuit between the gate electrode 3 of the select gate transistor and the contact plug is prevented. In addition, miniaturization can be achieved without deteriorating the short channel effect of the select gate transistor and the memory cell transistor.
[0048]
<Second embodiment>
FIGS. 5A and 5B show, as a second embodiment of the present invention, a MOS transistor in a memory cell array region and a MOS transistor in a peripheral region where a peripheral circuit thereof is formed (periphery) in a NAND nonvolatile memory. 2 shows a structure of a transistor, for example, a high breakdown voltage transistor to which a write voltage is applied.
[0049]
The peripheral region is electrically separated from the memory cell array region by an element isolation region 15 provided in the silicon substrate 1. Then, a MOS transistor having a gate electrode 17 provided on the silicon substrate 1 via a gate insulating film 16 and an impurity diffusion layer 18 provided in the silicon substrate 1 is formed.
[0050]
The interface between the impurity diffusion layer 18 and the contact plug 19 of this MOS transistor has a second step with respect to the interface between the semiconductor substrate 1 and the gate insulating film 16 in the channel portion. The second step is substantially the same height as the first step that the interface between the impurity diffusion layer 7b and the contact plug 11 in the memory cell array region has with respect to the interface between the semiconductor substrate 1 and the gate insulating film 2 in the channel portion. Contact plugs 19 are respectively contacted to the source and drain regions 18 of the MOS transistor, a metal wiring layer 20 is electrically connected to one contact plug 19, and a metal wiring layer is connected to the other contact plug 19. The metal wiring layer 22 is electrically connected via the layer 20. Further, an upper wiring layer and a protective film are formed by a generally known method, thereby completing a NAND nonvolatile memory.
[0051]
In this example, the gate electrode of the MOS transistor constituting the peripheral circuit has the same laminated gate structure as the select gate transistor in the memory cell array region, but the gate electrode is contacted in a region not shown. When the signal is applied, the transistor operates as a normal MOS transistor.
[0052]
In this example, when forming the memory cell array region as in the first embodiment, peripheral transistors are formed at the same time. That is, when the lithography step described above with reference to FIG. 2B is performed, a gate insulating film is formed between the gate electrodes of the opposing select gate transistors in the memory cell array region and on the sides of the gate electrodes of the peripheral transistors. By performing anisotropic etching until a part of the silicon substrate is removed, the structure shown in FIG. 5 can be obtained.
[0053]
Since the step formed in the impurity diffusion layer 18 of the peripheral transistor shown in this example is the same height as the step formed in the impurity diffusion layer 7b in the memory cell array region, the contact plug 11 and the contact plug 12 in the memory cell array region have the same height. With respect to the contact plug 19 in the peripheral region, the step of opening a contact hole and the step of forming a contact plug can be performed simultaneously. As a result, the peripheral transistor can be formed without increasing the number of manufacturing steps, and the manufacturing cost can be reduced.
[0054]
The characteristics of the peripheral transistor thus formed may be slightly reduced because the surface of the impurity diffusion layer 18 is etched, but the contact plug 19 of the peripheral transistor is replaced with the contact plugs 11 and 12 of the select gate transistor. Similarly to the above, even when the peripheral transistor is a high breakdown voltage transistor to which a write voltage is applied, for example, the contact plug 19 only has to play a role of mainly transmitting a voltage. There is no.
[0055]
That is, according to the above-described method for manufacturing a NAND nonvolatile semiconductor memory, the opening of the contact hole on the drain region and the source region of the peripheral transistor is performed in the same step as the opening of the contact hole of the select gate transistor. And the manufacturing cost can be reduced. In this case, the bit line contact plug and the common source line contact plug of the select gate transistor and the contact plugs of the drain region and the source region of the peripheral transistor can be formed in the same step, and the manufacturing cost can be reduced.
[0056]
In each of the above embodiments, a NAND nonvolatile memory has been described as an example. However, the present invention is not limited to the above example, and a nonvolatile memory such as another AND nonvolatile memory may be used. The present invention can be applied to a semiconductor memory having a cell transistor and a select gate transistor, a memory embedded device, or the like.
[0057]
【The invention's effect】
As described above, according to the semiconductor integrated circuit of the present invention, the characteristics of the nonvolatile memory cell transistor and the select gate transistor are deteriorated due to the short channel effect, or are formed in a self-aligned manner with respect to the gate electrode of the select gate transistor. Short-circuit between the contact plug and the gate electrode of the select gate transistor can be prevented.
[Brief description of the drawings]
FIG. 1 is a plan view and a cross-sectional view illustrating a part of a memory cell array in a NAND nonvolatile memory according to a first embodiment.
FIG. 2 is an exemplary sectional view showing a manufacturing step of the NAND-type nonvolatile memory according to the first embodiment;
FIG. 3 is an enlarged cross-sectional view showing a NAND nonvolatile memory in FIG. 2;
FIG. 4 is a sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment;
FIG. 5 is a sectional view showing a memory cell array region and a peripheral region in a NAND nonvolatile memory according to a second embodiment;
FIG. 6 is a plan view and a cross-sectional view showing a configuration of a memory cell array in a conventional NAND type nonvolatile memory.
FIG. 7 is a cross-sectional view showing a configuration of a memory cell array in a currently proposed NAND type nonvolatile memory.
[Explanation of symbols]
1 .... p-type silicon semiconductor substrate (or p-type well),
2 ... Tunnel insulating film,
3 ... Charge storage layer,
4: Inter-gate insulating film,
5 ... control gate,
6 ... gate cap film
7a, 7b... N-type diffusion layers,
8. Insulating film,
9 ... contact barrier film,
10 ... interlayer insulating film,
11 ... bit line contact plug,
12 ... Common source line contact plug,
13 ... bit line,
14 ... common source line,
15 ... element isolation region.

Claims (9)

A second conductivity type second semiconductor region having a conductivity type opposite to the first conductivity type formed apart from each other at a surface portion of the first conductivity type first semiconductor region formed on the semiconductor substrate; At least a charge storage layer and a control gate layer are stacked on the first semiconductor region between the second semiconductor regions via a first gate insulating film, and a first insulating film is formed on the second semiconductor region. A memory cell unit including one memory cell transistor;
A fourth semiconductor region and a fifth semiconductor region of the second conductivity type are formed apart from each other at a surface portion of the third semiconductor region of the first conductivity type formed on the semiconductor substrate, and are formed on the third semiconductor region. Forming a first gate electrode with a second gate insulating film interposed therebetween, forming a second insulating film on the fourth semiconductor region, wherein the fourth semiconductor region is one of the second semiconductor regions of the memory cell unit. A select gate transistor connected to
A first contact plug formed on a fifth semiconductor region of the select gate transistor;
A memory cell array in which a plurality of the memory cell units and a plurality of select gate transistors are formed, and a bit line or a source line is electrically connected to the first contact plug;
An interface between the fourth semiconductor region and the second insulating film of the select gate transistor is positioned so as to have no step with respect to an interface between the third semiconductor region and the second gate insulating film;
A part of the interface between the fifth semiconductor region and the first contact plug of the select gate transistor is located lower than the interface between the third semiconductor region and the second gate insulating film so as to have a first step. A semiconductor integrated circuit device characterized by the following. An interface between the first semiconductor region and the first gate insulating film of the memory cell transistor and an interface between the second semiconductor region and the first insulating film of the memory cell transistor are connected to the third semiconductor region and the second 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is located such that there is no step with respect to the interface of the gate insulating film. 3. The semiconductor integrated circuit device according to claim 1, wherein the first step is larger than a thickness of a second gate insulating film of the select gate transistor. 4. The semiconductor integrated circuit device according to claim 1, wherein the first step is located outside an edge of a first gate electrode of the select gate transistor. 5. The memory device according to claim 1, wherein the first gate insulating film of the memory cell transistor and the second gate insulating film of the select gate transistor are substantially the same gate insulating film formed at the same time. 4. A semiconductor integrated circuit device according to any one of the above. The semiconductor integrated circuit device according to claim 1, wherein the first contact plug is formed in a self-aligned manner with respect to a first gate electrode of the select gate transistor. A second conductive type seventh semiconductor region is formed at a surface layer of the first conductive type sixth semiconductor region formed on the semiconductor substrate and is spaced apart from each other, and the sixth semiconductor region between the seventh semiconductor regions is formed. A peripheral circuit transistor having a second gate electrode formed on the region via a third gate insulating film, and a third insulating film formed on the seventh semiconductor region;
A second contact plug formed on a seventh semiconductor region of the peripheral circuit transistor,
Part of the interface between the seventh semiconductor region and the second contact plug of the peripheral circuit transistor has a second step having the same height as the first step with respect to the interface between the sixth semiconductor region and the third gate insulating film. The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein the semiconductor integrated circuit device is positioned low so as to have. 8. The semiconductor integrated circuit device according to claim 7, wherein said first contact plug and said second contact plug are formed of substantially the same conductive material formed at the same time. 9. The semiconductor integrated circuit device according to claim 1, wherein the memory cell unit is a NAND cell type unit in which a plurality of memory cell transistors are connected in series.

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