JP2004030382A - Semiconductor device design method, semiconductor device design device, and program - Google Patents

Abstract

An element value error caused by rounding of a remarkable angle generated by exposure when manufacturing a semiconductor device is obtained.
A detecting means detects an element pattern having an excellent angle from physical data indicating an element pattern formed on a semiconductor substrate. The error calculating means 52 calculates an error caused by a portion having an excellent angle being rounded during exposure. The element value calculation means 53 calculates a change in the element value of the element based on the error calculated by the error calculation means 52.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device design apparatus, a semiconductor device design method, and a program, and more particularly, to a semiconductor device design apparatus, a semiconductor device design method, and a program for designing a semiconductor device including an element pattern having a remarkable angle.
[0002]
[Prior art]
When designing a semiconductor device, it is necessary to generate physical data indicating an element pattern formed on a semiconductor substrate based on a netlist (circuit connection information) and create a reticle from this physical data.
[0003]
By the way, when the element pattern included in the physical data has a remarkable angle, the formed element has an error in some cases because the part is rounded according to the exposure wavelength.
[0004]
FIG. 17 is a diagram for explaining such a situation. In this figure, a gate polysilicon 11 is formed on an L-shaped element region (element pattern having an excellent angle) 10.
[0005]
Here, a portion of the element region 10 having a remarkable angle (a portion originally designed to be a right angle) is rounded according to the exposure wavelength circle 12, as shown in the drawing. As a result, the channel width of the gate polysilicon 11 becomes W on the left side and W + ΔW on the right side, and an error occurs by ΔW, so that the element value deviates from the designed value.
[0006]
In order to prevent such an error from occurring, conventionally, as shown in FIG. 18, a method of setting a distance X from a pattern portion having a remarkable angle to the gate polysilicon 11 to be larger than a predetermined value. Was adopted.
[0007]
Further, as another method, as shown in FIG. 19, a method for preventing the occurrence of rounding as shown in FIG. 17 by forming a notch 21 in a portion having a remarkable angle of the reticle 20 is also adopted. I was
[0008]
[Problems to be solved by the invention]
However, in the former method, since the distance X between the element region 10 and the gate polysilicon 11 needs to be set large, there is a problem that the chip area becomes large as a whole.
[0009]
Also, in the latter method, it is necessary to make notches in all portions having a remarkable angle of the reticle, so that it takes time to manufacture the reticle, and the manufacturing period of the semiconductor device is extended or the manufacturing cost is increased. There was a problem that it would.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device design apparatus, a semiconductor device design method, and a program capable of designing a semiconductor device including an element pattern having a remarkable angle without causing an element error. The purpose is to provide.
[0011]
[Means for Solving the Problems]
In the present invention, in order to solve the above-mentioned problem, a detecting step of detecting an element pattern having a remarkable angle from physical data indicating an element pattern formed on a semiconductor substrate, an error occurring in a portion having the remarkable angle during exposure And an element value calculating step of calculating a change in an element value of the element based on the error calculated in the error calculating step. .
[0012]
Here, the detecting step detects an element pattern having a remarkable angle from physical data indicating the element pattern formed on the semiconductor substrate. The error calculating step calculates an error occurring in a portion having a remarkable angle during exposure. The element value calculation step calculates a change in the element value of the element based on the error calculated in the error calculation step.
[0013]
Detecting means 51 for detecting an element pattern having a remarkable angle from physical data indicating the element pattern formed on the semiconductor substrate; and error calculating means 52 for calculating an error occurring in the portion having the remarkable angle during exposure. And an element value calculating means 53 for calculating a change in the element value of the element based on the error calculated by the error calculating means 52.
[0014]
Here, the detecting means 51 detects an element pattern having an excellent angle from physical data indicating the element pattern formed on the semiconductor substrate. The error calculating means 52 calculates an error occurring in a portion having a remarkable angle during exposure. The element value calculation means 53 calculates a change in the element value of the element based on the error calculated by the error calculation means 52.
[0015]
A detecting step of detecting an element pattern having a remarkable angle from physical data indicating the element pattern formed on the semiconductor substrate; an error calculating step of calculating an error occurring in the portion having the remarkable angle during exposure; A program for causing a computer to function as an element value calculation step of calculating a change in the element value of the element based on the error calculated in the calculation step is provided.
[0016]
Here, the detecting step detects an element pattern having a remarkable angle from physical data indicating the element pattern formed on the semiconductor substrate. The error calculating step calculates an error occurring in a portion having a remarkable angle during exposure. The element value calculation step calculates a change in the element value of the element based on the error calculated in the error calculation step.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. As shown in the figure, the semiconductor device designing apparatus of the present invention includes a physical data DB (Data Base) 50, a detecting unit 51, an error calculating unit 52, an element value calculating unit 53, a net list changing unit 54, and a net list DB 55. Have.
[0018]
Here, the physical data DB 50 stores physical data indicating an element pattern formed on the semiconductor substrate.
The detecting means 51 detects an element pattern having a remarkable angle from the physical data stored in the physical data DB 50.
[0019]
The error calculating means 52 calculates an error occurring in a portion having a remarkable angle during exposure. The element value calculation means 53 calculates a change in the element value of the element based on the error calculated by the error calculation means 52.
[0020]
The netlist changing means 54 changes the element values of the elements included in the netlist based on the result of the element value calculating means 53.
Next, the operation of the above principle diagram will be described.
[0021]
First, the detecting means 51 reads out the physical data stored in the physical data DB 50, and detects an element pattern having an excellent angle included therein. Note that the element pattern having an excellent angle is, for example, an L-shaped pattern as shown in FIG.
[0022]
The error calculator 52 calculates a physical error (for example, rounding) that occurs when the element pattern having the remarkable angle detected by the detector 51 is actually exposed on the semiconductor substrate. As an actual calculation method, for example, a portion having a remarkable angle is rounded according to the exposure wavelength, and a change in channel width is calculated as ΔW.
[0023]
The element value calculation means 53 calculates a change in the element value (for example, a change in the resistance value or a change in the element value of the transistor) caused by the error (physical error) calculated by the error calculation means 52.
[0024]
If there is an element whose element value has been changed by the element value calculating means 53, the netlist changing means 54 changes the element value of the corresponding element included in the netlist, and supplies it to the netlist DB 55.
[0025]
As described above, the detecting means 51 detects the element pattern having the remarkable angle, the error calculating means 52 calculates the physical error occurring in the element pattern having the remarkable angle, and the element value calculating means 53 A change in the element value of the element caused by a physical error is calculated, and the netlist is changed by the netlist changing means 54 in accordance with the change in the element value. The generated element error can be reflected in the netlist. As a result, by re-calibrating the physical data using the netlist, it becomes possible to manufacture a semiconductor device close to the design data.
[0026]
Next, an embodiment of the present invention will be described.
FIG. 2 is a diagram illustrating a configuration example of the embodiment of the present invention.
As shown in this figure, a semiconductor device designing apparatus 60 of the present invention includes a CPU (Central Processing Unit) 60a, a ROM (Read Only Memory) 60b, an HDD (Hard Disk Drive) 60d, a GC (Graphics Card) 60e, and an I / O. An F (Interface) 60f, a bus 60g, a display device 61 connected to the outside, and an input device 62 are provided.
[0027]
Here, the CPU 60a controls each unit of the device according to programs and data stored in the HDD 60d.
The ROM 60b stores basic programs and data executed by the CPU 60a.
[0028]
The RAM 60c temporarily stores programs and data to be executed by the CPU 60a.
The HDD 60d stores programs and data executed by the CPU 60a and netlist data and physical data of the semiconductor device.
[0029]
The GC 60e draws an image according to a drawing command supplied from the CPU 60a, converts the obtained image into a video signal, and supplies the video signal to the display device 61.
The I / F 60f converts the format of the data supplied from the input device 62 so as to conform to the internal format of the semiconductor device design device 60.
[0030]
The bus 60g connects the CPU 60a, the ROM 60b, the RAM 60c, the HDD 60d, the GC 60e, and the I / F 60f to each other, and enables data transfer between them.
[0031]
The display device 61 includes, for example, a liquid crystal display or a CRT (Cathode Ray Tube) display, and displays and outputs a video signal supplied from the GC 60e.
[0032]
The input device 62 includes, for example, a keyboard and a mouse, and generates and outputs data according to a user operation.
Next, the operation of the above embodiment will be described.
[0033]
The CPU 60a reads physical data indicating an element pattern formed on the semiconductor substrate from the HDD 60d. FIG. 3 is a diagram illustrating an example of the physical data. In the example of this figure, a physical configuration of a semiconductor device including a diffusion layer, gate polysilicon, a contact, a wiring, and the like is shown.
[0034]
The CPU 60a detects an element pattern having an excellent angle θ (180 ° <θ <360 °) from the physical data read from the HDD 60d in this manner.
Specifically, the CPU 60a superimposes a rectangle 71 having a predetermined region on the element region (diffusion layer pattern) 70 as shown in FIG. It is determined whether the element pattern is a pentagon or more. If it is a pentagon or more, it is determined that a superior angle is included.
[0035]
Next, the CPU 60a specifies what element the specified element pattern constitutes from the physical data. As a specifying method, for example, when both the poly layer and the diffusion layer are present, it is determined that the transistor is a transistor.
[0036]
As a result of the determination, if the element pattern is a transistor, it is determined whether a pattern including a reflex angle is formed on the source side. That is, since the element value changes due to the error of the channel width when the reflex angle is formed on the source side, it is necessary to determine whether or not the element is on the source side. As a determination method, when there is a contact hole connected to the power supply wiring, it can be determined that the source side is used.
[0037]
FIG. 5 is a diagram illustrating an example of a transistor pattern. In this example, a contact hole 73 is arranged at a lower left portion of the element region 70, and the contact hole 73 is connected to a metal layer 74 that is a power supply. Therefore, it is necessary to consider the influence of an error on the lower reflex angle, but it is possible to ignore the influence on the upper reflex angle.
[0038]
FIG. 6 is a diagram illustrating another example of a transistor pattern. In this example, a contact hole 73 is arranged on the left side of the element region 70, and the contact hole 73 is connected to a metal layer 74 as a power supply. Therefore, it is necessary to consider the influence of the error on the left angle of reflex, but the effect of the right angle on the right side can be ignored.
[0039]
As a method of specifying a transistor, as will be described in detail in a flowchart described later, first, a logical product (P∩F) of the poly layer P and the diffusion layer F is calculated, and the obtained region (P∩F ) May be used to specify the transistor.
[0040]
Next, the CPU 60a determines whether or not the gate polysilicon layer exists near the reflex angle arranged on the source side, and if so, detects the distance X from the gate polysilicon layer.
[0041]
Specifically, as shown in FIG. 7, when the gate polysilicon 72 is included in the range surrounded by the rectangle 71, the CPU 60a calculates a distance X between the gate polysilicon 72 and the element region 70, and Once.
[0042]
Next, the CPU 60a obtains the error ΔW corresponding to the previously obtained distance X from the table indicating the relationship between the distance X stored in the HDD 60d and the error ΔW caused by the roundness.
[0043]
FIG. 8 is a graph showing the relationship between the distance X (μm) and ΔW (μm). In this figure, white circles indicate the mean of the predicted values. On the other hand, the black circles indicate the maximum value (worst) of the predicted value. As shown in this figure, since a certain relationship exists between the distance X and ΔW, ΔW is obtained based on this relationship.
[0044]
Next, the CPU 60a divides the target element into a transistor having a channel width of W (basic transistor) and a transistor having a channel width of ΔW (floating transistor), as shown in FIG. An element value when transistors are connected in parallel is obtained.
[0045]
Next, the CPU 60a searches the netlist for an element value corresponding to the element having the superior angle specified from the physical data, and adds the previously calculated element value.
10 to 12 show specific examples. The diagram on the left side of FIG. 10 shows the transistor before the element value is changed. In this example, the gate length L is 0.11 μm, the channel width W is 1.0 μm, and the transistors connected to the node numbers N185, N184, and VSS respectively show the state before the element value is changed. Have been. FIG. 11 is a netlist corresponding to such a transistor. Here, “M503” is a serial number given to the transistor, and “vss”, “N184”, “N185”, and “vss” indicate nodes to which the source, gate, drain, and well are connected, respectively. ing. “L” and “w” indicate a gate length and a channel width, respectively. “Ad” and “as” indicate a drain area and a source area, respectively. “Pd” and “ps” indicate a drain peripheral length and a source peripheral length, respectively. “Nrd” and “nrs” indicate a drain resistance value and a source resistance value, respectively. “Rdc” and “rds” indicate a drain contact resistance and a source contact resistance, respectively.
[0046]
In the circuit on the right side of FIG. 10, floating transistors due to rounding errors (0.04 μm) are connected in parallel. FIG. 12 is a netlist in consideration of the floating transistor thus newly added. In this example, data on the element of the transistor whose serial number is “M504” is newly added. In this example, it is assumed that the superior angle has an influence on the source of the transistor. Assuming that the channel width W of the transistor increases by 0.04 μm, the source junction area and the (as) source peripheral length (ps) are correspondingly increased. Was added to the parasitic element netlist (M504). It is assumed that the influence of rounding does not reach the drain portion, and ad = pd = 0.
[0047]
With the above processing, a netlist in which an error is considered is obtained. The user can execute a circuit simulation or the like of the entire semiconductor device using the netlist obtained in this manner, and determine whether the device operates normally. As a result, when a normal operation is hindered by an error, the characteristic can be improved to a target characteristic by changing the relevant portion.
[0048]
Next, a flowchart for realizing the above processing will be described. FIG. 13 is an example of a flowchart for realizing the processing described above. When this flowchart is started, the following steps are executed.
[0049]
Step S10:
The CPU 60a calculates a logical product (P∩F) of the poly (gate polysilicon layer) P and the diffusion layer F.
[0050]
Step S11:
The CPU 60a specifies a transistor from the area (P∩F) obtained in step S10.
[0051]
Step S12:
The CPU 60a calculates a logical product (F∩L) of the rectangle L in which the width of the poly-P of the transistor specified in step S11 is increased by a predetermined amount and the diffusion layer F.
[0052]
Step S13:
The CPU 60a determines whether or not the area (F∩L) obtained in step S12 is a quadrangle. If the area is a quadrangle, the process proceeds to step S17; otherwise, the process proceeds to step S14. For example, when the area is a hexagon as shown in FIG. 4, it is determined that the area includes a superior angle, and the process proceeds to step S14.
[0053]
Step S14:
The CPU 60a searches for a metal connected to the contact and the power supply from the area (F 電源 L).
[0054]
Step S15:
When the CPU 60a finds a corresponding area as a result of the search in step S14, the processing proceeds to step S16 because the target area is the source area, and otherwise proceeds to step S17.
[0055]
Step S16:
The CPU 60a adds a floating transistor to a corresponding transistor (Tr) in the netlist.
[0056]
Step S17:
The CPU 60a determines whether or not the processing for all the areas (P∩F) has been completed. If the processing has not been completed, the process returns to step S13; otherwise, the processing ends.
[0057]
With the above processing, it is possible to detect a transistor having an excellent angle and add a floating transistor to a corresponding portion of the netlist.
Note that, in the above processing, description has been made using a transistor as an example, but the present invention can also be applied to other elements (resistance, capacitor, inductor, and the like).
[0058]
FIG. 14 is a diagram showing an example in which the present invention is applied to a resistor. In the example of this figure, both ends (portions having a remarkable angle) of the narrowed portion of the resistance element formed by the diffusion layer 80 are rounded, and an error of the element occurs due to this portion. That is, since the resistance value of the resistive element is inversely proportional to the width W, the portion having an excellent angle is rounded and the width increases by ΔW, resulting in a decrease in the resistance value. Therefore, this decrease is represented by the floating resistance added in parallel to the original resistance.
[0059]
As described above, according to the present invention, it is possible to calibrate the resistance value even in the case where the resistance element has an excellent angle.
In addition to this, it is possible to calibrate the element values of the capacitors and inductors based on the same principle. For example, in the case of a capacitor, the capacitance value increases when the area of the electrode increases by ΔW, so that the stray capacitance may be added according to the increase.
[0060]
In the above embodiment, ΔW is determined in proportion to the distance X between the gate polysilicon 72 and the element region 70. However, for example, the range of X is determined as shown in FIG. ΔW may be determined.
[0061]
In the example of this figure, when X ≧ 0.25, ΔW is set to 0.00, and when 0.25>X> 0.15, such a layout is prohibited, and X = 0.15. In this case, ΔW is set to 0.04, and when X <0.15, such a layout is set to be prohibited.
[0062]
According to such a method, the error is calculated more accurately by setting X to fall within a predetermined range (X = 0.15 in this example) in which an accurate value is obtained by an experiment. It becomes possible.
[0063]
Further, in the above embodiment, the error in the case where the diffusion region is rounded has been described. Needless to say, it is also possible to apply
[0064]
FIG. 16 is a diagram illustrating a case where the gate polysilicon layer is rounded. As shown in this figure, when the gate polysilicon 72 is rounded, for example, a circuit in which the gate polysilicon 72 is divided into a rounded portion and a portion where the gate polysilicon 72 is not divided, and a transistor corresponding to each portion is connected in parallel. Can be considered.
[0065]
In the example shown in FIG. 16, the gate length of the portion where the gate polysilicon 72 is not rounded is L, and the gate length of the rounded portion is L + ΔL. Further, a channel width including a non-rounded portion is denoted by W1, and a channel width including a rounded portion is denoted by W2.
[0066]
In such a case, as shown on the right side of the figure, a transistor having a channel width of L and a gate length of W1 and a transistor having a channel width of L + ΔL and a gate length of W2 are connected in parallel. And the element value can be calculated.
[0067]
Further, in the above embodiment, when correcting an element having an error, a form in which a floating element is connected in parallel to a basic element is employed, but it goes without saying that there are various other methods. . For example, the basic element itself may be changed according to the error.
[0068]
Furthermore, in the above embodiment, the error of the element value detected based on the physical data is reflected in the netlist, but the netlist is created and displayed in parallel with the creation of the physical data. The physical data can be changed in real time with reference to the displayed netlist. According to such a method, a semiconductor device closer to the design value can be manufactured.
[0069]
Further, in the above embodiment, the description has been given by taking the element having the L-shaped structure as an example. However, it is needless to say that the present invention can be applied to, for example, the element having the T-shaped structure. . In short, the present invention can be applied to any structure having a remarkable angle.
[0070]
Finally, the above processing functions can be realized by a computer. In this case, a program is provided that describes the processing contents of the functions that the semiconductor device design apparatus should have. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing content can be recorded on a computer-readable recording medium. Computer-readable recording media include magnetic recording devices, optical disks, magneto-optical recording media, and semiconductor memories. The magnetic recording device includes a hard disk device (HDD), a flexible disk (FD), a magnetic tape, and the like. Examples of the optical disk include a DVD (Digital Versatile Disk), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disk Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). The magneto-optical recording medium includes an MO (Magneto-Optical disk) and the like.
[0071]
When distributing the program, for example, portable recording media such as DVDs and CD-ROMs on which the program is recorded are sold. Alternatively, the program may be stored in a storage device of a server computer, and the program may be transferred from the server computer to another computer via a network.
[0072]
The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, the computer may execute the processing according to the received program each time the program is transferred from the server computer.
[0073]
(Supplementary Note 1) a detecting step of detecting an element pattern having an excellent angle from physical data indicating the element pattern formed on the semiconductor substrate;
An error calculating step of calculating an error occurring in the portion having the remarkable angle during exposure,
An element value calculating step of calculating a change in an element value of the element based on the error calculated by the error calculating step;
A semiconductor device design method comprising:
[0074]
(Supplementary Note 2) The semiconductor device design method according to Supplementary Note 1, further comprising netlist changing means for changing an element value included in the netlist based on a result of the element value calculating step.
[0075]
(Supplementary Note 3) The semiconductor device design method according to Supplementary Note 1, wherein the error calculating step calculates the error by referring to a wavelength of a beam at the time of exposure.
(Supplementary Note 4) The semiconductor device design method according to Supplementary Note 1, wherein in the element value calculation step, a change in an element value caused by the error is calculated as a new element added in parallel to the element.
[0076]
(Supplementary Note 5) The element is a resistor, a capacitor, or an inductor, and the element value calculation step refers to the error calculated in the error calculation step, and calculates an error occurring in these elements. The semiconductor device design method according to Supplementary Note 1.
[0077]
(Supplementary Note 6) The semiconductor according to Supplementary Note 1, wherein the element is a transistor, and the element value calculating step calculates an error occurring in the transistor with reference to the error calculated in the error calculating step. Equipment design method.
[0078]
(Supplementary Note 7) The semiconductor device design method according to Supplementary Note 6, wherein the element value calculating step calculates the element value by focusing only on the remarkable angle formed on the source side of the transistor.
[0079]
(Supplementary Note 8) The element value calculating step is characterized in that, when a contact hole is present in the vicinity of the reflex angle and is connected to a power supply wiring, the reflex angle is determined to be on the source side. 8. The method of designing a semiconductor device according to supplementary note 7.
[0080]
(Supplementary note 9) The semiconductor according to Supplementary note 6, wherein the element value calculating step calculates the element value only when the portion having the remarkable angle and the gate region are closer to each other by a predetermined distance or more. Equipment design method.
[0081]
(Supplementary note 10) The semiconductor device design method according to supplementary note 6, wherein the error is calculated based on a distance between the portion having the remarkable angle and a gate region of the transistor.
[0082]
(Supplementary Note 11) The element value calculating step includes drawing a rectangle centered on the gate region, and changing the element value when the element pattern having the superior angle surrounded by the rectangle is a pentagon or more. 7. The method of designing a semiconductor device according to supplementary note 6, wherein
[0083]
(Supplementary Note 12) Detection means for detecting an element pattern having an excellent angle from physical data indicating an element pattern formed on a semiconductor substrate;
Error calculating means for calculating an error occurring in the portion having the remarkable angle upon exposure,
An element value calculation unit that calculates a change in an element value of the element based on the error calculated by the error calculation unit;
A semiconductor device design apparatus comprising:
[0084]
(Supplementary Note 13) a detecting step of detecting an element pattern having an excellent angle from physical data indicating the element pattern formed on the semiconductor substrate;
An error calculation step of calculating an error occurring in the portion having the remarkable angle during exposure, an element value calculation step of calculating a change in an element value of the element based on the error calculated by the error calculation step,
A program that causes a computer to function as.
[0085]
【The invention's effect】
As described above, in the present invention, an element pattern having a remarkable angle is detected, an error occurring in a portion having a remarkable angle upon exposure is calculated, and a change in the element value is calculated based on the result. Therefore, a semiconductor device can be faithfully manufactured based on a design.
[0086]
Further, according to the present invention, an element pattern having a remarkable angle is detected, an error occurring in a portion having a remarkable angle at the time of exposure is calculated, and the element value is changed based on the result. In addition, a highly reliable semiconductor device can be manufactured.
[0087]
Further, according to the present invention, a computer is made to perform a process of detecting an element pattern having a remarkable angle, calculating an error occurring in a portion having a remarkable angle upon exposure, and changing an element value based on the result. With this configuration, it is possible to quickly determine an error caused by rounding of a portion having a remarkable angle.
[Brief description of the drawings]
FIG. 1 is a principle diagram for explaining the operation principle of the present invention.
FIG. 2 is a diagram illustrating a configuration example of an embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of physical data.
FIG. 4 is a diagram for explaining a state of processing for detecting an element pattern having an excellent angle from physical data.
FIG. 5 illustrates an example of a transistor pattern.
FIG. 6 is a diagram showing another example of a transistor pattern.
FIG. 7 is a diagram for explaining a process for obtaining a distance between a gate polysilicon and a portion having an excellent angle.
FIG. 8 is a graph showing a relationship between a distance X between a gate polysilicon and a portion having a remarkable angle and an error ΔW generated when the portion having a remarkable angle is rounded.
FIG. 9 is a diagram for explaining a case in which an error ΔW is calculated assuming that it is a new element;
FIG. 10 is a diagram illustrating a specific calculation example of an error ΔW.
FIG. 11 is a diagram illustrating an example of a net list before an error ΔW is added.
FIG. 12 is a diagram illustrating an example of a netlist after an error ΔW has been added;
FIG. 13 is a flowchart illustrating a flow of a process performed in the embodiment illustrated in FIG. 2;
FIG. 14 is a diagram illustrating a process related to a resistance error.
FIG. 15 is a diagram illustrating another calculation method of an error.
FIG. 16 is a diagram for describing an error generated by rounding of gate polysilicon.
FIG. 17 is a diagram for describing an error that occurs when an element pattern having an excellent angle is rounded.
FIG. 18 is a diagram showing a conventional method of setting a large distance X from a pattern portion having a remarkable angle to a gate polysilicon to avoid occurrence of an error.
FIG. 19 is a view for explaining a conventional method for avoiding the occurrence of an error by forming a notch in a portion having a remarkable angle of a reticle.
[Explanation of symbols]
50 Physical Data DB
51 Detection means
52 Error calculation means
53 Element value calculation means
54 Netlist changing means
55 Netlist DB
60 Semiconductor device design equipment
60a CPU
60b ROM
60c RAM
60d HDD
60e GC
60f I / F
60g bath
61 Display device
62 Input device
70 element area
71 rectangle
72 gate polysilicon
73 Contact hole
74 metal layer
80 Diffusion layer
81 contacts

Claims (10)

A detecting step of detecting an element pattern having a remarkable angle from physical data indicating the element pattern formed on the semiconductor substrate,
An error calculating step of calculating an error occurring in the portion having the remarkable angle during exposure,
An element value calculating step of calculating a change in an element value of the element based on the error calculated by the error calculating step;
A semiconductor device design method comprising: 2. The semiconductor device design method according to claim 1, further comprising a net list changing unit for changing an element value included in the net list based on a result of the element value calculating step. 2. The semiconductor device design method according to claim 1, wherein in the error calculating step, the error is calculated with reference to a wavelength of a beam at the time of exposure. 2. The method according to claim 1, wherein in the element value calculating step, a change in an element value caused by the error is calculated as a new element added in parallel to the element. 2. The device according to claim 1, wherein the element is a resistor, a capacitor, or an inductor, and the element value calculating step calculates an error occurring in these elements by referring to the error calculated in the error calculating step. 3. Semiconductor device design method. 2. The method according to claim 1, wherein the element is a transistor, and the element value calculating step calculates an error generated in the transistor by referring to the error calculated in the error calculating step. . 7. The semiconductor device design method according to claim 6, wherein in the element value calculating step, the element value is calculated by paying attention only to the remarkable angle formed on the source side of the transistor. 8. The element value calculating step, when a contact hole exists in the vicinity of the reflex angle and is connected to a power supply wiring, judges that the reflex angle exists on the source side. Semiconductor device design method according to the above. Detecting means for detecting an element pattern having a remarkable angle from physical data indicating an element pattern formed on a semiconductor substrate,
Error calculating means for calculating an error occurring in the portion having the remarkable angle upon exposure,
An element value calculation unit that calculates a change in an element value of the element based on the error calculated by the error calculation unit;
A semiconductor device design apparatus comprising: A detecting step of detecting an element pattern having an excellent angle from physical data indicating the element pattern formed on the semiconductor substrate,
An error calculation step of calculating an error occurring in the portion having the remarkable angle during exposure, an element value calculation step of calculating a change in an element value of the element based on the error calculated by the error calculation step,
A program that causes a computer to function as.

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