JP2004031562A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is improved in reliability by mounting a chip size package on a wiring board where interconnect lines and auxiliary interconnect lines connected as bypasses to them are formed so as to keep the interconnect lines or auxiliary interconnect lines connected, even if either the interconnect lines or auxiliary interconnect lines are disconnected when thermal stress is applied. <P>SOLUTION: The semiconductor device is composed of the package board 2 which is provided with a main face 2a and a rear face and where the interconnect lines 2h and auxiliary interconnect lines 2i connected as bypasses to them are formed, a semiconductor chip mounted on the main face 2a, a plurality of wires 4 connecting the pads of the semiconductor chip to the corresponding connectors 2c of the package board 2, a plurality of solder bumps formed on the rear face, and a sealing part for sealing the semiconductor chip. The auxiliary interconnect lines 2i which are formed as bypasses for the interconnect lines 2h on the main face 2a are provided in a region corresponding to the rear end of the semiconductor chip, so that either the interconnect lines 2h or auxiliary interconnect lines are kept connected even if thermal stress is applied to disconnect either the interconnect lines 2h or auxiliary interconnect lines 2i, and the chip size package can be improved in reliability. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique that is effective when applied to improvement in reliability of thermal characteristics of a semiconductor device. In addition, the present invention relates to a technique which is effective when applied to improve the reliability of electrical characteristics.
[0002]
[Prior art]
The technology described below has been studied by the inventor when researching and completing the present invention, and the outline thereof is as follows.
[0003]
Among semiconductor devices of resin-encapsulated type, a semiconductor package in which a semiconductor chip is mounted on a wiring board and assembled with resin by resin molding is becoming thinner and smaller, and a CSP (Chip Size) has been widely used. A small package called “Package” has been developed.
[0004]
In a substrate type CSP, an organic substrate (wiring substrate) is often used as an interposer. However, as the size of the semiconductor package is reduced, the terminal pitch is becoming finer, and the number of pins tends to increase due to the increase in the number of pins.
[0005]
The semiconductor device having a resin substrate is described in, for example, JP-A-2000-124163.
[0006]
[Problems to be solved by the invention]
In the above technique, the wiring width of the wiring board must be formed as narrow as possible by fine pitching. However, since the thermal expansion coefficient of the copper foil, which is the wiring, and the solder resist, which is the insulating film that covers the surface of the wiring, are different, thermal stress in a thermal cycle test or the like is concentrated on the thin wiring, causing a problem of disconnection. .
[0007]
The present inventor has found that the disconnection mainly occurs on the surface of the wiring board on the chip mounting side (hereinafter, this surface is referred to as a main surface) and in an area corresponding to the edge of the back surface of the semiconductor chip. Was.
[0008]
This is because the strength (rigidity) of the substrate is different between the region where the semiconductor chip is present and the region where the semiconductor chip is not present, so that the amount of heat shrinkage is different between the outside and the inside of the boundary, thereby causing disconnection.
[0009]
An object of the present invention is to provide a semiconductor device for improving reliability and a method for manufacturing the same.
[0010]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0012]
That is, the present invention provides a wiring board having a main surface and a back surface opposite to the main surface, and on which a wiring and an auxiliary wiring electrically connected to the wiring in a bypass manner are formed, and a main surface of the wiring substrate. And a semiconductor chip electrically connected to the connection terminal on the main surface, and a plurality of external terminals provided on the wiring board and electrically connected to the surface electrodes of the semiconductor chip, respectively. And the auxiliary wiring is formed on at least one of the main surface and the back surface of the wiring substrate.
[0013]
Further, the present invention provides a step of preparing a wiring board having a wiring and an auxiliary wiring electrically connected in a bypass shape to the wiring board, and having the auxiliary wiring formed on a main surface thereof; Mounting the semiconductor chip on the wiring board such that the end of the back surface of the semiconductor chip is arranged on the auxiliary wiring on the surface, and connecting the front surface electrode of the semiconductor chip and the corresponding wiring board The method includes a step of connecting to a terminal and a step of sealing the semiconductor chip with a resin.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
In the following embodiments, the description of the same or similar parts will not be repeated in principle unless necessary.
[0015]
Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), a case where it is particularly specified and a case where it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.
[0016]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0017]
FIG. 1 is a perspective view showing a structure of a CSP as an example of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an example of a structure of the CSP shown in FIG. 1, and FIG. FIG. 4 is a plan view showing an example of a wiring pattern on the main surface side of the wiring substrate, FIG. 4 is a bottom view showing an example of a land shape on the back surface side of the wiring substrate shown in FIG. 3, and FIG. 5 is a main surface of the wiring substrate shown in FIG. FIG. 6 is an enlarged partial cross-sectional view showing an example of the structure of lands and solder bumps on the wiring board shown in FIG. 3, and FIG. 7 is used for assembling the CSP shown in FIG. FIG. 8 is a plan view showing an example of the structure of a multi-piece substrate, FIG. 8 is a cross-sectional view showing a structure after wire bonding in assembling the CSP shown in FIG. 1, and FIG. 9 is a structure at the time of resin molding in assembling the CSP shown in FIG. Indicating a break FIG, 10 is a side view showing the structure of a time singulation in the assembly of CSP illustrated in Fig.
[0018]
The semiconductor device of the present embodiment shown in FIGS. 1 and 2 is a small semiconductor package called a CSP 9, and a plurality of solder bumps (bump electrodes) 3 as external terminals are provided on a package substrate 2 serving as a wiring substrate. They are arranged in an array on the back surface 2b in a plurality of rows / a plurality of columns.
[0019]
However, in the CSP 9 shown in FIG. 2, the solder bumps 3 are not arranged near the center of the substrate below the chip, but the solder bumps 3 may be arranged also near this center.
[0020]
The CSP 9 of the present embodiment is assembled using a multi-piece substrate 7 in which a plurality of device regions 7a (regions of a semiconductor device) as shown in FIG. The device region 7a is collectively covered with one cavity 13c of the molding die 13 as shown in FIG. 9 and resin-molded (hereinafter referred to as collective molding), and the collective molding portion 8 formed thereby And the multi-piece substrate 7 are diced into individual pieces after molding.
[0021]
The structure of the CSP 9 will be described. A package which is a wiring board having a main surface 2a and a back surface 2b opposite to the main surface, and on which a wiring 2h and an auxiliary wiring 2i electrically connected in a bypass manner are formed. The substrate 2, the semiconductor chip 1 mounted on the main surface 2 a of the package substrate 2, and the pads 1 a which are surface electrodes of the semiconductor chip 1 and the corresponding connection terminals 2 c of the package substrate 2 are electrically connected to each other. A plurality of wires 4, a plurality of solder bumps (bump electrodes) 3 as external terminals provided on the back surface 2 b of the package substrate 2, and a sealing portion 6 for sealing the semiconductor chip 1 and the plurality of wires 4. The auxiliary wiring 2i of the package substrate 2 is formed in a region corresponding to the end of the back surface 1c of the semiconductor chip 1 on the main surface 2a. In P9, auxiliary wiring 2i is formed on the back surface 2b of the package substrate 2 as shown in FIG.
[0022]
The auxiliary wiring 2i is disconnected when a thermal stress caused by a difference in thermal expansion coefficient between the wiring 2h made of copper foil and the solder resist 2g which is an insulating film covering the surface is applied to the package substrate 2. It solves the problem of doing.
[0023]
That is, the auxiliary wiring 2i is electrically connected at both ends to the main wiring 2h and formed in a bypass shape. When the thermal stress is applied, the auxiliary wiring 2i is formed of the main wiring 2h and the auxiliary wiring 2i. Even if one of them is disconnected, the other remains.
[0024]
Therefore, it is preferable to provide the auxiliary wiring 2i in a place where disconnection due to thermal stress is likely to occur. Therefore, the wiring 2h formed so as to straddle the vicinity of the end of the back surface 1c of the semiconductor chip 1 between the inside and the outside thereof is likely to be disconnected due to the thermal stress. In other words, a large difference occurs in the rigidity of the package substrate 2 between the region where the semiconductor chip 1 is present and the region where the semiconductor chip 1 is not present. The wiring 2h straddling the end of the chip 1) is easily broken.
[0025]
Here, FIGS. 3 and 4 show the wiring patterns of the package substrate 2 of the CSP 9 of the present embodiment, where FIG. 3 shows the main surface 2a and FIG. 4 shows the back surface 2b. .
[0026]
FIGS. 3 to 5 show the wiring patterns of the main surface 2a and the back surface 2b, respectively, but the surface of each of them is insulated except for a part (where the wires 4 and the solder bumps 3 are connected). Although a solder resist 2g, which is a film, is formed, FIGS. 3 to 5 show only the wiring pattern on each surface through the solder resist 2g.
[0027]
As shown in FIG. 3, on the main surface 2a of the package substrate 2, a plurality of via wirings 2j are provided in an array around the outside of the chip mounting area, and further radially outward from each via wiring 2j. The connection terminal 2c to which the wire 4 is connected is formed in the middle of each wiring 2h. Of the wirings 2h on the main surface 2a, bypass auxiliary wirings 2i are formed for four wirings 2h.
[0028]
FIG. 5 shows the chip mountable area on the main surface 2a of the package substrate 2, and the area between the lower limit minimum chip mount area 11 and the upper limit maximum chip mount area 12 is the chip mountable area. Area.
[0029]
As a result, since the end of the back surface 1c of the semiconductor chip 1 is arranged in the area between the minimum chip mounting area 11 and the maximum chip mounting area 12, disconnection easily occurs in the area, and therefore, It is preferable to provide the auxiliary wiring 2i. In the example shown in FIG. 5, four auxiliary wirings 2i are provided in a region between the minimum chip mounting area 11 and the maximum chip mounting area 12.
[0030]
However, the area where the auxiliary wiring 2i is provided is not limited to the area corresponding to the vicinity of the end of the back surface 1c of the semiconductor chip 1, that is, the area between the minimum chip mounting area 11 and the maximum chip mounting area 12. May be provided in other regions, and may be provided not only on the main surface 2a but also on the back surface 2b.
[0031]
FIG. 4 shows the shape of the wiring pattern on the back surface 2b. A plurality of lands 2e to which the solder bumps 3 are connected are arranged in an array in a plurality of rows / columns except for the vicinity of the center. In addition, four auxiliary wirings 2i are formed. Each auxiliary wiring 2i has its inner end directly connected to the land 2e, and is connected to the wiring 2h on the main surface 2a side via a via wiring 2j as shown in FIG.
[0032]
In addition, the vicinity of the end near the outside of the auxiliary wiring 2i formed on the back surface 2b is connected to the wiring 2h on the main surface 2a side through a through-hole wiring or the like, whereby the auxiliary wiring 2i on the back surface 1c side is also connected. It is connected to the wiring 2h of the main surface 2a in a bypass shape.
[0033]
In addition, as in the case of the auxiliary wiring 2i on the back surface 2b in FIG. 4, by forming the wiring width as a whole smaller than the wiring 2h on the main surface 2a, thermal stress is applied to the wiring 2h and the auxiliary wiring 2i. When it is applied, the thinner side may be cut by intentionally concentrating heat stress on the thinner side.
[0034]
That is, when forming the auxiliary wiring 2i on the main surface 2a or the back surface 2b or both surfaces, by changing the wiring width from that of the main wiring 2h, when the thermal stress is applied, the thermal stress is concentrated on the thinner side. The thinner one may be cut off so that the thicker one remains.
[0035]
FIG. 6 shows a land structure of the package substrate 2. The land 2e of the main surface 2a and the back surface 2b are connected via a via wiring 2j. Except for the connection region of each land 2c, a solder resist 2g which is an insulating film is formed.
[0036]
That is, in the package substrate 2, a via paste 2j is formed by embedding a conductive paste or the like in the through-hole 2f formed in the base material 2d, lands 2c are formed on both sides thereof, and the vicinity of the center of each land 2c is formed. The exposed solder resist 2g as an insulating film is formed.
[0037]
As shown in FIG. 2, the semiconductor chip 1 is formed of, for example, silicon or the like, has a semiconductor integrated circuit formed on a main surface 1b thereof, and has a plurality of surface electrodes on a peripheral portion of the main surface 1b. Are formed.
[0038]
Further, the semiconductor chip 1 is fixed to the vicinity of substantially the center of the main surface 2a of the package substrate 2 by a die bonding material 5 which is an adhesive such as an insulating paste material or an insulating film material.
[0039]
Further, the wire 4 connected by wire bonding is, for example, a gold wire, and is connected to the connection terminal 2c on the main surface 2a side of the package substrate 2, whereby the pad 1a of the semiconductor chip 1 is connected to the connection terminal 2c. The corresponding connection terminal 2c of the package substrate 2 is connected.
[0040]
Next, a method for manufacturing the semiconductor device (CSP9) according to the present embodiment will be described.
[0041]
In the method of manufacturing the CSP 9 according to the present embodiment, a plurality of device regions 7a are collectively molded using a multi-piece substrate 7 in which a plurality of device regions 7a are formed in a matrix arrangement, and then, individualized by dicing. Is what you do.
[0042]
First, a multi-piece substrate 7 which is a wiring board shown in FIG. 7 having a wiring 2h and an auxiliary wiring 2i electrically connected thereto in a bypass shape, and having the auxiliary wiring 2i formed on the main surface 2a is provided. prepare.
[0043]
The multi-piece substrate 7 is an aggregate of the package substrates 2 shown in FIGS. 3 and 4, and is an organic substrate.
[0044]
That is, a plurality of device regions 7a partitioned by dicing lines 7b are formed in a matrix array on the multi-piece substrate 7, and are divided into individual package substrates 2 by dicing after batch molding.
[0045]
In each device region 7a, a mark 2k serving as an index of each package substrate 2 is formed at a corner portion on the front and back surfaces thereof.
[0046]
Further, the multi-cavity substrate 7 is provided with a guide hole 7c used for a conveyance guide at the time of assembly.
[0047]
After that, the semiconductor chip 1 is mounted on each device region 7a of the multi-piece substrate 7. In the present embodiment, the semiconductor chip 1 is mounted such that the end of the back surface 1c of the semiconductor chip 1 is arranged on the auxiliary wiring 2i in each device region 7a.
[0048]
At this time, first, a die bonding material 5 is applied to each device region 7a, and the semiconductor chip 1 is fixed via the die bonding material 5.
[0049]
Thereafter, as shown in FIG. 8, wire bonding is performed.
[0050]
Here, as shown in FIG. 2, the pads 1 a of the semiconductor chip 1 and the corresponding connection terminals 2 c of the device region 7 a of the multi-piece substrate 7 are electrically connected by wires 4.
[0051]
Thereafter, collective molding is performed.
[0052]
At this time, as shown in FIG. 9, a plurality of device regions 7a of the multi-piece substrate 7 are collectively covered by a cavity 13c of a mold 13 having an upper mold 13a and a lower mold 13b. A sealing resin is supplied into the cavity 13c while the device region 7a is collectively covered to perform resin sealing.
[0053]
Thereby, the collective molding section 8 shown in FIG. 10 is formed.
[0054]
After that, the solder bumps 3 are mounted on each device region 7ab of the multi-piece substrate 7. In this case, it is also possible to use a solder printing method for bump formation.
[0055]
Thereafter, as shown in FIG. 10, the batch molding unit 8 is cut into individual device regions by using a blade 10 as a cutting blade.
[0056]
Thus, the assembly of the CSP 9 of the present embodiment shown in FIGS. 1 and 2 is completed.
[0057]
The mounting of the solder bumps 3 may be performed after individualization.
[0058]
In the CSP 9 of the present embodiment, since the auxiliary wiring 2i connected in a bypass shape to the wiring 2h is formed on the package substrate 2, which of the wiring 2h and the auxiliary wiring 2i is applied when thermal stress is applied. Even if one of them is disconnected, the other is connected, and it is possible to cover one of the disconnections.
[0059]
Thus, since the wiring 2h is electrically connected, the reliability of the CSP 9 can be improved.
[0060]
In addition, by utilizing the back surface 2b of the package substrate 2 and providing the auxiliary wiring 2i also on the back surface 2b to utilize the wiring area on the front surface and the back surface in various ways, the reliability can be further improved and the voltage can be increased. Accordingly, it is possible to cope with the problem, and as a result, it is possible to improve the electrical characteristics. The present invention can also be applied to wiring design in which inductance, capacitance, resistance, and the like should be considered in terms of electrical characteristics in design.
[0061]
Thus, for example, the CSP 9 can be effectively mounted on a device requiring high durability such as for an automobile, and the safety can be improved and the reliability can be ensured.
[0062]
Further, by providing the auxiliary wiring 2i, the thermal stress can be dispersed to the wiring 2h and the auxiliary wiring 2i, and therefore, the thermal stress applied to one wiring 2h or the auxiliary wiring 2i can be reduced.
[0063]
As a result, it is possible to prevent disconnection.
[0064]
Further, by providing the auxiliary wiring 2i, the arrangement balance of the wiring patterns can be improved. Therefore, the rigidity of the package substrate 2 can be increased, and the warpage of the package substrate 2 can be reduced.
[0065]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment of the invention, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.
[0066]
For example, in the above-described embodiment, the case where the semiconductor device is the CSP 9 is described. However, if the semiconductor device has a wiring board on which the auxiliary wiring 2i is formed, an LGA (Land Grid Array) or the like is used. Is also good.
[0067]
Also, in assembling the semiconductor device, it is not always necessary to perform collective molding. At the time of molding, each device region of the multi-piece substrate 7 is covered with a separate cavity 13c of the mold 13 and resin molding is performed. Alternatively, the semiconductor device may be assembled from a state in which the multi-piece substrate 7 is singulated in advance to form the package substrate 2.
[0068]
Further, in the above-described embodiment, the case where one auxiliary wiring 2i is provided for one wiring 2h has been described, but the number of auxiliary wirings 2i provided for one wiring 2h may be one. Or two or more.
[0069]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0070]
By forming an auxiliary wiring connected in a bypass shape to the wiring on the wiring board, even if one of the wiring and the auxiliary wiring is broken when thermal stress is applied, the other is connected. , One of the disconnections can be covered. Thus, the wiring is electrically connected, so that the reliability of the semiconductor device can be improved. In addition, by adopting this structure in terms of electrical characteristics, design factors such as inductance, capacitance, and resistance on the substrate wiring, general-purpose design becomes possible.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a structure of a CSP which is an example of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a sectional view showing an example of the structure of the CSP shown in FIG.
FIG. 3 is a plan view showing an example of a wiring pattern on a main surface side of the wiring board of the CSP shown in FIG. 1;
FIG. 4 is a bottom view showing an example of a land shape on the back surface side of the wiring board shown in FIG. 3;
FIG. 5 is a plan view showing an example of a chip mountable area on a main surface of the wiring board shown in FIG. 3;
FIG. 6 is an enlarged partial cross-sectional view showing an example of a structure of lands and solder bumps on the wiring board shown in FIG.
FIG. 7 is a plan view showing an example of the structure of a multi-piece substrate used for assembling the CSP shown in FIG.
FIG. 8 is a sectional view showing a structure after wire bonding in assembling the CSP shown in FIG. 1;
FIG. 9 is a cross-sectional view showing a structure during resin molding in assembling the CSP shown in FIG. 1;
10 is a side view showing a structure of the CSP shown in FIG. 1 at the time of singulation.
[Explanation of symbols]
1 semiconductor chip 1a pad (surface electrode)
1b Main surface 1c Back surface 2 Package board (wiring board)
2a Main surface 2b Back surface 2c Connection terminal 2d Base 2e Land 2f Through hole 2g Solder resist 2h Wiring 2i Auxiliary wiring 2j Via wiring 2k Mark 3 Solder bump (bump electrode)
4 Wire 5 Die bond material 6 Sealing part 7 Multi-piece board (wiring board)
Reference numeral 7a Device area 7b Dicing line 7c Guide hole 8 Batch molding section 9 CSP (semiconductor device)
10 Blade 11 Minimum chip mounting area 12 Maximum chip mounting area 13 Mold die 13a Upper die 13b Lower die 13c Cavity

Claims (5)

A wiring board having a main surface and a back surface opposite to the main surface, on which wiring and auxiliary wiring electrically connected in a bypass shape are formed,
A semiconductor chip mounted on a main surface of the wiring board and electrically connected to a connection terminal on the main surface;
A plurality of external terminals provided on the wiring substrate and electrically connected to the surface electrodes of the semiconductor chip, respectively;
The semiconductor device, wherein the auxiliary wiring is formed on at least one of a main surface and a back surface of the wiring substrate. A wiring board having a main surface and a back surface opposite to the main surface, and a wiring and auxiliary wirings both ends of which are electrically connected to the wiring surface formed on the main surface,
A semiconductor chip mounted on a main surface of the wiring board and electrically connected to a connection terminal on the main surface;
A plurality of external terminals provided on the wiring substrate and electrically connected to the surface electrodes of the semiconductor chip, respectively;
The semiconductor device, wherein the auxiliary wiring is formed in a region corresponding to an end of a back surface of the semiconductor chip on a main surface of the wiring substrate. A wiring board having a main surface and a back surface opposite to the main surface, and having a wiring and auxiliary wirings both ends of which are electrically connected thereto,
A semiconductor chip mounted on a main surface of the wiring board and electrically connected to a connection terminal on the main surface;
A plurality of external terminals provided on the wiring substrate and electrically connected to the surface electrodes of the semiconductor chip, respectively;
A semiconductor device, wherein a wiring width is different between the wiring and the auxiliary wiring. A wiring board having a main surface and a back surface opposite to the main surface, and having a wiring and auxiliary wirings both ends of which are electrically connected thereto,
A semiconductor chip mounted on a main surface of the wiring board,
A plurality of wires for electrically connecting the surface electrodes of the semiconductor chip and the corresponding connection terminals of the wiring board, respectively,
A plurality of bump electrodes that are external terminals provided on the back surface of the wiring board,
Having a sealing portion for sealing the semiconductor chip and the plurality of wires,
The semiconductor device, wherein the auxiliary wiring is formed in a region corresponding to an end of a back surface of the semiconductor chip on a main surface of the wiring substrate and a back surface of the wiring substrate. Having a wiring and an auxiliary wiring electrically connected in a bypass shape to the wiring, a step of preparing a wiring board having the auxiliary wiring formed on a main surface,
Mounting the semiconductor chip on the wiring board such that an end of the back surface of the semiconductor chip is arranged on the auxiliary wiring on the main surface of the wiring board;
Connecting a surface electrode of the semiconductor chip and a corresponding connection terminal of the wiring board,
Sealing the semiconductor chip with a resin.

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