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JP2004039756A - Semiconductor device and method and apparatus of manufacturing the same - Google Patents

Semiconductor device and method and apparatus of manufacturing the same Download PDF

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Publication number
JP2004039756A
JP2004039756A JP2002192534A JP2002192534A JP2004039756A JP 2004039756 A JP2004039756 A JP 2004039756A JP 2002192534 A JP2002192534 A JP 2002192534A JP 2002192534 A JP2002192534 A JP 2002192534A JP 2004039756 A JP2004039756 A JP 2004039756A
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semiconductor element
substrate
semiconductor device
fixing material
conductive film
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JP3906914B2 (en
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Kyoko Kiritani
桐谷 恭子
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Sony Corp
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Sony Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

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Abstract

<P>PROBLEM TO BE SOLVED: To prevent the circumferential area of an interposer substrate from warping in the side of semiconductor element due to contraction of an anisotropic conductive film running out from the circumferential area of semiconductor element when it is hardened at the time of mounting semiconductor element on the interposer substrate via the anisotropic conductive film. <P>SOLUTION: An attracting groove 21 is formed to the region corresponding to the external side of the circumferential area of the semiconductor element 16 of a stage 14 for the mounting and the semiconductor element 16 is mounted on the interposer substrate 11 with the anisotropic conductive film 15 while the interposer substrate 11 is attracted with this attracting groove 21. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は半導体装置の製造方法、製造装置、および半導体装置に係り、とくに半導体素子を基板上にマウントして成る半導体装置の製造方法、製造装置、および半導体装置に関する。
【0002】
【従来の技術】
半導体装置の小型化のために、絶縁パッケージを用いない半導体装置が提供される傾向にある。この種の半導体装置はベアチップから成る半導体素子をインターポーザ基板上に直接マウントし、半導体素子のバンプ等の電極をインターポーザ基板の導電性の電極に接続するようにしたものである。従ってこのような半導体装置によって電子回路を形成する場合には、半導体素子をマウントしたインターポーザ基板をマザーボード上に配し、インターポーザ基板の接続用配線手段を介して半導体素子の電極がマザーボードの電極に接続されるようになる。
【0003】
この種の半導体装置の製造方法の一例を図10によって説明する。ここではまずインターポーザ基板1が用意される。インターポーザ基板1はその上にマウントされる半導体素子6よりも一回り大きな寸法を有し、予め配線パターン2や接続用ランド3が形成されている。そしてこのようなインターポーザ基板1を図10Bに示すようにステージ4上に配置するとともに、このインターポーザ基板1の上側に接続固定材料、例えば異方性導電膜5を接合する。そして上からベアチップから成る半導体素子6をマウントし、この半導体素子6の上から加熱および加圧することによって、上記異方性導電膜5を介して半導体素子6のバンプ7がインターポーザ基板1の配線パターン2に電気的に接続される。
【0004】
【発明が解決しようとする課題】
このように従来のインターポーザ基板を用いた半導体装置は、図10に示すように半導体素子6の外部引出し電極上にバンプ7を形成し、そしてインターポーザ基板1上に異方性導電膜5を貼付ける。そしてその上にバンプ7を有する半導体素子6をフリップチップによって仮置きする。そして最後に半導体素子6のバンプ7が形成されている面とは反対側の上面から加圧および加熱することによって、異方性導電膜5を硬化させてフリップチップ接続を行なうようにしていた。
【0005】
ここで図11に示すように半導体素子6の周辺より異方性導電膜5が少しはみ出した状態で硬化される。異方性導電膜は後述するように樹脂と導電性粒子とから構成されているが、この異方性導電膜5の硬化に伴って収縮を起す。従ってインターポーザ基板1は図11に示すように半導体素子6の周縁の近傍において周縁部が上に持上がるように変形する問題がある。
【0006】
上述のような異方性導電膜5の硬化に伴うインターポーザ基板1の周縁部の持上がるような変形は、薄い半導体装置の製造を妨げる原因になっている。またとくにインターポーザ基板1の周縁部であって接続用ランド3が形成されている部分が上に持上がると、この持上がった部分の裏面に形成されている導電性パターンがマザーボードと正しく接続されず、これによって半導体装置の実装の際にトラブルの発生の原因になる。またこのような半導体装置を何段にも積層する際に、上記インターポーザ基板1の周縁部の湾曲変形がトラブルの原因になる可能性がある。
【0007】
本発明はこのような問題点に鑑みてなされたものであって、異方性導電膜等の接続固定材料の硬化の際における収縮に伴う基板の変形を防止するようにした半導体装置の製造方法、製造装置、および半導体装置を提供することを目的とする。
【0008】
【課題を解決するための手段】
半導体装置の製造方法に関する主要な発明は、基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体装置の製造方法において、
前記基板の前記半導体素子の周縁の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域を前記ステージ側に吸着して前記接着固定材料を硬化させることを特徴とする半導体装置の製造方法に関するものである。
【0009】
ここで前記接着固定材料が異方性導電膜から構成され、前記異方性導電膜によって前記半導体素子が前記基板に固定されるとともに、前記半導体素子の電極が前記基板の電極に接続されてよい。また前記ステージ上の前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域に吸引溝が形成され、該吸引溝を通して前記基板が前記ステージ側に吸着されることが好適である。
【0010】
半導体素子の製造装置に関する主要な発明は、基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体素子の製造装置において、
前記基板の前記半導体素子の周縁の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域を前記ステージ側に吸着する吸着手段を具備する半導体素子の製造装置に関するものである。
【0011】
ここで前記吸着手段が前記ステージ上の前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域に形成された吸引溝であってよい。また前記吸着溝が前記半導体素子の側縁の近傍にほぼ沿って配列された電極に対して側方に位置する細長い溝であることが好適である。
【0012】
半導体装置に関する主要な発明は、半導体素子を接着固定材料を介して基板上にマウントして成る半導体装置において、
前記基板の前記半導体素子の周縁部の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域が前記半導体素子がマウントされた面が凹となるように湾曲していることを特徴とする半導体装置に関するものである。
【0013】
ここで前記接着固定材料が異方性導電膜であって、該異方性導電膜によって前記半導体素子が前記基板に固定されるとともに、前記半導体素子の電極が前記基板の電極に接続されるようにすることが好ましい。また上記製造方法の発明によって製造された半導体素子であることが好ましい。また上記製造装置の発明によって製造された半導体装置であることが好ましい。
【0014】
本願に含まれる発明の好ましい態様は、バンプ付き半導体素子とインターポーザ基板基板とフリップチップ接続用固定材料とによって製造される半導体装置において、フリップチップ接続と同時に該フリップチップ接続用固定材料を硬化する際に、フリップチップ接続部を除いた部分のインターポーザ基板を局部的に変形させ、これによってフリップチップ接続すると同時にフリップチップ接続固定材料を硬化することによって、フリップチップ接続用固定材料が硬化後に、インターポーザ基板の変形を極力低減するようにした半導体装置、およびこのような半導体装置の製造方法に関する。
【0015】
このような態様によれば、インターポーザ基板の接続固定材料がはみ出す領域の反りが抑制されることによってマザーボードへの実装や積層による3次元実装等の際の接続が容易に行ない得るようになる。またインターポーザ基板の周縁部の変形が防止されるために電子回路装置の歩留りが高くなって信頼性の向上がもたらされる。またこのことから半導体装置および電子回路装置のコストの低減に寄与するようになる。
【0016】
【発明の実施の形態】
以下本願の発明を図示の実施の形態によって説明する。この実施の形態は図3および図4に示すインターポーザ基板11上に異方性導電膜15を介してベアチップから成る半導体素子16をマウントした半導体装置の製造方法、製造装置、および半導体装置に関する。ここでインターポーザ基板11上には図3および図4に示すように予めその周縁部の近傍において配線パターン12と接続用ランド13とが形成される。
【0017】
このようなインターポーザ基板11上に半導体素子16をマウントするために図1、図2、および図4に示すようなステージ14が用いられる。ステージ14は矩形の板状体から構成されるとともに、例えばその両側には互いに平行に細長い吸引溝21が形成される。またこのような吸引溝21内の空気を吸引するための吸引孔22が上記吸引溝21に連通するように形成される。吸引孔22は真空吸引手段に接続される。
【0018】
このようなステージ14上に図3および図4Bに示すようにインターポーザ基板11を装着する。なお図4Aに示すように、インターポーザ基板11上には予め異方性導電膜15が接合されている。これに対して半導体素子16にはその電極の部分の上側にバンプ17がマウントされている。そしてこのようなバンプ17を有する半導体素子16を異方性導電膜15を介してインターポーザ基板11に対して加熱しながら加圧することによって、図5に示すような半導体装置が製作される。
【0019】
このような半導体装置は、半導体素子16の電極をバンプ17を介してインターポーザ基板11の配線パターン12に接続している。
【0020】
このような半導体装置の製造に際し、とくに半導体素子16をインターポーザ基板11に異方性導電膜15を介して接続する際に、ステージ14に形成された吸引溝21によってインターポーザ基板11の下面であってとくに半導体素子16のバンプ17が形成されている部分よりも側方であってインターポーザ基板11の接続用ランド13が形成されている部分を下方に吸引しながら異方性導電膜15を硬化させるようにしている。
【0021】
このように吸引溝21によってインターポーザ基板11を吸引しながら異方性導電膜15を硬化することによって、このようなインターポーザ基板11の周縁部の変形が防止される。すなわち異方性導電膜15の硬化の際に半導体素子16の周縁部からはみ出した部分が収縮するために、インターポーザ基板11の周縁部であってとくに図3に示す接続用ランド13の側方の部分が反るように変形を起し易い。ところがこのような変形が上述のステージ14の吸引溝21による吸引固定によって確実に防止される。
【0022】
ここで半導体素子16とインターポーザ基板11との接続は、図6〜図8に示す異方性導電膜(ACF Anisotorpic conductive film)15によって行なわれる。異方性導電膜15は図6に示すようにエポキシ樹脂等のマトリックス樹脂から構成されるとともに、その中に導電粒子25を分散させたものである。ここでそれぞれの導電粒子25は図7に示すように球状をなすとともに、その外周部に金属メッキから成る金属層26が形成され、さらにその外周面を覆うように薄い絶縁被膜27が形成されている。
【0023】
このような異方性導電膜15を半導体素子16とインターポーザ基板11との間に介在させて加熱および加圧を行なうと、図8に示すように半導体素子16の電極を構成するバンプ17とインターポーザ基板11の配線パターン12との間においてこれらのバンプ17、12の高さによって導電粒子25が押潰され、外側の絶縁被膜27が破壊されて金属層26が露出する。これによって導電粒子25による半導体素子16のバンプ17とインターポーザ基板11の配線パターン12との電気的な接続が達成される。これに対してバンプ17および配線パターン12が存在しない領域においては、半導体素子16とインターポーザ基板11との間の隙間が大きいために導電粒子25は球状の形態をそのまま維持し、外周面の絶縁被膜27によって短絡が防止される。すなわち樹脂バンプ17、配線パターン12以外の領域における導通が阻止され、これによって選択的な電気的接続が達成される。
【0024】
このように異方性導電膜15は、半導体素子16とインターポーザ基板11との接合、両者のバンプ17および配線パターン12の導通、および両者のバンプ17および配線パターン12が形成されていない領域の絶縁の3つの機能を同時に達成することになる。すなわち異方性導電膜15を半導体素子16とインターポーザ基板11とによって挟着した状態で熱圧着を行なうと、異方性導電膜15の厚さ方向には導電性を有し、面方向には絶縁性を有する電気的異方性を発現する。これによって対向するバンプ17と配線パターン12間の永久接着と、バンプ17、配線パターン12間の導通と、バンプ17および配線パターン12が形成されていない領域における半導体素子16とインターポーザ基板11の絶縁が同時に達成される。
【0025】
このように本実施の形態においては図3および図4に示すように半導体素子16の外部引出し電極上にバンプ17を形成する。一方インターポーザ基板11上には異方性導電膜15を貼付けておく。そしてこのようなインターポーザ基板11をステージ14上に装着した状態でバンプ17を有する半導体素子16をフリップチップによって仮置きする。この後に半導体素子16のバンプ17が形成されている面とは反対側の面から図4Bに示すように加熱および加圧することによって、異方性導電膜15を硬化させてフリップチップ接続を行なう。
【0026】
このようなフリップチップ接続の際に、フリップチップボンダのステージ14において、半導体素子16の周縁部の異方性導電膜15のはみ出し部と対応する部分のみを吸着するように吸引溝21を予め形成しておき、異方性導電膜15がはみ出す部分と対応する部分を吸引孔22および吸引溝21によって図9に示すように下方に吸引してインターポーザ基板11の当該部分が下に凸になるように、すなわち半導体素子16をマウントした上面が凹になるように変形させる。すると異方性導電膜15が硬化する際にこの異方性導電膜15が収縮しても、この収縮を湾曲するインターポーザ基板11の変形による弾性復元力の反力で相殺することができ、インターポーザ基板11のとくに接続用ランド13が形成されている側端側の部分が上方に変形することが防止される。
【0027】
ステージ14の吸引溝21によってインターポーザ基板11を局部的に吸引し、図9に示すように該吸引溝21の幅の部分を下方に凸になるように変形させると、インターポーザ基板11には当該部分に下に凸の湾曲したリブが形成される。このようなリブは図3から明らかなように半導体素子16のバンプ17が形成されている周縁部に沿って長く形成され、このようなリブがインターポーザ基板11の周縁部に剛性を付与するために、インターポーザ基板11が変形し難くなって基板形状をよりフラットにすることができる。
【0028】
また異方性導電膜15のはみ出し部分と対応する領域においてインターポーザ基板11を吸引することにより、インターポーザ基板11を積極的にその部分を変形させることが可能になる。そしてこのようなステージ14の吸引溝21の吸引圧およびこの吸引溝21の深さや掘り込み幅を変えることによって、インターポーザ基板11の変形量の調整が可能になり、インターポーザ基板11の全体としての平坦化を図ることが可能になる。
【0029】
なおこのような半導体装置において、とくに半導体素子16のバンプ17は、半導体素子16が例えば15.0×10.5×0.1mmの寸法の場合に、その上に形成される電極は直径が50〜100μmで高さが10〜50μmのバンプであってよい。またインターポーザ基板11上に異方性導電膜15を仮付けする。このときにインターポーザ基板11はフレキシブル基板でもリジット基板でもよいが、とくにインターポーザ基板11の変形の問題が発生するのは、基板11の厚さが100μm以下の場合である。従って100μm以下のインターポーザ基板上に半導体素子16をフリップチップ実装によって接合する際にステージ14上に吸引溝21を形成して吸引し、これによってインターポーザ基板11の変形を防止することが好ましい。このような接合は、半導体素子16の上面から加熱および加圧することによって異方性導電膜15を硬化させ、半導体素子16をインターポーザ基板11にフリップチップ接続により行なう。このときの半導体素子16に印加される温度は100〜250℃であり、加圧力は10〜20kgf程度である。また加熱および加圧時間は3〜60s程度である。
【0030】
このようにしてフリップチップ接続を行なうステージ14上に形成される吸引溝21の形状は、その深さが例えば100μmで、幅が1mmで、吸引圧が30mHgである。またここで吸引溝21の位置は、半導体素子16の短辺側の2個所のみを吸引すればよい。このような吸引によって今まで周縁部が200μm程度上に変形していたインターポーザ基板11の変形量が、50μm程度の変形量に抑えることができるようになり、1/3以下に変形が抑えられることが実験によって確認されている。
【0031】
以上本願発明を図示の実施の形態によって説明したが、本願発明は上記実施の形態によって限定されることなく、本願に含まれる発明の技術的思想の範囲内で各種の変更が可能である。例えば上記実施の形態においては半導体素子16とインターポーザ基板11との接合に異方性導電膜を用いたが、本願発明における接続固定材料は必ずしも異方性導電膜に限られることなく、ACP(Anisotorpic conductive paste)、NCF(Non conductive film)、NCP(Non conductive paste)等の別の接続固定材料を用いることも可能である。またステージ14上に形成される吸引溝の位置、あるいはまたインターポーザ基板11の変形位置は上記実施の形態に限られることなく、別の位置にもさらに吸引溝21によって断面弓形の変形を意図的に形成してもよい。
【0032】
【発明の効果】
半導体装置の製造方法に関する主要な発明は、基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体装置の製造方法において、基板の半導体素子の周縁の近傍であって接着固定材料が半導体素子の周縁からはみ出す部分と対応する領域をステージ側に吸着して接着固定材料を硬化させるようにしたものである。
【0033】
従ってこのような半導体装置の製造方法によれば、接着固定材料が硬化される際の収縮による基板の変形をステージ側に吸着することによって防止することができ、とくに基板の変形が効果的に防止される。
【0034】
半導体素子の製造装置に関する発明は、基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体素子の製造装置において、基板の半導体素子の周縁の近傍であって接着固定材料が半導体素子の周縁からはみ出す部分と対応する領域をステージ側に吸着する吸着手段を具備するものである。
【0035】
従ってこのような半導体素子の製造装置によれば、ステージ側に吸着する吸着手段によって接着固定材料が硬化する際の基板の変形を確実に防止するようにした半導体素子の製造装置が提供される。
【0036】
半導体装置に関する主要な発明は、半導体素子を接着固定材料を介して基板上にマウントして成る半導体装置において、基板の半導体素子の周縁部の近傍であって接着固定材料が半導体素子の周縁からはみ出す部分と対応する領域が半導体素子がマウントされた面が凹となるように湾曲しているものである。
【0037】
従ってこのような半導体装置によれば、上記基板の湾曲している部分の変形の弾性復元力によって接着固定材料の硬化に伴う収縮を相殺することが可能になるとともに、基板の湾曲している部分のリブ効果によって基板の剛性が高まり、これによって基板の変形がより確実に防止される。
【図面の簡単な説明】
【図1】半導体装置を製造するためのステージの平面図である。
【図2】図1におけるA−A線断面図である。
【図3】ステージ上において半導体素子をインターポーザ基板上にマウントしている状態を示す平面図である。
【図4】ステージ上においてインターポーザ基板に半導体素子を実装する動作を示す要部縦断面図である。
【図5】図4に示す方法によって製造された半導体装置の縦断面図であって、図3におけるB−B線断面図である。
【図6】異方性導電膜の拡大断面図である。
【図7】異方性導電膜に分散された樹脂粒子の拡大断面図である。
【図8】異方性導電膜による電気的な接続の動作を示す拡大断面図である。
【図9】ステージの吸引溝による吸引動作の原理を示す要部拡大断面図である。
【図10】従来の半導体装置の製造方法を示す要部縦断面図である。
【図11】従来の方法によって製造された半導体装置の縦断面図である。
【符号の説明】
1‥‥インターポーザ基板、2‥‥配線パターン、3‥‥接続用ランド、4‥‥ステージ、5‥‥異方性導電膜、6‥‥半導体素子(ベアチップ)、7‥‥バンプ、11‥‥インターポーザ基板、12‥‥配線パターン、13‥‥接続用ランド、14‥‥ステージ、15‥‥異方性導電膜、16‥‥半導体素子(ベアチップ)、17‥‥バンプ、21‥‥吸引溝、22‥‥吸引孔、25‥‥導電粒子、26‥‥金属層、27‥‥絶縁被膜
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, a manufacturing apparatus, and a semiconductor device, and more particularly to a method, a manufacturing apparatus, and a semiconductor device of a semiconductor device in which a semiconductor element is mounted on a substrate.
[0002]
[Prior art]
In order to reduce the size of semiconductor devices, there is a tendency to provide semiconductor devices that do not use an insulating package. In this type of semiconductor device, a semiconductor element formed of a bare chip is directly mounted on an interposer substrate, and electrodes such as bumps of the semiconductor element are connected to conductive electrodes of the interposer substrate. Therefore, when an electronic circuit is formed by such a semiconductor device, an interposer substrate on which a semiconductor element is mounted is arranged on a motherboard, and the electrodes of the semiconductor element are connected to the electrodes of the motherboard via wiring means for connection of the interposer substrate. Will be done.
[0003]
An example of a method for manufacturing this type of semiconductor device will be described with reference to FIG. Here, first, the interposer substrate 1 is prepared. The interposer substrate 1 has a dimension slightly larger than the semiconductor element 6 mounted thereon, and the wiring pattern 2 and the connection lands 3 are formed in advance. Then, such an interposer substrate 1 is arranged on the stage 4 as shown in FIG. 10B, and a connection fixing material, for example, an anisotropic conductive film 5 is joined to the upper side of the interposer substrate 1. Then, the semiconductor element 6 composed of a bare chip is mounted from above, and the semiconductor element 6 is heated and pressed from above, so that the bumps 7 of the semiconductor element 6 are interposed via the anisotropic conductive film 5 and the wiring pattern of the interposer substrate 1. 2 is electrically connected.
[0004]
[Problems to be solved by the invention]
As described above, in the conventional semiconductor device using the interposer substrate, the bump 7 is formed on the external lead electrode of the semiconductor element 6 and the anisotropic conductive film 5 is attached on the interposer substrate 1 as shown in FIG. . Then, the semiconductor element 6 having the bumps 7 thereon is temporarily placed by flip chip. Finally, the anisotropic conductive film 5 is hardened by applying pressure and heat from the upper surface of the semiconductor element 6 opposite to the surface on which the bumps 7 are formed, thereby performing flip-chip connection.
[0005]
Here, as shown in FIG. 11, the anisotropic conductive film 5 is hardened in a state where it slightly protrudes from the periphery of the semiconductor element 6. The anisotropic conductive film is composed of a resin and conductive particles as described later, and contracts as the anisotropic conductive film 5 cures. Therefore, there is a problem that the interposer substrate 1 is deformed such that the peripheral portion is lifted up near the peripheral edge of the semiconductor element 6 as shown in FIG.
[0006]
The deformation such as the lifting of the peripheral portion of the interposer substrate 1 accompanying the curing of the anisotropic conductive film 5 as described above is a factor that hinders the manufacture of a thin semiconductor device. In particular, when the portion on the periphery of the interposer substrate 1 where the connection lands 3 are formed is lifted upward, the conductive pattern formed on the back surface of the raised portion is not correctly connected to the motherboard. This causes trouble when mounting the semiconductor device. Further, when stacking such semiconductor devices in multiple layers, there is a possibility that the curved deformation of the peripheral portion of the interposer substrate 1 may cause a trouble.
[0007]
The present invention has been made in view of such problems, and a method of manufacturing a semiconductor device in which deformation of a substrate due to shrinkage during curing of a connection fixing material such as an anisotropic conductive film is prevented. , A manufacturing apparatus, and a semiconductor device.
[0008]
[Means for Solving the Problems]
A major invention relating to a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material.
A region near the periphery of the semiconductor element on the substrate and corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element is attracted to the stage side to cure the adhesive fixing material. The present invention relates to a method for manufacturing a semiconductor device.
[0009]
Here, the adhesive fixing material may be formed of an anisotropic conductive film, and the semiconductor element may be fixed to the substrate by the anisotropic conductive film, and an electrode of the semiconductor element may be connected to an electrode of the substrate. . Further, it is preferable that a suction groove is formed in a region corresponding to a portion where the adhesive fixing material protrudes from a peripheral edge of the semiconductor element on the stage, and the substrate is sucked toward the stage through the suction groove.
[0010]
A major invention related to a semiconductor device manufacturing apparatus is a semiconductor element manufacturing apparatus in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material.
The present invention relates to an apparatus for manufacturing a semiconductor device, comprising: suction means for suctioning, to the stage side, a region near the periphery of the semiconductor element on the substrate and corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element. is there.
[0011]
Here, the suction means may be a suction groove formed in a region corresponding to a portion on the stage where the adhesive fixing material protrudes from a peripheral edge of the semiconductor element. Further, it is preferable that the suction groove is an elongated groove positioned laterally with respect to electrodes arranged substantially along the vicinity of a side edge of the semiconductor element.
[0012]
The main invention relating to a semiconductor device is a semiconductor device in which a semiconductor element is mounted on a substrate via an adhesive fixing material,
A region near the periphery of the semiconductor element of the substrate and corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element is curved such that the surface on which the semiconductor element is mounted is concave. The present invention relates to a semiconductor device characterized by the above.
[0013]
Here, the adhesive fixing material is an anisotropic conductive film, and the semiconductor element is fixed to the substrate by the anisotropic conductive film, and an electrode of the semiconductor element is connected to an electrode of the substrate. Is preferable. Further, it is preferable that the semiconductor device is manufactured by the manufacturing method of the present invention. Further, it is preferable that the semiconductor device is manufactured by the invention of the manufacturing apparatus.
[0014]
In a preferred embodiment of the invention included in the present application, in a semiconductor device manufactured by using a semiconductor element with bumps, an interposer substrate, and a fixing material for flip chip connection, the method for curing the fixing material for flip chip connection simultaneously with flip chip connection Then, by partially deforming the interposer substrate except for the flip-chip connection portion, thereby curing the flip-chip connection fixing material at the same time as flip-chip connection, the interposer substrate is cured after the flip-chip connection fixing material is cured. The present invention relates to a semiconductor device in which deformation of the semiconductor device is reduced as much as possible, and a method for manufacturing such a semiconductor device.
[0015]
According to such an embodiment, the warpage of the region of the interposer substrate from which the connection fixing material protrudes is suppressed, so that connection can be easily performed in mounting on a motherboard or three-dimensional mounting by lamination. Further, since the peripheral portion of the interposer substrate is prevented from being deformed, the yield of the electronic circuit device is increased, and the reliability is improved. This also contributes to a reduction in the cost of the semiconductor device and the electronic circuit device.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to the illustrated embodiments. This embodiment relates to a method of manufacturing a semiconductor device in which a semiconductor element 16 made of a bare chip is mounted on an interposer substrate 11 shown in FIGS. 3 and 4 via an anisotropic conductive film 15, a manufacturing apparatus, and a semiconductor device. Here, as shown in FIGS. 3 and 4, a wiring pattern 12 and a connection land 13 are formed on the interposer substrate 11 in the vicinity of the periphery thereof in advance.
[0017]
In order to mount the semiconductor element 16 on such an interposer substrate 11, a stage 14 as shown in FIGS. 1, 2 and 4 is used. The stage 14 is formed of a rectangular plate, and for example, elongated suction grooves 21 are formed on both sides thereof in parallel with each other. Further, a suction hole 22 for sucking the air in the suction groove 21 is formed so as to communicate with the suction groove 21. The suction holes 22 are connected to vacuum suction means.
[0018]
The interposer substrate 11 is mounted on such a stage 14 as shown in FIGS. 3 and 4B. As shown in FIG. 4A, an anisotropic conductive film 15 is bonded on the interposer substrate 11 in advance. On the other hand, a bump 17 is mounted on the semiconductor element 16 above the electrode. Then, the semiconductor element 16 having such bumps 17 is heated and pressed against the interposer substrate 11 via the anisotropic conductive film 15 to produce a semiconductor device as shown in FIG.
[0019]
In such a semiconductor device, the electrodes of the semiconductor element 16 are connected to the wiring patterns 12 of the interposer substrate 11 via the bumps 17.
[0020]
In the manufacture of such a semiconductor device, particularly when the semiconductor element 16 is connected to the interposer substrate 11 via the anisotropic conductive film 15, the lower surface of the interposer substrate 11 is formed by the suction groove 21 formed in the stage 14. In particular, the anisotropic conductive film 15 is cured while sucking downward the portion of the interposer substrate 11 where the connection lands 13 are formed on the side of the semiconductor element 16 where the bumps 17 are formed. I have to.
[0021]
By thus hardening the anisotropic conductive film 15 while sucking the interposer substrate 11 by the suction groove 21, deformation of the peripheral portion of the interposer substrate 11 is prevented. That is, when the anisotropic conductive film 15 is cured, the portion protruding from the peripheral portion of the semiconductor element 16 shrinks, so that the peripheral portion of the interposer substrate 11, particularly the side of the connection land 13 shown in FIG. It is easy to deform so that the part is warped. However, such deformation is reliably prevented by the suction and fixing by the suction groove 21 of the stage 14 described above.
[0022]
Here, the connection between the semiconductor element 16 and the interposer substrate 11 is made by an anisotropic conductive film (ACF Anisotropic conductive film) 15 shown in FIGS. The anisotropic conductive film 15 is made of a matrix resin such as an epoxy resin as shown in FIG. 6, and has conductive particles 25 dispersed therein. Here, each of the conductive particles 25 has a spherical shape as shown in FIG. 7, a metal layer 26 made of metal plating is formed on the outer periphery thereof, and a thin insulating film 27 is further formed to cover the outer peripheral surface thereof. I have.
[0023]
When heating and pressurization are performed with such an anisotropic conductive film 15 interposed between the semiconductor element 16 and the interposer substrate 11, as shown in FIG. The conductive particles 25 are crushed by the height of these bumps 17 and 12 between the wiring pattern 12 of the substrate 11 and the outer insulating coating 27 is destroyed and the metal layer 26 is exposed. As a result, electrical connection between the bumps 17 of the semiconductor element 16 and the wiring patterns 12 of the interposer substrate 11 by the conductive particles 25 is achieved. On the other hand, in a region where the bump 17 and the wiring pattern 12 do not exist, the gap between the semiconductor element 16 and the interposer substrate 11 is large. 27 prevents a short circuit. That is, conduction in regions other than the resin bumps 17 and the wiring patterns 12 is prevented, thereby achieving selective electrical connection.
[0024]
As described above, the anisotropic conductive film 15 joins the semiconductor element 16 to the interposer substrate 11, conducts the bumps 17 and the wiring patterns 12 of both, and insulates the regions where the bumps 17 and the wiring patterns 12 are not formed. The three functions are simultaneously achieved. That is, when thermocompression bonding is performed in a state where the anisotropic conductive film 15 is sandwiched between the semiconductor element 16 and the interposer substrate 11, the anisotropic conductive film 15 has conductivity in the thickness direction, and has conductivity in the surface direction. It exhibits electrical anisotropy with insulation properties. As a result, permanent bonding between the opposing bumps 17 and the wiring pattern 12, conduction between the bumps 17 and the wiring pattern 12, and insulation between the semiconductor element 16 and the interposer substrate 11 in a region where the bump 17 and the wiring pattern 12 are not formed are achieved. Achieved at the same time.
[0025]
As described above, in the present embodiment, the bumps 17 are formed on the external lead electrodes of the semiconductor element 16 as shown in FIGS. On the other hand, an anisotropic conductive film 15 is pasted on the interposer substrate 11. Then, with the interposer substrate 11 mounted on the stage 14, the semiconductor element 16 having the bumps 17 is temporarily placed by flip chip. Thereafter, as shown in FIG. 4B, the anisotropic conductive film 15 is cured by applying heat and pressure from the surface of the semiconductor element 16 opposite to the surface on which the bumps 17 are formed, and flip-chip connection is performed.
[0026]
At the time of such flip-chip connection, the suction groove 21 is formed in advance on the stage 14 of the flip-chip bonder so that only the portion corresponding to the protruding portion of the anisotropic conductive film 15 on the periphery of the semiconductor element 16 is suctioned. In addition, a portion corresponding to the portion where the anisotropic conductive film 15 protrudes is sucked downward by the suction hole 22 and the suction groove 21 as shown in FIG. 9 so that the portion of the interposer substrate 11 becomes convex downward. That is, the upper surface on which the semiconductor element 16 is mounted is deformed so as to be concave. Then, even if the anisotropic conductive film 15 contracts when the anisotropic conductive film 15 cures, the contraction can be offset by the reaction force of the elastic restoring force due to the deformation of the curved interposer substrate 11, The portion on the side end side of the substrate 11 where the connection lands 13 are formed is prevented from being deformed upward.
[0027]
When the interposer substrate 11 is locally sucked by the suction groove 21 of the stage 14 and the width of the suction groove 21 is deformed so as to protrude downward as shown in FIG. A downwardly curved rib is formed at the bottom. As shown in FIG. 3, such ribs are formed to be long along the peripheral portion of the semiconductor element 16 where the bumps 17 are formed. In order to provide rigidity to the peripheral portion of the interposer substrate 11, In addition, the interposer substrate 11 is hardly deformed, and the substrate shape can be made flatter.
[0028]
Further, by sucking the interposer substrate 11 in a region corresponding to the protruding portion of the anisotropic conductive film 15, the interposer substrate 11 can be positively deformed. The deformation amount of the interposer substrate 11 can be adjusted by changing the suction pressure of the suction groove 21 of the stage 14 and the depth and the dug width of the suction groove 21, and the flatness of the entire interposer substrate 11 can be adjusted. Can be achieved.
[0029]
In such a semiconductor device, in particular, when the semiconductor element 16 has a size of 15.0 × 10.5 × 0.1 mm, for example, the bump 17 of the semiconductor element 16 has an electrode formed thereon with a diameter of 50 mm. The bump may be 100100 μm and 10-50 μm in height. Further, an anisotropic conductive film 15 is temporarily attached on the interposer substrate 11. At this time, the interposer substrate 11 may be a flexible substrate or a rigid substrate, but the problem of deformation of the interposer substrate 11 particularly occurs when the thickness of the substrate 11 is 100 μm or less. Therefore, when the semiconductor element 16 is bonded to an interposer substrate of 100 μm or less by flip-chip mounting, it is preferable to form the suction groove 21 on the stage 14 and suck the semiconductor device 16, thereby preventing the deformation of the interposer substrate 11. Such bonding is performed by applying heat and pressure from the upper surface of the semiconductor element 16 to cure the anisotropic conductive film 15 and connecting the semiconductor element 16 to the interposer substrate 11 by flip-chip connection. At this time, the temperature applied to the semiconductor element 16 is 100 to 250 ° C., and the pressure is about 10 to 20 kgf. The heating and pressurizing time is about 3 to 60 s.
[0030]
The shape of the suction groove 21 formed on the stage 14 for performing the flip-chip connection in this manner has a depth of, for example, 100 μm, a width of 1 mm, and a suction pressure of 30 mHg. In this case, the position of the suction groove 21 may be such that only the two short sides of the semiconductor element 16 are sucked. By such suction, the deformation amount of the interposer substrate 11 whose peripheral portion has been deformed up to about 200 μm can be suppressed to about 50 μm, and the deformation is suppressed to 1/3 or less. Has been confirmed by experiment.
[0031]
Although the invention of the present application has been described with reference to the illustrated embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made within the technical idea of the invention included in the present application. For example, in the above embodiment, an anisotropic conductive film is used for joining the semiconductor element 16 and the interposer substrate 11, but the connection fixing material in the present invention is not necessarily limited to the anisotropic conductive film, but may be an ACP (Anisotopic). It is also possible to use another connection fixing material such as a conductive paste, an NCF (Non conductive film), or an NCP (Non conductive paste). In addition, the position of the suction groove formed on the stage 14 or the deformation position of the interposer substrate 11 is not limited to the above-described embodiment. It may be formed.
[0032]
【The invention's effect】
A main invention relating to a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material. A region near the portion where the adhesive fixing material protrudes from the periphery of the semiconductor element is attracted to the stage side to cure the adhesive fixing material.
[0033]
Therefore, according to such a method of manufacturing a semiconductor device, deformation of the substrate due to shrinkage when the adhesive fixing material is cured can be prevented by adsorbing to the stage side, and particularly, deformation of the substrate is effectively prevented. Is done.
[0034]
An invention related to a semiconductor device manufacturing apparatus is a semiconductor device manufacturing apparatus in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material. There is provided suction means for sucking, to the stage side, a region corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element.
[0035]
Therefore, according to such an apparatus for manufacturing a semiconductor element, there is provided an apparatus for manufacturing a semiconductor element in which the substrate is reliably prevented from being deformed when the adhesive fixing material is hardened by the suction means that is suctioned to the stage side.
[0036]
A main invention relating to a semiconductor device is a semiconductor device in which a semiconductor element is mounted on a substrate via an adhesive fixing material, wherein the adhesive fixing material protrudes from the periphery of the semiconductor element in the vicinity of the peripheral portion of the semiconductor element on the substrate. The region corresponding to the portion is curved such that the surface on which the semiconductor element is mounted is concave.
[0037]
Therefore, according to such a semiconductor device, the elastic restoring force of the deformation of the curved portion of the substrate makes it possible to cancel the shrinkage due to the curing of the adhesive fixing material, and at the same time, the curved portion of the substrate The rigidity of the substrate is increased by the rib effect, and the deformation of the substrate is more reliably prevented.
[Brief description of the drawings]
FIG. 1 is a plan view of a stage for manufacturing a semiconductor device.
FIG. 2 is a sectional view taken along line AA in FIG.
FIG. 3 is a plan view showing a state where a semiconductor element is mounted on an interposer substrate on a stage.
FIG. 4 is an essential part longitudinal cross sectional view showing an operation of mounting a semiconductor element on an interposer substrate on a stage.
5 is a longitudinal sectional view of the semiconductor device manufactured by the method shown in FIG. 4, and is a sectional view taken along the line BB in FIG. 3;
FIG. 6 is an enlarged sectional view of an anisotropic conductive film.
FIG. 7 is an enlarged cross-sectional view of resin particles dispersed in an anisotropic conductive film.
FIG. 8 is an enlarged sectional view showing an operation of electrical connection by an anisotropic conductive film.
FIG. 9 is an enlarged sectional view of a main part showing a principle of a suction operation by a suction groove of a stage.
FIG. 10 is a vertical sectional view showing a main part of a conventional method for manufacturing a semiconductor device.
FIG. 11 is a longitudinal sectional view of a semiconductor device manufactured by a conventional method.
[Explanation of symbols]
1 {interposer substrate, 2} wiring pattern, 3} connection land, 4 # stage, 5 # anisotropic conductive film, 6 # semiconductor element (bare chip), 7 # bump, 11 # Interposer substrate, 12 wiring pattern, 13 connection land, 14 stage, 15 anisotropic conductive film, 16 semiconductor element (bare chip), 17 bump, 21 suction groove, 22 ‥‥ suction hole, 25 ‥‥ conductive particles, 26 ‥‥ metal layer, 27 ‥‥ insulation coating

Claims (10)

基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体装置の製造方法において、
前記基板の前記半導体素子の周縁の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域を前記ステージ側に吸着して前記接着固定材料を硬化させることを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material,
A region near the periphery of the semiconductor element on the substrate and corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element is attracted to the stage side to cure the adhesive fixing material. A method for manufacturing a semiconductor device.
前記接着固定材料が異方性導電膜から構成され、前記異方性導電膜によって前記半導体素子が前記基板に固定されるとともに、前記半導体素子の電極が前記基板の電極に接続されることを特徴とする請求項1に記載の半導体装置の製造方法。The adhesive fixing material is composed of an anisotropic conductive film, the semiconductor element is fixed to the substrate by the anisotropic conductive film, and an electrode of the semiconductor element is connected to an electrode of the substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein 前記ステージ上の前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域に吸引溝が形成され、該吸引溝を通して前記基板が前記ステージ側に吸着されることを特徴とする請求項1に記載の半導体装置の製造方法。2. A suction groove is formed in a region corresponding to a portion where the adhesive fixing material protrudes from a peripheral edge of the semiconductor element on the stage, and the substrate is suctioned to the stage through the suction groove. 13. The method for manufacturing a semiconductor device according to claim 1. 基板をステージ上に配し、接着固定材料を介して半導体素子を基板上にマウントするようにした半導体素子の製造装置において、
前記基板の前記半導体素子の周縁の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域を前記ステージ側に吸着する吸着手段を具備する半導体素子の製造装置。
In a semiconductor device manufacturing apparatus in which a substrate is arranged on a stage and a semiconductor element is mounted on the substrate via an adhesive fixing material,
An apparatus for manufacturing a semiconductor device, comprising: suction means for sucking, on the stage side, a region near the periphery of the semiconductor element on the substrate, the area corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element.
前記吸着手段が前記ステージ上の前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域に形成された吸引溝であることを特徴とする請求項4に記載の半導体装置の製造装置。5. The apparatus according to claim 4, wherein the suction means is a suction groove formed in a region corresponding to a portion of the stage on which the adhesive fixing material protrudes from a peripheral edge of the semiconductor element. 前記吸着溝が前記半導体素子の側縁の近傍にほぼ沿って配列された電極に対して側方に位置する細長い溝であることを特徴とする請求項4に記載の半導体装置。5. The semiconductor device according to claim 4, wherein said at least one suction groove is an elongated groove located on a side of an electrode arranged substantially along a side edge of said semiconductor element. 半導体素子を接着固定材料を介して基板上にマウントして成る半導体装置において、
前記基板の前記半導体素子の周縁部の近傍であって前記接着固定材料が前記半導体素子の周縁からはみ出す部分と対応する領域が前記半導体素子がマウントされた面が凹となるように湾曲していることを特徴とする半導体装置。
In a semiconductor device in which a semiconductor element is mounted on a substrate via an adhesive fixing material,
A region near the periphery of the semiconductor element of the substrate and corresponding to a portion where the adhesive fixing material protrudes from the periphery of the semiconductor element is curved such that the surface on which the semiconductor element is mounted is concave. A semiconductor device characterized by the above-mentioned.
前記接着固定材料が異方性導電膜であって、該異方性導電膜によって前記半導体素子が前記基板に固定されるとともに、前記半導体素子の電極が前記基板の電極に接続されることを特徴とする請求項7に記載の半導体装置。The adhesive fixing material is an anisotropic conductive film, and the semiconductor element is fixed to the substrate by the anisotropic conductive film, and an electrode of the semiconductor element is connected to an electrode of the substrate. The semiconductor device according to claim 7, wherein 請求項1〜請求項3の何れかの製造方法によって製造されたことを特徴とする半導体装置。A semiconductor device manufactured by the manufacturing method according to claim 1. 請求項4〜請求項6の何れかの製造装置によって製造されたことを特徴とする半導体装置。A semiconductor device manufactured by the manufacturing apparatus according to claim 4.
JP2002192534A 2002-07-01 2002-07-01 Semiconductor device manufacturing method and semiconductor device Expired - Fee Related JP3906914B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006030260A (en) * 2004-07-12 2006-02-02 Seiko Epson Corp Semiconductor element mounting substrate, semiconductor element mounting substrate manufacturing method, mounting apparatus, mounting method, electro-optical device, electronic device
JP2006222286A (en) * 2005-02-10 2006-08-24 Matsushita Electric Ind Co Ltd Component mounting apparatus and component mounting method
JP2010010693A (en) * 2009-07-31 2010-01-14 Seiko Epson Corp Mounting device, and method of manufacturing semiconductor element mounting substrate
CN110958782A (en) * 2018-09-27 2020-04-03 颀邦科技股份有限公司 Method and device for laminating substrate and chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006030260A (en) * 2004-07-12 2006-02-02 Seiko Epson Corp Semiconductor element mounting substrate, semiconductor element mounting substrate manufacturing method, mounting apparatus, mounting method, electro-optical device, electronic device
JP2006222286A (en) * 2005-02-10 2006-08-24 Matsushita Electric Ind Co Ltd Component mounting apparatus and component mounting method
JP2010010693A (en) * 2009-07-31 2010-01-14 Seiko Epson Corp Mounting device, and method of manufacturing semiconductor element mounting substrate
CN110958782A (en) * 2018-09-27 2020-04-03 颀邦科技股份有限公司 Method and device for laminating substrate and chip

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