JP2004140231A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of supplying the output voltage of a voltage step-down circuit even to a load disposed at a distance from the voltage step-down circuit without greatly dropping its voltage value. <P>SOLUTION: The semiconductor device is equipped with the voltage step-down circuit which steps down and outputs a source voltage once the source voltage is inputted, and a power supply wire which supplies the output voltage of the voltage step-down circuit to a plurality of loads. The power supply wire comprises a 1st wire extending from the voltage step-down circuit to a 1st branch point, and a 2nd wire extending from the branch point to the plurality of load. When the load which has the largest resistance value from the branch point to its position on the 2nd wire is regarded as a 1st load, and the load having the largest value from the branch point to its position on a path which does not overlap with the path from the branch point to the 1st load is regarded as a 2nd load; the 1st branch point is provided where the difference between the 1st resistance value from the 1st branch point of the 2nd wire to the 1st load and the resistance value from the branch point to the 2nd load is less than a half as large as the 1st resistance value. <P>COPYRIGHT: (C)2004,JPO

Description

この場合、３つの負荷１０８，１１０，１１２のうち、降圧回路１０６から離れた負荷１１０，１１２には、所望の電圧Ｖよりも低い電圧が印可される。特に、負荷１１２には、所望の電圧Ｖよりも大幅に低い電圧が印可される。これにより、例えば、負荷１１２がトランジスタである場合、トランジスタに十分な電圧が印可されず、スイッチング速度が低下するといった問題があった。
【０００５】
例えば、従来の半導体集積回路は、複数の機能モジュールの各々に対して専用の降圧回路を備える（例えば、特許文献１参照。）。この構成を用いれば、半導体集積回路の電源配線を等価的に短くすることができ、電源配線における不所望な電圧降下を低減できる。
【０００６】
【特許文献１】
特開平５−２６６２２４号公報（第３−４頁、図１−図３）
【０００７】
【発明が解決しようとする課題】
しかし、特許文献１などに開示される構成を実現するためには、１つの半導体チップ上に複数の降圧回路を設けなければならない。半導体チップに設置される降圧回路の個数が多いと、半導体チップの消費電力が大きくなるという問題があった。
【０００８】
近年は、高性能化に向けた素子数の増加により、半導体チップのチップサイズが大きくなっている。その一方で、上述のように降圧回路の個数が制限されるので、降圧回路と負荷との間の電源配線の距離がますます長くなることが考えられる。
【０００９】
本発明の目的は、降圧回路から離れて位置された負荷に対しても、降圧回路の出力電圧を、その電圧値を大幅に低下させることなく供給できる半導体装置を提供することである。
【００１０】
【課題を解決するための手段】
本発明に係る半導体装置は、電源電圧が入力されるとその電源電圧を降圧して出力する降圧回路と、前記の降圧回路の出力電圧を複数の負荷に供給する電源配線とを備える半導体装置である。この半導体装置において、前記の電源配線は、２以上の方向に分岐する少なくとも１つの分岐点を有する。また、前記の電源配線は、前記の降圧回路から最初の前記の分岐点となる第１の分岐点まで延びた第１の配線と、その第１の分岐点から複数の前記の負荷まで延びた第２の配線とから成る。前記の第１の分岐点は、前記の第２の配線における前記の第１の分岐点から複数の前記の負荷のうち第１の負荷までの第１の抵抗値と前記の第２の配線における前記の第１の分岐点から複数の前記の負荷のうち第２の負荷までの第２の抵抗値との差が、前記の第１の抵抗値の２分の１よりも小さくなる位置に設けられる。ここで、前記の第１の負荷は、複数の前記の負荷のうち、前記の第２の配線において前記の第１の分岐点からその位置までの抵抗値が最大である負荷であり、前記の第２の負荷は、複数の前記の負荷の個数が２である場合に、前記の第１の負荷以外の負荷であり、複数の前記の負荷の個数が３以上である場合に、複数の前記の負荷のうち、前記の第２の配線に沿って前記の第１の分岐点から前記の第１の負荷までの経路と重複しない経路において、前記の第１の分岐点からその位置までの抵抗値が最大となる負荷である。
【００１１】
【発明の実施の形態】
実施の形態１．
以下に、添付の図面を参照して、本発明の実施の形態について説明する。
図１は、本発明による半導体装置（半導体チップ）における部品の配置を図式的に示す。図１を参照すると、半導体チップ２には、外部電源パッド４、降圧回路６、負荷８，１０，１２、外部電源パッド４と降圧回路６とを接続する電源配線１６、および、降圧回路６と各々の負荷とを接続する電源配線が形成される。降圧回路６と各々の負荷とを接続する電源配線は、第１の配線１８と第２の配線２０とから成る。第２の配線２０は、負荷８，１０，１２に共通に接続される配線であり、第１の配線１８は、その第２の配線２０と降圧回路６とを接続する配線である。負荷８，１０，１２は、例えば、トランジスタ等の、降圧回路６の出力電圧を電源電圧とする素子である。図１において、第２の配線２０は、負荷の配置に合わせて十字型形状をしている。ここで、説明を簡単にするために、負荷８，１０，１２のみを示しているが、第２の配線２０に接続される他の負荷が存在してもよい。また、第２の配線２０と負荷１０との接続点をＱ１、第２の配線２０と負荷８，１２との接続点を、それぞれ、Ｑ２，Ｑ３として示す。
【００１２】
本実施の形態による半導体チップ２において、第１の配線１８は、第２の配線２０に接続点Ｑ１で接続される。また、第２の配線２０に沿って、接続点Ｑ１から接続点Ｑ２までの長さと、接続点Ｑ１から接続点Ｑ３までの長さは等しい。
【００１３】
図２は、図１の半導体チップ２において実現される集積回路の回路図である。図２において、降圧回路６は、外部電源３０に接続される。降圧回路６は、外部電源３０から電源電圧が入力されると、それを所望の電圧に降圧して出力する。ここで、降圧回路６が出力する電圧をＶ、降圧回路６が出力する電流をＩとする。降圧回路６から出力された電流Ｉは、第１の配線１８および第２の配線２０を通って、負荷８，１０，１２に供給される。本実施の形態による半導体チップ２においては、降圧回路６から接続点Ｑ１までの電源配線（第１の配線１８）の長さは、従来の半導体チップ（図１０）におけるその長さと比較して長く、配線抵抗は無視できない。よって、第１の配線１８の配線抵抗の値をＲ１とすると、接続点Ｑ１における電圧は、Ｖ−Ｉ×Ｒ１となる。これにより、接続点Ｑ１に接続される負荷１０には、Ｖ−Ｉ×Ｒ１の電圧が印可される。次に、電流Ｉは、接続点Ｑ１で２方向に分岐する（簡単のために、負荷８，１０，１２の入力インピーダンスは十分に高く、その入力端子に流れ込む電流は無視できるほど小さいものとする。）。ここで、第２の配線２０において、接続点Ｑ１から負荷８が接続される接続点Ｑ２までの配線抵抗の抵抗値をＲ２、接続点Ｑ１から負荷１２が接続される接続点Ｑ３までの配線抵抗の抵抗値をＲ３とし、さらに、簡単のために、Ｒ２とＲ３が等しいとすると、電流Ｉは、接続点Ｑ１で、Ｉ／２ずつに分配される。このとき、負荷８および負荷１２に印可される電圧は、第２の配線２０における電圧降下によって、それぞれ、Ｖ−Ｉ×Ｒ１−Ｉ／２×Ｒ２、および、Ｖ−Ｉ×Ｒ１−Ｉ／２×Ｒ３となる。結局、負荷８，１０，１２に印可される電圧を、それぞれ、Ｖ_８，Ｖ_１０，Ｖ_１２とすると、以下の式（２）が成り立つ。
【数２】

【００１４】
本実施の形態による半導体チップ２においては、Ｖ−Ｉ×Ｒ１が各々の負荷に印可されるべき所望の電源電圧に等しくなるようにＲ１を設定する。そのとき、第２の配線は、抵抗値Ｒ１を有するように形成される。
【００１５】
また、図１において、矢印２２は、降圧回路６の出力電圧が降圧回路６にフィードバックされることを示す。以下に、詳細に説明する。図３は、降圧回路６の構成の一例を示す図である。この降圧回路６は、差動増幅回路３２、その差動増幅回路３２の出力電圧をゲート電圧とするｐチャネルＭＯＳトランジスタＴｒ１、トランジスタＴｒ１のドレイン電流の一部を電圧に変換する変換回路３４を備える。差動増幅回路３２は、差動回路とカレントミラー回路とから成る一般的な回路であるため、構成および動作の詳細な説明は省略する。図３の降圧回路６において、トランジスタＴｒ１のドレイン電流Ｉａの一部Ｉｂ（＝αＩａ：αは比例定数）は、変換回路３４によって電圧Ｖ１に変換され、差動増幅回路３２に入力される（矢印２２は、電流Ｉｂがフィードバックされる様子を示す）。この電圧Ｖ１の値は、電流Ｉｂの値に比例する。差動増幅回路３２は、電圧Ｖ１と基準電圧Ｖ２とを比較し、その比較結果に応じて電圧Ｖ３を出力する。この電圧Ｖ３は、トランジスタＴｒ１のゲートに印加され、トランジスタＴｒ１は、このゲート電圧に応じてドレイン電流Ｉａを出力する。降圧回路６において電流Ｉａの値が所望の値で一定に保持されるとき、電圧Ｖ１および電圧Ｖ２は等しく、差動増幅回路３２は平衡状態にあり、出力電圧Ｖ３も一定である。しかし、何らかの原因で電流Ｉａが増加すると、電圧Ｖ１が基準電圧Ｖ２より大きくなり、出力電圧Ｖ３の値は、差動増幅回路３２が平衡状態にあるときの出力電圧の値Ｖｏよりも大きくなる。このとき、トランジスタＴｒ１のドレイン電流Ｉａの値が減少し、電流Ｉａの増大が抑制される。一方、電流Ｉａが減少すると、電圧Ｖ１が基準電圧Ｖ２より小さくなり、出力電圧Ｖ３の値は、Ｖｏよりも小さくなる。このとき、トランジスタＴｒ１のドレイン電流Ｉａの値が増大し、電流Ｉａの減少が抑制される。以上のことから、降圧回路６は、その構成により、出力電流Ｉを一定の値（１−α）Ｉａに保持できる。出力電流Ｉが一定に保持されることは、負荷に印可される電圧が一定に保持されることを意味する。
【００１６】
本実施の形態による半導体チップ２においては、第２の配線２０に沿って第１の配線１８と第２の配線２０との接続点Ｑ１に最も近い負荷と、第２の配線２０に沿ってその接続点Ｑ１から最も遠い負荷との間の第２の配線２０に沿った距離が、従来の半導体チップ１０２よりも短くなる。
【００１７】
ここで、本実施の形態による半導体チップ２の電源配線における電圧降下について、従来の半導体チップ１０２と比較して説明する。図１と図１０を比較すると、第１の配線と第２の配線との接続点（以下、「接続点Ａ１」という。）に最も近い負荷と接続点Ａ１から最も遠い負荷との間の第２の配線に沿った距離は、図１０において、接続点Ｐ１から接続点Ｐ３までの距離であるのに対し、図１において、接続点Ｑ１から接続点Ｑ２（または、接続点Ｑ３）までの距離である。一般に、配線の抵抗値は、その長さに比例し、配線の長さが長いほど、抵抗値は大きい。半導体チップ２および半導体チップ１０２においては、簡単のために、配線の抵抗値が、その配線の長さによってのみ変化するものとする。
【００１８】
まず、図１において、負荷８，１０，１２を、メモリセルを含むコア回路を構成するトランジスタとする。このようなトランジスタには、ゲート酸化膜の信頼性上の問題から、所定値を超える電圧がかけられない。この所定値を、例えば、１．９Ｖとする。外部電源電圧Ｖａを３．３Ｖ±０．１Ｖとし、Ｒ１、Ｒ２およびＲ３（図２）を、それぞれ、２（Ω）、１（Ω）および１（Ω）とする。また、降圧回路６が出力する電流Ｉの値を、２００ｍＶとする。このとき、式（２）を用いれば、トランジスタ１０に印加される電圧を１．９Ｖにするために、降圧回路の出力電圧を、２．３Ｖにする必要がある。また、その場合には、式（２）により、トランジスタ８およびトランジスタ１２に印可される電圧は、ともに１．８Ｖである。
【００１９】
一方、図１０において、負荷１０８，１１０，１１２も、負荷８等と同様に、性能上１．９Ｖを超える電圧を印加できないトランジスタとする。また、本実施の形態による半導体チップ２と同様に、電源電圧Ｖａを３．３Ｖ±０．１Ｖとし、降圧回路が出力する電流Ｉの値を２００ｍＡとする。Ｒ４およびＲ５（図１１）は、配線の抵抗値がその配線の長さに比例することを考慮すると、図１と図１０とを比較して、ともに１（Ω）とすることができる。このとき、接続点Ｐ１においてトランジスタ１０８に印可される電圧を１．９Ｖとすると、トランジスタ１１０およびトランジスタ１１２に印可される電圧は、それぞれ、式（１）により、１．７Ｖおよび１．５Ｖである。
【００２０】
従来の半導体チップ（図１１）においては、トランジスタ１１２（接続点Ａ１から最も遠い負荷）の性能が、トランジスタ１０８（接続点Ａ１に最も近い負荷）に比べて、２０％以上劣化する（トランジスタ１１２に印可される電圧の大きさが、トランジスタ１０８に印可される電圧の大きさよりも大幅に小さくなることによる）。この性能劣化は、高速性が要求される半導体チップにおいては許容できない。しかし、本実施の形態による半導体チップ（図２）においては、トランジスタ８（接続点Ａ１から最も遠い負荷、トランジスタ１２も同様）の性能が、トランジスタ１０（接続点Ａ１に最も近い負荷）に比べて、５％程度しか劣化しない（トランジスタ８に印可される電圧の大きさと、トランジスタ１０に印加される電圧の大きさの差が小さいことによる）。トランジスタの性能劣化は１０％以下であれば許容範囲とみなせるので、本実施の形態による半導体チップ２におけるトランジスタの性能劣化は、十分な許容範囲内にある。従って、本実施の形態による半導体チップ２では、従来の半導体チップ１０２と比べて、トランジスタの性能劣化が大幅に改善されている。つまり、本実施の形態による半導体チップにおいては、降圧回路から離れて位置された負荷に対しても、降圧回路の出力電圧を、その電圧値を大幅に低下させることなく供給できる。
【００２１】
一般的に、従来の半導体チップと比較して、トランジスタの性能劣化を改善するためには、第１の配線と第２の配線との接続点Ａ１（負荷が接続されているとは限らない）は、降圧回路から複数の負荷へ延びる（第１の配線および第２の配線から成る）電源配線がその点から２以上の方向に分岐するような分岐点であることが必要である。なお、第２の配線も、２以上の方向に分岐する分岐点を有する場合があり、接続点Ａ１は、降圧回路から複数の負荷へ延びる電源配線に存在する少なくとも１以上の分岐点のうち最初の分岐点であるといえる。
【００２２】
また、それぞれの負荷に印可される電圧の差があまり大きくならないように、接続点Ａ１は、以下に説明する条件を満たすことが好ましい。従来の半導体チップおよび本実施の形態による半導体チップにおいて、電源配線の抵抗値は、その電源配線の長さによってのみ変化するとしたが、実際には、電源配線の抵抗値は、配線の幅等の他の条件によっても変化する。従って、電源配線における電圧降下は、電源配線の長さではなく、電源配線の抵抗値を基に考えるべきである。ここで、第２の配線に接続された全ての負荷のうち、第２の配線に沿って接続点Ａ１からその位置までの抵抗値が最大である負荷を第１の負荷とする。接続点Ａ１は、第２の配線における分岐点であるため、第２の配線は、接続点Ａ１から第１の負荷へ延びる第１の配線経路と、接続点Ａ１からその他の方向へ延びる（第１の配線経路と重複しない）第２の配線経路とを有する。第２の配線に接続される負荷の個数が３以上である場合には、それらの負荷のうち、第２の配線経路において接続点Ａ１からその位置までの抵抗値が最大である負荷を第２の負荷とする。また、第２の配線に接続される負荷の個数が２である場合には、第１の負荷以外のもう１つの負荷を第２の負荷とする。いずれの場合であっても、接続点Ａ１は、第２の配線における接続点Ａ１から第１の負荷までの抵抗値と第２の配線における接続点Ａ１から第２の負荷までの抵抗値との差が、第２の配線における接続点Ａ１から第１の負荷までの抵抗値の２分の１よりも小さくなるような位置に設けられることが好ましい。このとき、第２の配線における接続点Ａ１から第１の負荷までの抵抗値をＲａ、第２の配線における接続点Ａ１から第２の負荷までの抵抗値をＲｂとすると、以下の式（３）が成り立つ。
【数３】

【００２３】
本実施の形態による半導体チップ２においては、第１の負荷が負荷８（または負荷１２）、第２の負荷が負荷１２（第１の負荷が負荷１２である場合は負荷８）であり、Ｒａ＝Ｒｂ＝Ｒ２＝Ｒ３であるので、０＜Ｒ２／２が成り立ち、式（３）を満たす。また、ＲａとＲａが異なる場合であっても、式（３）に示される関係を満たせば、従来の半導体チップにおけるトランジスタの性能劣化を改善できる。例えば、接続点Ａ１が図４に示されるような位置にある場合において、ＲａおよびＲａを、それぞれ、１．３（Ω）および０．７（Ω）（１．３−０．７＜１．３／２）とすると、降圧回路６が出力する電流Ｉの値が２００ｍＶ、Ｒ１が２（Ω）、かつ、降圧回路の出力電圧が２．３Ｖの場合に、トランジスタ８およびトランジスタ１２に印可される電圧は、それぞれ、式（２）より、１．７７Ｖ以上、１．８３Ｖ以上である。また、トランジスタ１０に印可される電圧は、１．８７Ｖ以上である。このとき、トランジスタの性能劣化は、大きい方で５％程度である（この場合、トランジスタ１０は、トランジスタ８よりも接続点Ａ１に近いので、トランジスタ１０の性能劣化は、トランジスタ８よりも小さい。）。これは、性能劣化の許容範囲である１０％以下という条件を満たし、従来の半導体チップに比べて、トランジスタの性能劣化が十分に改善されていることを意味する。
【００２４】
なお、第２の配線２０および負荷の配置が図１や図４に示される配置と異なっても、接続点Ａ１が、降圧回路から複数の負荷へ延びる電源配線の最初の分岐点であり、式（３）に示される関係を満たす位置にあれば、第１の配線を同じ第２の配線の端部に接続する半導体チップと比較して、トランジスタの性能劣化を改善できる。例えば、第２の配線、負荷および接続点Ａ１の配置が図５に示されるような場合には、接続点Ａ１が第２の配線の端部にある従来の半導体チップにおけるトランジスタの性能劣化を改善できる。図５において、第１の負荷は負荷２４であり、第２の負荷は負荷２６である。この負荷２６は、第２の配線２０に接続される複数の負荷のうち、第２の配線２０に沿った接続点Ａ１（Ｑ１）から第１の負荷２４へ延びる第１の配線経路に重複しない経路において、接続点Ａ１からその位置までの抵抗値が最大であるような負荷である（例えば、接続点Ａ１から接続点Ｑ２へ延びる経路は、第１の配線経路に重複するとみなされる。）。
【００２５】
なお、図１、図４および図５においては、配線の抵抗値がその配線の長さによってのみ変化すると仮定して接続点Ａ１の位置を定めているが、これは常に適切というわけではない。実際には、配線の抵抗値は、その配線の幅等の他の条件によっても変化するので、接続点Ａ１は、式（３）を満たすような位置であれば、配線の長さ（接続点Ａ１から負荷までの配線の長さ）に制限されず、他の位置に設けることができる。
【００２６】
実施の形態２．
図６は、本実施の形態による半導体チップ４２の断面を図式的に示す。この半導体チップ４２は、２つの電源配線層とその間の絶縁層から成る。実施の形態１による半導体チップ２においては、第１の配線１８を、降圧回路６や第２の配線２０と同じ表面に形成していたが、本実施の形態による半導体チップ４２においては、第１の配線１８を、降圧回路６や第２の配線２０が形成された層４４とは別の層４６に形成する。２つの層４４，４６の間は絶縁層４８であり、絶縁層４８には、２つの層４４，４６を電気的に接続するバイアホール５０が形成される。図７は、本実施の形態による半導体チップ４２の分解図である。図７に示されるように、層４４に形成された降圧回路６および第２の配線２０は、それぞれ、絶縁層４８を貫通するバイアホール５０を介して、層４６に形成された第１の配線１８に接続される。
【００２７】
本実施の形態による半導体チップ４２においては、第１の配線１８等と第２の配線２０とを同一の層に形成する必要がなく、第１の配線１８を１つの配線層に自由にレイアウトすることができる。従って、第１の配線１８を第２の配線２０等と同一の層に配置する場合と比較して、第１の配線１８の配置によるチップ面積の拡大を防止でき、半導体チップのチップサイズを小さくできる。これは、実施の形態１において、第１の配線１８と第２の配線２０を接続点Ｑ１で接続することにより、第１の配線１８が従来の第１の配線（例えば、図１０における配線１１８）よりも長くなってしまうという課題を克服するものである。
【００２８】
なお、本実施の形態による半導体チップにおいては、第１の配線１８等を形成する層と第２の配線２０を形成する層を完全に別にしたが、第２の配線２０等を形成する層に、第１の配線１８の一部が形成されてもよい。その場合には、一方の層に形成された第１の配線１８の一部と他方の層に形成された第１の配線１８が、バイアホールを介して接続される。
【００２９】
実施の形態３．
図８は、実施の形態３の半導体チップ６２における部品の配置を図式的に示す。本実施の形態による半導体チップ６２が、実施の形態１による半導体チップ２と異なる点は、矢印６４に示されるように、降圧回路６６に、第１の配線１８と第２の配線２０との接続点Ａ１（本実施の形態では、接続点Ｑ１に等しい）の電圧をフィードバックする点である。これは、半導体装置の消費電流が動作状態によって大幅に変化するとき、非常に有効である。以下に、詳細に説明する。図９は、本実施の形態による半導体チップ６２の降圧回路６６の回路図である。この降圧回路６６において、端子Ｃには、降圧回路６６外部の他の回路により、接続点Ａ１の電圧が入力される（矢印６４は、この接続点Ａ１の電圧がフィードバックされる様子を示す）。接続点Ａ１の電圧は、差動増幅回路６８の入力電圧Ｖ１として、基準電圧Ｖ２と比較される。差動増幅器回路６８は、比較結果に応じて電圧Ｖ３を出力する。この電圧Ｖ３は、トランジスタＴｒ２のゲートに印加され、トランジスタＴｒ２は、このゲート電圧に応じてドレイン電流Ｉを出力する。ここで、トランジスタＴｒ２は、ｎチャネルＭＯＳトランジスタである。
【００３０】
本実施の形態による降圧回路６６においては、端子Ｃに入力される電圧（すなわち、接続点Ａ１における電圧：Ｖ−Ｉ×Ｒ１）が、所望の電圧よりも大きくなる（降圧回路６６の出力電流Ｉが小さくなる）と、平衡状態のときと比較して、差動増幅回路６８の出力電圧Ｖ３が大きくなり、トランジスタＴｒ２のゲートに印加される電圧も大きくなる。トランジスタＴｒ２は、ｎチャネルＭＯＳトランジスタであるため、ゲート電圧に印加される電圧が大きくなると、ドレイン電流Ｉの値が増大し、出力電流Ｉの減少が抑制される。反対に、端子Ｃに入力される電圧が所望の電圧よりも小さくなると、出力電流Ｉの増大が抑制される。結果として、接続点Ａ１の電圧をフィードバックすることにより、降圧回路６６の出力電流Ｉが一定の値に保持される。ここで、出力電流Ｉが一定に保持されることは、接続点Ａ１の電圧（Ｖ−Ｉ×Ｒ１）が一定に保持されることを意味する。
【００３１】
消費電流が大幅に変化する半導体装置においては、消費電流（Ｉ）が少なくなったときに、接続点Ａ１の電圧（Ｖ−Ｉ×Ｒ１）が、負荷に印可されるべき所望の電圧よりも大きくなる場合がある。その際には、トランジスタ等の負荷に信頼性上の問題が発生する。本実施の形態による半導体装置においては、接続点Ａ１（Ｑ１）の電圧を降圧回路６にフィードバックすることにより、接続点Ａ１における電圧が、トランジスタ等の素子の許容電源電圧を超えないようにすることができる。
【００３２】
なお、第１の配線１８と第２の配線２０の接続点における電圧を降圧回路にフィードバックする構成は、実施の形態２による積層構造から成る半導体装置においても実現可能である。
【００３３】
【発明の効果】
本発明による半導体装置によれば、電源電圧が入力されるとその電源電圧を降圧して出力する降圧回路と、降圧回路の出力電圧を複数の負荷に供給する電源配線とを備え、電源配線は、２以上の方向に分岐する少なくとも１つの分岐点を有し、その電源配線は、降圧回路から最初の分岐点となる第１の分岐点まで延びた第１の配線と、その第１の分岐点から複数の負荷まで延びた第２の配線とから成り、第１の分岐点は、第２の配線におけるその第１の分岐点から複数の負荷のうち第１の負荷までの第１の抵抗値と第２の配線におけるその第１の分岐点から複数の負荷のうち第２の負荷までの第２の抵抗値との差が、第１の抵抗値の２分の１よりも小さくなる位置に設けられ、その第１の負荷は、複数の負荷のうち、第２の配線において第１の分岐点からその位置までの抵抗値が最大である負荷であり、その第２の負荷は、複数の負荷の個数が２である場合に、第１の負荷以外の負荷であり、複数の負荷の個数が３以上である場合に、複数の負荷のうち、第２の配線に沿って第１の分岐点から第１の負荷までの経路と重複しない経路において、第１の分岐点からその位置までの抵抗値が最大となる負荷であるので、降圧回路から離れて位置された負荷に対しても、降圧回路の出力電圧を、その電圧値を大幅に低下させることなく供給できる。
【図面の簡単な説明】
【図１】実施の形態１による半導体チップの部品の配置を図式的に示す図。
【図２】図１の半導体チップにおいて実現される集積回路の回路図。
【図３】実施の形態１による降圧回路の一例を示す回路図。
【図４】実施の形態１による半導体チップの部品の配置の変形例を示す図。
【図５】実施の形態１による半導体チップの部品の配置の変形例を示す図。
【図６】実施の形態２による半導体チップの断面を図式的に示す図。
【図７】実施の形態２による半導体チップの分解図。
【図８】実施の形態３による半導体チップの部品の配置を図式的に示す図。
【図９】実施の形態３による降圧回路の一例を示す回路図。
【図１０】従来の半導体チップの部品の配置を図式的に示す図。
【図１１】図１０の半導体チップにおいて実現される集積回路の回路図。
【符号の説明】
２　半導体チップ、　４　外部電源パッド、　６　降圧回路、　８、１０、１２　負荷、　１８、２０　配線。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a power supply voltage step-down circuit.
[0002]
[Prior art]
Generally, a semiconductor device such as a memory or a microprocessor is strongly required to reduce power consumption of an internal circuit. In order to satisfy this requirement, for example, it is conceivable to lower the power supply voltage of the internal circuit. However, the value of the power supply voltage supplied from the outside is standardized, and it is not desirable to change this. Therefore, a method has been adopted in which a step-down circuit is provided inside the device, and the power supply voltage supplied from the outside is reduced by the step-down circuit and supplied to the internal circuit.
[0003]
FIG. 10 schematically shows the arrangement of components in a conventional semiconductor device (semiconductor chip) having a step-down circuit. Referring to FIG. 10, an external power supply pad 104, a step-down circuit 106, loads 108, 110, 112, a power supply wiring 116 connecting the external power supply pad 104 and the step-down circuit 106, and a step-down circuit 106 A power supply wiring connecting each load is formed. The power supply wiring connecting the step-down circuit 106 and each load is composed of a first wiring 118 and a second wiring 120. The second wiring 120 is a wiring commonly connected to the loads 108, 110, and 112, and the first wiring 118 is a wiring connecting the second wiring 120 and the step-down circuit 106. Each of the loads 108, 110, and 112 is an element such as a transistor that uses the output voltage of the step-down circuit 106 as a power supply voltage. Arrow 22 indicates that the output voltage is fed back to step-down circuit 6. In FIG. 10, the second wiring 120 has a cross shape in accordance with the arrangement of the load. For simplicity, only the loads 108, 110, and 112 are shown, but other loads connected to the second wiring 120 may exist. In addition, connection points between the second wiring 120 and the loads 108, 110, and 112 are indicated as P1, P2, and P3, respectively. The first wiring 118 is usually connected to the second wiring 120 such that its length becomes shorter. Here, one end of the first wiring 118 is connected to the end of the second wiring 120 closest to the step-down circuit 106 (the connection point P1 in FIG. 10). As a result, the area occupied by the power supply wiring in the semiconductor chip 102 is reduced, and the size of the chip can be reduced.
[0004]
However, in the above-described configuration, a load located away from the step-down circuit 106, that is, a load having a long distance from the step-down circuit 106 (a distance along the wiring path) has a desired voltage due to a voltage drop in the wiring resistance. There is a problem that a voltage lower than the voltage is applied. The details will be described below with reference to FIGS. FIG. 11 is a circuit diagram of an integrated circuit realized in the semiconductor chip 102 of FIG. 11, the step-down circuit 106 is connected to an external power supply 130. When the power supply voltage is input from the external power supply 130, the step-down circuit 106 steps down the power supply voltage to a desired voltage and outputs it. Here, the voltage output from the step-down circuit 106 is V, and the current output from the step-down circuit 106 is I. The current I output from the step-down circuit 106 is supplied to the loads 108, 110, 112 through the first wiring 118 and the second wiring 120. Assuming that the wiring resistance of the first wiring 118 is negligible because of its short length, the output voltage V of the step-down circuit 106 is applied to the load 108 (at the connection point P1). On the other hand, in the second wiring 120, the resistance from the connection point P1 where the load 108 is connected to the connection point P2 where the load 110 is connected is R4, and the connection where the load 112 is connected to the connection point P2 where the load 110 is connected. Assuming that the resistance up to the point P3 is R5, voltages of VI × R4 and VI × R4-I × R5 are applied to the load 110 and the load 112, respectively, due to a voltage drop in the wiring resistance. Here, for the sake of simplicity, it is assumed that the input impedances of the loads 108, 110, and 112 are sufficiently high, and the current flowing into the input terminals is small enough to be ignored. After all, the voltages applied to the loads 108, 110, 112 are respectively ₁₀₈ , V ₁₁₀ , V ₁₁₂ Then, the following equation (1) holds.
(Equation 1)

In this case, a voltage lower than the desired voltage V is applied to the loads 110 and 112 that are apart from the step-down circuit 106 among the three loads 108, 110 and 112. In particular, a voltage much lower than the desired voltage V is applied to the load 112. Accordingly, for example, when the load 112 is a transistor, there is a problem that a sufficient voltage is not applied to the transistor and the switching speed is reduced.
[0005]
For example, a conventional semiconductor integrated circuit includes a dedicated step-down circuit for each of a plurality of functional modules (for example, see Patent Document 1). With this configuration, the power supply wiring of the semiconductor integrated circuit can be equivalently shortened, and an undesired voltage drop in the power supply wiring can be reduced.
[0006]
[Patent Document 1]
JP-A-5-266224 (page 3-4, FIGS. 1-3)
[0007]
[Problems to be solved by the invention]
However, in order to realize the configuration disclosed in Patent Document 1 or the like, a plurality of step-down circuits must be provided on one semiconductor chip. When the number of step-down circuits provided on the semiconductor chip is large, there is a problem that the power consumption of the semiconductor chip increases.
[0008]
In recent years, the chip size of a semiconductor chip has increased due to an increase in the number of elements for higher performance. On the other hand, since the number of step-down circuits is limited as described above, the distance of the power supply wiring between the step-down circuit and the load may be further increased.
[0009]
An object of the present invention is to provide a semiconductor device capable of supplying an output voltage of a step-down circuit to a load located away from the step-down circuit without significantly lowering its voltage value.
[0010]
[Means for Solving the Problems]
A semiconductor device according to the present invention is a semiconductor device comprising: a step-down circuit that steps down a power supply voltage when a power supply voltage is input and outputs the voltage; and a power supply line that supplies an output voltage of the step-down circuit to a plurality of loads. is there. In this semiconductor device, the power supply wiring has at least one branch point branched in two or more directions. Further, the power supply wiring extends from the step-down circuit to a first branch point which is the first branch point, and extends from the first branch point to the plurality of loads. And second wiring. The first branch point includes a first resistance value from the first branch point in the second wiring to a first load among the plurality of loads and a first resistance value in the second wiring. Provided at a position where a difference from a second resistance value from the first branch point to a second load of the plurality of loads is smaller than half of the first resistance value. Can be Here, the first load is a load having a maximum resistance value from the first branch point to the position of the second wiring in the second wiring, among the plurality of loads. The second load is a load other than the first load when the number of the plurality of loads is two, and the plurality of the plurality of loads when the number of the plurality of loads is three or more. Out of the load, on a path that does not overlap with a path from the first branch point to the first load along the second wiring, a resistance from the first branch point to the position thereof. This is the load with the maximum value.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 schematically shows an arrangement of components in a semiconductor device (semiconductor chip) according to the present invention. Referring to FIG. 1, the semiconductor chip 2 includes an external power supply pad 4, a step-down circuit 6, loads 8, 10, and 12, a power supply line 16 connecting the external power supply pad 4 and the step-down circuit 6, and a step-down circuit 6. A power supply wiring connecting each load is formed. The power supply wiring for connecting the step-down circuit 6 to each load includes a first wiring 18 and a second wiring 20. The second wiring 20 is a wiring commonly connected to the loads 8, 10, and 12, and the first wiring 18 is a wiring connecting the second wiring 20 and the step-down circuit 6. Each of the loads 8, 10, and 12 is an element such as a transistor that uses the output voltage of the step-down circuit 6 as a power supply voltage. In FIG. 1, the second wiring 20 has a cross shape in accordance with the arrangement of the load. Here, for simplicity, only the loads 8, 10, and 12 are shown, but other loads connected to the second wiring 20 may exist. The connection point between the second wiring 20 and the load 10 is shown as Q1, and the connection point between the second wiring 20 and the loads 8, 12 is shown as Q2, Q3, respectively.
[0012]
In the semiconductor chip 2 according to the present embodiment, the first wiring 18 is connected to the second wiring 20 at the connection point Q1. Along the second wiring 20, the length from the connection point Q1 to the connection point Q2 is equal to the length from the connection point Q1 to the connection point Q3.
[0013]
FIG. 2 is a circuit diagram of an integrated circuit realized in the semiconductor chip 2 of FIG. 2, the step-down circuit 6 is connected to an external power supply 30. When the power supply voltage is input from the external power supply 30, the step-down circuit 6 steps down the voltage to a desired voltage and outputs it. Here, the voltage output from the step-down circuit 6 is V, and the current output from the step-down circuit 6 is I. The current I output from the step-down circuit 6 is supplied to the loads 8, 10, and 12 through the first wiring 18 and the second wiring 20. In semiconductor chip 2 according to the present embodiment, the length of power supply wiring (first wiring 18) from step-down circuit 6 to connection point Q1 is longer than that of a conventional semiconductor chip (FIG. 10). In addition, wiring resistance cannot be ignored. Therefore, when the value of the wiring resistance of the first wiring 18 is R1, the voltage at the connection point Q1 is VI-R1. As a result, a voltage of VI × R1 is applied to the load 10 connected to the connection point Q1. Next, the current I branches in two directions at the connection point Q1 (for simplicity, it is assumed that the input impedances of the loads 8, 10, and 12 are sufficiently high and the current flowing into the input terminals is negligibly small. .). Here, in the second wiring 20, the resistance value of the wiring resistance from the connection point Q1 to the connection point Q2 to which the load 8 is connected is R2, and the wiring resistance from the connection point Q1 to the connection point Q3 to which the load 12 is connected. Is R3, and for simplicity, assuming that R2 and R3 are equal, the current I is distributed at the connection point Q1 by I / 2. At this time, the voltages applied to the load 8 and the load 12 are changed by VI × R1-I / 2 × R2 and VI × R1-I / 2, respectively, due to the voltage drop in the second wiring 20. × R3. Eventually, the voltages applied to the loads 8, 10, and 12 are respectively represented by V ₈ , V ₁₀ , V ₁₂ Then, the following equation (2) holds.
(Equation 2)

[0014]
In the semiconductor chip 2 according to the present embodiment, R1 is set such that VI × R1 is equal to a desired power supply voltage to be applied to each load. At this time, the second wiring is formed to have the resistance value R1.
[0015]
In FIG. 1, an arrow 22 indicates that the output voltage of the step-down circuit 6 is fed back to the step-down circuit 6. The details will be described below. FIG. 3 is a diagram illustrating an example of the configuration of the step-down circuit 6. The step-down circuit 6 includes a differential amplifier circuit 32, a p-channel MOS transistor Tr1 having an output voltage of the differential amplifier circuit 32 as a gate voltage, and a conversion circuit 34 for converting a part of the drain current of the transistor Tr1 to a voltage. . Since the differential amplifier circuit 32 is a general circuit including a differential circuit and a current mirror circuit, detailed description of the configuration and operation is omitted. In the step-down circuit 6 of FIG. 3, a part Ib (= αIa: α is a proportional constant) of the drain current Ia of the transistor Tr1 is converted into a voltage V1 by the conversion circuit 34 and input to the differential amplifier circuit 32 (arrow). 22 shows how the current Ib is fed back). The value of the voltage V1 is proportional to the value of the current Ib. The differential amplifier circuit 32 compares the voltage V1 with the reference voltage V2, and outputs a voltage V3 according to the comparison result. The voltage V3 is applied to the gate of the transistor Tr1, and the transistor Tr1 outputs a drain current Ia according to the gate voltage. When the value of current Ia is kept constant at a desired value in step-down circuit 6, voltage V1 and voltage V2 are equal, differential amplifier circuit 32 is in a balanced state, and output voltage V3 is also constant. However, if the current Ia increases for some reason, the voltage V1 becomes larger than the reference voltage V2, and the value of the output voltage V3 becomes larger than the value Vo of the output voltage when the differential amplifier circuit 32 is in a balanced state. At this time, the value of the drain current Ia of the transistor Tr1 decreases, and an increase in the current Ia is suppressed. On the other hand, when the current Ia decreases, the voltage V1 becomes smaller than the reference voltage V2, and the value of the output voltage V3 becomes smaller than Vo. At this time, the value of the drain current Ia of the transistor Tr1 increases, and the decrease of the current Ia is suppressed. From the above, the voltage step-down circuit 6 can maintain the output current I at a constant value (1−α) Ia by its configuration. The fact that the output current I is kept constant means that the voltage applied to the load is kept constant.
[0016]
In the semiconductor chip 2 according to the present embodiment, the load closest to the connection point Q1 between the first wiring 18 and the second wiring 20 along the second wiring 20 and the load along the second wiring 20 The distance along the second wiring 20 from the connection point Q1 to the farthest load is shorter than that of the conventional semiconductor chip 102.
[0017]
Here, a voltage drop in the power supply wiring of the semiconductor chip 2 according to the present embodiment will be described in comparison with the conventional semiconductor chip 102. Comparing FIG. 1 with FIG. 10, the load between the load closest to the connection point between the first wiring and the second wiring (hereinafter, referred to as “connection point A1”) and the load farthest from the connection point A1 will be described. The distance along the wiring 2 is the distance from the connection point P1 to the connection point P3 in FIG. 10, while the distance from the connection point Q1 to the connection point Q2 (or the connection point Q3) in FIG. It is. Generally, the resistance value of a wiring is proportional to its length, and the longer the wiring length, the larger the resistance value. In the semiconductor chip 2 and the semiconductor chip 102, for the sake of simplicity, it is assumed that the resistance value of the wiring changes only depending on the length of the wiring.
[0018]
First, in FIG. 1, the loads 8, 10, and 12 are transistors constituting a core circuit including a memory cell. A voltage exceeding a predetermined value cannot be applied to such a transistor due to a reliability problem of the gate oxide film. This predetermined value is, for example, 1.9V. The external power supply voltage Va is set to 3.3V ± 0.1V, and R1, R2 and R3 (FIG. 2) are set to 2 (Ω), 1 (Ω) and 1 (Ω), respectively. The value of the current I output from the step-down circuit 6 is set to 200 mV. At this time, if Expression (2) is used, the output voltage of the step-down circuit needs to be 2.3 V in order to make the voltage applied to the transistor 10 1.9 V. In that case, the voltage applied to both the transistor 8 and the transistor 12 is 1.8 V according to the equation (2).
[0019]
On the other hand, in FIG. 10, similarly to the load 8 and the like, the loads 108, 110, and 112 are transistors that cannot apply a voltage exceeding 1.9 V in performance. Similarly to the semiconductor chip 2 according to the present embodiment, the power supply voltage Va is set to 3.3 V ± 0.1 V, and the value of the current I output from the step-down circuit is set to 200 mA. Considering that the resistance value of the wiring is proportional to the length of the wiring, R4 and R5 (FIG. 11) can both be set to 1 (Ω) by comparing FIGS. 1 and 10. At this time, assuming that the voltage applied to transistor 108 at connection point P1 is 1.9 V, the voltages applied to transistor 110 and transistor 112 are 1.7 V and 1.5 V, respectively, according to equation (1). .
[0020]
In the conventional semiconductor chip (FIG. 11), the performance of the transistor 112 (the load farthest from the connection point A1) is deteriorated by 20% or more as compared with the transistor 108 (the load closest to the connection point A1). The magnitude of the applied voltage is much smaller than the magnitude of the voltage applied to the transistor 108). This performance degradation cannot be tolerated in a semiconductor chip that requires high speed. However, in the semiconductor chip according to the present embodiment (FIG. 2), the performance of the transistor 8 (the load farthest from the connection point A1, and the same for the transistor 12) is higher than that of the transistor 10 (the load closest to the connection point A1). 5% (due to the small difference between the magnitude of the voltage applied to the transistor 8 and the magnitude of the voltage applied to the transistor 10). If the performance degradation of the transistor is 10% or less, it can be regarded as an allowable range. Therefore, the performance degradation of the transistor in the semiconductor chip 2 according to the present embodiment is within a sufficient allowable range. Therefore, in the semiconductor chip 2 according to the present embodiment, the performance degradation of the transistor is significantly improved as compared with the conventional semiconductor chip 102. That is, in the semiconductor chip according to the present embodiment, the output voltage of the step-down circuit can be supplied to a load located away from the step-down circuit without greatly reducing the voltage value.
[0021]
In general, in order to improve the performance degradation of the transistor as compared with a conventional semiconductor chip, a connection point A1 between the first wiring and the second wiring (the load is not necessarily connected). Needs to be a branch point such that a power supply wiring (consisting of a first wiring and a second wiring) extending from the step-down circuit to a plurality of loads branches from that point in two or more directions. In some cases, the second wiring also has a branch point that branches in two or more directions, and the connection point A1 is a first connection point among at least one or more branch points existing in a power supply wiring extending from the step-down circuit to a plurality of loads. It can be said that this is a branch point.
[0022]
Further, it is preferable that the connection point A1 satisfies the condition described below so that the difference between the voltages applied to the respective loads does not become too large. In the conventional semiconductor chip and the semiconductor chip according to the present embodiment, the resistance value of the power supply wiring changes only depending on the length of the power supply wiring. However, actually, the resistance value of the power supply wiring depends on the width of the wiring and the like. It changes depending on other conditions. Therefore, the voltage drop in the power supply wiring should be considered based not on the length of the power supply wiring but on the resistance value of the power supply wiring. Here, among all loads connected to the second wiring, the load having the largest resistance value from the connection point A1 to the position along the second wiring is defined as the first load. Since the connection point A1 is a branch point in the second wiring, the second wiring extends from the connection point A1 to the first load in the first wiring path and from the connection point A1 in the other direction (the second wiring path). A second wiring path (which does not overlap with the first wiring path). If the number of loads connected to the second wiring is three or more, the load having the largest resistance from the connection point A1 to the position in the second wiring path among the loads is set to the second. Load. When the number of loads connected to the second wiring is two, another load other than the first load is set as the second load. In any case, the connection point A1 is determined by the resistance value between the connection point A1 in the second wiring and the first load and the resistance value from the connection point A1 in the second wiring to the second load. It is preferable that the difference is provided at a position where the difference is smaller than half the resistance value from the connection point A1 of the second wiring to the first load. At this time, assuming that the resistance value from the connection point A1 in the second wiring to the first load is Ra and the resistance value from the connection point A1 in the second wiring to the second load is Rb, the following equation (3) ) Holds.
[Equation 3]

[0023]
In the semiconductor chip 2 according to the present embodiment, the first load is the load 8 (or the load 12), the second load is the load 12 (or the load 8 when the first load is the load 12), and Ra = Rb = R2 = R3, so that 0 <R2 / 2 holds and satisfies the expression (3). Further, even when Ra and Ra are different, deterioration of the performance of the transistor in the conventional semiconductor chip can be improved as long as the relationship shown in Expression (3) is satisfied. For example, when the connection point A1 is at the position as shown in FIG. 4, Ra and Ra are set to 1.3 (Ω) and 0.7 (Ω), respectively (1.3−0.7 <1. 3/2), when the value of the current I output from the step-down circuit 6 is 200 mV, R1 is 2 (Ω), and the output voltage of the step-down circuit is 2.3 V, the voltage is applied to the transistors 8 and 12. The respective voltages are 1.77 V or more and 1.83 V or more according to the equation (2). The voltage applied to the transistor 10 is 1.87 V or more. At this time, the performance deterioration of the transistor is about 5% at the largest (in this case, the performance deterioration of the transistor 10 is smaller than that of the transistor 8 because the transistor 10 is closer to the connection point A1 than the transistor 8). . This means that the condition of 10% or less, which is an allowable range of performance deterioration, is satisfied, and the performance deterioration of the transistor is sufficiently improved as compared with the conventional semiconductor chip.
[0024]
Note that, even if the arrangement of the second wiring 20 and the load is different from the arrangement shown in FIGS. 1 and 4, the connection point A1 is the first branch point of the power supply wiring extending from the step-down circuit to a plurality of loads. If the position satisfies the relationship shown in (3), the performance degradation of the transistor can be improved as compared with a semiconductor chip in which the first wiring is connected to the end of the same second wiring. For example, when the arrangement of the second wiring, the load, and the connection point A1 is as shown in FIG. 5, the performance deterioration of the transistor in the conventional semiconductor chip in which the connection point A1 is at the end of the second wiring is improved. it can. In FIG. 5, the first load is a load 24, and the second load is a load 26. The load 26 does not overlap the first wiring path extending from the connection point A1 (Q1) along the second wiring 20 to the first load 24 among the plurality of loads connected to the second wiring 20. In the path, the load is such that the resistance value from the connection point A1 to the position is the maximum (for example, the path extending from the connection point A1 to the connection point Q2 is considered to overlap the first wiring path).
[0025]
In FIGS. 1, 4 and 5, the position of the connection point A1 is determined on the assumption that the resistance value of the wiring changes only depending on the length of the wiring, but this is not always appropriate. Actually, the resistance value of the wiring changes depending on other conditions such as the width of the wiring, so that the connection point A1 has the length of the wiring (connection point The length is not limited to the length of the wiring from A1 to the load, but may be provided at another position.
[0026]
Embodiment 2 FIG.
FIG. 6 schematically shows a cross section of the semiconductor chip 42 according to the present embodiment. The semiconductor chip 42 includes two power supply wiring layers and an insulating layer therebetween. In the semiconductor chip 2 according to the first embodiment, the first wiring 18 is formed on the same surface as the step-down circuit 6 and the second wiring 20. However, in the semiconductor chip 42 according to the present embodiment, the first wiring 18 is formed. Is formed on a layer 46 different from the layer 44 on which the step-down circuit 6 and the second wiring 20 are formed. An insulating layer 48 is provided between the two layers 44 and 46, and a via hole 50 for electrically connecting the two layers 44 and 46 is formed in the insulating layer 48. FIG. 7 is an exploded view of the semiconductor chip 42 according to the present embodiment. As shown in FIG. 7, the step-down circuit 6 and the second wiring 20 formed on the layer 44 are respectively connected to the first wiring formed on the layer 46 via via holes 50 penetrating the insulating layer 48. 18 is connected.
[0027]
In the semiconductor chip 42 according to the present embodiment, it is not necessary to form the first wiring 18 and the like and the second wiring 20 in the same layer, and the first wiring 18 is freely laid out in one wiring layer. be able to. Therefore, as compared with the case where the first wiring 18 is arranged in the same layer as the second wiring 20 and the like, the chip area can be prevented from being increased due to the arrangement of the first wiring 18 and the chip size of the semiconductor chip can be reduced. it can. This is because, in the first embodiment, the first wiring 18 and the second wiring 20 are connected at the connection point Q1, so that the first wiring 18 is replaced with the conventional first wiring (for example, the wiring 118 in FIG. 10). ) To overcome the problem of becoming longer.
[0028]
In the semiconductor chip according to the present embodiment, the layer forming the first wiring 18 and the like and the layer forming the second wiring 20 are completely separated. , A part of the first wiring 18 may be formed. In that case, a part of the first wiring 18 formed in one layer and the first wiring 18 formed in the other layer are connected via via holes.
[0029]
Embodiment 3 FIG.
FIG. 8 schematically shows the arrangement of components in the semiconductor chip 62 according to the third embodiment. The difference between the semiconductor chip 62 according to the present embodiment and the semiconductor chip 2 according to the first embodiment is that, as indicated by an arrow 64, the step-down circuit 66 connects the first wiring 18 and the second wiring 20 to each other. The point is that the voltage at the point A1 (equal to the connection point Q1 in the present embodiment) is fed back. This is very effective when the current consumption of the semiconductor device greatly changes depending on the operation state. The details will be described below. FIG. 9 is a circuit diagram of the step-down circuit 66 of the semiconductor chip 62 according to the present embodiment. In the step-down circuit 66, the voltage at the connection point A1 is input to the terminal C by another circuit outside the step-down circuit 66 (an arrow 64 indicates that the voltage at the connection point A1 is fed back). The voltage at the connection point A1 is compared with the reference voltage V2 as the input voltage V1 of the differential amplifier circuit 68. The differential amplifier circuit 68 outputs the voltage V3 according to the comparison result. The voltage V3 is applied to the gate of the transistor Tr2, and the transistor Tr2 outputs a drain current I according to the gate voltage. Here, the transistor Tr2 is an n-channel MOS transistor.
[0030]
In voltage step-down circuit 66 according to the present embodiment, the voltage input to terminal C (that is, the voltage at node A1: VI-R1) becomes higher than the desired voltage (the output current I of step-down circuit 66). Becomes smaller), the output voltage V3 of the differential amplifier circuit 68 increases, and the voltage applied to the gate of the transistor Tr2 also increases as compared with the state of the equilibrium state. Since the transistor Tr2 is an n-channel MOS transistor, when the voltage applied to the gate voltage increases, the value of the drain current I increases, and the decrease in the output current I is suppressed. Conversely, when the voltage input to the terminal C becomes lower than the desired voltage, the increase in the output current I is suppressed. As a result, the output current I of the step-down circuit 66 is maintained at a constant value by feeding back the voltage at the connection point A1. Here, the fact that the output current I is kept constant means that the voltage (VI-R1) of the connection point A1 is kept constant.
[0031]
In a semiconductor device in which the current consumption changes greatly, when the current consumption (I) decreases, the voltage (VI-R1) at the connection point A1 becomes larger than a desired voltage to be applied to the load. May be. In that case, a reliability problem occurs in the load of the transistor and the like. In the semiconductor device according to the present embodiment, the voltage at the connection point A1 (Q1) is fed back to the step-down circuit 6 so that the voltage at the connection point A1 does not exceed the allowable power supply voltage of an element such as a transistor. Can be.
[0032]
Note that the configuration in which the voltage at the connection point between the first wiring 18 and the second wiring 20 is fed back to the step-down circuit can also be realized in the semiconductor device having the stacked structure according to the second embodiment.
[0033]
【The invention's effect】
According to the semiconductor device of the present invention, when a power supply voltage is input, the power supply voltage includes a step-down circuit that steps down and outputs the power supply voltage, and a power supply line that supplies an output voltage of the step-down circuit to a plurality of loads. A power supply line extending from the step-down circuit to a first branch point serving as a first branch point; and a first branch line extending from the step-down circuit to the first branch point. A second wire extending from the point to a plurality of loads, and the first branch point is a first resistance of the second wire from the first branch point to the first load of the plurality of loads. Where the difference between the second resistance value and the second resistance value of the second wiring from the first branch point to the second load among the plurality of loads is smaller than half the first resistance value. And the first load is the first load in the second wiring among the plurality of loads. When the number of the plurality of loads is 2, the second load is a load other than the first load, and the second load is a load other than the first load. When the number is three or more, a path from the first branch point to the position on the path that does not overlap with the path from the first branch point to the first load along the second wiring among the plurality of loads. Is the load having the maximum resistance value, the output voltage of the step-down circuit can be supplied to a load located far from the step-down circuit without significantly lowering the voltage value.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing an arrangement of components of a semiconductor chip according to a first embodiment.
FIG. 2 is a circuit diagram of an integrated circuit realized in the semiconductor chip of FIG. 1;
FIG. 3 is a circuit diagram illustrating an example of a step-down circuit according to the first embodiment;
FIG. 4 is a diagram showing a modification of the arrangement of the components of the semiconductor chip according to the first embodiment;
FIG. 5 is a diagram showing a modification of the arrangement of components of the semiconductor chip according to the first embodiment.
FIG. 6 is a diagram schematically showing a cross section of a semiconductor chip according to a second embodiment.
FIG. 7 is an exploded view of a semiconductor chip according to a second embodiment.
FIG. 8 is a diagram schematically showing an arrangement of components of a semiconductor chip according to a third embodiment.
FIG. 9 is a circuit diagram illustrating an example of a step-down circuit according to Embodiment 3;
FIG. 10 is a diagram schematically showing the arrangement of components of a conventional semiconductor chip.
FIG. 11 is a circuit diagram of an integrated circuit realized in the semiconductor chip of FIG. 10;
[Explanation of symbols]
2 semiconductor chip, 4 external power supply pad, 6 step-down circuit, 8, 10, 12 load, 18, 20 wiring.

Claims (3)

A semiconductor device comprising: a step-down circuit that steps down a power supply voltage when a power supply voltage is input and outputs the voltage;
The power supply wiring has at least one branch point branching in two or more directions,
The power supply line includes a first line extending from the step-down circuit to a first branch point serving as the first branch point, and a second line extending from the first branch point to a plurality of loads. Consisting of
The first branch point is:
A first resistance value from the first branch point in the second wiring to the first load among the plurality of loads and a plurality of the loads from the first branch point in the second wiring to the first load. A difference between the first resistance value and a second resistance value up to a second load is provided at a position where the difference is smaller than a half of the first resistance value;
The first load is
A load having a maximum resistance value from the first branch point to the position in the second wiring among the plurality of loads;
The second load is
When the number of the plurality of loads is 2, the load is a load other than the first load,
When the number of the plurality of loads is 3 or more, among the plurality of loads, a path that does not overlap with a path from the first branch point to the first load along the second wiring, A semiconductor device having a load having a maximum resistance value from the first branch point to the position. A first power supply wiring layer on which the step-down circuit and the second wiring are formed; a second power supply wiring layer on which at least a part of the first wiring is formed; A power supply wiring layer and an insulating layer sandwiched between the second power supply wiring layer,
2. The semiconductor device according to claim 1, wherein the step-down circuit, the first wiring, and the second wiring are electrically connected by a via hole provided in the insulating layer. The step-down circuit includes a differential amplifier circuit,
A voltage at a connection point between the first wiring and the second wiring is fed back to the differential amplifier circuit and input;
3. The differential amplifier circuit according to claim 1, wherein the voltage that is fed back and input is compared with a reference voltage, and an output voltage of the step-down circuit is controlled based on a result of the comparison. 3. The semiconductor device according to claim 1.

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